mars.simulator
Class Exceptions

java.lang.Object
  extended by mars.simulator.Exceptions

public class Exceptions
extends Object

Represents an error/interrupt that occurs during execution (simulation).

Author:
Pete Sanderson

Field Summary
static int ADDRESS_EXCEPTION_LOAD
           
static int ADDRESS_EXCEPTION_STORE
           
static int ARITHMETIC_OVERFLOW_EXCEPTION
           
static int BREAKPOINT_EXCEPTION
           
static int DIVIDE_BY_ZERO_EXCEPTION
           
static int EXTERNAL_INTERRUPT_DISPLAY
           
static int EXTERNAL_INTERRUPT_KEYBOARD
          The exception number is stored in coprocessor 0 cause register ($13) Note: the codes for External Interrupts have been modified from MIPS specs in order to encode two pieces of information.
static int FLOATING_POINT_OVERFLOW
           
static int FLOATING_POINT_UNDERFLOW
           
static int RESERVED_INSTRUCTION_EXCEPTION
           
static int SYSCALL_EXCEPTION
           
static int TRAP_EXCEPTION
           
 
Constructor Summary
Exceptions()
           
 
Method Summary
static void setRegisters(int cause)
          Given MIPS exception cause code, will place that code into coprocessor 0 CAUSE register ($13), set the EPC register to "current" program counter, and set Exception Level bit in STATUS register.
static void setRegisters(int cause, int addr)
          Given MIPS exception cause code and bad address, place the bad address into VADDR register ($8) then call overloaded setRegisters with the cause code to do the rest.
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Field Detail

EXTERNAL_INTERRUPT_KEYBOARD

public static final int EXTERNAL_INTERRUPT_KEYBOARD
The exception number is stored in coprocessor 0 cause register ($13) Note: the codes for External Interrupts have been modified from MIPS specs in order to encode two pieces of information. According to spec, there is one External Interrupt code, 0. But then how to distinguish keyboard interrupt from display interrupt? The Cause register has Interupt Pending bits that can be set. Bit 8 represents keyboard, bit 9 represents display. Those bits are included into this code, but shifted right two positions since the interrupt code will be shifted left two positions for inserting cause code into bit positions 2-6 in Cause register. DPS 23 July 2008.

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Constant Field Values

EXTERNAL_INTERRUPT_DISPLAY

public static final int EXTERNAL_INTERRUPT_DISPLAY
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Constant Field Values

ADDRESS_EXCEPTION_LOAD

public static final int ADDRESS_EXCEPTION_LOAD
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Constant Field Values

ADDRESS_EXCEPTION_STORE

public static final int ADDRESS_EXCEPTION_STORE
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SYSCALL_EXCEPTION

public static final int SYSCALL_EXCEPTION
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BREAKPOINT_EXCEPTION

public static final int BREAKPOINT_EXCEPTION
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RESERVED_INSTRUCTION_EXCEPTION

public static final int RESERVED_INSTRUCTION_EXCEPTION
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ARITHMETIC_OVERFLOW_EXCEPTION

public static final int ARITHMETIC_OVERFLOW_EXCEPTION
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TRAP_EXCEPTION

public static final int TRAP_EXCEPTION
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DIVIDE_BY_ZERO_EXCEPTION

public static final int DIVIDE_BY_ZERO_EXCEPTION
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FLOATING_POINT_OVERFLOW

public static final int FLOATING_POINT_OVERFLOW
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FLOATING_POINT_UNDERFLOW

public static final int FLOATING_POINT_UNDERFLOW
See Also:
Constant Field Values
Constructor Detail

Exceptions

public Exceptions()
Method Detail

setRegisters

public static void setRegisters(int cause)
Given MIPS exception cause code, will place that code into coprocessor 0 CAUSE register ($13), set the EPC register to "current" program counter, and set Exception Level bit in STATUS register.

Parameters:
cause - The cause code (see Exceptions for a list)

setRegisters

public static void setRegisters(int cause,
                                int addr)
Given MIPS exception cause code and bad address, place the bad address into VADDR register ($8) then call overloaded setRegisters with the cause code to do the rest.

Parameters:
cause - The cause code (see Exceptions for a list). Should be address exception.
addr - The address that caused the exception.