1#![allow(improper_ctypes)]
9
10#[cfg(test)]
11use stdarch_test::assert_instr;
12
13use super::*;
14
15#[doc = "CRC32 single round checksum for bytes (8 bits)."]
16#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
17#[inline]
18#[target_feature(enable = "crc")]
19#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
20#[cfg_attr(test, assert_instr(crc32b))]
21#[cfg_attr(
22 target_arch = "arm",
23 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
24)]
25#[cfg_attr(
26 not(target_arch = "arm"),
27 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
28)]
29pub fn __crc32b(crc: u32, data: u8) -> u32 {
30 unsafe extern "unadjusted" {
31 #[cfg_attr(
32 any(target_arch = "aarch64", target_arch = "arm64ec"),
33 link_name = "llvm.aarch64.crc32b"
34 )]
35 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
36 fn ___crc32b(crc: u32, data: u32) -> u32;
37 }
38 unsafe { ___crc32b(crc, data as u32) }
39}
40#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
41#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
42#[inline]
43#[target_feature(enable = "crc")]
44#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
45#[cfg_attr(test, assert_instr(crc32cb))]
46#[cfg_attr(
47 target_arch = "arm",
48 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
49)]
50#[cfg_attr(
51 not(target_arch = "arm"),
52 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
53)]
54pub fn __crc32cb(crc: u32, data: u8) -> u32 {
55 unsafe extern "unadjusted" {
56 #[cfg_attr(
57 any(target_arch = "aarch64", target_arch = "arm64ec"),
58 link_name = "llvm.aarch64.crc32cb"
59 )]
60 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
61 fn ___crc32cb(crc: u32, data: u32) -> u32;
62 }
63 unsafe { ___crc32cb(crc, data as u32) }
64}
65#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
66#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
67#[inline]
68#[target_feature(enable = "crc")]
69#[cfg(target_arch = "arm")]
70#[cfg_attr(test, assert_instr(crc32cw))]
71#[cfg_attr(
72 target_arch = "arm",
73 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
74)]
75pub fn __crc32cd(crc: u32, data: u64) -> u32 {
76 let b: u32 = (data & 0xFFFFFFFF) as u32;
77 let c: u32 = (data >> 32) as u32;
78 unsafe extern "unadjusted" {
79 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
80 fn ___crc32cw(crc: u32, data: u32) -> u32;
81 }
82 unsafe { ___crc32cw(___crc32cw(crc, b), c) }
83}
84#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
85#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
86#[inline]
87#[target_feature(enable = "crc")]
88#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
89#[cfg_attr(test, assert_instr(crc32ch))]
90#[cfg_attr(
91 target_arch = "arm",
92 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
93)]
94#[cfg_attr(
95 not(target_arch = "arm"),
96 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
97)]
98pub fn __crc32ch(crc: u32, data: u16) -> u32 {
99 unsafe extern "unadjusted" {
100 #[cfg_attr(
101 any(target_arch = "aarch64", target_arch = "arm64ec"),
102 link_name = "llvm.aarch64.crc32ch"
103 )]
104 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
105 fn ___crc32ch(crc: u32, data: u32) -> u32;
106 }
107 unsafe { ___crc32ch(crc, data as u32) }
108}
109#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
111#[inline]
112#[target_feature(enable = "crc")]
113#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
114#[cfg_attr(test, assert_instr(crc32cw))]
115#[cfg_attr(
116 target_arch = "arm",
117 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
118)]
119#[cfg_attr(
120 not(target_arch = "arm"),
121 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
122)]
123pub fn __crc32cw(crc: u32, data: u32) -> u32 {
124 unsafe extern "unadjusted" {
125 #[cfg_attr(
126 any(target_arch = "aarch64", target_arch = "arm64ec"),
127 link_name = "llvm.aarch64.crc32cw"
128 )]
129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
130 fn ___crc32cw(crc: u32, data: u32) -> u32;
131 }
132 unsafe { ___crc32cw(crc, data) }
133}
134#[doc = "CRC32 single round checksum for quad words (64 bits)."]
135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
136#[inline]
137#[target_feature(enable = "crc")]
138#[cfg(target_arch = "arm")]
139#[cfg_attr(test, assert_instr(crc32w))]
140#[cfg_attr(
141 target_arch = "arm",
142 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
143)]
144pub fn __crc32d(crc: u32, data: u64) -> u32 {
145 let b: u32 = (data & 0xFFFFFFFF) as u32;
146 let c: u32 = (data >> 32) as u32;
147 unsafe extern "unadjusted" {
148 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
149 fn ___crc32w(crc: u32, data: u32) -> u32;
150 }
151 unsafe { ___crc32w(___crc32w(crc, b), c) }
152}
153#[doc = "CRC32 single round checksum for bytes (16 bits)."]
154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
155#[inline]
156#[target_feature(enable = "crc")]
157#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
158#[cfg_attr(test, assert_instr(crc32h))]
159#[cfg_attr(
160 target_arch = "arm",
161 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
162)]
163#[cfg_attr(
164 not(target_arch = "arm"),
165 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
166)]
167pub fn __crc32h(crc: u32, data: u16) -> u32 {
168 unsafe extern "unadjusted" {
169 #[cfg_attr(
170 any(target_arch = "aarch64", target_arch = "arm64ec"),
171 link_name = "llvm.aarch64.crc32h"
172 )]
173 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
174 fn ___crc32h(crc: u32, data: u32) -> u32;
175 }
176 unsafe { ___crc32h(crc, data as u32) }
177}
178#[doc = "CRC32 single round checksum for bytes (32 bits)."]
179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
180#[inline]
181#[target_feature(enable = "crc")]
182#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
183#[cfg_attr(test, assert_instr(crc32w))]
184#[cfg_attr(
185 target_arch = "arm",
186 unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
187)]
188#[cfg_attr(
189 not(target_arch = "arm"),
190 stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
191)]
192pub fn __crc32w(crc: u32, data: u32) -> u32 {
193 unsafe extern "unadjusted" {
194 #[cfg_attr(
195 any(target_arch = "aarch64", target_arch = "arm64ec"),
196 link_name = "llvm.aarch64.crc32w"
197 )]
198 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
199 fn ___crc32w(crc: u32, data: u32) -> u32;
200 }
201 unsafe { ___crc32w(crc, data) }
202}
203#[doc = "Signed Add and Accumulate Long Pairwise."]
204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
205#[inline]
206#[target_feature(enable = "neon")]
207#[cfg(target_arch = "arm")]
208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
210#[cfg_attr(
211 target_arch = "arm",
212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
213)]
214fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
215 unsafe extern "unadjusted" {
216 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
217 fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
218 }
219 unsafe { _priv_vpadal_s8(a, b) }
220}
221#[doc = "Signed Add and Accumulate Long Pairwise."]
222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
223#[inline]
224#[target_feature(enable = "neon")]
225#[cfg(target_arch = "arm")]
226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
228#[cfg_attr(
229 target_arch = "arm",
230 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
231)]
232fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
233 unsafe extern "unadjusted" {
234 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
235 fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
236 }
237 unsafe { _priv_vpadalq_s8(a, b) }
238}
239#[doc = "Signed Add and Accumulate Long Pairwise."]
240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
241#[inline]
242#[target_feature(enable = "neon")]
243#[cfg(target_arch = "arm")]
244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
246#[cfg_attr(
247 target_arch = "arm",
248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
249)]
250fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
251 unsafe extern "unadjusted" {
252 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
253 fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
254 }
255 unsafe { _priv_vpadal_s16(a, b) }
256}
257#[doc = "Signed Add and Accumulate Long Pairwise."]
258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
259#[inline]
260#[target_feature(enable = "neon")]
261#[cfg(target_arch = "arm")]
262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
263#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
264#[cfg_attr(
265 target_arch = "arm",
266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
267)]
268fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
269 unsafe extern "unadjusted" {
270 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
271 fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
272 }
273 unsafe { _priv_vpadalq_s16(a, b) }
274}
275#[doc = "Signed Add and Accumulate Long Pairwise."]
276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
277#[inline]
278#[target_feature(enable = "neon")]
279#[cfg(target_arch = "arm")]
280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
281#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
282#[cfg_attr(
283 target_arch = "arm",
284 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
285)]
286fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
287 unsafe extern "unadjusted" {
288 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
289 fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
290 }
291 unsafe { _priv_vpadal_s32(a, b) }
292}
293#[doc = "Signed Add and Accumulate Long Pairwise."]
294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
295#[inline]
296#[target_feature(enable = "neon")]
297#[cfg(target_arch = "arm")]
298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
299#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
300#[cfg_attr(
301 target_arch = "arm",
302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
303)]
304fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
305 unsafe extern "unadjusted" {
306 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
307 fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
308 }
309 unsafe { _priv_vpadalq_s32(a, b) }
310}
311#[doc = "Signed Add and Accumulate Long Pairwise."]
312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
313#[inline]
314#[target_feature(enable = "neon")]
315#[cfg(target_arch = "arm")]
316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
317#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
318#[cfg_attr(
319 target_arch = "arm",
320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
321)]
322fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
323 unsafe extern "unadjusted" {
324 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
325 fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
326 }
327 unsafe { _priv_vpadal_u8(a, b) }
328}
329#[doc = "Signed Add and Accumulate Long Pairwise."]
330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
331#[inline]
332#[target_feature(enable = "neon")]
333#[cfg(target_arch = "arm")]
334#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
336#[cfg_attr(
337 target_arch = "arm",
338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
339)]
340fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
341 unsafe extern "unadjusted" {
342 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
343 fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
344 }
345 unsafe { _priv_vpadalq_u8(a, b) }
346}
347#[doc = "Signed Add and Accumulate Long Pairwise."]
348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
349#[inline]
350#[target_feature(enable = "neon")]
351#[cfg(target_arch = "arm")]
352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
353#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
354#[cfg_attr(
355 target_arch = "arm",
356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
357)]
358fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
359 unsafe extern "unadjusted" {
360 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
361 fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
362 }
363 unsafe { _priv_vpadal_u16(a, b) }
364}
365#[doc = "Signed Add and Accumulate Long Pairwise."]
366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
367#[inline]
368#[target_feature(enable = "neon")]
369#[cfg(target_arch = "arm")]
370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
371#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
372#[cfg_attr(
373 target_arch = "arm",
374 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
375)]
376fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
377 unsafe extern "unadjusted" {
378 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
379 fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
380 }
381 unsafe { _priv_vpadalq_u16(a, b) }
382}
383#[doc = "Signed Add and Accumulate Long Pairwise."]
384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
385#[inline]
386#[target_feature(enable = "neon")]
387#[cfg(target_arch = "arm")]
388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
389#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
390#[cfg_attr(
391 target_arch = "arm",
392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
393)]
394fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
395 unsafe extern "unadjusted" {
396 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
397 fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
398 }
399 unsafe { _priv_vpadal_u32(a, b) }
400}
401#[doc = "Signed Add and Accumulate Long Pairwise."]
402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
403#[inline]
404#[target_feature(enable = "neon")]
405#[cfg(target_arch = "arm")]
406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
408#[cfg_attr(
409 target_arch = "arm",
410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
411)]
412fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
413 unsafe extern "unadjusted" {
414 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
415 fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
416 }
417 unsafe { _priv_vpadalq_u32(a, b) }
418}
419#[doc = "Absolute difference and accumulate (64-bit)"]
420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
421#[inline]
422#[target_feature(enable = "neon")]
423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
424#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
425#[cfg_attr(
426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
427 assert_instr(saba)
428)]
429#[cfg_attr(
430 not(target_arch = "arm"),
431 stable(feature = "neon_intrinsics", since = "1.59.0")
432)]
433#[cfg_attr(
434 target_arch = "arm",
435 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
436)]
437pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
438 unsafe { simd_add(a, vabd_s16(b, c)) }
439}
440#[doc = "Absolute difference and accumulate (64-bit)"]
441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
442#[inline]
443#[target_feature(enable = "neon")]
444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
446#[cfg_attr(
447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
448 assert_instr(saba)
449)]
450#[cfg_attr(
451 not(target_arch = "arm"),
452 stable(feature = "neon_intrinsics", since = "1.59.0")
453)]
454#[cfg_attr(
455 target_arch = "arm",
456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
457)]
458pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
459 unsafe { simd_add(a, vabd_s32(b, c)) }
460}
461#[doc = "Absolute difference and accumulate (64-bit)"]
462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
463#[inline]
464#[target_feature(enable = "neon")]
465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
466#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
467#[cfg_attr(
468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
469 assert_instr(saba)
470)]
471#[cfg_attr(
472 not(target_arch = "arm"),
473 stable(feature = "neon_intrinsics", since = "1.59.0")
474)]
475#[cfg_attr(
476 target_arch = "arm",
477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
478)]
479pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
480 unsafe { simd_add(a, vabd_s8(b, c)) }
481}
482#[doc = "Absolute difference and accumulate (64-bit)"]
483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
484#[inline]
485#[target_feature(enable = "neon")]
486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
488#[cfg_attr(
489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
490 assert_instr(uaba)
491)]
492#[cfg_attr(
493 not(target_arch = "arm"),
494 stable(feature = "neon_intrinsics", since = "1.59.0")
495)]
496#[cfg_attr(
497 target_arch = "arm",
498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
499)]
500pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
501 unsafe { simd_add(a, vabd_u16(b, c)) }
502}
503#[doc = "Absolute difference and accumulate (64-bit)"]
504#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
505#[inline]
506#[target_feature(enable = "neon")]
507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
508#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
509#[cfg_attr(
510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
511 assert_instr(uaba)
512)]
513#[cfg_attr(
514 not(target_arch = "arm"),
515 stable(feature = "neon_intrinsics", since = "1.59.0")
516)]
517#[cfg_attr(
518 target_arch = "arm",
519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
520)]
521pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
522 unsafe { simd_add(a, vabd_u32(b, c)) }
523}
524#[doc = "Absolute difference and accumulate (64-bit)"]
525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
526#[inline]
527#[target_feature(enable = "neon")]
528#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
529#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
530#[cfg_attr(
531 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
532 assert_instr(uaba)
533)]
534#[cfg_attr(
535 not(target_arch = "arm"),
536 stable(feature = "neon_intrinsics", since = "1.59.0")
537)]
538#[cfg_attr(
539 target_arch = "arm",
540 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
541)]
542pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
543 unsafe { simd_add(a, vabd_u8(b, c)) }
544}
545#[doc = "Signed Absolute difference and Accumulate Long"]
546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
547#[inline]
548#[target_feature(enable = "neon")]
549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
551#[cfg_attr(
552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
553 assert_instr(sabal)
554)]
555#[cfg_attr(
556 not(target_arch = "arm"),
557 stable(feature = "neon_intrinsics", since = "1.59.0")
558)]
559#[cfg_attr(
560 target_arch = "arm",
561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
562)]
563pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
564 let d: int8x8_t = vabd_s8(b, c);
565 unsafe {
566 let e: uint8x8_t = simd_cast(d);
567 simd_add(a, simd_cast(e))
568 }
569}
570#[doc = "Signed Absolute difference and Accumulate Long"]
571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
572#[inline]
573#[target_feature(enable = "neon")]
574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
575#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
576#[cfg_attr(
577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
578 assert_instr(sabal)
579)]
580#[cfg_attr(
581 not(target_arch = "arm"),
582 stable(feature = "neon_intrinsics", since = "1.59.0")
583)]
584#[cfg_attr(
585 target_arch = "arm",
586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
587)]
588pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
589 let d: int16x4_t = vabd_s16(b, c);
590 unsafe {
591 let e: uint16x4_t = simd_cast(d);
592 simd_add(a, simd_cast(e))
593 }
594}
595#[doc = "Signed Absolute difference and Accumulate Long"]
596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
597#[inline]
598#[target_feature(enable = "neon")]
599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
601#[cfg_attr(
602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
603 assert_instr(sabal)
604)]
605#[cfg_attr(
606 not(target_arch = "arm"),
607 stable(feature = "neon_intrinsics", since = "1.59.0")
608)]
609#[cfg_attr(
610 target_arch = "arm",
611 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
612)]
613pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
614 let d: int32x2_t = vabd_s32(b, c);
615 unsafe {
616 let e: uint32x2_t = simd_cast(d);
617 simd_add(a, simd_cast(e))
618 }
619}
620#[doc = "Unsigned Absolute difference and Accumulate Long"]
621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
622#[inline]
623#[target_feature(enable = "neon")]
624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
625#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
626#[cfg_attr(
627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
628 assert_instr(uabal)
629)]
630#[cfg_attr(
631 not(target_arch = "arm"),
632 stable(feature = "neon_intrinsics", since = "1.59.0")
633)]
634#[cfg_attr(
635 target_arch = "arm",
636 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
637)]
638pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
639 let d: uint8x8_t = vabd_u8(b, c);
640 unsafe { simd_add(a, simd_cast(d)) }
641}
642#[doc = "Unsigned Absolute difference and Accumulate Long"]
643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
644#[inline]
645#[target_feature(enable = "neon")]
646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
647#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
648#[cfg_attr(
649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
650 assert_instr(uabal)
651)]
652#[cfg_attr(
653 not(target_arch = "arm"),
654 stable(feature = "neon_intrinsics", since = "1.59.0")
655)]
656#[cfg_attr(
657 target_arch = "arm",
658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
659)]
660pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
661 let d: uint16x4_t = vabd_u16(b, c);
662 unsafe { simd_add(a, simd_cast(d)) }
663}
664#[doc = "Unsigned Absolute difference and Accumulate Long"]
665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
666#[inline]
667#[target_feature(enable = "neon")]
668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
670#[cfg_attr(
671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
672 assert_instr(uabal)
673)]
674#[cfg_attr(
675 not(target_arch = "arm"),
676 stable(feature = "neon_intrinsics", since = "1.59.0")
677)]
678#[cfg_attr(
679 target_arch = "arm",
680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
681)]
682pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
683 let d: uint32x2_t = vabd_u32(b, c);
684 unsafe { simd_add(a, simd_cast(d)) }
685}
686#[doc = "Absolute difference and accumulate (128-bit)"]
687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
688#[inline]
689#[target_feature(enable = "neon")]
690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
691#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
692#[cfg_attr(
693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
694 assert_instr(saba)
695)]
696#[cfg_attr(
697 not(target_arch = "arm"),
698 stable(feature = "neon_intrinsics", since = "1.59.0")
699)]
700#[cfg_attr(
701 target_arch = "arm",
702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
703)]
704pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
705 unsafe { simd_add(a, vabdq_s16(b, c)) }
706}
707#[doc = "Absolute difference and accumulate (128-bit)"]
708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
709#[inline]
710#[target_feature(enable = "neon")]
711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
713#[cfg_attr(
714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
715 assert_instr(saba)
716)]
717#[cfg_attr(
718 not(target_arch = "arm"),
719 stable(feature = "neon_intrinsics", since = "1.59.0")
720)]
721#[cfg_attr(
722 target_arch = "arm",
723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
724)]
725pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
726 unsafe { simd_add(a, vabdq_s32(b, c)) }
727}
728#[doc = "Absolute difference and accumulate (128-bit)"]
729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
730#[inline]
731#[target_feature(enable = "neon")]
732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
733#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
734#[cfg_attr(
735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
736 assert_instr(saba)
737)]
738#[cfg_attr(
739 not(target_arch = "arm"),
740 stable(feature = "neon_intrinsics", since = "1.59.0")
741)]
742#[cfg_attr(
743 target_arch = "arm",
744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
745)]
746pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
747 unsafe { simd_add(a, vabdq_s8(b, c)) }
748}
749#[doc = "Absolute difference and accumulate (128-bit)"]
750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
751#[inline]
752#[target_feature(enable = "neon")]
753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
755#[cfg_attr(
756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
757 assert_instr(uaba)
758)]
759#[cfg_attr(
760 not(target_arch = "arm"),
761 stable(feature = "neon_intrinsics", since = "1.59.0")
762)]
763#[cfg_attr(
764 target_arch = "arm",
765 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
766)]
767pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
768 unsafe { simd_add(a, vabdq_u16(b, c)) }
769}
770#[doc = "Absolute difference and accumulate (128-bit)"]
771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
772#[inline]
773#[target_feature(enable = "neon")]
774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
775#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
776#[cfg_attr(
777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
778 assert_instr(uaba)
779)]
780#[cfg_attr(
781 not(target_arch = "arm"),
782 stable(feature = "neon_intrinsics", since = "1.59.0")
783)]
784#[cfg_attr(
785 target_arch = "arm",
786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
787)]
788pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
789 unsafe { simd_add(a, vabdq_u32(b, c)) }
790}
791#[doc = "Absolute difference and accumulate (128-bit)"]
792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
793#[inline]
794#[target_feature(enable = "neon")]
795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
796#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
797#[cfg_attr(
798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
799 assert_instr(uaba)
800)]
801#[cfg_attr(
802 not(target_arch = "arm"),
803 stable(feature = "neon_intrinsics", since = "1.59.0")
804)]
805#[cfg_attr(
806 target_arch = "arm",
807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
808)]
809pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
810 unsafe { simd_add(a, vabdq_u8(b, c)) }
811}
812#[doc = "Absolute difference between the arguments of Floating"]
813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
814#[inline]
815#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
817#[cfg_attr(
818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
819 assert_instr(fabd)
820)]
821#[target_feature(enable = "neon,fp16")]
822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
823pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
824 unsafe extern "unadjusted" {
825 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f16")]
826 #[cfg_attr(
827 any(target_arch = "aarch64", target_arch = "arm64ec"),
828 link_name = "llvm.aarch64.neon.fabd.v4f16"
829 )]
830 fn _vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
831 }
832 unsafe { _vabd_f16(a, b) }
833}
834#[doc = "Absolute difference between the arguments of Floating"]
835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
836#[inline]
837#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
838#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
839#[cfg_attr(
840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
841 assert_instr(fabd)
842)]
843#[target_feature(enable = "neon,fp16")]
844#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
845pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
846 unsafe extern "unadjusted" {
847 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8f16")]
848 #[cfg_attr(
849 any(target_arch = "aarch64", target_arch = "arm64ec"),
850 link_name = "llvm.aarch64.neon.fabd.v8f16"
851 )]
852 fn _vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
853 }
854 unsafe { _vabdq_f16(a, b) }
855}
856#[doc = "Absolute difference between the arguments of Floating"]
857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
858#[inline]
859#[target_feature(enable = "neon")]
860#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
861#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
862#[cfg_attr(
863 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
864 assert_instr(fabd)
865)]
866#[cfg_attr(
867 not(target_arch = "arm"),
868 stable(feature = "neon_intrinsics", since = "1.59.0")
869)]
870#[cfg_attr(
871 target_arch = "arm",
872 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
873)]
874pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
875 unsafe extern "unadjusted" {
876 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")]
877 #[cfg_attr(
878 any(target_arch = "aarch64", target_arch = "arm64ec"),
879 link_name = "llvm.aarch64.neon.fabd.v2f32"
880 )]
881 fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
882 }
883 unsafe { _vabd_f32(a, b) }
884}
885#[doc = "Absolute difference between the arguments of Floating"]
886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
887#[inline]
888#[target_feature(enable = "neon")]
889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
890#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
891#[cfg_attr(
892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
893 assert_instr(fabd)
894)]
895#[cfg_attr(
896 not(target_arch = "arm"),
897 stable(feature = "neon_intrinsics", since = "1.59.0")
898)]
899#[cfg_attr(
900 target_arch = "arm",
901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
902)]
903pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
904 unsafe extern "unadjusted" {
905 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")]
906 #[cfg_attr(
907 any(target_arch = "aarch64", target_arch = "arm64ec"),
908 link_name = "llvm.aarch64.neon.fabd.v4f32"
909 )]
910 fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
911 }
912 unsafe { _vabdq_f32(a, b) }
913}
914#[doc = "Absolute difference between the arguments"]
915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
916#[inline]
917#[target_feature(enable = "neon")]
918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
919#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
920#[cfg_attr(
921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
922 assert_instr(sabd)
923)]
924#[cfg_attr(
925 not(target_arch = "arm"),
926 stable(feature = "neon_intrinsics", since = "1.59.0")
927)]
928#[cfg_attr(
929 target_arch = "arm",
930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
931)]
932pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
933 unsafe extern "unadjusted" {
934 #[cfg_attr(
935 any(target_arch = "aarch64", target_arch = "arm64ec"),
936 link_name = "llvm.aarch64.neon.sabd.v8i8"
937 )]
938 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")]
939 fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
940 }
941 unsafe { _vabd_s8(a, b) }
942}
943#[doc = "Absolute difference between the arguments"]
944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
945#[inline]
946#[target_feature(enable = "neon")]
947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
948#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
949#[cfg_attr(
950 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
951 assert_instr(sabd)
952)]
953#[cfg_attr(
954 not(target_arch = "arm"),
955 stable(feature = "neon_intrinsics", since = "1.59.0")
956)]
957#[cfg_attr(
958 target_arch = "arm",
959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
960)]
961pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
962 unsafe extern "unadjusted" {
963 #[cfg_attr(
964 any(target_arch = "aarch64", target_arch = "arm64ec"),
965 link_name = "llvm.aarch64.neon.sabd.v16i8"
966 )]
967 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")]
968 fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
969 }
970 unsafe { _vabdq_s8(a, b) }
971}
972#[doc = "Absolute difference between the arguments"]
973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
974#[inline]
975#[target_feature(enable = "neon")]
976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
977#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
978#[cfg_attr(
979 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
980 assert_instr(sabd)
981)]
982#[cfg_attr(
983 not(target_arch = "arm"),
984 stable(feature = "neon_intrinsics", since = "1.59.0")
985)]
986#[cfg_attr(
987 target_arch = "arm",
988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
989)]
990pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
991 unsafe extern "unadjusted" {
992 #[cfg_attr(
993 any(target_arch = "aarch64", target_arch = "arm64ec"),
994 link_name = "llvm.aarch64.neon.sabd.v4i16"
995 )]
996 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")]
997 fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
998 }
999 unsafe { _vabd_s16(a, b) }
1000}
1001#[doc = "Absolute difference between the arguments"]
1002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
1003#[inline]
1004#[target_feature(enable = "neon")]
1005#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1006#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
1007#[cfg_attr(
1008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1009 assert_instr(sabd)
1010)]
1011#[cfg_attr(
1012 not(target_arch = "arm"),
1013 stable(feature = "neon_intrinsics", since = "1.59.0")
1014)]
1015#[cfg_attr(
1016 target_arch = "arm",
1017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1018)]
1019pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1020 unsafe extern "unadjusted" {
1021 #[cfg_attr(
1022 any(target_arch = "aarch64", target_arch = "arm64ec"),
1023 link_name = "llvm.aarch64.neon.sabd.v8i16"
1024 )]
1025 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")]
1026 fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
1027 }
1028 unsafe { _vabdq_s16(a, b) }
1029}
1030#[doc = "Absolute difference between the arguments"]
1031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
1032#[inline]
1033#[target_feature(enable = "neon")]
1034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1035#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1036#[cfg_attr(
1037 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1038 assert_instr(sabd)
1039)]
1040#[cfg_attr(
1041 not(target_arch = "arm"),
1042 stable(feature = "neon_intrinsics", since = "1.59.0")
1043)]
1044#[cfg_attr(
1045 target_arch = "arm",
1046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1047)]
1048pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1049 unsafe extern "unadjusted" {
1050 #[cfg_attr(
1051 any(target_arch = "aarch64", target_arch = "arm64ec"),
1052 link_name = "llvm.aarch64.neon.sabd.v2i32"
1053 )]
1054 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")]
1055 fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
1056 }
1057 unsafe { _vabd_s32(a, b) }
1058}
1059#[doc = "Absolute difference between the arguments"]
1060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
1061#[inline]
1062#[target_feature(enable = "neon")]
1063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1064#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
1065#[cfg_attr(
1066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1067 assert_instr(sabd)
1068)]
1069#[cfg_attr(
1070 not(target_arch = "arm"),
1071 stable(feature = "neon_intrinsics", since = "1.59.0")
1072)]
1073#[cfg_attr(
1074 target_arch = "arm",
1075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1076)]
1077pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1078 unsafe extern "unadjusted" {
1079 #[cfg_attr(
1080 any(target_arch = "aarch64", target_arch = "arm64ec"),
1081 link_name = "llvm.aarch64.neon.sabd.v4i32"
1082 )]
1083 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")]
1084 fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
1085 }
1086 unsafe { _vabdq_s32(a, b) }
1087}
1088#[doc = "Absolute difference between the arguments"]
1089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
1090#[inline]
1091#[target_feature(enable = "neon")]
1092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1093#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1094#[cfg_attr(
1095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1096 assert_instr(uabd)
1097)]
1098#[cfg_attr(
1099 not(target_arch = "arm"),
1100 stable(feature = "neon_intrinsics", since = "1.59.0")
1101)]
1102#[cfg_attr(
1103 target_arch = "arm",
1104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1105)]
1106pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1107 unsafe extern "unadjusted" {
1108 #[cfg_attr(
1109 any(target_arch = "aarch64", target_arch = "arm64ec"),
1110 link_name = "llvm.aarch64.neon.uabd.v8i8"
1111 )]
1112 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")]
1113 fn _vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
1114 }
1115 unsafe { _vabd_u8(a, b) }
1116}
1117#[doc = "Absolute difference between the arguments"]
1118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
1119#[inline]
1120#[target_feature(enable = "neon")]
1121#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1122#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
1123#[cfg_attr(
1124 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1125 assert_instr(uabd)
1126)]
1127#[cfg_attr(
1128 not(target_arch = "arm"),
1129 stable(feature = "neon_intrinsics", since = "1.59.0")
1130)]
1131#[cfg_attr(
1132 target_arch = "arm",
1133 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1134)]
1135pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1136 unsafe extern "unadjusted" {
1137 #[cfg_attr(
1138 any(target_arch = "aarch64", target_arch = "arm64ec"),
1139 link_name = "llvm.aarch64.neon.uabd.v16i8"
1140 )]
1141 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")]
1142 fn _vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
1143 }
1144 unsafe { _vabdq_u8(a, b) }
1145}
1146#[doc = "Absolute difference between the arguments"]
1147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
1148#[inline]
1149#[target_feature(enable = "neon")]
1150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1152#[cfg_attr(
1153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1154 assert_instr(uabd)
1155)]
1156#[cfg_attr(
1157 not(target_arch = "arm"),
1158 stable(feature = "neon_intrinsics", since = "1.59.0")
1159)]
1160#[cfg_attr(
1161 target_arch = "arm",
1162 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1163)]
1164pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1165 unsafe extern "unadjusted" {
1166 #[cfg_attr(
1167 any(target_arch = "aarch64", target_arch = "arm64ec"),
1168 link_name = "llvm.aarch64.neon.uabd.v4i16"
1169 )]
1170 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")]
1171 fn _vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
1172 }
1173 unsafe { _vabd_u16(a, b) }
1174}
1175#[doc = "Absolute difference between the arguments"]
1176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
1177#[inline]
1178#[target_feature(enable = "neon")]
1179#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
1181#[cfg_attr(
1182 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1183 assert_instr(uabd)
1184)]
1185#[cfg_attr(
1186 not(target_arch = "arm"),
1187 stable(feature = "neon_intrinsics", since = "1.59.0")
1188)]
1189#[cfg_attr(
1190 target_arch = "arm",
1191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1192)]
1193pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1194 unsafe extern "unadjusted" {
1195 #[cfg_attr(
1196 any(target_arch = "aarch64", target_arch = "arm64ec"),
1197 link_name = "llvm.aarch64.neon.uabd.v8i16"
1198 )]
1199 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")]
1200 fn _vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
1201 }
1202 unsafe { _vabdq_u16(a, b) }
1203}
1204#[doc = "Absolute difference between the arguments"]
1205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
1206#[inline]
1207#[target_feature(enable = "neon")]
1208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1209#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1210#[cfg_attr(
1211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1212 assert_instr(uabd)
1213)]
1214#[cfg_attr(
1215 not(target_arch = "arm"),
1216 stable(feature = "neon_intrinsics", since = "1.59.0")
1217)]
1218#[cfg_attr(
1219 target_arch = "arm",
1220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1221)]
1222pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1223 unsafe extern "unadjusted" {
1224 #[cfg_attr(
1225 any(target_arch = "aarch64", target_arch = "arm64ec"),
1226 link_name = "llvm.aarch64.neon.uabd.v2i32"
1227 )]
1228 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")]
1229 fn _vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
1230 }
1231 unsafe { _vabd_u32(a, b) }
1232}
1233#[doc = "Absolute difference between the arguments"]
1234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
1235#[inline]
1236#[target_feature(enable = "neon")]
1237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1238#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
1239#[cfg_attr(
1240 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1241 assert_instr(uabd)
1242)]
1243#[cfg_attr(
1244 not(target_arch = "arm"),
1245 stable(feature = "neon_intrinsics", since = "1.59.0")
1246)]
1247#[cfg_attr(
1248 target_arch = "arm",
1249 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1250)]
1251pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1252 unsafe extern "unadjusted" {
1253 #[cfg_attr(
1254 any(target_arch = "aarch64", target_arch = "arm64ec"),
1255 link_name = "llvm.aarch64.neon.uabd.v4i32"
1256 )]
1257 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")]
1258 fn _vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
1259 }
1260 unsafe { _vabdq_u32(a, b) }
1261}
1262#[doc = "Signed Absolute difference Long"]
1263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
1264#[inline]
1265#[target_feature(enable = "neon")]
1266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1267#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
1268#[cfg_attr(
1269 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1270 assert_instr(sabdl)
1271)]
1272#[cfg_attr(
1273 not(target_arch = "arm"),
1274 stable(feature = "neon_intrinsics", since = "1.59.0")
1275)]
1276#[cfg_attr(
1277 target_arch = "arm",
1278 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1279)]
1280pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
1281 unsafe {
1282 let c: uint8x8_t = simd_cast(vabd_s8(a, b));
1283 simd_cast(c)
1284 }
1285}
1286#[doc = "Signed Absolute difference Long"]
1287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
1288#[inline]
1289#[target_feature(enable = "neon")]
1290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1291#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
1292#[cfg_attr(
1293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1294 assert_instr(sabdl)
1295)]
1296#[cfg_attr(
1297 not(target_arch = "arm"),
1298 stable(feature = "neon_intrinsics", since = "1.59.0")
1299)]
1300#[cfg_attr(
1301 target_arch = "arm",
1302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1303)]
1304pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
1305 unsafe {
1306 let c: uint16x4_t = simd_cast(vabd_s16(a, b));
1307 simd_cast(c)
1308 }
1309}
1310#[doc = "Signed Absolute difference Long"]
1311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
1312#[inline]
1313#[target_feature(enable = "neon")]
1314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
1316#[cfg_attr(
1317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1318 assert_instr(sabdl)
1319)]
1320#[cfg_attr(
1321 not(target_arch = "arm"),
1322 stable(feature = "neon_intrinsics", since = "1.59.0")
1323)]
1324#[cfg_attr(
1325 target_arch = "arm",
1326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1327)]
1328pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
1329 unsafe {
1330 let c: uint32x2_t = simd_cast(vabd_s32(a, b));
1331 simd_cast(c)
1332 }
1333}
1334#[doc = "Unsigned Absolute difference Long"]
1335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
1336#[inline]
1337#[target_feature(enable = "neon")]
1338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
1340#[cfg_attr(
1341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1342 assert_instr(uabdl)
1343)]
1344#[cfg_attr(
1345 not(target_arch = "arm"),
1346 stable(feature = "neon_intrinsics", since = "1.59.0")
1347)]
1348#[cfg_attr(
1349 target_arch = "arm",
1350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1351)]
1352pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
1353 unsafe { simd_cast(vabd_u8(a, b)) }
1354}
1355#[doc = "Unsigned Absolute difference Long"]
1356#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
1357#[inline]
1358#[target_feature(enable = "neon")]
1359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1360#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
1361#[cfg_attr(
1362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1363 assert_instr(uabdl)
1364)]
1365#[cfg_attr(
1366 not(target_arch = "arm"),
1367 stable(feature = "neon_intrinsics", since = "1.59.0")
1368)]
1369#[cfg_attr(
1370 target_arch = "arm",
1371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1372)]
1373pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
1374 unsafe { simd_cast(vabd_u16(a, b)) }
1375}
1376#[doc = "Unsigned Absolute difference Long"]
1377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
1378#[inline]
1379#[target_feature(enable = "neon")]
1380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1381#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
1382#[cfg_attr(
1383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1384 assert_instr(uabdl)
1385)]
1386#[cfg_attr(
1387 not(target_arch = "arm"),
1388 stable(feature = "neon_intrinsics", since = "1.59.0")
1389)]
1390#[cfg_attr(
1391 target_arch = "arm",
1392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1393)]
1394pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
1395 unsafe { simd_cast(vabd_u32(a, b)) }
1396}
1397#[doc = "Floating-point absolute value"]
1398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
1399#[inline]
1400#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1402#[cfg_attr(
1403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1404 assert_instr(fabs)
1405)]
1406#[target_feature(enable = "neon,fp16")]
1407#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1408pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
1409 unsafe { simd_fabs(a) }
1410}
1411#[doc = "Floating-point absolute value"]
1412#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
1413#[inline]
1414#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1416#[cfg_attr(
1417 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1418 assert_instr(fabs)
1419)]
1420#[target_feature(enable = "neon,fp16")]
1421#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1422pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
1423 unsafe { simd_fabs(a) }
1424}
1425#[doc = "Floating-point absolute value"]
1426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
1427#[inline]
1428#[target_feature(enable = "neon")]
1429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1431#[cfg_attr(
1432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1433 assert_instr(fabs)
1434)]
1435#[cfg_attr(
1436 not(target_arch = "arm"),
1437 stable(feature = "neon_intrinsics", since = "1.59.0")
1438)]
1439#[cfg_attr(
1440 target_arch = "arm",
1441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1442)]
1443pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
1444 unsafe { simd_fabs(a) }
1445}
1446#[doc = "Floating-point absolute value"]
1447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
1448#[inline]
1449#[target_feature(enable = "neon")]
1450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1452#[cfg_attr(
1453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1454 assert_instr(fabs)
1455)]
1456#[cfg_attr(
1457 not(target_arch = "arm"),
1458 stable(feature = "neon_intrinsics", since = "1.59.0")
1459)]
1460#[cfg_attr(
1461 target_arch = "arm",
1462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1463)]
1464pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
1465 unsafe { simd_fabs(a) }
1466}
1467#[doc = "Absolute value (wrapping)."]
1468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
1469#[inline]
1470#[target_feature(enable = "neon")]
1471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1473#[cfg_attr(
1474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1475 assert_instr(abs)
1476)]
1477#[cfg_attr(
1478 not(target_arch = "arm"),
1479 stable(feature = "neon_intrinsics", since = "1.59.0")
1480)]
1481#[cfg_attr(
1482 target_arch = "arm",
1483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1484)]
1485pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
1486 unsafe {
1487 let neg: int8x8_t = simd_neg(a);
1488 let mask: int8x8_t = simd_ge(a, neg);
1489 simd_select(mask, a, neg)
1490 }
1491}
1492#[doc = "Absolute value (wrapping)."]
1493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
1494#[inline]
1495#[target_feature(enable = "neon")]
1496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1498#[cfg_attr(
1499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1500 assert_instr(abs)
1501)]
1502#[cfg_attr(
1503 not(target_arch = "arm"),
1504 stable(feature = "neon_intrinsics", since = "1.59.0")
1505)]
1506#[cfg_attr(
1507 target_arch = "arm",
1508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1509)]
1510pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
1511 unsafe {
1512 let neg: int8x16_t = simd_neg(a);
1513 let mask: int8x16_t = simd_ge(a, neg);
1514 simd_select(mask, a, neg)
1515 }
1516}
1517#[doc = "Absolute value (wrapping)."]
1518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
1519#[inline]
1520#[target_feature(enable = "neon")]
1521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1522#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1523#[cfg_attr(
1524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1525 assert_instr(abs)
1526)]
1527#[cfg_attr(
1528 not(target_arch = "arm"),
1529 stable(feature = "neon_intrinsics", since = "1.59.0")
1530)]
1531#[cfg_attr(
1532 target_arch = "arm",
1533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1534)]
1535pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
1536 unsafe {
1537 let neg: int16x4_t = simd_neg(a);
1538 let mask: int16x4_t = simd_ge(a, neg);
1539 simd_select(mask, a, neg)
1540 }
1541}
1542#[doc = "Absolute value (wrapping)."]
1543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
1544#[inline]
1545#[target_feature(enable = "neon")]
1546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1548#[cfg_attr(
1549 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1550 assert_instr(abs)
1551)]
1552#[cfg_attr(
1553 not(target_arch = "arm"),
1554 stable(feature = "neon_intrinsics", since = "1.59.0")
1555)]
1556#[cfg_attr(
1557 target_arch = "arm",
1558 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1559)]
1560pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
1561 unsafe {
1562 let neg: int16x8_t = simd_neg(a);
1563 let mask: int16x8_t = simd_ge(a, neg);
1564 simd_select(mask, a, neg)
1565 }
1566}
1567#[doc = "Absolute value (wrapping)."]
1568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
1569#[inline]
1570#[target_feature(enable = "neon")]
1571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1573#[cfg_attr(
1574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1575 assert_instr(abs)
1576)]
1577#[cfg_attr(
1578 not(target_arch = "arm"),
1579 stable(feature = "neon_intrinsics", since = "1.59.0")
1580)]
1581#[cfg_attr(
1582 target_arch = "arm",
1583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1584)]
1585pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
1586 unsafe {
1587 let neg: int32x2_t = simd_neg(a);
1588 let mask: int32x2_t = simd_ge(a, neg);
1589 simd_select(mask, a, neg)
1590 }
1591}
1592#[doc = "Absolute value (wrapping)."]
1593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
1594#[inline]
1595#[target_feature(enable = "neon")]
1596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1597#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1598#[cfg_attr(
1599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1600 assert_instr(abs)
1601)]
1602#[cfg_attr(
1603 not(target_arch = "arm"),
1604 stable(feature = "neon_intrinsics", since = "1.59.0")
1605)]
1606#[cfg_attr(
1607 target_arch = "arm",
1608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1609)]
1610pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
1611 unsafe {
1612 let neg: int32x4_t = simd_neg(a);
1613 let mask: int32x4_t = simd_ge(a, neg);
1614 simd_select(mask, a, neg)
1615 }
1616}
1617#[doc = "Floating-point absolute value"]
1618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
1619#[inline]
1620#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
1622#[cfg_attr(
1623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1624 assert_instr(fabs)
1625)]
1626#[target_feature(enable = "neon,fp16")]
1627#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1628pub fn vabsh_f16(a: f16) -> f16 {
1629 unsafe { simd_extract!(vabs_f16(vdup_n_f16(a)), 0) }
1630}
1631#[doc = "Floating-point Add (vector)."]
1632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
1633#[inline]
1634#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1636#[cfg_attr(
1637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1638 assert_instr(fadd)
1639)]
1640#[target_feature(enable = "neon,fp16")]
1641#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1642pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
1643 unsafe { simd_add(a, b) }
1644}
1645#[doc = "Floating-point Add (vector)."]
1646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
1647#[inline]
1648#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
1649#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
1650#[cfg_attr(
1651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1652 assert_instr(fadd)
1653)]
1654#[target_feature(enable = "neon,fp16")]
1655#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
1656pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
1657 unsafe { simd_add(a, b) }
1658}
1659#[doc = "Vector add."]
1660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
1661#[inline]
1662#[target_feature(enable = "neon")]
1663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1665#[cfg_attr(
1666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1667 assert_instr(fadd)
1668)]
1669#[cfg_attr(
1670 not(target_arch = "arm"),
1671 stable(feature = "neon_intrinsics", since = "1.59.0")
1672)]
1673#[cfg_attr(
1674 target_arch = "arm",
1675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1676)]
1677pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
1678 unsafe { simd_add(a, b) }
1679}
1680#[doc = "Vector add."]
1681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
1682#[inline]
1683#[target_feature(enable = "neon")]
1684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1686#[cfg_attr(
1687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1688 assert_instr(add)
1689)]
1690#[cfg_attr(
1691 not(target_arch = "arm"),
1692 stable(feature = "neon_intrinsics", since = "1.59.0")
1693)]
1694#[cfg_attr(
1695 target_arch = "arm",
1696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1697)]
1698pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
1699 unsafe { simd_add(a, b) }
1700}
1701#[doc = "Vector add."]
1702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
1703#[inline]
1704#[target_feature(enable = "neon")]
1705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1706#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1707#[cfg_attr(
1708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1709 assert_instr(add)
1710)]
1711#[cfg_attr(
1712 not(target_arch = "arm"),
1713 stable(feature = "neon_intrinsics", since = "1.59.0")
1714)]
1715#[cfg_attr(
1716 target_arch = "arm",
1717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1718)]
1719pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
1720 unsafe { simd_add(a, b) }
1721}
1722#[doc = "Vector add."]
1723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
1724#[inline]
1725#[target_feature(enable = "neon")]
1726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1728#[cfg_attr(
1729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1730 assert_instr(add)
1731)]
1732#[cfg_attr(
1733 not(target_arch = "arm"),
1734 stable(feature = "neon_intrinsics", since = "1.59.0")
1735)]
1736#[cfg_attr(
1737 target_arch = "arm",
1738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1739)]
1740pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
1741 unsafe { simd_add(a, b) }
1742}
1743#[doc = "Vector add."]
1744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
1745#[inline]
1746#[target_feature(enable = "neon")]
1747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1749#[cfg_attr(
1750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1751 assert_instr(add)
1752)]
1753#[cfg_attr(
1754 not(target_arch = "arm"),
1755 stable(feature = "neon_intrinsics", since = "1.59.0")
1756)]
1757#[cfg_attr(
1758 target_arch = "arm",
1759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1760)]
1761pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
1762 unsafe { simd_add(a, b) }
1763}
1764#[doc = "Vector add."]
1765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
1766#[inline]
1767#[target_feature(enable = "neon")]
1768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1770#[cfg_attr(
1771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1772 assert_instr(add)
1773)]
1774#[cfg_attr(
1775 not(target_arch = "arm"),
1776 stable(feature = "neon_intrinsics", since = "1.59.0")
1777)]
1778#[cfg_attr(
1779 target_arch = "arm",
1780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1781)]
1782pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
1783 unsafe { simd_add(a, b) }
1784}
1785#[doc = "Vector add."]
1786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
1787#[inline]
1788#[target_feature(enable = "neon")]
1789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1791#[cfg_attr(
1792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1793 assert_instr(add)
1794)]
1795#[cfg_attr(
1796 not(target_arch = "arm"),
1797 stable(feature = "neon_intrinsics", since = "1.59.0")
1798)]
1799#[cfg_attr(
1800 target_arch = "arm",
1801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1802)]
1803pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
1804 unsafe { simd_add(a, b) }
1805}
1806#[doc = "Vector add."]
1807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
1808#[inline]
1809#[target_feature(enable = "neon")]
1810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1812#[cfg_attr(
1813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1814 assert_instr(fadd)
1815)]
1816#[cfg_attr(
1817 not(target_arch = "arm"),
1818 stable(feature = "neon_intrinsics", since = "1.59.0")
1819)]
1820#[cfg_attr(
1821 target_arch = "arm",
1822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1823)]
1824pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
1825 unsafe { simd_add(a, b) }
1826}
1827#[doc = "Vector add."]
1828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
1829#[inline]
1830#[target_feature(enable = "neon")]
1831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1833#[cfg_attr(
1834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1835 assert_instr(add)
1836)]
1837#[cfg_attr(
1838 not(target_arch = "arm"),
1839 stable(feature = "neon_intrinsics", since = "1.59.0")
1840)]
1841#[cfg_attr(
1842 target_arch = "arm",
1843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1844)]
1845pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
1846 unsafe { simd_add(a, b) }
1847}
1848#[doc = "Vector add."]
1849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
1850#[inline]
1851#[target_feature(enable = "neon")]
1852#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1853#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1854#[cfg_attr(
1855 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1856 assert_instr(add)
1857)]
1858#[cfg_attr(
1859 not(target_arch = "arm"),
1860 stable(feature = "neon_intrinsics", since = "1.59.0")
1861)]
1862#[cfg_attr(
1863 target_arch = "arm",
1864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1865)]
1866pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
1867 unsafe { simd_add(a, b) }
1868}
1869#[doc = "Vector add."]
1870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
1871#[inline]
1872#[target_feature(enable = "neon")]
1873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1874#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1875#[cfg_attr(
1876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1877 assert_instr(add)
1878)]
1879#[cfg_attr(
1880 not(target_arch = "arm"),
1881 stable(feature = "neon_intrinsics", since = "1.59.0")
1882)]
1883#[cfg_attr(
1884 target_arch = "arm",
1885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1886)]
1887pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
1888 unsafe { simd_add(a, b) }
1889}
1890#[doc = "Vector add."]
1891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
1892#[inline]
1893#[target_feature(enable = "neon")]
1894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1896#[cfg_attr(
1897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1898 assert_instr(add)
1899)]
1900#[cfg_attr(
1901 not(target_arch = "arm"),
1902 stable(feature = "neon_intrinsics", since = "1.59.0")
1903)]
1904#[cfg_attr(
1905 target_arch = "arm",
1906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1907)]
1908pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
1909 unsafe { simd_add(a, b) }
1910}
1911#[doc = "Vector add."]
1912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
1913#[inline]
1914#[target_feature(enable = "neon")]
1915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1917#[cfg_attr(
1918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1919 assert_instr(add)
1920)]
1921#[cfg_attr(
1922 not(target_arch = "arm"),
1923 stable(feature = "neon_intrinsics", since = "1.59.0")
1924)]
1925#[cfg_attr(
1926 target_arch = "arm",
1927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1928)]
1929pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
1930 unsafe { simd_add(a, b) }
1931}
1932#[doc = "Vector add."]
1933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
1934#[inline]
1935#[target_feature(enable = "neon")]
1936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1938#[cfg_attr(
1939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1940 assert_instr(add)
1941)]
1942#[cfg_attr(
1943 not(target_arch = "arm"),
1944 stable(feature = "neon_intrinsics", since = "1.59.0")
1945)]
1946#[cfg_attr(
1947 target_arch = "arm",
1948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1949)]
1950pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
1951 unsafe { simd_add(a, b) }
1952}
1953#[doc = "Vector add."]
1954#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
1955#[inline]
1956#[target_feature(enable = "neon")]
1957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1959#[cfg_attr(
1960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1961 assert_instr(add)
1962)]
1963#[cfg_attr(
1964 not(target_arch = "arm"),
1965 stable(feature = "neon_intrinsics", since = "1.59.0")
1966)]
1967#[cfg_attr(
1968 target_arch = "arm",
1969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1970)]
1971pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
1972 unsafe { simd_add(a, b) }
1973}
1974#[doc = "Vector add."]
1975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
1976#[inline]
1977#[target_feature(enable = "neon")]
1978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
1979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
1980#[cfg_attr(
1981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
1982 assert_instr(add)
1983)]
1984#[cfg_attr(
1985 not(target_arch = "arm"),
1986 stable(feature = "neon_intrinsics", since = "1.59.0")
1987)]
1988#[cfg_attr(
1989 target_arch = "arm",
1990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
1991)]
1992pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
1993 unsafe { simd_add(a, b) }
1994}
1995#[doc = "Bitwise exclusive OR"]
1996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
1997#[inline]
1998#[target_feature(enable = "neon")]
1999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2001#[cfg_attr(
2002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2003 assert_instr(nop)
2004)]
2005#[cfg_attr(
2006 not(target_arch = "arm"),
2007 stable(feature = "neon_intrinsics", since = "1.59.0")
2008)]
2009#[cfg_attr(
2010 target_arch = "arm",
2011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2012)]
2013pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
2014 unsafe { simd_xor(a, b) }
2015}
2016#[doc = "Bitwise exclusive OR"]
2017#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
2018#[inline]
2019#[target_feature(enable = "neon")]
2020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2022#[cfg_attr(
2023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2024 assert_instr(nop)
2025)]
2026#[cfg_attr(
2027 not(target_arch = "arm"),
2028 stable(feature = "neon_intrinsics", since = "1.59.0")
2029)]
2030#[cfg_attr(
2031 target_arch = "arm",
2032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2033)]
2034pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
2035 unsafe { simd_xor(a, b) }
2036}
2037#[doc = "Bitwise exclusive OR"]
2038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
2039#[inline]
2040#[target_feature(enable = "neon")]
2041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2043#[cfg_attr(
2044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2045 assert_instr(nop)
2046)]
2047#[cfg_attr(
2048 not(target_arch = "arm"),
2049 stable(feature = "neon_intrinsics", since = "1.59.0")
2050)]
2051#[cfg_attr(
2052 target_arch = "arm",
2053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2054)]
2055pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
2056 unsafe { simd_xor(a, b) }
2057}
2058#[doc = "Bitwise exclusive OR"]
2059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
2060#[inline]
2061#[target_feature(enable = "neon")]
2062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2064#[cfg_attr(
2065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2066 assert_instr(nop)
2067)]
2068#[cfg_attr(
2069 not(target_arch = "arm"),
2070 stable(feature = "neon_intrinsics", since = "1.59.0")
2071)]
2072#[cfg_attr(
2073 target_arch = "arm",
2074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2075)]
2076pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
2077 unsafe { simd_xor(a, b) }
2078}
2079#[doc = "Bitwise exclusive OR"]
2080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
2081#[inline]
2082#[target_feature(enable = "neon")]
2083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2084#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2085#[cfg_attr(
2086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2087 assert_instr(nop)
2088)]
2089#[cfg_attr(
2090 not(target_arch = "arm"),
2091 stable(feature = "neon_intrinsics", since = "1.59.0")
2092)]
2093#[cfg_attr(
2094 target_arch = "arm",
2095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2096)]
2097pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
2098 unsafe { simd_xor(a, b) }
2099}
2100#[doc = "Bitwise exclusive OR"]
2101#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
2102#[inline]
2103#[target_feature(enable = "neon")]
2104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2105#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2106#[cfg_attr(
2107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2108 assert_instr(nop)
2109)]
2110#[cfg_attr(
2111 not(target_arch = "arm"),
2112 stable(feature = "neon_intrinsics", since = "1.59.0")
2113)]
2114#[cfg_attr(
2115 target_arch = "arm",
2116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2117)]
2118pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
2119 unsafe { simd_xor(a, b) }
2120}
2121#[doc = "Add"]
2122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
2123#[inline]
2124#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
2125#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
2126#[cfg_attr(
2127 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2128 assert_instr(fadd)
2129)]
2130#[target_feature(enable = "neon,fp16")]
2131#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
2132pub fn vaddh_f16(a: f16, b: f16) -> f16 {
2133 a + b
2134}
2135#[doc = "Add returning High Narrow (high half)."]
2136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
2137#[inline]
2138#[target_feature(enable = "neon")]
2139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2141#[cfg_attr(
2142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2143 assert_instr(addhn2)
2144)]
2145#[cfg_attr(
2146 not(target_arch = "arm"),
2147 stable(feature = "neon_intrinsics", since = "1.59.0")
2148)]
2149#[cfg_attr(
2150 target_arch = "arm",
2151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2152)]
2153pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
2154 unsafe {
2155 let x = simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8)));
2156 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2157 }
2158}
2159#[doc = "Add returning High Narrow (high half)."]
2160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
2161#[inline]
2162#[target_feature(enable = "neon")]
2163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2165#[cfg_attr(
2166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2167 assert_instr(addhn2)
2168)]
2169#[cfg_attr(
2170 not(target_arch = "arm"),
2171 stable(feature = "neon_intrinsics", since = "1.59.0")
2172)]
2173#[cfg_attr(
2174 target_arch = "arm",
2175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2176)]
2177pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
2178 unsafe {
2179 let x = simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16)));
2180 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2181 }
2182}
2183#[doc = "Add returning High Narrow (high half)."]
2184#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
2185#[inline]
2186#[target_feature(enable = "neon")]
2187#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2188#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2189#[cfg_attr(
2190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2191 assert_instr(addhn2)
2192)]
2193#[cfg_attr(
2194 not(target_arch = "arm"),
2195 stable(feature = "neon_intrinsics", since = "1.59.0")
2196)]
2197#[cfg_attr(
2198 target_arch = "arm",
2199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2200)]
2201pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
2202 unsafe {
2203 let x = simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32)));
2204 simd_shuffle!(r, x, [0, 1, 2, 3])
2205 }
2206}
2207#[doc = "Add returning High Narrow (high half)."]
2208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
2209#[inline]
2210#[target_feature(enable = "neon")]
2211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2213#[cfg_attr(
2214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2215 assert_instr(addhn2)
2216)]
2217#[cfg_attr(
2218 not(target_arch = "arm"),
2219 stable(feature = "neon_intrinsics", since = "1.59.0")
2220)]
2221#[cfg_attr(
2222 target_arch = "arm",
2223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2224)]
2225pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t {
2226 unsafe {
2227 let x = simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8)));
2228 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
2229 }
2230}
2231#[doc = "Add returning High Narrow (high half)."]
2232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
2233#[inline]
2234#[target_feature(enable = "neon")]
2235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2237#[cfg_attr(
2238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2239 assert_instr(addhn2)
2240)]
2241#[cfg_attr(
2242 not(target_arch = "arm"),
2243 stable(feature = "neon_intrinsics", since = "1.59.0")
2244)]
2245#[cfg_attr(
2246 target_arch = "arm",
2247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2248)]
2249pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_t {
2250 unsafe {
2251 let x = simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16)));
2252 simd_shuffle!(r, x, [0, 1, 2, 3, 4, 5, 6, 7])
2253 }
2254}
2255#[doc = "Add returning High Narrow (high half)."]
2256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
2257#[inline]
2258#[target_feature(enable = "neon")]
2259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2261#[cfg_attr(
2262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2263 assert_instr(addhn2)
2264)]
2265#[cfg_attr(
2266 not(target_arch = "arm"),
2267 stable(feature = "neon_intrinsics", since = "1.59.0")
2268)]
2269#[cfg_attr(
2270 target_arch = "arm",
2271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2272)]
2273pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_t {
2274 unsafe {
2275 let x = simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32)));
2276 simd_shuffle!(r, x, [0, 1, 2, 3])
2277 }
2278}
2279#[doc = "Add returning High Narrow."]
2280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
2281#[inline]
2282#[target_feature(enable = "neon")]
2283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2285#[cfg_attr(
2286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2287 assert_instr(addhn)
2288)]
2289#[cfg_attr(
2290 not(target_arch = "arm"),
2291 stable(feature = "neon_intrinsics", since = "1.59.0")
2292)]
2293#[cfg_attr(
2294 target_arch = "arm",
2295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2296)]
2297pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
2298 unsafe { simd_cast(simd_shr(simd_add(a, b), int16x8_t::splat(8))) }
2299}
2300#[doc = "Add returning High Narrow."]
2301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
2302#[inline]
2303#[target_feature(enable = "neon")]
2304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2306#[cfg_attr(
2307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2308 assert_instr(addhn)
2309)]
2310#[cfg_attr(
2311 not(target_arch = "arm"),
2312 stable(feature = "neon_intrinsics", since = "1.59.0")
2313)]
2314#[cfg_attr(
2315 target_arch = "arm",
2316 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2317)]
2318pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
2319 unsafe { simd_cast(simd_shr(simd_add(a, b), int32x4_t::splat(16))) }
2320}
2321#[doc = "Add returning High Narrow."]
2322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
2323#[inline]
2324#[target_feature(enable = "neon")]
2325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2327#[cfg_attr(
2328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2329 assert_instr(addhn)
2330)]
2331#[cfg_attr(
2332 not(target_arch = "arm"),
2333 stable(feature = "neon_intrinsics", since = "1.59.0")
2334)]
2335#[cfg_attr(
2336 target_arch = "arm",
2337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2338)]
2339pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
2340 unsafe { simd_cast(simd_shr(simd_add(a, b), int64x2_t::splat(32))) }
2341}
2342#[doc = "Add returning High Narrow."]
2343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
2344#[inline]
2345#[target_feature(enable = "neon")]
2346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2348#[cfg_attr(
2349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2350 assert_instr(addhn)
2351)]
2352#[cfg_attr(
2353 not(target_arch = "arm"),
2354 stable(feature = "neon_intrinsics", since = "1.59.0")
2355)]
2356#[cfg_attr(
2357 target_arch = "arm",
2358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2359)]
2360pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
2361 unsafe { simd_cast(simd_shr(simd_add(a, b), uint16x8_t::splat(8))) }
2362}
2363#[doc = "Add returning High Narrow."]
2364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
2365#[inline]
2366#[target_feature(enable = "neon")]
2367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2369#[cfg_attr(
2370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2371 assert_instr(addhn)
2372)]
2373#[cfg_attr(
2374 not(target_arch = "arm"),
2375 stable(feature = "neon_intrinsics", since = "1.59.0")
2376)]
2377#[cfg_attr(
2378 target_arch = "arm",
2379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2380)]
2381pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
2382 unsafe { simd_cast(simd_shr(simd_add(a, b), uint32x4_t::splat(16))) }
2383}
2384#[doc = "Add returning High Narrow."]
2385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
2386#[inline]
2387#[target_feature(enable = "neon")]
2388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
2390#[cfg_attr(
2391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2392 assert_instr(addhn)
2393)]
2394#[cfg_attr(
2395 not(target_arch = "arm"),
2396 stable(feature = "neon_intrinsics", since = "1.59.0")
2397)]
2398#[cfg_attr(
2399 target_arch = "arm",
2400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2401)]
2402pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
2403 unsafe { simd_cast(simd_shr(simd_add(a, b), uint64x2_t::splat(32))) }
2404}
2405#[doc = "Signed Add Long (vector, high half)."]
2406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
2407#[inline]
2408#[target_feature(enable = "neon")]
2409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2411#[cfg_attr(
2412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2413 assert_instr(saddl2)
2414)]
2415#[cfg_attr(
2416 not(target_arch = "arm"),
2417 stable(feature = "neon_intrinsics", since = "1.59.0")
2418)]
2419#[cfg_attr(
2420 target_arch = "arm",
2421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2422)]
2423pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
2424 unsafe {
2425 let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2426 let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2427 let a: int32x4_t = simd_cast(a);
2428 let b: int32x4_t = simd_cast(b);
2429 simd_add(a, b)
2430 }
2431}
2432#[doc = "Signed Add Long (vector, high half)."]
2433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
2434#[inline]
2435#[target_feature(enable = "neon")]
2436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2438#[cfg_attr(
2439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2440 assert_instr(saddl2)
2441)]
2442#[cfg_attr(
2443 not(target_arch = "arm"),
2444 stable(feature = "neon_intrinsics", since = "1.59.0")
2445)]
2446#[cfg_attr(
2447 target_arch = "arm",
2448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2449)]
2450pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
2451 unsafe {
2452 let a: int32x2_t = simd_shuffle!(a, a, [2, 3]);
2453 let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2454 let a: int64x2_t = simd_cast(a);
2455 let b: int64x2_t = simd_cast(b);
2456 simd_add(a, b)
2457 }
2458}
2459#[doc = "Signed Add Long (vector, high half)."]
2460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
2461#[inline]
2462#[target_feature(enable = "neon")]
2463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2465#[cfg_attr(
2466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2467 assert_instr(saddl2)
2468)]
2469#[cfg_attr(
2470 not(target_arch = "arm"),
2471 stable(feature = "neon_intrinsics", since = "1.59.0")
2472)]
2473#[cfg_attr(
2474 target_arch = "arm",
2475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2476)]
2477pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
2478 unsafe {
2479 let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2480 let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2481 let a: int16x8_t = simd_cast(a);
2482 let b: int16x8_t = simd_cast(b);
2483 simd_add(a, b)
2484 }
2485}
2486#[doc = "Signed Add Long (vector, high half)."]
2487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
2488#[inline]
2489#[target_feature(enable = "neon")]
2490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2491#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2492#[cfg_attr(
2493 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2494 assert_instr(uaddl2)
2495)]
2496#[cfg_attr(
2497 not(target_arch = "arm"),
2498 stable(feature = "neon_intrinsics", since = "1.59.0")
2499)]
2500#[cfg_attr(
2501 target_arch = "arm",
2502 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2503)]
2504pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
2505 unsafe {
2506 let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
2507 let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2508 let a: uint32x4_t = simd_cast(a);
2509 let b: uint32x4_t = simd_cast(b);
2510 simd_add(a, b)
2511 }
2512}
2513#[doc = "Signed Add Long (vector, high half)."]
2514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
2515#[inline]
2516#[target_feature(enable = "neon")]
2517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2518#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2519#[cfg_attr(
2520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2521 assert_instr(uaddl2)
2522)]
2523#[cfg_attr(
2524 not(target_arch = "arm"),
2525 stable(feature = "neon_intrinsics", since = "1.59.0")
2526)]
2527#[cfg_attr(
2528 target_arch = "arm",
2529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2530)]
2531pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
2532 unsafe {
2533 let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
2534 let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2535 let a: uint64x2_t = simd_cast(a);
2536 let b: uint64x2_t = simd_cast(b);
2537 simd_add(a, b)
2538 }
2539}
2540#[doc = "Signed Add Long (vector, high half)."]
2541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
2542#[inline]
2543#[target_feature(enable = "neon")]
2544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2546#[cfg_attr(
2547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2548 assert_instr(uaddl2)
2549)]
2550#[cfg_attr(
2551 not(target_arch = "arm"),
2552 stable(feature = "neon_intrinsics", since = "1.59.0")
2553)]
2554#[cfg_attr(
2555 target_arch = "arm",
2556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2557)]
2558pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
2559 unsafe {
2560 let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
2561 let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2562 let a: uint16x8_t = simd_cast(a);
2563 let b: uint16x8_t = simd_cast(b);
2564 simd_add(a, b)
2565 }
2566}
2567#[doc = "Add Long (vector)."]
2568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
2569#[inline]
2570#[target_feature(enable = "neon")]
2571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2573#[cfg_attr(
2574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2575 assert_instr(saddl)
2576)]
2577#[cfg_attr(
2578 not(target_arch = "arm"),
2579 stable(feature = "neon_intrinsics", since = "1.59.0")
2580)]
2581#[cfg_attr(
2582 target_arch = "arm",
2583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2584)]
2585pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
2586 unsafe {
2587 let a: int32x4_t = simd_cast(a);
2588 let b: int32x4_t = simd_cast(b);
2589 simd_add(a, b)
2590 }
2591}
2592#[doc = "Add Long (vector)."]
2593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
2594#[inline]
2595#[target_feature(enable = "neon")]
2596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2597#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2598#[cfg_attr(
2599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2600 assert_instr(saddl)
2601)]
2602#[cfg_attr(
2603 not(target_arch = "arm"),
2604 stable(feature = "neon_intrinsics", since = "1.59.0")
2605)]
2606#[cfg_attr(
2607 target_arch = "arm",
2608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2609)]
2610pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
2611 unsafe {
2612 let a: int64x2_t = simd_cast(a);
2613 let b: int64x2_t = simd_cast(b);
2614 simd_add(a, b)
2615 }
2616}
2617#[doc = "Add Long (vector)."]
2618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
2619#[inline]
2620#[target_feature(enable = "neon")]
2621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2623#[cfg_attr(
2624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2625 assert_instr(saddl)
2626)]
2627#[cfg_attr(
2628 not(target_arch = "arm"),
2629 stable(feature = "neon_intrinsics", since = "1.59.0")
2630)]
2631#[cfg_attr(
2632 target_arch = "arm",
2633 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2634)]
2635pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
2636 unsafe {
2637 let a: int16x8_t = simd_cast(a);
2638 let b: int16x8_t = simd_cast(b);
2639 simd_add(a, b)
2640 }
2641}
2642#[doc = "Add Long (vector)."]
2643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
2644#[inline]
2645#[target_feature(enable = "neon")]
2646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2648#[cfg_attr(
2649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2650 assert_instr(uaddl)
2651)]
2652#[cfg_attr(
2653 not(target_arch = "arm"),
2654 stable(feature = "neon_intrinsics", since = "1.59.0")
2655)]
2656#[cfg_attr(
2657 target_arch = "arm",
2658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2659)]
2660pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
2661 unsafe {
2662 let a: uint32x4_t = simd_cast(a);
2663 let b: uint32x4_t = simd_cast(b);
2664 simd_add(a, b)
2665 }
2666}
2667#[doc = "Add Long (vector)."]
2668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
2669#[inline]
2670#[target_feature(enable = "neon")]
2671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2673#[cfg_attr(
2674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2675 assert_instr(uaddl)
2676)]
2677#[cfg_attr(
2678 not(target_arch = "arm"),
2679 stable(feature = "neon_intrinsics", since = "1.59.0")
2680)]
2681#[cfg_attr(
2682 target_arch = "arm",
2683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2684)]
2685pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
2686 unsafe {
2687 let a: uint64x2_t = simd_cast(a);
2688 let b: uint64x2_t = simd_cast(b);
2689 simd_add(a, b)
2690 }
2691}
2692#[doc = "Add Long (vector)."]
2693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
2694#[inline]
2695#[target_feature(enable = "neon")]
2696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
2698#[cfg_attr(
2699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2700 assert_instr(uaddl)
2701)]
2702#[cfg_attr(
2703 not(target_arch = "arm"),
2704 stable(feature = "neon_intrinsics", since = "1.59.0")
2705)]
2706#[cfg_attr(
2707 target_arch = "arm",
2708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2709)]
2710pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
2711 unsafe {
2712 let a: uint16x8_t = simd_cast(a);
2713 let b: uint16x8_t = simd_cast(b);
2714 simd_add(a, b)
2715 }
2716}
2717#[doc = "Bitwise exclusive OR"]
2718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
2719#[inline]
2720#[target_feature(enable = "neon")]
2721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
2723#[cfg_attr(
2724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2725 assert_instr(nop)
2726)]
2727#[cfg_attr(
2728 not(target_arch = "arm"),
2729 stable(feature = "neon_intrinsics", since = "1.59.0")
2730)]
2731#[cfg_attr(
2732 target_arch = "arm",
2733 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2734)]
2735pub fn vaddq_p128(a: p128, b: p128) -> p128 {
2736 a ^ b
2737}
2738#[doc = "Add Wide (high half)."]
2739#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
2740#[inline]
2741#[target_feature(enable = "neon")]
2742#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2743#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2744#[cfg_attr(
2745 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2746 assert_instr(saddw2)
2747)]
2748#[cfg_attr(
2749 not(target_arch = "arm"),
2750 stable(feature = "neon_intrinsics", since = "1.59.0")
2751)]
2752#[cfg_attr(
2753 target_arch = "arm",
2754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2755)]
2756pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
2757 unsafe {
2758 let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2759 let b: int32x4_t = simd_cast(b);
2760 simd_add(a, b)
2761 }
2762}
2763#[doc = "Add Wide (high half)."]
2764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
2765#[inline]
2766#[target_feature(enable = "neon")]
2767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2768#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2769#[cfg_attr(
2770 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2771 assert_instr(saddw2)
2772)]
2773#[cfg_attr(
2774 not(target_arch = "arm"),
2775 stable(feature = "neon_intrinsics", since = "1.59.0")
2776)]
2777#[cfg_attr(
2778 target_arch = "arm",
2779 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2780)]
2781pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
2782 unsafe {
2783 let b: int32x2_t = simd_shuffle!(b, b, [2, 3]);
2784 let b: int64x2_t = simd_cast(b);
2785 simd_add(a, b)
2786 }
2787}
2788#[doc = "Add Wide (high half)."]
2789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
2790#[inline]
2791#[target_feature(enable = "neon")]
2792#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2793#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2794#[cfg_attr(
2795 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2796 assert_instr(saddw2)
2797)]
2798#[cfg_attr(
2799 not(target_arch = "arm"),
2800 stable(feature = "neon_intrinsics", since = "1.59.0")
2801)]
2802#[cfg_attr(
2803 target_arch = "arm",
2804 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2805)]
2806pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
2807 unsafe {
2808 let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2809 let b: int16x8_t = simd_cast(b);
2810 simd_add(a, b)
2811 }
2812}
2813#[doc = "Add Wide (high half)."]
2814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
2815#[inline]
2816#[target_feature(enable = "neon")]
2817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2819#[cfg_attr(
2820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2821 assert_instr(uaddw2)
2822)]
2823#[cfg_attr(
2824 not(target_arch = "arm"),
2825 stable(feature = "neon_intrinsics", since = "1.59.0")
2826)]
2827#[cfg_attr(
2828 target_arch = "arm",
2829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2830)]
2831pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
2832 unsafe {
2833 let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
2834 let b: uint32x4_t = simd_cast(b);
2835 simd_add(a, b)
2836 }
2837}
2838#[doc = "Add Wide (high half)."]
2839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
2840#[inline]
2841#[target_feature(enable = "neon")]
2842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2844#[cfg_attr(
2845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2846 assert_instr(uaddw2)
2847)]
2848#[cfg_attr(
2849 not(target_arch = "arm"),
2850 stable(feature = "neon_intrinsics", since = "1.59.0")
2851)]
2852#[cfg_attr(
2853 target_arch = "arm",
2854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2855)]
2856pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
2857 unsafe {
2858 let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
2859 let b: uint64x2_t = simd_cast(b);
2860 simd_add(a, b)
2861 }
2862}
2863#[doc = "Add Wide (high half)."]
2864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
2865#[inline]
2866#[target_feature(enable = "neon")]
2867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2869#[cfg_attr(
2870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2871 assert_instr(uaddw2)
2872)]
2873#[cfg_attr(
2874 not(target_arch = "arm"),
2875 stable(feature = "neon_intrinsics", since = "1.59.0")
2876)]
2877#[cfg_attr(
2878 target_arch = "arm",
2879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2880)]
2881pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
2882 unsafe {
2883 let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
2884 let b: uint16x8_t = simd_cast(b);
2885 simd_add(a, b)
2886 }
2887}
2888#[doc = "Add Wide"]
2889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
2890#[inline]
2891#[target_feature(enable = "neon")]
2892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2894#[cfg_attr(
2895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2896 assert_instr(saddw)
2897)]
2898#[cfg_attr(
2899 not(target_arch = "arm"),
2900 stable(feature = "neon_intrinsics", since = "1.59.0")
2901)]
2902#[cfg_attr(
2903 target_arch = "arm",
2904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2905)]
2906pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
2907 unsafe {
2908 let b: int32x4_t = simd_cast(b);
2909 simd_add(a, b)
2910 }
2911}
2912#[doc = "Add Wide"]
2913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
2914#[inline]
2915#[target_feature(enable = "neon")]
2916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2918#[cfg_attr(
2919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2920 assert_instr(saddw)
2921)]
2922#[cfg_attr(
2923 not(target_arch = "arm"),
2924 stable(feature = "neon_intrinsics", since = "1.59.0")
2925)]
2926#[cfg_attr(
2927 target_arch = "arm",
2928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2929)]
2930pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
2931 unsafe {
2932 let b: int64x2_t = simd_cast(b);
2933 simd_add(a, b)
2934 }
2935}
2936#[doc = "Add Wide"]
2937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
2938#[inline]
2939#[target_feature(enable = "neon")]
2940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2942#[cfg_attr(
2943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2944 assert_instr(saddw)
2945)]
2946#[cfg_attr(
2947 not(target_arch = "arm"),
2948 stable(feature = "neon_intrinsics", since = "1.59.0")
2949)]
2950#[cfg_attr(
2951 target_arch = "arm",
2952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2953)]
2954pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
2955 unsafe {
2956 let b: int16x8_t = simd_cast(b);
2957 simd_add(a, b)
2958 }
2959}
2960#[doc = "Add Wide"]
2961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
2962#[inline]
2963#[target_feature(enable = "neon")]
2964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2965#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2966#[cfg_attr(
2967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2968 assert_instr(uaddw)
2969)]
2970#[cfg_attr(
2971 not(target_arch = "arm"),
2972 stable(feature = "neon_intrinsics", since = "1.59.0")
2973)]
2974#[cfg_attr(
2975 target_arch = "arm",
2976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
2977)]
2978pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
2979 unsafe {
2980 let b: uint32x4_t = simd_cast(b);
2981 simd_add(a, b)
2982 }
2983}
2984#[doc = "Add Wide"]
2985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
2986#[inline]
2987#[target_feature(enable = "neon")]
2988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2989#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
2990#[cfg_attr(
2991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
2992 assert_instr(uaddw)
2993)]
2994#[cfg_attr(
2995 not(target_arch = "arm"),
2996 stable(feature = "neon_intrinsics", since = "1.59.0")
2997)]
2998#[cfg_attr(
2999 target_arch = "arm",
3000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3001)]
3002pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
3003 unsafe {
3004 let b: uint64x2_t = simd_cast(b);
3005 simd_add(a, b)
3006 }
3007}
3008#[doc = "Add Wide"]
3009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
3010#[inline]
3011#[target_feature(enable = "neon")]
3012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
3014#[cfg_attr(
3015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3016 assert_instr(uaddw)
3017)]
3018#[cfg_attr(
3019 not(target_arch = "arm"),
3020 stable(feature = "neon_intrinsics", since = "1.59.0")
3021)]
3022#[cfg_attr(
3023 target_arch = "arm",
3024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3025)]
3026pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
3027 unsafe {
3028 let b: uint16x8_t = simd_cast(b);
3029 simd_add(a, b)
3030 }
3031}
3032#[doc = "AES single round encryption."]
3033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
3034#[inline]
3035#[target_feature(enable = "aes")]
3036#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3037#[cfg_attr(test, assert_instr(aesd))]
3038#[cfg_attr(
3039 target_arch = "arm",
3040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3041)]
3042#[cfg_attr(
3043 not(target_arch = "arm"),
3044 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3045)]
3046pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3047 unsafe extern "unadjusted" {
3048 #[cfg_attr(
3049 any(target_arch = "aarch64", target_arch = "arm64ec"),
3050 link_name = "llvm.aarch64.crypto.aesd"
3051 )]
3052 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
3053 fn _vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3054 }
3055 unsafe { _vaesdq_u8(data, key) }
3056}
3057#[doc = "AES single round encryption."]
3058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
3059#[inline]
3060#[target_feature(enable = "aes")]
3061#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3062#[cfg_attr(test, assert_instr(aese))]
3063#[cfg_attr(
3064 target_arch = "arm",
3065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3066)]
3067#[cfg_attr(
3068 not(target_arch = "arm"),
3069 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3070)]
3071pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
3072 unsafe extern "unadjusted" {
3073 #[cfg_attr(
3074 any(target_arch = "aarch64", target_arch = "arm64ec"),
3075 link_name = "llvm.aarch64.crypto.aese"
3076 )]
3077 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
3078 fn _vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
3079 }
3080 unsafe { _vaeseq_u8(data, key) }
3081}
3082#[doc = "AES inverse mix columns."]
3083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
3084#[inline]
3085#[target_feature(enable = "aes")]
3086#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3087#[cfg_attr(test, assert_instr(aesimc))]
3088#[cfg_attr(
3089 target_arch = "arm",
3090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3091)]
3092#[cfg_attr(
3093 not(target_arch = "arm"),
3094 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3095)]
3096pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
3097 unsafe extern "unadjusted" {
3098 #[cfg_attr(
3099 any(target_arch = "aarch64", target_arch = "arm64ec"),
3100 link_name = "llvm.aarch64.crypto.aesimc"
3101 )]
3102 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
3103 fn _vaesimcq_u8(data: uint8x16_t) -> uint8x16_t;
3104 }
3105 unsafe { _vaesimcq_u8(data) }
3106}
3107#[doc = "AES mix columns."]
3108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
3109#[inline]
3110#[target_feature(enable = "aes")]
3111#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
3112#[cfg_attr(test, assert_instr(aesmc))]
3113#[cfg_attr(
3114 target_arch = "arm",
3115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3116)]
3117#[cfg_attr(
3118 not(target_arch = "arm"),
3119 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
3120)]
3121pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
3122 unsafe extern "unadjusted" {
3123 #[cfg_attr(
3124 any(target_arch = "aarch64", target_arch = "arm64ec"),
3125 link_name = "llvm.aarch64.crypto.aesmc"
3126 )]
3127 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
3128 fn _vaesmcq_u8(data: uint8x16_t) -> uint8x16_t;
3129 }
3130 unsafe { _vaesmcq_u8(data) }
3131}
3132#[doc = "Vector bitwise and"]
3133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
3134#[inline]
3135#[target_feature(enable = "neon")]
3136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3138#[cfg_attr(
3139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3140 assert_instr(and)
3141)]
3142#[cfg_attr(
3143 not(target_arch = "arm"),
3144 stable(feature = "neon_intrinsics", since = "1.59.0")
3145)]
3146#[cfg_attr(
3147 target_arch = "arm",
3148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3149)]
3150pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3151 unsafe { simd_and(a, b) }
3152}
3153#[doc = "Vector bitwise and"]
3154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
3155#[inline]
3156#[target_feature(enable = "neon")]
3157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3159#[cfg_attr(
3160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3161 assert_instr(and)
3162)]
3163#[cfg_attr(
3164 not(target_arch = "arm"),
3165 stable(feature = "neon_intrinsics", since = "1.59.0")
3166)]
3167#[cfg_attr(
3168 target_arch = "arm",
3169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3170)]
3171pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3172 unsafe { simd_and(a, b) }
3173}
3174#[doc = "Vector bitwise and"]
3175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
3176#[inline]
3177#[target_feature(enable = "neon")]
3178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3180#[cfg_attr(
3181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3182 assert_instr(and)
3183)]
3184#[cfg_attr(
3185 not(target_arch = "arm"),
3186 stable(feature = "neon_intrinsics", since = "1.59.0")
3187)]
3188#[cfg_attr(
3189 target_arch = "arm",
3190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3191)]
3192pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3193 unsafe { simd_and(a, b) }
3194}
3195#[doc = "Vector bitwise and"]
3196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
3197#[inline]
3198#[target_feature(enable = "neon")]
3199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3201#[cfg_attr(
3202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3203 assert_instr(and)
3204)]
3205#[cfg_attr(
3206 not(target_arch = "arm"),
3207 stable(feature = "neon_intrinsics", since = "1.59.0")
3208)]
3209#[cfg_attr(
3210 target_arch = "arm",
3211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3212)]
3213pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3214 unsafe { simd_and(a, b) }
3215}
3216#[doc = "Vector bitwise and"]
3217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
3218#[inline]
3219#[target_feature(enable = "neon")]
3220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3222#[cfg_attr(
3223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3224 assert_instr(and)
3225)]
3226#[cfg_attr(
3227 not(target_arch = "arm"),
3228 stable(feature = "neon_intrinsics", since = "1.59.0")
3229)]
3230#[cfg_attr(
3231 target_arch = "arm",
3232 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3233)]
3234pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3235 unsafe { simd_and(a, b) }
3236}
3237#[doc = "Vector bitwise and"]
3238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
3239#[inline]
3240#[target_feature(enable = "neon")]
3241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3243#[cfg_attr(
3244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3245 assert_instr(and)
3246)]
3247#[cfg_attr(
3248 not(target_arch = "arm"),
3249 stable(feature = "neon_intrinsics", since = "1.59.0")
3250)]
3251#[cfg_attr(
3252 target_arch = "arm",
3253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3254)]
3255pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3256 unsafe { simd_and(a, b) }
3257}
3258#[doc = "Vector bitwise and"]
3259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
3260#[inline]
3261#[target_feature(enable = "neon")]
3262#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3263#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3264#[cfg_attr(
3265 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3266 assert_instr(and)
3267)]
3268#[cfg_attr(
3269 not(target_arch = "arm"),
3270 stable(feature = "neon_intrinsics", since = "1.59.0")
3271)]
3272#[cfg_attr(
3273 target_arch = "arm",
3274 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3275)]
3276pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3277 unsafe { simd_and(a, b) }
3278}
3279#[doc = "Vector bitwise and"]
3280#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
3281#[inline]
3282#[target_feature(enable = "neon")]
3283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3285#[cfg_attr(
3286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3287 assert_instr(and)
3288)]
3289#[cfg_attr(
3290 not(target_arch = "arm"),
3291 stable(feature = "neon_intrinsics", since = "1.59.0")
3292)]
3293#[cfg_attr(
3294 target_arch = "arm",
3295 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3296)]
3297pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3298 unsafe { simd_and(a, b) }
3299}
3300#[doc = "Vector bitwise and"]
3301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
3302#[inline]
3303#[target_feature(enable = "neon")]
3304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3306#[cfg_attr(
3307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3308 assert_instr(and)
3309)]
3310#[cfg_attr(
3311 not(target_arch = "arm"),
3312 stable(feature = "neon_intrinsics", since = "1.59.0")
3313)]
3314#[cfg_attr(
3315 target_arch = "arm",
3316 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3317)]
3318pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3319 unsafe { simd_and(a, b) }
3320}
3321#[doc = "Vector bitwise and"]
3322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
3323#[inline]
3324#[target_feature(enable = "neon")]
3325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3327#[cfg_attr(
3328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3329 assert_instr(and)
3330)]
3331#[cfg_attr(
3332 not(target_arch = "arm"),
3333 stable(feature = "neon_intrinsics", since = "1.59.0")
3334)]
3335#[cfg_attr(
3336 target_arch = "arm",
3337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3338)]
3339pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3340 unsafe { simd_and(a, b) }
3341}
3342#[doc = "Vector bitwise and"]
3343#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
3344#[inline]
3345#[target_feature(enable = "neon")]
3346#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3347#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3348#[cfg_attr(
3349 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3350 assert_instr(and)
3351)]
3352#[cfg_attr(
3353 not(target_arch = "arm"),
3354 stable(feature = "neon_intrinsics", since = "1.59.0")
3355)]
3356#[cfg_attr(
3357 target_arch = "arm",
3358 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3359)]
3360pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3361 unsafe { simd_and(a, b) }
3362}
3363#[doc = "Vector bitwise and"]
3364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
3365#[inline]
3366#[target_feature(enable = "neon")]
3367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3369#[cfg_attr(
3370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3371 assert_instr(and)
3372)]
3373#[cfg_attr(
3374 not(target_arch = "arm"),
3375 stable(feature = "neon_intrinsics", since = "1.59.0")
3376)]
3377#[cfg_attr(
3378 target_arch = "arm",
3379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3380)]
3381pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3382 unsafe { simd_and(a, b) }
3383}
3384#[doc = "Vector bitwise and"]
3385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
3386#[inline]
3387#[target_feature(enable = "neon")]
3388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3390#[cfg_attr(
3391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3392 assert_instr(and)
3393)]
3394#[cfg_attr(
3395 not(target_arch = "arm"),
3396 stable(feature = "neon_intrinsics", since = "1.59.0")
3397)]
3398#[cfg_attr(
3399 target_arch = "arm",
3400 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3401)]
3402pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3403 unsafe { simd_and(a, b) }
3404}
3405#[doc = "Vector bitwise and"]
3406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
3407#[inline]
3408#[target_feature(enable = "neon")]
3409#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3410#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3411#[cfg_attr(
3412 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3413 assert_instr(and)
3414)]
3415#[cfg_attr(
3416 not(target_arch = "arm"),
3417 stable(feature = "neon_intrinsics", since = "1.59.0")
3418)]
3419#[cfg_attr(
3420 target_arch = "arm",
3421 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3422)]
3423pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3424 unsafe { simd_and(a, b) }
3425}
3426#[doc = "Vector bitwise and"]
3427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
3428#[inline]
3429#[target_feature(enable = "neon")]
3430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3431#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3432#[cfg_attr(
3433 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3434 assert_instr(and)
3435)]
3436#[cfg_attr(
3437 not(target_arch = "arm"),
3438 stable(feature = "neon_intrinsics", since = "1.59.0")
3439)]
3440#[cfg_attr(
3441 target_arch = "arm",
3442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3443)]
3444pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3445 unsafe { simd_and(a, b) }
3446}
3447#[doc = "Vector bitwise and"]
3448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
3449#[inline]
3450#[target_feature(enable = "neon")]
3451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
3453#[cfg_attr(
3454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3455 assert_instr(and)
3456)]
3457#[cfg_attr(
3458 not(target_arch = "arm"),
3459 stable(feature = "neon_intrinsics", since = "1.59.0")
3460)]
3461#[cfg_attr(
3462 target_arch = "arm",
3463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3464)]
3465pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3466 unsafe { simd_and(a, b) }
3467}
3468#[doc = "Vector bitwise bit clear."]
3469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
3470#[inline]
3471#[target_feature(enable = "neon")]
3472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3474#[cfg_attr(
3475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3476 assert_instr(bic)
3477)]
3478#[cfg_attr(
3479 not(target_arch = "arm"),
3480 stable(feature = "neon_intrinsics", since = "1.59.0")
3481)]
3482#[cfg_attr(
3483 target_arch = "arm",
3484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3485)]
3486pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
3487 let c = int16x4_t::splat(-1);
3488 unsafe { simd_and(simd_xor(b, c), a) }
3489}
3490#[doc = "Vector bitwise bit clear."]
3491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
3492#[inline]
3493#[target_feature(enable = "neon")]
3494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3496#[cfg_attr(
3497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3498 assert_instr(bic)
3499)]
3500#[cfg_attr(
3501 not(target_arch = "arm"),
3502 stable(feature = "neon_intrinsics", since = "1.59.0")
3503)]
3504#[cfg_attr(
3505 target_arch = "arm",
3506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3507)]
3508pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
3509 let c = int32x2_t::splat(-1);
3510 unsafe { simd_and(simd_xor(b, c), a) }
3511}
3512#[doc = "Vector bitwise bit clear."]
3513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
3514#[inline]
3515#[target_feature(enable = "neon")]
3516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3518#[cfg_attr(
3519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3520 assert_instr(bic)
3521)]
3522#[cfg_attr(
3523 not(target_arch = "arm"),
3524 stable(feature = "neon_intrinsics", since = "1.59.0")
3525)]
3526#[cfg_attr(
3527 target_arch = "arm",
3528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3529)]
3530pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
3531 let c = int64x1_t::splat(-1);
3532 unsafe { simd_and(simd_xor(b, c), a) }
3533}
3534#[doc = "Vector bitwise bit clear."]
3535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
3536#[inline]
3537#[target_feature(enable = "neon")]
3538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3540#[cfg_attr(
3541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3542 assert_instr(bic)
3543)]
3544#[cfg_attr(
3545 not(target_arch = "arm"),
3546 stable(feature = "neon_intrinsics", since = "1.59.0")
3547)]
3548#[cfg_attr(
3549 target_arch = "arm",
3550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3551)]
3552pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
3553 let c = int8x8_t::splat(-1);
3554 unsafe { simd_and(simd_xor(b, c), a) }
3555}
3556#[doc = "Vector bitwise bit clear."]
3557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
3558#[inline]
3559#[target_feature(enable = "neon")]
3560#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3561#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3562#[cfg_attr(
3563 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3564 assert_instr(bic)
3565)]
3566#[cfg_attr(
3567 not(target_arch = "arm"),
3568 stable(feature = "neon_intrinsics", since = "1.59.0")
3569)]
3570#[cfg_attr(
3571 target_arch = "arm",
3572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3573)]
3574pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
3575 let c = int16x8_t::splat(-1);
3576 unsafe { simd_and(simd_xor(b, c), a) }
3577}
3578#[doc = "Vector bitwise bit clear."]
3579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
3580#[inline]
3581#[target_feature(enable = "neon")]
3582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3584#[cfg_attr(
3585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3586 assert_instr(bic)
3587)]
3588#[cfg_attr(
3589 not(target_arch = "arm"),
3590 stable(feature = "neon_intrinsics", since = "1.59.0")
3591)]
3592#[cfg_attr(
3593 target_arch = "arm",
3594 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3595)]
3596pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
3597 let c = int32x4_t::splat(-1);
3598 unsafe { simd_and(simd_xor(b, c), a) }
3599}
3600#[doc = "Vector bitwise bit clear."]
3601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
3602#[inline]
3603#[target_feature(enable = "neon")]
3604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3605#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3606#[cfg_attr(
3607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3608 assert_instr(bic)
3609)]
3610#[cfg_attr(
3611 not(target_arch = "arm"),
3612 stable(feature = "neon_intrinsics", since = "1.59.0")
3613)]
3614#[cfg_attr(
3615 target_arch = "arm",
3616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3617)]
3618pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
3619 let c = int64x2_t::splat(-1);
3620 unsafe { simd_and(simd_xor(b, c), a) }
3621}
3622#[doc = "Vector bitwise bit clear."]
3623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
3624#[inline]
3625#[target_feature(enable = "neon")]
3626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3628#[cfg_attr(
3629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3630 assert_instr(bic)
3631)]
3632#[cfg_attr(
3633 not(target_arch = "arm"),
3634 stable(feature = "neon_intrinsics", since = "1.59.0")
3635)]
3636#[cfg_attr(
3637 target_arch = "arm",
3638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3639)]
3640pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
3641 let c = int8x16_t::splat(-1);
3642 unsafe { simd_and(simd_xor(b, c), a) }
3643}
3644#[doc = "Vector bitwise bit clear."]
3645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
3646#[inline]
3647#[target_feature(enable = "neon")]
3648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3649#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3650#[cfg_attr(
3651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3652 assert_instr(bic)
3653)]
3654#[cfg_attr(
3655 not(target_arch = "arm"),
3656 stable(feature = "neon_intrinsics", since = "1.59.0")
3657)]
3658#[cfg_attr(
3659 target_arch = "arm",
3660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3661)]
3662pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
3663 let c = int16x4_t::splat(-1);
3664 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3665}
3666#[doc = "Vector bitwise bit clear."]
3667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
3668#[inline]
3669#[target_feature(enable = "neon")]
3670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3672#[cfg_attr(
3673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3674 assert_instr(bic)
3675)]
3676#[cfg_attr(
3677 not(target_arch = "arm"),
3678 stable(feature = "neon_intrinsics", since = "1.59.0")
3679)]
3680#[cfg_attr(
3681 target_arch = "arm",
3682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3683)]
3684pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
3685 let c = int32x2_t::splat(-1);
3686 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3687}
3688#[doc = "Vector bitwise bit clear."]
3689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
3690#[inline]
3691#[target_feature(enable = "neon")]
3692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3694#[cfg_attr(
3695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3696 assert_instr(bic)
3697)]
3698#[cfg_attr(
3699 not(target_arch = "arm"),
3700 stable(feature = "neon_intrinsics", since = "1.59.0")
3701)]
3702#[cfg_attr(
3703 target_arch = "arm",
3704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3705)]
3706pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
3707 let c = int64x1_t::splat(-1);
3708 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3709}
3710#[doc = "Vector bitwise bit clear."]
3711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
3712#[inline]
3713#[target_feature(enable = "neon")]
3714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3715#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3716#[cfg_attr(
3717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3718 assert_instr(bic)
3719)]
3720#[cfg_attr(
3721 not(target_arch = "arm"),
3722 stable(feature = "neon_intrinsics", since = "1.59.0")
3723)]
3724#[cfg_attr(
3725 target_arch = "arm",
3726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3727)]
3728pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
3729 let c = int8x8_t::splat(-1);
3730 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3731}
3732#[doc = "Vector bitwise bit clear."]
3733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
3734#[inline]
3735#[target_feature(enable = "neon")]
3736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3738#[cfg_attr(
3739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3740 assert_instr(bic)
3741)]
3742#[cfg_attr(
3743 not(target_arch = "arm"),
3744 stable(feature = "neon_intrinsics", since = "1.59.0")
3745)]
3746#[cfg_attr(
3747 target_arch = "arm",
3748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3749)]
3750pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
3751 let c = int16x8_t::splat(-1);
3752 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3753}
3754#[doc = "Vector bitwise bit clear."]
3755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
3756#[inline]
3757#[target_feature(enable = "neon")]
3758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3760#[cfg_attr(
3761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3762 assert_instr(bic)
3763)]
3764#[cfg_attr(
3765 not(target_arch = "arm"),
3766 stable(feature = "neon_intrinsics", since = "1.59.0")
3767)]
3768#[cfg_attr(
3769 target_arch = "arm",
3770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3771)]
3772pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
3773 let c = int32x4_t::splat(-1);
3774 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3775}
3776#[doc = "Vector bitwise bit clear."]
3777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
3778#[inline]
3779#[target_feature(enable = "neon")]
3780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3782#[cfg_attr(
3783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3784 assert_instr(bic)
3785)]
3786#[cfg_attr(
3787 not(target_arch = "arm"),
3788 stable(feature = "neon_intrinsics", since = "1.59.0")
3789)]
3790#[cfg_attr(
3791 target_arch = "arm",
3792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3793)]
3794pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
3795 let c = int64x2_t::splat(-1);
3796 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3797}
3798#[doc = "Vector bitwise bit clear."]
3799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
3800#[inline]
3801#[target_feature(enable = "neon")]
3802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
3804#[cfg_attr(
3805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3806 assert_instr(bic)
3807)]
3808#[cfg_attr(
3809 not(target_arch = "arm"),
3810 stable(feature = "neon_intrinsics", since = "1.59.0")
3811)]
3812#[cfg_attr(
3813 target_arch = "arm",
3814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3815)]
3816pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
3817 let c = int8x16_t::splat(-1);
3818 unsafe { simd_and(simd_xor(b, transmute(c)), a) }
3819}
3820#[doc = "Bitwise Select."]
3821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
3822#[inline]
3823#[target_feature(enable = "neon,fp16")]
3824#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3825#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3826#[cfg_attr(
3827 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3828 assert_instr(bsl)
3829)]
3830#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3831pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
3832 let not = int16x4_t::splat(-1);
3833 unsafe {
3834 transmute(simd_or(
3835 simd_and(a, transmute(b)),
3836 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3837 ))
3838 }
3839}
3840#[doc = "Bitwise Select."]
3841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
3842#[inline]
3843#[target_feature(enable = "neon,fp16")]
3844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3845#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3846#[cfg_attr(
3847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3848 assert_instr(bsl)
3849)]
3850#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
3851pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
3852 let not = int16x8_t::splat(-1);
3853 unsafe {
3854 transmute(simd_or(
3855 simd_and(a, transmute(b)),
3856 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3857 ))
3858 }
3859}
3860#[doc = "Bitwise Select."]
3861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
3862#[inline]
3863#[target_feature(enable = "neon")]
3864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3866#[cfg_attr(
3867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3868 assert_instr(bsl)
3869)]
3870#[cfg_attr(
3871 not(target_arch = "arm"),
3872 stable(feature = "neon_intrinsics", since = "1.59.0")
3873)]
3874#[cfg_attr(
3875 target_arch = "arm",
3876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3877)]
3878pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
3879 let not = int32x2_t::splat(-1);
3880 unsafe {
3881 transmute(simd_or(
3882 simd_and(a, transmute(b)),
3883 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3884 ))
3885 }
3886}
3887#[doc = "Bitwise Select."]
3888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
3889#[inline]
3890#[target_feature(enable = "neon")]
3891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3893#[cfg_attr(
3894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3895 assert_instr(bsl)
3896)]
3897#[cfg_attr(
3898 not(target_arch = "arm"),
3899 stable(feature = "neon_intrinsics", since = "1.59.0")
3900)]
3901#[cfg_attr(
3902 target_arch = "arm",
3903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3904)]
3905pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
3906 let not = int16x4_t::splat(-1);
3907 unsafe {
3908 transmute(simd_or(
3909 simd_and(a, transmute(b)),
3910 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3911 ))
3912 }
3913}
3914#[doc = "Bitwise Select."]
3915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
3916#[inline]
3917#[target_feature(enable = "neon")]
3918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3920#[cfg_attr(
3921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3922 assert_instr(bsl)
3923)]
3924#[cfg_attr(
3925 not(target_arch = "arm"),
3926 stable(feature = "neon_intrinsics", since = "1.59.0")
3927)]
3928#[cfg_attr(
3929 target_arch = "arm",
3930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3931)]
3932pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
3933 let not = int8x8_t::splat(-1);
3934 unsafe {
3935 transmute(simd_or(
3936 simd_and(a, transmute(b)),
3937 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3938 ))
3939 }
3940}
3941#[doc = "Bitwise Select."]
3942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
3943#[inline]
3944#[target_feature(enable = "neon")]
3945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3947#[cfg_attr(
3948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3949 assert_instr(bsl)
3950)]
3951#[cfg_attr(
3952 not(target_arch = "arm"),
3953 stable(feature = "neon_intrinsics", since = "1.59.0")
3954)]
3955#[cfg_attr(
3956 target_arch = "arm",
3957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3958)]
3959pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
3960 let not = int16x4_t::splat(-1);
3961 unsafe {
3962 transmute(simd_or(
3963 simd_and(a, transmute(b)),
3964 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3965 ))
3966 }
3967}
3968#[doc = "Bitwise Select."]
3969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
3970#[inline]
3971#[target_feature(enable = "neon")]
3972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
3973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
3974#[cfg_attr(
3975 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
3976 assert_instr(bsl)
3977)]
3978#[cfg_attr(
3979 not(target_arch = "arm"),
3980 stable(feature = "neon_intrinsics", since = "1.59.0")
3981)]
3982#[cfg_attr(
3983 target_arch = "arm",
3984 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
3985)]
3986pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
3987 let not = int32x2_t::splat(-1);
3988 unsafe {
3989 transmute(simd_or(
3990 simd_and(a, transmute(b)),
3991 simd_and(simd_xor(a, transmute(not)), transmute(c)),
3992 ))
3993 }
3994}
3995#[doc = "Bitwise Select."]
3996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
3997#[inline]
3998#[target_feature(enable = "neon")]
3999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4000#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4001#[cfg_attr(
4002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4003 assert_instr(bsl)
4004)]
4005#[cfg_attr(
4006 not(target_arch = "arm"),
4007 stable(feature = "neon_intrinsics", since = "1.59.0")
4008)]
4009#[cfg_attr(
4010 target_arch = "arm",
4011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4012)]
4013pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
4014 let not = int64x1_t::splat(-1);
4015 unsafe {
4016 transmute(simd_or(
4017 simd_and(a, transmute(b)),
4018 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4019 ))
4020 }
4021}
4022#[doc = "Bitwise Select."]
4023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
4024#[inline]
4025#[target_feature(enable = "neon")]
4026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4028#[cfg_attr(
4029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4030 assert_instr(bsl)
4031)]
4032#[cfg_attr(
4033 not(target_arch = "arm"),
4034 stable(feature = "neon_intrinsics", since = "1.59.0")
4035)]
4036#[cfg_attr(
4037 target_arch = "arm",
4038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4039)]
4040pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
4041 let not = int8x8_t::splat(-1);
4042 unsafe {
4043 transmute(simd_or(
4044 simd_and(a, transmute(b)),
4045 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4046 ))
4047 }
4048}
4049#[doc = "Bitwise Select."]
4050#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
4051#[inline]
4052#[target_feature(enable = "neon")]
4053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4055#[cfg_attr(
4056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4057 assert_instr(bsl)
4058)]
4059#[cfg_attr(
4060 not(target_arch = "arm"),
4061 stable(feature = "neon_intrinsics", since = "1.59.0")
4062)]
4063#[cfg_attr(
4064 target_arch = "arm",
4065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4066)]
4067pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
4068 let not = int32x4_t::splat(-1);
4069 unsafe {
4070 transmute(simd_or(
4071 simd_and(a, transmute(b)),
4072 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4073 ))
4074 }
4075}
4076#[doc = "Bitwise Select."]
4077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
4078#[inline]
4079#[target_feature(enable = "neon")]
4080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4082#[cfg_attr(
4083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4084 assert_instr(bsl)
4085)]
4086#[cfg_attr(
4087 not(target_arch = "arm"),
4088 stable(feature = "neon_intrinsics", since = "1.59.0")
4089)]
4090#[cfg_attr(
4091 target_arch = "arm",
4092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4093)]
4094pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
4095 let not = int16x8_t::splat(-1);
4096 unsafe {
4097 transmute(simd_or(
4098 simd_and(a, transmute(b)),
4099 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4100 ))
4101 }
4102}
4103#[doc = "Bitwise Select."]
4104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
4105#[inline]
4106#[target_feature(enable = "neon")]
4107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4109#[cfg_attr(
4110 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4111 assert_instr(bsl)
4112)]
4113#[cfg_attr(
4114 not(target_arch = "arm"),
4115 stable(feature = "neon_intrinsics", since = "1.59.0")
4116)]
4117#[cfg_attr(
4118 target_arch = "arm",
4119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4120)]
4121pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
4122 let not = int8x16_t::splat(-1);
4123 unsafe {
4124 transmute(simd_or(
4125 simd_and(a, transmute(b)),
4126 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4127 ))
4128 }
4129}
4130#[doc = "Bitwise Select."]
4131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
4132#[inline]
4133#[target_feature(enable = "neon")]
4134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4136#[cfg_attr(
4137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4138 assert_instr(bsl)
4139)]
4140#[cfg_attr(
4141 not(target_arch = "arm"),
4142 stable(feature = "neon_intrinsics", since = "1.59.0")
4143)]
4144#[cfg_attr(
4145 target_arch = "arm",
4146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4147)]
4148pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
4149 let not = int16x8_t::splat(-1);
4150 unsafe {
4151 transmute(simd_or(
4152 simd_and(a, transmute(b)),
4153 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4154 ))
4155 }
4156}
4157#[doc = "Bitwise Select."]
4158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
4159#[inline]
4160#[target_feature(enable = "neon")]
4161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4163#[cfg_attr(
4164 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4165 assert_instr(bsl)
4166)]
4167#[cfg_attr(
4168 not(target_arch = "arm"),
4169 stable(feature = "neon_intrinsics", since = "1.59.0")
4170)]
4171#[cfg_attr(
4172 target_arch = "arm",
4173 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4174)]
4175pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
4176 let not = int32x4_t::splat(-1);
4177 unsafe {
4178 transmute(simd_or(
4179 simd_and(a, transmute(b)),
4180 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4181 ))
4182 }
4183}
4184#[doc = "Bitwise Select."]
4185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
4186#[inline]
4187#[target_feature(enable = "neon")]
4188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4189#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4190#[cfg_attr(
4191 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4192 assert_instr(bsl)
4193)]
4194#[cfg_attr(
4195 not(target_arch = "arm"),
4196 stable(feature = "neon_intrinsics", since = "1.59.0")
4197)]
4198#[cfg_attr(
4199 target_arch = "arm",
4200 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4201)]
4202pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
4203 let not = int64x2_t::splat(-1);
4204 unsafe {
4205 transmute(simd_or(
4206 simd_and(a, transmute(b)),
4207 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4208 ))
4209 }
4210}
4211#[doc = "Bitwise Select."]
4212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
4213#[inline]
4214#[target_feature(enable = "neon")]
4215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4217#[cfg_attr(
4218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4219 assert_instr(bsl)
4220)]
4221#[cfg_attr(
4222 not(target_arch = "arm"),
4223 stable(feature = "neon_intrinsics", since = "1.59.0")
4224)]
4225#[cfg_attr(
4226 target_arch = "arm",
4227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4228)]
4229pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
4230 let not = int8x16_t::splat(-1);
4231 unsafe {
4232 transmute(simd_or(
4233 simd_and(a, transmute(b)),
4234 simd_and(simd_xor(a, transmute(not)), transmute(c)),
4235 ))
4236 }
4237}
4238#[doc = "Bitwise Select."]
4239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
4240#[inline]
4241#[target_feature(enable = "neon")]
4242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4244#[cfg_attr(
4245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4246 assert_instr(bsl)
4247)]
4248#[cfg_attr(
4249 not(target_arch = "arm"),
4250 stable(feature = "neon_intrinsics", since = "1.59.0")
4251)]
4252#[cfg_attr(
4253 target_arch = "arm",
4254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4255)]
4256pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
4257 let not = int16x4_t::splat(-1);
4258 unsafe {
4259 transmute(simd_or(
4260 simd_and(a, b),
4261 simd_and(simd_xor(a, transmute(not)), c),
4262 ))
4263 }
4264}
4265#[doc = "Bitwise Select."]
4266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
4267#[inline]
4268#[target_feature(enable = "neon")]
4269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4271#[cfg_attr(
4272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4273 assert_instr(bsl)
4274)]
4275#[cfg_attr(
4276 not(target_arch = "arm"),
4277 stable(feature = "neon_intrinsics", since = "1.59.0")
4278)]
4279#[cfg_attr(
4280 target_arch = "arm",
4281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4282)]
4283pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
4284 let not = int32x2_t::splat(-1);
4285 unsafe {
4286 transmute(simd_or(
4287 simd_and(a, b),
4288 simd_and(simd_xor(a, transmute(not)), c),
4289 ))
4290 }
4291}
4292#[doc = "Bitwise Select."]
4293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
4294#[inline]
4295#[target_feature(enable = "neon")]
4296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4298#[cfg_attr(
4299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4300 assert_instr(bsl)
4301)]
4302#[cfg_attr(
4303 not(target_arch = "arm"),
4304 stable(feature = "neon_intrinsics", since = "1.59.0")
4305)]
4306#[cfg_attr(
4307 target_arch = "arm",
4308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4309)]
4310pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
4311 let not = int64x1_t::splat(-1);
4312 unsafe {
4313 transmute(simd_or(
4314 simd_and(a, b),
4315 simd_and(simd_xor(a, transmute(not)), c),
4316 ))
4317 }
4318}
4319#[doc = "Bitwise Select."]
4320#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
4321#[inline]
4322#[target_feature(enable = "neon")]
4323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4325#[cfg_attr(
4326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4327 assert_instr(bsl)
4328)]
4329#[cfg_attr(
4330 not(target_arch = "arm"),
4331 stable(feature = "neon_intrinsics", since = "1.59.0")
4332)]
4333#[cfg_attr(
4334 target_arch = "arm",
4335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4336)]
4337pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
4338 let not = int8x8_t::splat(-1);
4339 unsafe {
4340 transmute(simd_or(
4341 simd_and(a, b),
4342 simd_and(simd_xor(a, transmute(not)), c),
4343 ))
4344 }
4345}
4346#[doc = "Bitwise Select."]
4347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
4348#[inline]
4349#[target_feature(enable = "neon")]
4350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4352#[cfg_attr(
4353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4354 assert_instr(bsl)
4355)]
4356#[cfg_attr(
4357 not(target_arch = "arm"),
4358 stable(feature = "neon_intrinsics", since = "1.59.0")
4359)]
4360#[cfg_attr(
4361 target_arch = "arm",
4362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4363)]
4364pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
4365 let not = int16x8_t::splat(-1);
4366 unsafe {
4367 transmute(simd_or(
4368 simd_and(a, b),
4369 simd_and(simd_xor(a, transmute(not)), c),
4370 ))
4371 }
4372}
4373#[doc = "Bitwise Select."]
4374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
4375#[inline]
4376#[target_feature(enable = "neon")]
4377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4379#[cfg_attr(
4380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4381 assert_instr(bsl)
4382)]
4383#[cfg_attr(
4384 not(target_arch = "arm"),
4385 stable(feature = "neon_intrinsics", since = "1.59.0")
4386)]
4387#[cfg_attr(
4388 target_arch = "arm",
4389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4390)]
4391pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
4392 let not = int32x4_t::splat(-1);
4393 unsafe {
4394 transmute(simd_or(
4395 simd_and(a, b),
4396 simd_and(simd_xor(a, transmute(not)), c),
4397 ))
4398 }
4399}
4400#[doc = "Bitwise Select."]
4401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
4402#[inline]
4403#[target_feature(enable = "neon")]
4404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4405#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4406#[cfg_attr(
4407 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4408 assert_instr(bsl)
4409)]
4410#[cfg_attr(
4411 not(target_arch = "arm"),
4412 stable(feature = "neon_intrinsics", since = "1.59.0")
4413)]
4414#[cfg_attr(
4415 target_arch = "arm",
4416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4417)]
4418pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
4419 let not = int64x2_t::splat(-1);
4420 unsafe {
4421 transmute(simd_or(
4422 simd_and(a, b),
4423 simd_and(simd_xor(a, transmute(not)), c),
4424 ))
4425 }
4426}
4427#[doc = "Bitwise Select."]
4428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
4429#[inline]
4430#[target_feature(enable = "neon")]
4431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
4433#[cfg_attr(
4434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4435 assert_instr(bsl)
4436)]
4437#[cfg_attr(
4438 not(target_arch = "arm"),
4439 stable(feature = "neon_intrinsics", since = "1.59.0")
4440)]
4441#[cfg_attr(
4442 target_arch = "arm",
4443 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4444)]
4445pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
4446 let not = int8x16_t::splat(-1);
4447 unsafe {
4448 transmute(simd_or(
4449 simd_and(a, b),
4450 simd_and(simd_xor(a, transmute(not)), c),
4451 ))
4452 }
4453}
4454#[doc = "Floating-point absolute compare greater than or equal"]
4455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
4456#[inline]
4457#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4458#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4459#[cfg_attr(
4460 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4461 assert_instr(facge)
4462)]
4463#[target_feature(enable = "neon,fp16")]
4464#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4465pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4466 unsafe extern "unadjusted" {
4467 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i16.v4f16")]
4468 #[cfg_attr(
4469 any(target_arch = "aarch64", target_arch = "arm64ec"),
4470 link_name = "llvm.aarch64.neon.facge.v4i16.v4f16"
4471 )]
4472 fn _vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4473 }
4474 unsafe { _vcage_f16(a, b) }
4475}
4476#[doc = "Floating-point absolute compare greater than or equal"]
4477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
4478#[inline]
4479#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4480#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4481#[cfg_attr(
4482 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4483 assert_instr(facge)
4484)]
4485#[target_feature(enable = "neon,fp16")]
4486#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4487pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4488 unsafe extern "unadjusted" {
4489 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v8i16.v8f16")]
4490 #[cfg_attr(
4491 any(target_arch = "aarch64", target_arch = "arm64ec"),
4492 link_name = "llvm.aarch64.neon.facge.v8i16.v8f16"
4493 )]
4494 fn _vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4495 }
4496 unsafe { _vcageq_f16(a, b) }
4497}
4498#[doc = "Floating-point absolute compare greater than or equal"]
4499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
4500#[inline]
4501#[target_feature(enable = "neon")]
4502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4504#[cfg_attr(
4505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4506 assert_instr(facge)
4507)]
4508#[cfg_attr(
4509 not(target_arch = "arm"),
4510 stable(feature = "neon_intrinsics", since = "1.59.0")
4511)]
4512#[cfg_attr(
4513 target_arch = "arm",
4514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4515)]
4516pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4517 unsafe extern "unadjusted" {
4518 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")]
4519 #[cfg_attr(
4520 any(target_arch = "aarch64", target_arch = "arm64ec"),
4521 link_name = "llvm.aarch64.neon.facge.v2i32.v2f32"
4522 )]
4523 fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4524 }
4525 unsafe { _vcage_f32(a, b) }
4526}
4527#[doc = "Floating-point absolute compare greater than or equal"]
4528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
4529#[inline]
4530#[target_feature(enable = "neon")]
4531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4532#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4533#[cfg_attr(
4534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4535 assert_instr(facge)
4536)]
4537#[cfg_attr(
4538 not(target_arch = "arm"),
4539 stable(feature = "neon_intrinsics", since = "1.59.0")
4540)]
4541#[cfg_attr(
4542 target_arch = "arm",
4543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4544)]
4545pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4546 unsafe extern "unadjusted" {
4547 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")]
4548 #[cfg_attr(
4549 any(target_arch = "aarch64", target_arch = "arm64ec"),
4550 link_name = "llvm.aarch64.neon.facge.v4i32.v4f32"
4551 )]
4552 fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4553 }
4554 unsafe { _vcageq_f32(a, b) }
4555}
4556#[doc = "Floating-point absolute compare greater than"]
4557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
4558#[inline]
4559#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4561#[cfg_attr(
4562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4563 assert_instr(facgt)
4564)]
4565#[target_feature(enable = "neon,fp16")]
4566#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4567pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4568 unsafe extern "unadjusted" {
4569 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i16.v4f16")]
4570 #[cfg_attr(
4571 any(target_arch = "aarch64", target_arch = "arm64ec"),
4572 link_name = "llvm.aarch64.neon.facgt.v4i16.v4f16"
4573 )]
4574 fn _vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t;
4575 }
4576 unsafe { _vcagt_f16(a, b) }
4577}
4578#[doc = "Floating-point absolute compare greater than"]
4579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
4580#[inline]
4581#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4582#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4583#[cfg_attr(
4584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4585 assert_instr(facgt)
4586)]
4587#[target_feature(enable = "neon,fp16")]
4588#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4589pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4590 unsafe extern "unadjusted" {
4591 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v8i16.v8f16")]
4592 #[cfg_attr(
4593 any(target_arch = "aarch64", target_arch = "arm64ec"),
4594 link_name = "llvm.aarch64.neon.facgt.v8i16.v8f16"
4595 )]
4596 fn _vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t;
4597 }
4598 unsafe { _vcagtq_f16(a, b) }
4599}
4600#[doc = "Floating-point absolute compare greater than"]
4601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
4602#[inline]
4603#[target_feature(enable = "neon")]
4604#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4605#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4606#[cfg_attr(
4607 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4608 assert_instr(facgt)
4609)]
4610#[cfg_attr(
4611 not(target_arch = "arm"),
4612 stable(feature = "neon_intrinsics", since = "1.59.0")
4613)]
4614#[cfg_attr(
4615 target_arch = "arm",
4616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4617)]
4618pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4619 unsafe extern "unadjusted" {
4620 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")]
4621 #[cfg_attr(
4622 any(target_arch = "aarch64", target_arch = "arm64ec"),
4623 link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32"
4624 )]
4625 fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t;
4626 }
4627 unsafe { _vcagt_f32(a, b) }
4628}
4629#[doc = "Floating-point absolute compare greater than"]
4630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
4631#[inline]
4632#[target_feature(enable = "neon")]
4633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4635#[cfg_attr(
4636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4637 assert_instr(facgt)
4638)]
4639#[cfg_attr(
4640 not(target_arch = "arm"),
4641 stable(feature = "neon_intrinsics", since = "1.59.0")
4642)]
4643#[cfg_attr(
4644 target_arch = "arm",
4645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4646)]
4647pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4648 unsafe extern "unadjusted" {
4649 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")]
4650 #[cfg_attr(
4651 any(target_arch = "aarch64", target_arch = "arm64ec"),
4652 link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32"
4653 )]
4654 fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t;
4655 }
4656 unsafe { _vcagtq_f32(a, b) }
4657}
4658#[doc = "Floating-point absolute compare less than or equal"]
4659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
4660#[inline]
4661#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4662#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4663#[cfg_attr(
4664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4665 assert_instr(facge)
4666)]
4667#[target_feature(enable = "neon,fp16")]
4668#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4669pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4670 vcage_f16(b, a)
4671}
4672#[doc = "Floating-point absolute compare less than or equal"]
4673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
4674#[inline]
4675#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4676#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
4677#[cfg_attr(
4678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4679 assert_instr(facge)
4680)]
4681#[target_feature(enable = "neon,fp16")]
4682#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4683pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4684 vcageq_f16(b, a)
4685}
4686#[doc = "Floating-point absolute compare less than or equal"]
4687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
4688#[inline]
4689#[target_feature(enable = "neon")]
4690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4691#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4692#[cfg_attr(
4693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4694 assert_instr(facge)
4695)]
4696#[cfg_attr(
4697 not(target_arch = "arm"),
4698 stable(feature = "neon_intrinsics", since = "1.59.0")
4699)]
4700#[cfg_attr(
4701 target_arch = "arm",
4702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4703)]
4704pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4705 vcage_f32(b, a)
4706}
4707#[doc = "Floating-point absolute compare less than or equal"]
4708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
4709#[inline]
4710#[target_feature(enable = "neon")]
4711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
4713#[cfg_attr(
4714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4715 assert_instr(facge)
4716)]
4717#[cfg_attr(
4718 not(target_arch = "arm"),
4719 stable(feature = "neon_intrinsics", since = "1.59.0")
4720)]
4721#[cfg_attr(
4722 target_arch = "arm",
4723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4724)]
4725pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4726 vcageq_f32(b, a)
4727}
4728#[doc = "Floating-point absolute compare less than"]
4729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
4730#[inline]
4731#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4732#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4733#[cfg_attr(
4734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4735 assert_instr(facgt)
4736)]
4737#[target_feature(enable = "neon,fp16")]
4738#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4739pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4740 vcagt_f16(b, a)
4741}
4742#[doc = "Floating-point absolute compare less than"]
4743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
4744#[inline]
4745#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4746#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
4747#[cfg_attr(
4748 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4749 assert_instr(facgt)
4750)]
4751#[target_feature(enable = "neon,fp16")]
4752#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4753pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4754 vcagtq_f16(b, a)
4755}
4756#[doc = "Floating-point absolute compare less than"]
4757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
4758#[inline]
4759#[target_feature(enable = "neon")]
4760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4761#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4762#[cfg_attr(
4763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4764 assert_instr(facgt)
4765)]
4766#[cfg_attr(
4767 not(target_arch = "arm"),
4768 stable(feature = "neon_intrinsics", since = "1.59.0")
4769)]
4770#[cfg_attr(
4771 target_arch = "arm",
4772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4773)]
4774pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4775 vcagt_f32(b, a)
4776}
4777#[doc = "Floating-point absolute compare less than"]
4778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
4779#[inline]
4780#[target_feature(enable = "neon")]
4781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4782#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
4783#[cfg_attr(
4784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4785 assert_instr(facgt)
4786)]
4787#[cfg_attr(
4788 not(target_arch = "arm"),
4789 stable(feature = "neon_intrinsics", since = "1.59.0")
4790)]
4791#[cfg_attr(
4792 target_arch = "arm",
4793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4794)]
4795pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4796 vcagtq_f32(b, a)
4797}
4798#[doc = "Floating-point compare equal"]
4799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
4800#[inline]
4801#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4802#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4803#[cfg_attr(
4804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4805 assert_instr(fcmeq)
4806)]
4807#[target_feature(enable = "neon,fp16")]
4808#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4809pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
4810 unsafe { simd_eq(a, b) }
4811}
4812#[doc = "Floating-point compare equal"]
4813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
4814#[inline]
4815#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
4816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
4817#[cfg_attr(
4818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4819 assert_instr(fcmeq)
4820)]
4821#[target_feature(enable = "neon,fp16")]
4822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
4823pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
4824 unsafe { simd_eq(a, b) }
4825}
4826#[doc = "Floating-point compare equal"]
4827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
4828#[inline]
4829#[target_feature(enable = "neon")]
4830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4832#[cfg_attr(
4833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4834 assert_instr(fcmeq)
4835)]
4836#[cfg_attr(
4837 not(target_arch = "arm"),
4838 stable(feature = "neon_intrinsics", since = "1.59.0")
4839)]
4840#[cfg_attr(
4841 target_arch = "arm",
4842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4843)]
4844pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
4845 unsafe { simd_eq(a, b) }
4846}
4847#[doc = "Floating-point compare equal"]
4848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
4849#[inline]
4850#[target_feature(enable = "neon")]
4851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
4853#[cfg_attr(
4854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4855 assert_instr(fcmeq)
4856)]
4857#[cfg_attr(
4858 not(target_arch = "arm"),
4859 stable(feature = "neon_intrinsics", since = "1.59.0")
4860)]
4861#[cfg_attr(
4862 target_arch = "arm",
4863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4864)]
4865pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
4866 unsafe { simd_eq(a, b) }
4867}
4868#[doc = "Compare bitwise Equal (vector)"]
4869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
4870#[inline]
4871#[target_feature(enable = "neon")]
4872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4874#[cfg_attr(
4875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4876 assert_instr(cmeq)
4877)]
4878#[cfg_attr(
4879 not(target_arch = "arm"),
4880 stable(feature = "neon_intrinsics", since = "1.59.0")
4881)]
4882#[cfg_attr(
4883 target_arch = "arm",
4884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4885)]
4886pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
4887 unsafe { simd_eq(a, b) }
4888}
4889#[doc = "Compare bitwise Equal (vector)"]
4890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
4891#[inline]
4892#[target_feature(enable = "neon")]
4893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
4895#[cfg_attr(
4896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4897 assert_instr(cmeq)
4898)]
4899#[cfg_attr(
4900 not(target_arch = "arm"),
4901 stable(feature = "neon_intrinsics", since = "1.59.0")
4902)]
4903#[cfg_attr(
4904 target_arch = "arm",
4905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4906)]
4907pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
4908 unsafe { simd_eq(a, b) }
4909}
4910#[doc = "Compare bitwise Equal (vector)"]
4911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
4912#[inline]
4913#[target_feature(enable = "neon")]
4914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4915#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4916#[cfg_attr(
4917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4918 assert_instr(cmeq)
4919)]
4920#[cfg_attr(
4921 not(target_arch = "arm"),
4922 stable(feature = "neon_intrinsics", since = "1.59.0")
4923)]
4924#[cfg_attr(
4925 target_arch = "arm",
4926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4927)]
4928pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
4929 unsafe { simd_eq(a, b) }
4930}
4931#[doc = "Compare bitwise Equal (vector)"]
4932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
4933#[inline]
4934#[target_feature(enable = "neon")]
4935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
4937#[cfg_attr(
4938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4939 assert_instr(cmeq)
4940)]
4941#[cfg_attr(
4942 not(target_arch = "arm"),
4943 stable(feature = "neon_intrinsics", since = "1.59.0")
4944)]
4945#[cfg_attr(
4946 target_arch = "arm",
4947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4948)]
4949pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
4950 unsafe { simd_eq(a, b) }
4951}
4952#[doc = "Compare bitwise Equal (vector)"]
4953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
4954#[inline]
4955#[target_feature(enable = "neon")]
4956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4957#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4958#[cfg_attr(
4959 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4960 assert_instr(cmeq)
4961)]
4962#[cfg_attr(
4963 not(target_arch = "arm"),
4964 stable(feature = "neon_intrinsics", since = "1.59.0")
4965)]
4966#[cfg_attr(
4967 target_arch = "arm",
4968 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4969)]
4970pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
4971 unsafe { simd_eq(a, b) }
4972}
4973#[doc = "Compare bitwise Equal (vector)"]
4974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
4975#[inline]
4976#[target_feature(enable = "neon")]
4977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
4979#[cfg_attr(
4980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
4981 assert_instr(cmeq)
4982)]
4983#[cfg_attr(
4984 not(target_arch = "arm"),
4985 stable(feature = "neon_intrinsics", since = "1.59.0")
4986)]
4987#[cfg_attr(
4988 target_arch = "arm",
4989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
4990)]
4991pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
4992 unsafe { simd_eq(a, b) }
4993}
4994#[doc = "Compare bitwise Equal (vector)"]
4995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
4996#[inline]
4997#[target_feature(enable = "neon")]
4998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
4999#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5000#[cfg_attr(
5001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5002 assert_instr(cmeq)
5003)]
5004#[cfg_attr(
5005 not(target_arch = "arm"),
5006 stable(feature = "neon_intrinsics", since = "1.59.0")
5007)]
5008#[cfg_attr(
5009 target_arch = "arm",
5010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5011)]
5012pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5013 unsafe { simd_eq(a, b) }
5014}
5015#[doc = "Compare bitwise Equal (vector)"]
5016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
5017#[inline]
5018#[target_feature(enable = "neon")]
5019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5020#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5021#[cfg_attr(
5022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5023 assert_instr(cmeq)
5024)]
5025#[cfg_attr(
5026 not(target_arch = "arm"),
5027 stable(feature = "neon_intrinsics", since = "1.59.0")
5028)]
5029#[cfg_attr(
5030 target_arch = "arm",
5031 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5032)]
5033pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5034 unsafe { simd_eq(a, b) }
5035}
5036#[doc = "Compare bitwise Equal (vector)"]
5037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
5038#[inline]
5039#[target_feature(enable = "neon")]
5040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5041#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5042#[cfg_attr(
5043 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5044 assert_instr(cmeq)
5045)]
5046#[cfg_attr(
5047 not(target_arch = "arm"),
5048 stable(feature = "neon_intrinsics", since = "1.59.0")
5049)]
5050#[cfg_attr(
5051 target_arch = "arm",
5052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5053)]
5054pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5055 unsafe { simd_eq(a, b) }
5056}
5057#[doc = "Compare bitwise Equal (vector)"]
5058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
5059#[inline]
5060#[target_feature(enable = "neon")]
5061#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
5063#[cfg_attr(
5064 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5065 assert_instr(cmeq)
5066)]
5067#[cfg_attr(
5068 not(target_arch = "arm"),
5069 stable(feature = "neon_intrinsics", since = "1.59.0")
5070)]
5071#[cfg_attr(
5072 target_arch = "arm",
5073 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5074)]
5075pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5076 unsafe { simd_eq(a, b) }
5077}
5078#[doc = "Compare bitwise Equal (vector)"]
5079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
5080#[inline]
5081#[target_feature(enable = "neon")]
5082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5084#[cfg_attr(
5085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5086 assert_instr(cmeq)
5087)]
5088#[cfg_attr(
5089 not(target_arch = "arm"),
5090 stable(feature = "neon_intrinsics", since = "1.59.0")
5091)]
5092#[cfg_attr(
5093 target_arch = "arm",
5094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5095)]
5096pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5097 unsafe { simd_eq(a, b) }
5098}
5099#[doc = "Compare bitwise Equal (vector)"]
5100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
5101#[inline]
5102#[target_feature(enable = "neon")]
5103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5104#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
5105#[cfg_attr(
5106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5107 assert_instr(cmeq)
5108)]
5109#[cfg_attr(
5110 not(target_arch = "arm"),
5111 stable(feature = "neon_intrinsics", since = "1.59.0")
5112)]
5113#[cfg_attr(
5114 target_arch = "arm",
5115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5116)]
5117pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5118 unsafe { simd_eq(a, b) }
5119}
5120#[doc = "Compare bitwise Equal (vector)"]
5121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
5122#[inline]
5123#[target_feature(enable = "neon")]
5124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5125#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5126#[cfg_attr(
5127 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5128 assert_instr(cmeq)
5129)]
5130#[cfg_attr(
5131 not(target_arch = "arm"),
5132 stable(feature = "neon_intrinsics", since = "1.59.0")
5133)]
5134#[cfg_attr(
5135 target_arch = "arm",
5136 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5137)]
5138pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
5139 unsafe { simd_eq(a, b) }
5140}
5141#[doc = "Compare bitwise Equal (vector)"]
5142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
5143#[inline]
5144#[target_feature(enable = "neon")]
5145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5146#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
5147#[cfg_attr(
5148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5149 assert_instr(cmeq)
5150)]
5151#[cfg_attr(
5152 not(target_arch = "arm"),
5153 stable(feature = "neon_intrinsics", since = "1.59.0")
5154)]
5155#[cfg_attr(
5156 target_arch = "arm",
5157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5158)]
5159pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
5160 unsafe { simd_eq(a, b) }
5161}
5162#[doc = "Floating-point compare greater than or equal"]
5163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
5164#[inline]
5165#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5166#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5167#[cfg_attr(
5168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5169 assert_instr(fcmge)
5170)]
5171#[target_feature(enable = "neon,fp16")]
5172#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5173pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5174 unsafe { simd_ge(a, b) }
5175}
5176#[doc = "Floating-point compare greater than or equal"]
5177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
5178#[inline]
5179#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5180#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5181#[cfg_attr(
5182 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5183 assert_instr(fcmge)
5184)]
5185#[target_feature(enable = "neon,fp16")]
5186#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5187pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5188 unsafe { simd_ge(a, b) }
5189}
5190#[doc = "Floating-point compare greater than or equal"]
5191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
5192#[inline]
5193#[target_feature(enable = "neon")]
5194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5196#[cfg_attr(
5197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5198 assert_instr(fcmge)
5199)]
5200#[cfg_attr(
5201 not(target_arch = "arm"),
5202 stable(feature = "neon_intrinsics", since = "1.59.0")
5203)]
5204#[cfg_attr(
5205 target_arch = "arm",
5206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5207)]
5208pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5209 unsafe { simd_ge(a, b) }
5210}
5211#[doc = "Floating-point compare greater than or equal"]
5212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
5213#[inline]
5214#[target_feature(enable = "neon")]
5215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5217#[cfg_attr(
5218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5219 assert_instr(fcmge)
5220)]
5221#[cfg_attr(
5222 not(target_arch = "arm"),
5223 stable(feature = "neon_intrinsics", since = "1.59.0")
5224)]
5225#[cfg_attr(
5226 target_arch = "arm",
5227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5228)]
5229pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5230 unsafe { simd_ge(a, b) }
5231}
5232#[doc = "Compare signed greater than or equal"]
5233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
5234#[inline]
5235#[target_feature(enable = "neon")]
5236#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5237#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5238#[cfg_attr(
5239 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5240 assert_instr(cmge)
5241)]
5242#[cfg_attr(
5243 not(target_arch = "arm"),
5244 stable(feature = "neon_intrinsics", since = "1.59.0")
5245)]
5246#[cfg_attr(
5247 target_arch = "arm",
5248 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5249)]
5250pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5251 unsafe { simd_ge(a, b) }
5252}
5253#[doc = "Compare signed greater than or equal"]
5254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
5255#[inline]
5256#[target_feature(enable = "neon")]
5257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5258#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5259#[cfg_attr(
5260 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5261 assert_instr(cmge)
5262)]
5263#[cfg_attr(
5264 not(target_arch = "arm"),
5265 stable(feature = "neon_intrinsics", since = "1.59.0")
5266)]
5267#[cfg_attr(
5268 target_arch = "arm",
5269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5270)]
5271pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5272 unsafe { simd_ge(a, b) }
5273}
5274#[doc = "Compare signed greater than or equal"]
5275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
5276#[inline]
5277#[target_feature(enable = "neon")]
5278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5280#[cfg_attr(
5281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5282 assert_instr(cmge)
5283)]
5284#[cfg_attr(
5285 not(target_arch = "arm"),
5286 stable(feature = "neon_intrinsics", since = "1.59.0")
5287)]
5288#[cfg_attr(
5289 target_arch = "arm",
5290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5291)]
5292pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5293 unsafe { simd_ge(a, b) }
5294}
5295#[doc = "Compare signed greater than or equal"]
5296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
5297#[inline]
5298#[target_feature(enable = "neon")]
5299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5300#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5301#[cfg_attr(
5302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5303 assert_instr(cmge)
5304)]
5305#[cfg_attr(
5306 not(target_arch = "arm"),
5307 stable(feature = "neon_intrinsics", since = "1.59.0")
5308)]
5309#[cfg_attr(
5310 target_arch = "arm",
5311 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5312)]
5313pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5314 unsafe { simd_ge(a, b) }
5315}
5316#[doc = "Compare signed greater than or equal"]
5317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
5318#[inline]
5319#[target_feature(enable = "neon")]
5320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5321#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5322#[cfg_attr(
5323 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5324 assert_instr(cmge)
5325)]
5326#[cfg_attr(
5327 not(target_arch = "arm"),
5328 stable(feature = "neon_intrinsics", since = "1.59.0")
5329)]
5330#[cfg_attr(
5331 target_arch = "arm",
5332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5333)]
5334pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5335 unsafe { simd_ge(a, b) }
5336}
5337#[doc = "Compare signed greater than or equal"]
5338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
5339#[inline]
5340#[target_feature(enable = "neon")]
5341#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5342#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
5343#[cfg_attr(
5344 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5345 assert_instr(cmge)
5346)]
5347#[cfg_attr(
5348 not(target_arch = "arm"),
5349 stable(feature = "neon_intrinsics", since = "1.59.0")
5350)]
5351#[cfg_attr(
5352 target_arch = "arm",
5353 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5354)]
5355pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5356 unsafe { simd_ge(a, b) }
5357}
5358#[doc = "Compare unsigned greater than or equal"]
5359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
5360#[inline]
5361#[target_feature(enable = "neon")]
5362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5363#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5364#[cfg_attr(
5365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5366 assert_instr(cmhs)
5367)]
5368#[cfg_attr(
5369 not(target_arch = "arm"),
5370 stable(feature = "neon_intrinsics", since = "1.59.0")
5371)]
5372#[cfg_attr(
5373 target_arch = "arm",
5374 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5375)]
5376pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5377 unsafe { simd_ge(a, b) }
5378}
5379#[doc = "Compare unsigned greater than or equal"]
5380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
5381#[inline]
5382#[target_feature(enable = "neon")]
5383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5384#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
5385#[cfg_attr(
5386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5387 assert_instr(cmhs)
5388)]
5389#[cfg_attr(
5390 not(target_arch = "arm"),
5391 stable(feature = "neon_intrinsics", since = "1.59.0")
5392)]
5393#[cfg_attr(
5394 target_arch = "arm",
5395 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5396)]
5397pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5398 unsafe { simd_ge(a, b) }
5399}
5400#[doc = "Compare unsigned greater than or equal"]
5401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
5402#[inline]
5403#[target_feature(enable = "neon")]
5404#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5405#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5406#[cfg_attr(
5407 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5408 assert_instr(cmhs)
5409)]
5410#[cfg_attr(
5411 not(target_arch = "arm"),
5412 stable(feature = "neon_intrinsics", since = "1.59.0")
5413)]
5414#[cfg_attr(
5415 target_arch = "arm",
5416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5417)]
5418pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5419 unsafe { simd_ge(a, b) }
5420}
5421#[doc = "Compare unsigned greater than or equal"]
5422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
5423#[inline]
5424#[target_feature(enable = "neon")]
5425#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5426#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
5427#[cfg_attr(
5428 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5429 assert_instr(cmhs)
5430)]
5431#[cfg_attr(
5432 not(target_arch = "arm"),
5433 stable(feature = "neon_intrinsics", since = "1.59.0")
5434)]
5435#[cfg_attr(
5436 target_arch = "arm",
5437 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5438)]
5439pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5440 unsafe { simd_ge(a, b) }
5441}
5442#[doc = "Compare unsigned greater than or equal"]
5443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
5444#[inline]
5445#[target_feature(enable = "neon")]
5446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5447#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5448#[cfg_attr(
5449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5450 assert_instr(cmhs)
5451)]
5452#[cfg_attr(
5453 not(target_arch = "arm"),
5454 stable(feature = "neon_intrinsics", since = "1.59.0")
5455)]
5456#[cfg_attr(
5457 target_arch = "arm",
5458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5459)]
5460pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5461 unsafe { simd_ge(a, b) }
5462}
5463#[doc = "Compare unsigned greater than or equal"]
5464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
5465#[inline]
5466#[target_feature(enable = "neon")]
5467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5468#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
5469#[cfg_attr(
5470 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5471 assert_instr(cmhs)
5472)]
5473#[cfg_attr(
5474 not(target_arch = "arm"),
5475 stable(feature = "neon_intrinsics", since = "1.59.0")
5476)]
5477#[cfg_attr(
5478 target_arch = "arm",
5479 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5480)]
5481pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5482 unsafe { simd_ge(a, b) }
5483}
5484#[doc = "Floating-point compare greater than or equal to zero"]
5485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
5486#[inline]
5487#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5488#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5489#[cfg_attr(
5490 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5491 assert_instr(fcmge)
5492)]
5493#[target_feature(enable = "neon,fp16")]
5494#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5495pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
5496 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5497 unsafe { simd_ge(a, transmute(b)) }
5498}
5499#[doc = "Floating-point compare greater than or equal to zero"]
5500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
5501#[inline]
5502#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5503#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5504#[cfg_attr(
5505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5506 assert_instr(fcmge)
5507)]
5508#[target_feature(enable = "neon,fp16")]
5509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5510pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
5511 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5512 unsafe { simd_ge(a, transmute(b)) }
5513}
5514#[doc = "Floating-point compare greater than"]
5515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
5516#[inline]
5517#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5518#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5519#[cfg_attr(
5520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5521 assert_instr(fcmgt)
5522)]
5523#[target_feature(enable = "neon,fp16")]
5524#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5525pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5526 unsafe { simd_gt(a, b) }
5527}
5528#[doc = "Floating-point compare greater than"]
5529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
5530#[inline]
5531#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5532#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5533#[cfg_attr(
5534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5535 assert_instr(fcmgt)
5536)]
5537#[target_feature(enable = "neon,fp16")]
5538#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5539pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5540 unsafe { simd_gt(a, b) }
5541}
5542#[doc = "Floating-point compare greater than"]
5543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
5544#[inline]
5545#[target_feature(enable = "neon")]
5546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5547#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5548#[cfg_attr(
5549 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5550 assert_instr(fcmgt)
5551)]
5552#[cfg_attr(
5553 not(target_arch = "arm"),
5554 stable(feature = "neon_intrinsics", since = "1.59.0")
5555)]
5556#[cfg_attr(
5557 target_arch = "arm",
5558 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5559)]
5560pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5561 unsafe { simd_gt(a, b) }
5562}
5563#[doc = "Floating-point compare greater than"]
5564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
5565#[inline]
5566#[target_feature(enable = "neon")]
5567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
5569#[cfg_attr(
5570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5571 assert_instr(fcmgt)
5572)]
5573#[cfg_attr(
5574 not(target_arch = "arm"),
5575 stable(feature = "neon_intrinsics", since = "1.59.0")
5576)]
5577#[cfg_attr(
5578 target_arch = "arm",
5579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5580)]
5581pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5582 unsafe { simd_gt(a, b) }
5583}
5584#[doc = "Compare signed greater than"]
5585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
5586#[inline]
5587#[target_feature(enable = "neon")]
5588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5589#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5590#[cfg_attr(
5591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5592 assert_instr(cmgt)
5593)]
5594#[cfg_attr(
5595 not(target_arch = "arm"),
5596 stable(feature = "neon_intrinsics", since = "1.59.0")
5597)]
5598#[cfg_attr(
5599 target_arch = "arm",
5600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5601)]
5602pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5603 unsafe { simd_gt(a, b) }
5604}
5605#[doc = "Compare signed greater than"]
5606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
5607#[inline]
5608#[target_feature(enable = "neon")]
5609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5610#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
5611#[cfg_attr(
5612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5613 assert_instr(cmgt)
5614)]
5615#[cfg_attr(
5616 not(target_arch = "arm"),
5617 stable(feature = "neon_intrinsics", since = "1.59.0")
5618)]
5619#[cfg_attr(
5620 target_arch = "arm",
5621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5622)]
5623pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5624 unsafe { simd_gt(a, b) }
5625}
5626#[doc = "Compare signed greater than"]
5627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
5628#[inline]
5629#[target_feature(enable = "neon")]
5630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5631#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5632#[cfg_attr(
5633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5634 assert_instr(cmgt)
5635)]
5636#[cfg_attr(
5637 not(target_arch = "arm"),
5638 stable(feature = "neon_intrinsics", since = "1.59.0")
5639)]
5640#[cfg_attr(
5641 target_arch = "arm",
5642 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5643)]
5644pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5645 unsafe { simd_gt(a, b) }
5646}
5647#[doc = "Compare signed greater than"]
5648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
5649#[inline]
5650#[target_feature(enable = "neon")]
5651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5652#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
5653#[cfg_attr(
5654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5655 assert_instr(cmgt)
5656)]
5657#[cfg_attr(
5658 not(target_arch = "arm"),
5659 stable(feature = "neon_intrinsics", since = "1.59.0")
5660)]
5661#[cfg_attr(
5662 target_arch = "arm",
5663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5664)]
5665pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
5666 unsafe { simd_gt(a, b) }
5667}
5668#[doc = "Compare signed greater than"]
5669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
5670#[inline]
5671#[target_feature(enable = "neon")]
5672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5673#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5674#[cfg_attr(
5675 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5676 assert_instr(cmgt)
5677)]
5678#[cfg_attr(
5679 not(target_arch = "arm"),
5680 stable(feature = "neon_intrinsics", since = "1.59.0")
5681)]
5682#[cfg_attr(
5683 target_arch = "arm",
5684 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5685)]
5686pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
5687 unsafe { simd_gt(a, b) }
5688}
5689#[doc = "Compare signed greater than"]
5690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
5691#[inline]
5692#[target_feature(enable = "neon")]
5693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5694#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
5695#[cfg_attr(
5696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5697 assert_instr(cmgt)
5698)]
5699#[cfg_attr(
5700 not(target_arch = "arm"),
5701 stable(feature = "neon_intrinsics", since = "1.59.0")
5702)]
5703#[cfg_attr(
5704 target_arch = "arm",
5705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5706)]
5707pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
5708 unsafe { simd_gt(a, b) }
5709}
5710#[doc = "Compare unsigned greater than"]
5711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
5712#[inline]
5713#[target_feature(enable = "neon")]
5714#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5715#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5716#[cfg_attr(
5717 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5718 assert_instr(cmhi)
5719)]
5720#[cfg_attr(
5721 not(target_arch = "arm"),
5722 stable(feature = "neon_intrinsics", since = "1.59.0")
5723)]
5724#[cfg_attr(
5725 target_arch = "arm",
5726 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5727)]
5728pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
5729 unsafe { simd_gt(a, b) }
5730}
5731#[doc = "Compare unsigned greater than"]
5732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
5733#[inline]
5734#[target_feature(enable = "neon")]
5735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
5737#[cfg_attr(
5738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5739 assert_instr(cmhi)
5740)]
5741#[cfg_attr(
5742 not(target_arch = "arm"),
5743 stable(feature = "neon_intrinsics", since = "1.59.0")
5744)]
5745#[cfg_attr(
5746 target_arch = "arm",
5747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5748)]
5749pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
5750 unsafe { simd_gt(a, b) }
5751}
5752#[doc = "Compare unsigned greater than"]
5753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
5754#[inline]
5755#[target_feature(enable = "neon")]
5756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5757#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5758#[cfg_attr(
5759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5760 assert_instr(cmhi)
5761)]
5762#[cfg_attr(
5763 not(target_arch = "arm"),
5764 stable(feature = "neon_intrinsics", since = "1.59.0")
5765)]
5766#[cfg_attr(
5767 target_arch = "arm",
5768 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5769)]
5770pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
5771 unsafe { simd_gt(a, b) }
5772}
5773#[doc = "Compare unsigned greater than"]
5774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
5775#[inline]
5776#[target_feature(enable = "neon")]
5777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5778#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
5779#[cfg_attr(
5780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5781 assert_instr(cmhi)
5782)]
5783#[cfg_attr(
5784 not(target_arch = "arm"),
5785 stable(feature = "neon_intrinsics", since = "1.59.0")
5786)]
5787#[cfg_attr(
5788 target_arch = "arm",
5789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5790)]
5791pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
5792 unsafe { simd_gt(a, b) }
5793}
5794#[doc = "Compare unsigned greater than"]
5795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
5796#[inline]
5797#[target_feature(enable = "neon")]
5798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5799#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5800#[cfg_attr(
5801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5802 assert_instr(cmhi)
5803)]
5804#[cfg_attr(
5805 not(target_arch = "arm"),
5806 stable(feature = "neon_intrinsics", since = "1.59.0")
5807)]
5808#[cfg_attr(
5809 target_arch = "arm",
5810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5811)]
5812pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
5813 unsafe { simd_gt(a, b) }
5814}
5815#[doc = "Compare unsigned greater than"]
5816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
5817#[inline]
5818#[target_feature(enable = "neon")]
5819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5820#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
5821#[cfg_attr(
5822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5823 assert_instr(cmhi)
5824)]
5825#[cfg_attr(
5826 not(target_arch = "arm"),
5827 stable(feature = "neon_intrinsics", since = "1.59.0")
5828)]
5829#[cfg_attr(
5830 target_arch = "arm",
5831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5832)]
5833pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
5834 unsafe { simd_gt(a, b) }
5835}
5836#[doc = "Floating-point compare greater than zero"]
5837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
5838#[inline]
5839#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5841#[cfg_attr(
5842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5843 assert_instr(fcmgt)
5844)]
5845#[target_feature(enable = "neon,fp16")]
5846#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5847pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
5848 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
5849 unsafe { simd_gt(a, transmute(b)) }
5850}
5851#[doc = "Floating-point compare greater than zero"]
5852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
5853#[inline]
5854#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5855#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
5856#[cfg_attr(
5857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5858 assert_instr(fcmgt)
5859)]
5860#[target_feature(enable = "neon,fp16")]
5861#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5862pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
5863 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
5864 unsafe { simd_gt(a, transmute(b)) }
5865}
5866#[doc = "Floating-point compare less than or equal"]
5867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
5868#[inline]
5869#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5870#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5871#[cfg_attr(
5872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5873 assert_instr(fcmge)
5874)]
5875#[target_feature(enable = "neon,fp16")]
5876#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5877pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
5878 unsafe { simd_le(a, b) }
5879}
5880#[doc = "Floating-point compare less than or equal"]
5881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
5882#[inline]
5883#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
5884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
5885#[cfg_attr(
5886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5887 assert_instr(fcmge)
5888)]
5889#[target_feature(enable = "neon,fp16")]
5890#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
5891pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
5892 unsafe { simd_le(a, b) }
5893}
5894#[doc = "Floating-point compare less than or equal"]
5895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
5896#[inline]
5897#[target_feature(enable = "neon")]
5898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5899#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5900#[cfg_attr(
5901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5902 assert_instr(fcmge)
5903)]
5904#[cfg_attr(
5905 not(target_arch = "arm"),
5906 stable(feature = "neon_intrinsics", since = "1.59.0")
5907)]
5908#[cfg_attr(
5909 target_arch = "arm",
5910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5911)]
5912pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
5913 unsafe { simd_le(a, b) }
5914}
5915#[doc = "Floating-point compare less than or equal"]
5916#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
5917#[inline]
5918#[target_feature(enable = "neon")]
5919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5920#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
5921#[cfg_attr(
5922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5923 assert_instr(fcmge)
5924)]
5925#[cfg_attr(
5926 not(target_arch = "arm"),
5927 stable(feature = "neon_intrinsics", since = "1.59.0")
5928)]
5929#[cfg_attr(
5930 target_arch = "arm",
5931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5932)]
5933pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
5934 unsafe { simd_le(a, b) }
5935}
5936#[doc = "Compare signed less than or equal"]
5937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
5938#[inline]
5939#[target_feature(enable = "neon")]
5940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5941#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5942#[cfg_attr(
5943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5944 assert_instr(cmge)
5945)]
5946#[cfg_attr(
5947 not(target_arch = "arm"),
5948 stable(feature = "neon_intrinsics", since = "1.59.0")
5949)]
5950#[cfg_attr(
5951 target_arch = "arm",
5952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5953)]
5954pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
5955 unsafe { simd_le(a, b) }
5956}
5957#[doc = "Compare signed less than or equal"]
5958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
5959#[inline]
5960#[target_feature(enable = "neon")]
5961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5962#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
5963#[cfg_attr(
5964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5965 assert_instr(cmge)
5966)]
5967#[cfg_attr(
5968 not(target_arch = "arm"),
5969 stable(feature = "neon_intrinsics", since = "1.59.0")
5970)]
5971#[cfg_attr(
5972 target_arch = "arm",
5973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5974)]
5975pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
5976 unsafe { simd_le(a, b) }
5977}
5978#[doc = "Compare signed less than or equal"]
5979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
5980#[inline]
5981#[target_feature(enable = "neon")]
5982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
5983#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
5984#[cfg_attr(
5985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
5986 assert_instr(cmge)
5987)]
5988#[cfg_attr(
5989 not(target_arch = "arm"),
5990 stable(feature = "neon_intrinsics", since = "1.59.0")
5991)]
5992#[cfg_attr(
5993 target_arch = "arm",
5994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
5995)]
5996pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
5997 unsafe { simd_le(a, b) }
5998}
5999#[doc = "Compare signed less than or equal"]
6000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
6001#[inline]
6002#[target_feature(enable = "neon")]
6003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6004#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
6005#[cfg_attr(
6006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6007 assert_instr(cmge)
6008)]
6009#[cfg_attr(
6010 not(target_arch = "arm"),
6011 stable(feature = "neon_intrinsics", since = "1.59.0")
6012)]
6013#[cfg_attr(
6014 target_arch = "arm",
6015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6016)]
6017pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6018 unsafe { simd_le(a, b) }
6019}
6020#[doc = "Compare signed less than or equal"]
6021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
6022#[inline]
6023#[target_feature(enable = "neon")]
6024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6025#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6026#[cfg_attr(
6027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6028 assert_instr(cmge)
6029)]
6030#[cfg_attr(
6031 not(target_arch = "arm"),
6032 stable(feature = "neon_intrinsics", since = "1.59.0")
6033)]
6034#[cfg_attr(
6035 target_arch = "arm",
6036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6037)]
6038pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6039 unsafe { simd_le(a, b) }
6040}
6041#[doc = "Compare signed less than or equal"]
6042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
6043#[inline]
6044#[target_feature(enable = "neon")]
6045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6046#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
6047#[cfg_attr(
6048 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6049 assert_instr(cmge)
6050)]
6051#[cfg_attr(
6052 not(target_arch = "arm"),
6053 stable(feature = "neon_intrinsics", since = "1.59.0")
6054)]
6055#[cfg_attr(
6056 target_arch = "arm",
6057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6058)]
6059pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6060 unsafe { simd_le(a, b) }
6061}
6062#[doc = "Compare unsigned less than or equal"]
6063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
6064#[inline]
6065#[target_feature(enable = "neon")]
6066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6067#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6068#[cfg_attr(
6069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6070 assert_instr(cmhs)
6071)]
6072#[cfg_attr(
6073 not(target_arch = "arm"),
6074 stable(feature = "neon_intrinsics", since = "1.59.0")
6075)]
6076#[cfg_attr(
6077 target_arch = "arm",
6078 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6079)]
6080pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6081 unsafe { simd_le(a, b) }
6082}
6083#[doc = "Compare unsigned less than or equal"]
6084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
6085#[inline]
6086#[target_feature(enable = "neon")]
6087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6088#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
6089#[cfg_attr(
6090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6091 assert_instr(cmhs)
6092)]
6093#[cfg_attr(
6094 not(target_arch = "arm"),
6095 stable(feature = "neon_intrinsics", since = "1.59.0")
6096)]
6097#[cfg_attr(
6098 target_arch = "arm",
6099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6100)]
6101pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6102 unsafe { simd_le(a, b) }
6103}
6104#[doc = "Compare unsigned less than or equal"]
6105#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
6106#[inline]
6107#[target_feature(enable = "neon")]
6108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6109#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6110#[cfg_attr(
6111 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6112 assert_instr(cmhs)
6113)]
6114#[cfg_attr(
6115 not(target_arch = "arm"),
6116 stable(feature = "neon_intrinsics", since = "1.59.0")
6117)]
6118#[cfg_attr(
6119 target_arch = "arm",
6120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6121)]
6122pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6123 unsafe { simd_le(a, b) }
6124}
6125#[doc = "Compare unsigned less than or equal"]
6126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
6127#[inline]
6128#[target_feature(enable = "neon")]
6129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6130#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
6131#[cfg_attr(
6132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6133 assert_instr(cmhs)
6134)]
6135#[cfg_attr(
6136 not(target_arch = "arm"),
6137 stable(feature = "neon_intrinsics", since = "1.59.0")
6138)]
6139#[cfg_attr(
6140 target_arch = "arm",
6141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6142)]
6143pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6144 unsafe { simd_le(a, b) }
6145}
6146#[doc = "Compare unsigned less than or equal"]
6147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
6148#[inline]
6149#[target_feature(enable = "neon")]
6150#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6151#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6152#[cfg_attr(
6153 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6154 assert_instr(cmhs)
6155)]
6156#[cfg_attr(
6157 not(target_arch = "arm"),
6158 stable(feature = "neon_intrinsics", since = "1.59.0")
6159)]
6160#[cfg_attr(
6161 target_arch = "arm",
6162 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6163)]
6164pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6165 unsafe { simd_le(a, b) }
6166}
6167#[doc = "Compare unsigned less than or equal"]
6168#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
6169#[inline]
6170#[target_feature(enable = "neon")]
6171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6172#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
6173#[cfg_attr(
6174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6175 assert_instr(cmhs)
6176)]
6177#[cfg_attr(
6178 not(target_arch = "arm"),
6179 stable(feature = "neon_intrinsics", since = "1.59.0")
6180)]
6181#[cfg_attr(
6182 target_arch = "arm",
6183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6184)]
6185pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6186 unsafe { simd_le(a, b) }
6187}
6188#[doc = "Floating-point compare less than or equal to zero"]
6189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
6190#[inline]
6191#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6193#[cfg_attr(
6194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6195 assert_instr(fcmle)
6196)]
6197#[target_feature(enable = "neon,fp16")]
6198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6199pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
6200 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6201 unsafe { simd_le(a, transmute(b)) }
6202}
6203#[doc = "Floating-point compare less than or equal to zero"]
6204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
6205#[inline]
6206#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6207#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
6208#[cfg_attr(
6209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6210 assert_instr(fcmle)
6211)]
6212#[target_feature(enable = "neon,fp16")]
6213#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6214pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
6215 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6216 unsafe { simd_le(a, transmute(b)) }
6217}
6218#[doc = "Count leading sign bits"]
6219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
6220#[inline]
6221#[target_feature(enable = "neon")]
6222#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6223#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6224#[cfg_attr(
6225 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6226 assert_instr(cls)
6227)]
6228#[cfg_attr(
6229 not(target_arch = "arm"),
6230 stable(feature = "neon_intrinsics", since = "1.59.0")
6231)]
6232#[cfg_attr(
6233 target_arch = "arm",
6234 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6235)]
6236pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
6237 unsafe extern "unadjusted" {
6238 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")]
6239 #[cfg_attr(
6240 any(target_arch = "aarch64", target_arch = "arm64ec"),
6241 link_name = "llvm.aarch64.neon.cls.v8i8"
6242 )]
6243 fn _vcls_s8(a: int8x8_t) -> int8x8_t;
6244 }
6245 unsafe { _vcls_s8(a) }
6246}
6247#[doc = "Count leading sign bits"]
6248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
6249#[inline]
6250#[target_feature(enable = "neon")]
6251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6252#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
6253#[cfg_attr(
6254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6255 assert_instr(cls)
6256)]
6257#[cfg_attr(
6258 not(target_arch = "arm"),
6259 stable(feature = "neon_intrinsics", since = "1.59.0")
6260)]
6261#[cfg_attr(
6262 target_arch = "arm",
6263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6264)]
6265pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
6266 unsafe extern "unadjusted" {
6267 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")]
6268 #[cfg_attr(
6269 any(target_arch = "aarch64", target_arch = "arm64ec"),
6270 link_name = "llvm.aarch64.neon.cls.v16i8"
6271 )]
6272 fn _vclsq_s8(a: int8x16_t) -> int8x16_t;
6273 }
6274 unsafe { _vclsq_s8(a) }
6275}
6276#[doc = "Count leading sign bits"]
6277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
6278#[inline]
6279#[target_feature(enable = "neon")]
6280#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6281#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6282#[cfg_attr(
6283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6284 assert_instr(cls)
6285)]
6286#[cfg_attr(
6287 not(target_arch = "arm"),
6288 stable(feature = "neon_intrinsics", since = "1.59.0")
6289)]
6290#[cfg_attr(
6291 target_arch = "arm",
6292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6293)]
6294pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
6295 unsafe extern "unadjusted" {
6296 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")]
6297 #[cfg_attr(
6298 any(target_arch = "aarch64", target_arch = "arm64ec"),
6299 link_name = "llvm.aarch64.neon.cls.v4i16"
6300 )]
6301 fn _vcls_s16(a: int16x4_t) -> int16x4_t;
6302 }
6303 unsafe { _vcls_s16(a) }
6304}
6305#[doc = "Count leading sign bits"]
6306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
6307#[inline]
6308#[target_feature(enable = "neon")]
6309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
6311#[cfg_attr(
6312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6313 assert_instr(cls)
6314)]
6315#[cfg_attr(
6316 not(target_arch = "arm"),
6317 stable(feature = "neon_intrinsics", since = "1.59.0")
6318)]
6319#[cfg_attr(
6320 target_arch = "arm",
6321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6322)]
6323pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
6324 unsafe extern "unadjusted" {
6325 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")]
6326 #[cfg_attr(
6327 any(target_arch = "aarch64", target_arch = "arm64ec"),
6328 link_name = "llvm.aarch64.neon.cls.v8i16"
6329 )]
6330 fn _vclsq_s16(a: int16x8_t) -> int16x8_t;
6331 }
6332 unsafe { _vclsq_s16(a) }
6333}
6334#[doc = "Count leading sign bits"]
6335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
6336#[inline]
6337#[target_feature(enable = "neon")]
6338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6339#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6340#[cfg_attr(
6341 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6342 assert_instr(cls)
6343)]
6344#[cfg_attr(
6345 not(target_arch = "arm"),
6346 stable(feature = "neon_intrinsics", since = "1.59.0")
6347)]
6348#[cfg_attr(
6349 target_arch = "arm",
6350 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6351)]
6352pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
6353 unsafe extern "unadjusted" {
6354 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")]
6355 #[cfg_attr(
6356 any(target_arch = "aarch64", target_arch = "arm64ec"),
6357 link_name = "llvm.aarch64.neon.cls.v2i32"
6358 )]
6359 fn _vcls_s32(a: int32x2_t) -> int32x2_t;
6360 }
6361 unsafe { _vcls_s32(a) }
6362}
6363#[doc = "Count leading sign bits"]
6364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
6365#[inline]
6366#[target_feature(enable = "neon")]
6367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6368#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
6369#[cfg_attr(
6370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6371 assert_instr(cls)
6372)]
6373#[cfg_attr(
6374 not(target_arch = "arm"),
6375 stable(feature = "neon_intrinsics", since = "1.59.0")
6376)]
6377#[cfg_attr(
6378 target_arch = "arm",
6379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6380)]
6381pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
6382 unsafe extern "unadjusted" {
6383 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")]
6384 #[cfg_attr(
6385 any(target_arch = "aarch64", target_arch = "arm64ec"),
6386 link_name = "llvm.aarch64.neon.cls.v4i32"
6387 )]
6388 fn _vclsq_s32(a: int32x4_t) -> int32x4_t;
6389 }
6390 unsafe { _vclsq_s32(a) }
6391}
6392#[doc = "Count leading sign bits"]
6393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
6394#[inline]
6395#[target_feature(enable = "neon")]
6396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6398#[cfg_attr(
6399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6400 assert_instr(cls)
6401)]
6402#[cfg_attr(
6403 not(target_arch = "arm"),
6404 stable(feature = "neon_intrinsics", since = "1.59.0")
6405)]
6406#[cfg_attr(
6407 target_arch = "arm",
6408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6409)]
6410pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
6411 unsafe { vcls_s8(transmute(a)) }
6412}
6413#[doc = "Count leading sign bits"]
6414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
6415#[inline]
6416#[target_feature(enable = "neon")]
6417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6419#[cfg_attr(
6420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6421 assert_instr(cls)
6422)]
6423#[cfg_attr(
6424 not(target_arch = "arm"),
6425 stable(feature = "neon_intrinsics", since = "1.59.0")
6426)]
6427#[cfg_attr(
6428 target_arch = "arm",
6429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6430)]
6431pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
6432 unsafe { vclsq_s8(transmute(a)) }
6433}
6434#[doc = "Count leading sign bits"]
6435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
6436#[inline]
6437#[target_feature(enable = "neon")]
6438#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6439#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6440#[cfg_attr(
6441 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6442 assert_instr(cls)
6443)]
6444#[cfg_attr(
6445 not(target_arch = "arm"),
6446 stable(feature = "neon_intrinsics", since = "1.59.0")
6447)]
6448#[cfg_attr(
6449 target_arch = "arm",
6450 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6451)]
6452pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
6453 unsafe { vcls_s16(transmute(a)) }
6454}
6455#[doc = "Count leading sign bits"]
6456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
6457#[inline]
6458#[target_feature(enable = "neon")]
6459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6461#[cfg_attr(
6462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6463 assert_instr(cls)
6464)]
6465#[cfg_attr(
6466 not(target_arch = "arm"),
6467 stable(feature = "neon_intrinsics", since = "1.59.0")
6468)]
6469#[cfg_attr(
6470 target_arch = "arm",
6471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6472)]
6473pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
6474 unsafe { vclsq_s16(transmute(a)) }
6475}
6476#[doc = "Count leading sign bits"]
6477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
6478#[inline]
6479#[target_feature(enable = "neon")]
6480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6482#[cfg_attr(
6483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6484 assert_instr(cls)
6485)]
6486#[cfg_attr(
6487 not(target_arch = "arm"),
6488 stable(feature = "neon_intrinsics", since = "1.59.0")
6489)]
6490#[cfg_attr(
6491 target_arch = "arm",
6492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6493)]
6494pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
6495 unsafe { vcls_s32(transmute(a)) }
6496}
6497#[doc = "Count leading sign bits"]
6498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
6499#[inline]
6500#[target_feature(enable = "neon")]
6501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
6503#[cfg_attr(
6504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6505 assert_instr(cls)
6506)]
6507#[cfg_attr(
6508 not(target_arch = "arm"),
6509 stable(feature = "neon_intrinsics", since = "1.59.0")
6510)]
6511#[cfg_attr(
6512 target_arch = "arm",
6513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6514)]
6515pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
6516 unsafe { vclsq_s32(transmute(a)) }
6517}
6518#[doc = "Floating-point compare less than"]
6519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
6520#[inline]
6521#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6523#[cfg_attr(
6524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6525 assert_instr(fcmgt)
6526)]
6527#[target_feature(enable = "neon,fp16")]
6528#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6529pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
6530 unsafe { simd_lt(a, b) }
6531}
6532#[doc = "Floating-point compare less than"]
6533#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
6534#[inline]
6535#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6536#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
6537#[cfg_attr(
6538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6539 assert_instr(fcmgt)
6540)]
6541#[target_feature(enable = "neon,fp16")]
6542#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6543pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
6544 unsafe { simd_lt(a, b) }
6545}
6546#[doc = "Floating-point compare less than"]
6547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
6548#[inline]
6549#[target_feature(enable = "neon")]
6550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6551#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6552#[cfg_attr(
6553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6554 assert_instr(fcmgt)
6555)]
6556#[cfg_attr(
6557 not(target_arch = "arm"),
6558 stable(feature = "neon_intrinsics", since = "1.59.0")
6559)]
6560#[cfg_attr(
6561 target_arch = "arm",
6562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6563)]
6564pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
6565 unsafe { simd_lt(a, b) }
6566}
6567#[doc = "Floating-point compare less than"]
6568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
6569#[inline]
6570#[target_feature(enable = "neon")]
6571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6572#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
6573#[cfg_attr(
6574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6575 assert_instr(fcmgt)
6576)]
6577#[cfg_attr(
6578 not(target_arch = "arm"),
6579 stable(feature = "neon_intrinsics", since = "1.59.0")
6580)]
6581#[cfg_attr(
6582 target_arch = "arm",
6583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6584)]
6585pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
6586 unsafe { simd_lt(a, b) }
6587}
6588#[doc = "Compare signed less than"]
6589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
6590#[inline]
6591#[target_feature(enable = "neon")]
6592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6593#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6594#[cfg_attr(
6595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6596 assert_instr(cmgt)
6597)]
6598#[cfg_attr(
6599 not(target_arch = "arm"),
6600 stable(feature = "neon_intrinsics", since = "1.59.0")
6601)]
6602#[cfg_attr(
6603 target_arch = "arm",
6604 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6605)]
6606pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
6607 unsafe { simd_lt(a, b) }
6608}
6609#[doc = "Compare signed less than"]
6610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
6611#[inline]
6612#[target_feature(enable = "neon")]
6613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
6615#[cfg_attr(
6616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6617 assert_instr(cmgt)
6618)]
6619#[cfg_attr(
6620 not(target_arch = "arm"),
6621 stable(feature = "neon_intrinsics", since = "1.59.0")
6622)]
6623#[cfg_attr(
6624 target_arch = "arm",
6625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6626)]
6627pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
6628 unsafe { simd_lt(a, b) }
6629}
6630#[doc = "Compare signed less than"]
6631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
6632#[inline]
6633#[target_feature(enable = "neon")]
6634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6636#[cfg_attr(
6637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6638 assert_instr(cmgt)
6639)]
6640#[cfg_attr(
6641 not(target_arch = "arm"),
6642 stable(feature = "neon_intrinsics", since = "1.59.0")
6643)]
6644#[cfg_attr(
6645 target_arch = "arm",
6646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6647)]
6648pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
6649 unsafe { simd_lt(a, b) }
6650}
6651#[doc = "Compare signed less than"]
6652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
6653#[inline]
6654#[target_feature(enable = "neon")]
6655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6656#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
6657#[cfg_attr(
6658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6659 assert_instr(cmgt)
6660)]
6661#[cfg_attr(
6662 not(target_arch = "arm"),
6663 stable(feature = "neon_intrinsics", since = "1.59.0")
6664)]
6665#[cfg_attr(
6666 target_arch = "arm",
6667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6668)]
6669pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
6670 unsafe { simd_lt(a, b) }
6671}
6672#[doc = "Compare signed less than"]
6673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
6674#[inline]
6675#[target_feature(enable = "neon")]
6676#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6677#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6678#[cfg_attr(
6679 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6680 assert_instr(cmgt)
6681)]
6682#[cfg_attr(
6683 not(target_arch = "arm"),
6684 stable(feature = "neon_intrinsics", since = "1.59.0")
6685)]
6686#[cfg_attr(
6687 target_arch = "arm",
6688 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6689)]
6690pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
6691 unsafe { simd_lt(a, b) }
6692}
6693#[doc = "Compare signed less than"]
6694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
6695#[inline]
6696#[target_feature(enable = "neon")]
6697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6698#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
6699#[cfg_attr(
6700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6701 assert_instr(cmgt)
6702)]
6703#[cfg_attr(
6704 not(target_arch = "arm"),
6705 stable(feature = "neon_intrinsics", since = "1.59.0")
6706)]
6707#[cfg_attr(
6708 target_arch = "arm",
6709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6710)]
6711pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
6712 unsafe { simd_lt(a, b) }
6713}
6714#[doc = "Compare unsigned less than"]
6715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
6716#[inline]
6717#[target_feature(enable = "neon")]
6718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6720#[cfg_attr(
6721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6722 assert_instr(cmhi)
6723)]
6724#[cfg_attr(
6725 not(target_arch = "arm"),
6726 stable(feature = "neon_intrinsics", since = "1.59.0")
6727)]
6728#[cfg_attr(
6729 target_arch = "arm",
6730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6731)]
6732pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
6733 unsafe { simd_lt(a, b) }
6734}
6735#[doc = "Compare unsigned less than"]
6736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
6737#[inline]
6738#[target_feature(enable = "neon")]
6739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6740#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
6741#[cfg_attr(
6742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6743 assert_instr(cmhi)
6744)]
6745#[cfg_attr(
6746 not(target_arch = "arm"),
6747 stable(feature = "neon_intrinsics", since = "1.59.0")
6748)]
6749#[cfg_attr(
6750 target_arch = "arm",
6751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6752)]
6753pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
6754 unsafe { simd_lt(a, b) }
6755}
6756#[doc = "Compare unsigned less than"]
6757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
6758#[inline]
6759#[target_feature(enable = "neon")]
6760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6761#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6762#[cfg_attr(
6763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6764 assert_instr(cmhi)
6765)]
6766#[cfg_attr(
6767 not(target_arch = "arm"),
6768 stable(feature = "neon_intrinsics", since = "1.59.0")
6769)]
6770#[cfg_attr(
6771 target_arch = "arm",
6772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6773)]
6774pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
6775 unsafe { simd_lt(a, b) }
6776}
6777#[doc = "Compare unsigned less than"]
6778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
6779#[inline]
6780#[target_feature(enable = "neon")]
6781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6782#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
6783#[cfg_attr(
6784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6785 assert_instr(cmhi)
6786)]
6787#[cfg_attr(
6788 not(target_arch = "arm"),
6789 stable(feature = "neon_intrinsics", since = "1.59.0")
6790)]
6791#[cfg_attr(
6792 target_arch = "arm",
6793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6794)]
6795pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
6796 unsafe { simd_lt(a, b) }
6797}
6798#[doc = "Compare unsigned less than"]
6799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
6800#[inline]
6801#[target_feature(enable = "neon")]
6802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6803#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6804#[cfg_attr(
6805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6806 assert_instr(cmhi)
6807)]
6808#[cfg_attr(
6809 not(target_arch = "arm"),
6810 stable(feature = "neon_intrinsics", since = "1.59.0")
6811)]
6812#[cfg_attr(
6813 target_arch = "arm",
6814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6815)]
6816pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
6817 unsafe { simd_lt(a, b) }
6818}
6819#[doc = "Compare unsigned less than"]
6820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
6821#[inline]
6822#[target_feature(enable = "neon")]
6823#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6824#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
6825#[cfg_attr(
6826 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6827 assert_instr(cmhi)
6828)]
6829#[cfg_attr(
6830 not(target_arch = "arm"),
6831 stable(feature = "neon_intrinsics", since = "1.59.0")
6832)]
6833#[cfg_attr(
6834 target_arch = "arm",
6835 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6836)]
6837pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
6838 unsafe { simd_lt(a, b) }
6839}
6840#[doc = "Floating-point compare less than"]
6841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
6842#[inline]
6843#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6844#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6845#[cfg_attr(
6846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6847 assert_instr(fcmlt)
6848)]
6849#[target_feature(enable = "neon,fp16")]
6850#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6851pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
6852 let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0);
6853 unsafe { simd_lt(a, transmute(b)) }
6854}
6855#[doc = "Floating-point compare less than"]
6856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
6857#[inline]
6858#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
6859#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
6860#[cfg_attr(
6861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6862 assert_instr(fcmlt)
6863)]
6864#[target_feature(enable = "neon,fp16")]
6865#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
6866pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
6867 let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0);
6868 unsafe { simd_lt(a, transmute(b)) }
6869}
6870#[doc = "Count leading zero bits"]
6871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
6872#[inline]
6873#[target_feature(enable = "neon")]
6874#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6875#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6876#[cfg_attr(
6877 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6878 assert_instr(clz)
6879)]
6880#[cfg_attr(
6881 not(target_arch = "arm"),
6882 stable(feature = "neon_intrinsics", since = "1.59.0")
6883)]
6884#[cfg_attr(
6885 target_arch = "arm",
6886 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6887)]
6888pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
6889 unsafe { simd_ctlz(a) }
6890}
6891#[doc = "Count leading zero bits"]
6892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
6893#[inline]
6894#[target_feature(enable = "neon")]
6895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6896#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
6897#[cfg_attr(
6898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6899 assert_instr(clz)
6900)]
6901#[cfg_attr(
6902 not(target_arch = "arm"),
6903 stable(feature = "neon_intrinsics", since = "1.59.0")
6904)]
6905#[cfg_attr(
6906 target_arch = "arm",
6907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6908)]
6909pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
6910 unsafe { simd_ctlz(a) }
6911}
6912#[doc = "Count leading zero bits"]
6913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
6914#[inline]
6915#[target_feature(enable = "neon")]
6916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6917#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6918#[cfg_attr(
6919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6920 assert_instr(clz)
6921)]
6922#[cfg_attr(
6923 not(target_arch = "arm"),
6924 stable(feature = "neon_intrinsics", since = "1.59.0")
6925)]
6926#[cfg_attr(
6927 target_arch = "arm",
6928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6929)]
6930pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
6931 unsafe { simd_ctlz(a) }
6932}
6933#[doc = "Count leading zero bits"]
6934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
6935#[inline]
6936#[target_feature(enable = "neon")]
6937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6938#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
6939#[cfg_attr(
6940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6941 assert_instr(clz)
6942)]
6943#[cfg_attr(
6944 not(target_arch = "arm"),
6945 stable(feature = "neon_intrinsics", since = "1.59.0")
6946)]
6947#[cfg_attr(
6948 target_arch = "arm",
6949 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6950)]
6951pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
6952 unsafe { simd_ctlz(a) }
6953}
6954#[doc = "Count leading zero bits"]
6955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
6956#[inline]
6957#[target_feature(enable = "neon")]
6958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
6960#[cfg_attr(
6961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6962 assert_instr(clz)
6963)]
6964#[cfg_attr(
6965 not(target_arch = "arm"),
6966 stable(feature = "neon_intrinsics", since = "1.59.0")
6967)]
6968#[cfg_attr(
6969 target_arch = "arm",
6970 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6971)]
6972pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
6973 unsafe { simd_ctlz(a) }
6974}
6975#[doc = "Count leading zero bits"]
6976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
6977#[inline]
6978#[target_feature(enable = "neon")]
6979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
6980#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
6981#[cfg_attr(
6982 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
6983 assert_instr(clz)
6984)]
6985#[cfg_attr(
6986 not(target_arch = "arm"),
6987 stable(feature = "neon_intrinsics", since = "1.59.0")
6988)]
6989#[cfg_attr(
6990 target_arch = "arm",
6991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
6992)]
6993pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
6994 unsafe { simd_ctlz(a) }
6995}
6996#[doc = "Count leading zero bits"]
6997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
6998#[inline]
6999#[cfg(target_endian = "little")]
7000#[target_feature(enable = "neon")]
7001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7002#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7003#[cfg_attr(
7004 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7005 assert_instr(clz)
7006)]
7007#[cfg_attr(
7008 not(target_arch = "arm"),
7009 stable(feature = "neon_intrinsics", since = "1.59.0")
7010)]
7011#[cfg_attr(
7012 target_arch = "arm",
7013 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7014)]
7015pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7016 unsafe { transmute(vclz_s16(transmute(a))) }
7017}
7018#[doc = "Count leading zero bits"]
7019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
7020#[inline]
7021#[cfg(target_endian = "big")]
7022#[target_feature(enable = "neon")]
7023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7024#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7025#[cfg_attr(
7026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7027 assert_instr(clz)
7028)]
7029#[cfg_attr(
7030 not(target_arch = "arm"),
7031 stable(feature = "neon_intrinsics", since = "1.59.0")
7032)]
7033#[cfg_attr(
7034 target_arch = "arm",
7035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7036)]
7037pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
7038 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7039 unsafe {
7040 let ret_val: uint16x4_t = transmute(vclz_s16(transmute(a)));
7041 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7042 }
7043}
7044#[doc = "Count leading zero bits"]
7045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7046#[inline]
7047#[cfg(target_endian = "little")]
7048#[target_feature(enable = "neon")]
7049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7050#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7051#[cfg_attr(
7052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7053 assert_instr(clz)
7054)]
7055#[cfg_attr(
7056 not(target_arch = "arm"),
7057 stable(feature = "neon_intrinsics", since = "1.59.0")
7058)]
7059#[cfg_attr(
7060 target_arch = "arm",
7061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7062)]
7063pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7064 unsafe { transmute(vclzq_s16(transmute(a))) }
7065}
7066#[doc = "Count leading zero bits"]
7067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
7068#[inline]
7069#[cfg(target_endian = "big")]
7070#[target_feature(enable = "neon")]
7071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7072#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
7073#[cfg_attr(
7074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7075 assert_instr(clz)
7076)]
7077#[cfg_attr(
7078 not(target_arch = "arm"),
7079 stable(feature = "neon_intrinsics", since = "1.59.0")
7080)]
7081#[cfg_attr(
7082 target_arch = "arm",
7083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7084)]
7085pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
7086 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7087 unsafe {
7088 let ret_val: uint16x8_t = transmute(vclzq_s16(transmute(a)));
7089 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7090 }
7091}
7092#[doc = "Count leading zero bits"]
7093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7094#[inline]
7095#[cfg(target_endian = "little")]
7096#[target_feature(enable = "neon")]
7097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7099#[cfg_attr(
7100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7101 assert_instr(clz)
7102)]
7103#[cfg_attr(
7104 not(target_arch = "arm"),
7105 stable(feature = "neon_intrinsics", since = "1.59.0")
7106)]
7107#[cfg_attr(
7108 target_arch = "arm",
7109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7110)]
7111pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7112 unsafe { transmute(vclz_s32(transmute(a))) }
7113}
7114#[doc = "Count leading zero bits"]
7115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
7116#[inline]
7117#[cfg(target_endian = "big")]
7118#[target_feature(enable = "neon")]
7119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7120#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7121#[cfg_attr(
7122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7123 assert_instr(clz)
7124)]
7125#[cfg_attr(
7126 not(target_arch = "arm"),
7127 stable(feature = "neon_intrinsics", since = "1.59.0")
7128)]
7129#[cfg_attr(
7130 target_arch = "arm",
7131 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7132)]
7133pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
7134 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
7135 unsafe {
7136 let ret_val: uint32x2_t = transmute(vclz_s32(transmute(a)));
7137 simd_shuffle!(ret_val, ret_val, [1, 0])
7138 }
7139}
7140#[doc = "Count leading zero bits"]
7141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7142#[inline]
7143#[cfg(target_endian = "little")]
7144#[target_feature(enable = "neon")]
7145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7146#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7147#[cfg_attr(
7148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7149 assert_instr(clz)
7150)]
7151#[cfg_attr(
7152 not(target_arch = "arm"),
7153 stable(feature = "neon_intrinsics", since = "1.59.0")
7154)]
7155#[cfg_attr(
7156 target_arch = "arm",
7157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7158)]
7159pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7160 unsafe { transmute(vclzq_s32(transmute(a))) }
7161}
7162#[doc = "Count leading zero bits"]
7163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
7164#[inline]
7165#[cfg(target_endian = "big")]
7166#[target_feature(enable = "neon")]
7167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
7169#[cfg_attr(
7170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7171 assert_instr(clz)
7172)]
7173#[cfg_attr(
7174 not(target_arch = "arm"),
7175 stable(feature = "neon_intrinsics", since = "1.59.0")
7176)]
7177#[cfg_attr(
7178 target_arch = "arm",
7179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7180)]
7181pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
7182 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
7183 unsafe {
7184 let ret_val: uint32x4_t = transmute(vclzq_s32(transmute(a)));
7185 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7186 }
7187}
7188#[doc = "Count leading zero bits"]
7189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7190#[inline]
7191#[cfg(target_endian = "little")]
7192#[target_feature(enable = "neon")]
7193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7194#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7195#[cfg_attr(
7196 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7197 assert_instr(clz)
7198)]
7199#[cfg_attr(
7200 not(target_arch = "arm"),
7201 stable(feature = "neon_intrinsics", since = "1.59.0")
7202)]
7203#[cfg_attr(
7204 target_arch = "arm",
7205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7206)]
7207pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7208 unsafe { transmute(vclz_s8(transmute(a))) }
7209}
7210#[doc = "Count leading zero bits"]
7211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
7212#[inline]
7213#[cfg(target_endian = "big")]
7214#[target_feature(enable = "neon")]
7215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7217#[cfg_attr(
7218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7219 assert_instr(clz)
7220)]
7221#[cfg_attr(
7222 not(target_arch = "arm"),
7223 stable(feature = "neon_intrinsics", since = "1.59.0")
7224)]
7225#[cfg_attr(
7226 target_arch = "arm",
7227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7228)]
7229pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
7230 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7231 unsafe {
7232 let ret_val: uint8x8_t = transmute(vclz_s8(transmute(a)));
7233 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7234 }
7235}
7236#[doc = "Count leading zero bits"]
7237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7238#[inline]
7239#[cfg(target_endian = "little")]
7240#[target_feature(enable = "neon")]
7241#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7242#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7243#[cfg_attr(
7244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7245 assert_instr(clz)
7246)]
7247#[cfg_attr(
7248 not(target_arch = "arm"),
7249 stable(feature = "neon_intrinsics", since = "1.59.0")
7250)]
7251#[cfg_attr(
7252 target_arch = "arm",
7253 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7254)]
7255pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7256 unsafe { transmute(vclzq_s8(transmute(a))) }
7257}
7258#[doc = "Count leading zero bits"]
7259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
7260#[inline]
7261#[cfg(target_endian = "big")]
7262#[target_feature(enable = "neon")]
7263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7264#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
7265#[cfg_attr(
7266 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7267 assert_instr(clz)
7268)]
7269#[cfg_attr(
7270 not(target_arch = "arm"),
7271 stable(feature = "neon_intrinsics", since = "1.59.0")
7272)]
7273#[cfg_attr(
7274 target_arch = "arm",
7275 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7276)]
7277pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
7278 let a: uint8x16_t =
7279 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7280 unsafe {
7281 let ret_val: uint8x16_t = transmute(vclzq_s8(transmute(a)));
7282 simd_shuffle!(
7283 ret_val,
7284 ret_val,
7285 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7286 )
7287 }
7288}
7289#[doc = "Population count per byte."]
7290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
7291#[inline]
7292#[target_feature(enable = "neon")]
7293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7295#[cfg_attr(
7296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7297 assert_instr(cnt)
7298)]
7299#[cfg_attr(
7300 not(target_arch = "arm"),
7301 stable(feature = "neon_intrinsics", since = "1.59.0")
7302)]
7303#[cfg_attr(
7304 target_arch = "arm",
7305 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7306)]
7307pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
7308 unsafe { simd_ctpop(a) }
7309}
7310#[doc = "Population count per byte."]
7311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
7312#[inline]
7313#[target_feature(enable = "neon")]
7314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7316#[cfg_attr(
7317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7318 assert_instr(cnt)
7319)]
7320#[cfg_attr(
7321 not(target_arch = "arm"),
7322 stable(feature = "neon_intrinsics", since = "1.59.0")
7323)]
7324#[cfg_attr(
7325 target_arch = "arm",
7326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7327)]
7328pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
7329 unsafe { simd_ctpop(a) }
7330}
7331#[doc = "Population count per byte."]
7332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7333#[inline]
7334#[cfg(target_endian = "little")]
7335#[target_feature(enable = "neon")]
7336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7338#[cfg_attr(
7339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7340 assert_instr(cnt)
7341)]
7342#[cfg_attr(
7343 not(target_arch = "arm"),
7344 stable(feature = "neon_intrinsics", since = "1.59.0")
7345)]
7346#[cfg_attr(
7347 target_arch = "arm",
7348 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7349)]
7350pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7351 unsafe { transmute(vcnt_s8(transmute(a))) }
7352}
7353#[doc = "Population count per byte."]
7354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
7355#[inline]
7356#[cfg(target_endian = "big")]
7357#[target_feature(enable = "neon")]
7358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7360#[cfg_attr(
7361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7362 assert_instr(cnt)
7363)]
7364#[cfg_attr(
7365 not(target_arch = "arm"),
7366 stable(feature = "neon_intrinsics", since = "1.59.0")
7367)]
7368#[cfg_attr(
7369 target_arch = "arm",
7370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7371)]
7372pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
7373 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7374 unsafe {
7375 let ret_val: uint8x8_t = transmute(vcnt_s8(transmute(a)));
7376 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7377 }
7378}
7379#[doc = "Population count per byte."]
7380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7381#[inline]
7382#[cfg(target_endian = "little")]
7383#[target_feature(enable = "neon")]
7384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7386#[cfg_attr(
7387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7388 assert_instr(cnt)
7389)]
7390#[cfg_attr(
7391 not(target_arch = "arm"),
7392 stable(feature = "neon_intrinsics", since = "1.59.0")
7393)]
7394#[cfg_attr(
7395 target_arch = "arm",
7396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7397)]
7398pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7399 unsafe { transmute(vcntq_s8(transmute(a))) }
7400}
7401#[doc = "Population count per byte."]
7402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
7403#[inline]
7404#[cfg(target_endian = "big")]
7405#[target_feature(enable = "neon")]
7406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7408#[cfg_attr(
7409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7410 assert_instr(cnt)
7411)]
7412#[cfg_attr(
7413 not(target_arch = "arm"),
7414 stable(feature = "neon_intrinsics", since = "1.59.0")
7415)]
7416#[cfg_attr(
7417 target_arch = "arm",
7418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7419)]
7420pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
7421 let a: uint8x16_t =
7422 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7423 unsafe {
7424 let ret_val: uint8x16_t = transmute(vcntq_s8(transmute(a)));
7425 simd_shuffle!(
7426 ret_val,
7427 ret_val,
7428 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7429 )
7430 }
7431}
7432#[doc = "Population count per byte."]
7433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7434#[inline]
7435#[cfg(target_endian = "little")]
7436#[target_feature(enable = "neon")]
7437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7439#[cfg_attr(
7440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7441 assert_instr(cnt)
7442)]
7443#[cfg_attr(
7444 not(target_arch = "arm"),
7445 stable(feature = "neon_intrinsics", since = "1.59.0")
7446)]
7447#[cfg_attr(
7448 target_arch = "arm",
7449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7450)]
7451pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7452 unsafe { transmute(vcnt_s8(transmute(a))) }
7453}
7454#[doc = "Population count per byte."]
7455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
7456#[inline]
7457#[cfg(target_endian = "big")]
7458#[target_feature(enable = "neon")]
7459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7461#[cfg_attr(
7462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7463 assert_instr(cnt)
7464)]
7465#[cfg_attr(
7466 not(target_arch = "arm"),
7467 stable(feature = "neon_intrinsics", since = "1.59.0")
7468)]
7469#[cfg_attr(
7470 target_arch = "arm",
7471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7472)]
7473pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
7474 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
7475 unsafe {
7476 let ret_val: poly8x8_t = transmute(vcnt_s8(transmute(a)));
7477 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7478 }
7479}
7480#[doc = "Population count per byte."]
7481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7482#[inline]
7483#[cfg(target_endian = "little")]
7484#[target_feature(enable = "neon")]
7485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7487#[cfg_attr(
7488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7489 assert_instr(cnt)
7490)]
7491#[cfg_attr(
7492 not(target_arch = "arm"),
7493 stable(feature = "neon_intrinsics", since = "1.59.0")
7494)]
7495#[cfg_attr(
7496 target_arch = "arm",
7497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7498)]
7499pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7500 unsafe { transmute(vcntq_s8(transmute(a))) }
7501}
7502#[doc = "Population count per byte."]
7503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
7504#[inline]
7505#[cfg(target_endian = "big")]
7506#[target_feature(enable = "neon")]
7507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
7509#[cfg_attr(
7510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7511 assert_instr(cnt)
7512)]
7513#[cfg_attr(
7514 not(target_arch = "arm"),
7515 stable(feature = "neon_intrinsics", since = "1.59.0")
7516)]
7517#[cfg_attr(
7518 target_arch = "arm",
7519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7520)]
7521pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
7522 let a: poly8x16_t =
7523 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
7524 unsafe {
7525 let ret_val: poly8x16_t = transmute(vcntq_s8(transmute(a)));
7526 simd_shuffle!(
7527 ret_val,
7528 ret_val,
7529 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
7530 )
7531 }
7532}
7533#[doc = "Join two smaller vectors into a single larger vector"]
7534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
7535#[inline]
7536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7537#[target_feature(enable = "neon,fp16")]
7538#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7539#[cfg_attr(test, assert_instr(nop))]
7540pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
7541 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7542}
7543#[doc = "Join two smaller vectors into a single larger vector"]
7544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
7545#[inline]
7546#[target_feature(enable = "neon")]
7547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7549#[cfg_attr(
7550 not(target_arch = "arm"),
7551 stable(feature = "neon_intrinsics", since = "1.59.0")
7552)]
7553#[cfg_attr(
7554 target_arch = "arm",
7555 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7556)]
7557pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
7558 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7559}
7560#[doc = "Join two smaller vectors into a single larger vector"]
7561#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
7562#[inline]
7563#[target_feature(enable = "neon")]
7564#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7565#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7566#[cfg_attr(
7567 not(target_arch = "arm"),
7568 stable(feature = "neon_intrinsics", since = "1.59.0")
7569)]
7570#[cfg_attr(
7571 target_arch = "arm",
7572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7573)]
7574pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
7575 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7576}
7577#[doc = "Join two smaller vectors into a single larger vector"]
7578#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
7579#[inline]
7580#[target_feature(enable = "neon")]
7581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7583#[cfg_attr(
7584 not(target_arch = "arm"),
7585 stable(feature = "neon_intrinsics", since = "1.59.0")
7586)]
7587#[cfg_attr(
7588 target_arch = "arm",
7589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7590)]
7591pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
7592 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7593}
7594#[doc = "Join two smaller vectors into a single larger vector"]
7595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
7596#[inline]
7597#[target_feature(enable = "neon")]
7598#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7599#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7600#[cfg_attr(
7601 not(target_arch = "arm"),
7602 stable(feature = "neon_intrinsics", since = "1.59.0")
7603)]
7604#[cfg_attr(
7605 target_arch = "arm",
7606 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7607)]
7608pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
7609 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7610}
7611#[doc = "Join two smaller vectors into a single larger vector"]
7612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
7613#[inline]
7614#[target_feature(enable = "neon")]
7615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7617#[cfg_attr(
7618 not(target_arch = "arm"),
7619 stable(feature = "neon_intrinsics", since = "1.59.0")
7620)]
7621#[cfg_attr(
7622 target_arch = "arm",
7623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7624)]
7625pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
7626 unsafe { simd_shuffle!(a, b, [0, 1]) }
7627}
7628#[doc = "Join two smaller vectors into a single larger vector"]
7629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
7630#[inline]
7631#[target_feature(enable = "neon")]
7632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7633#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7634#[cfg_attr(
7635 not(target_arch = "arm"),
7636 stable(feature = "neon_intrinsics", since = "1.59.0")
7637)]
7638#[cfg_attr(
7639 target_arch = "arm",
7640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7641)]
7642pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
7643 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7644}
7645#[doc = "Join two smaller vectors into a single larger vector"]
7646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
7647#[inline]
7648#[target_feature(enable = "neon")]
7649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7651#[cfg_attr(
7652 not(target_arch = "arm"),
7653 stable(feature = "neon_intrinsics", since = "1.59.0")
7654)]
7655#[cfg_attr(
7656 target_arch = "arm",
7657 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7658)]
7659pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
7660 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7661}
7662#[doc = "Join two smaller vectors into a single larger vector"]
7663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
7664#[inline]
7665#[target_feature(enable = "neon")]
7666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7668#[cfg_attr(
7669 not(target_arch = "arm"),
7670 stable(feature = "neon_intrinsics", since = "1.59.0")
7671)]
7672#[cfg_attr(
7673 target_arch = "arm",
7674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7675)]
7676pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
7677 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3]) }
7678}
7679#[doc = "Join two smaller vectors into a single larger vector"]
7680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
7681#[inline]
7682#[target_feature(enable = "neon")]
7683#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7684#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7685#[cfg_attr(
7686 not(target_arch = "arm"),
7687 stable(feature = "neon_intrinsics", since = "1.59.0")
7688)]
7689#[cfg_attr(
7690 target_arch = "arm",
7691 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7692)]
7693pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
7694 unsafe { simd_shuffle!(a, b, [0, 1]) }
7695}
7696#[doc = "Join two smaller vectors into a single larger vector"]
7697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
7698#[inline]
7699#[target_feature(enable = "neon")]
7700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7701#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7702#[cfg_attr(
7703 not(target_arch = "arm"),
7704 stable(feature = "neon_intrinsics", since = "1.59.0")
7705)]
7706#[cfg_attr(
7707 target_arch = "arm",
7708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7709)]
7710pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
7711 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
7712}
7713#[doc = "Join two smaller vectors into a single larger vector"]
7714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
7715#[inline]
7716#[target_feature(enable = "neon")]
7717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7718#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7719#[cfg_attr(
7720 not(target_arch = "arm"),
7721 stable(feature = "neon_intrinsics", since = "1.59.0")
7722)]
7723#[cfg_attr(
7724 target_arch = "arm",
7725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7726)]
7727pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
7728 unsafe { simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]) }
7729}
7730#[doc = "Join two smaller vectors into a single larger vector"]
7731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
7732#[inline]
7733#[target_feature(enable = "neon")]
7734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7736#[cfg_attr(
7737 not(target_arch = "arm"),
7738 stable(feature = "neon_intrinsics", since = "1.59.0")
7739)]
7740#[cfg_attr(
7741 target_arch = "arm",
7742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7743)]
7744pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
7745 unsafe { simd_shuffle!(a, b, [0, 1]) }
7746}
7747#[doc = "Insert vector element from another vector element"]
7748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7749#[inline]
7750#[cfg(target_endian = "little")]
7751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7753#[cfg_attr(
7754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7755 assert_instr(nop)
7756)]
7757#[target_feature(enable = "neon,fp16")]
7758#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7759pub fn vcreate_f16(a: u64) -> float16x4_t {
7760 unsafe { transmute(a) }
7761}
7762#[doc = "Insert vector element from another vector element"]
7763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
7764#[inline]
7765#[cfg(target_endian = "big")]
7766#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7767#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7768#[cfg_attr(
7769 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7770 assert_instr(nop)
7771)]
7772#[target_feature(enable = "neon,fp16")]
7773#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
7774pub fn vcreate_f16(a: u64) -> float16x4_t {
7775 unsafe {
7776 let ret_val: float16x4_t = transmute(a);
7777 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7778 }
7779}
7780#[doc = "Insert vector element from another vector element"]
7781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7782#[inline]
7783#[cfg(target_endian = "little")]
7784#[target_feature(enable = "neon")]
7785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7787#[cfg_attr(
7788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7789 assert_instr(nop)
7790)]
7791#[cfg_attr(
7792 not(target_arch = "arm"),
7793 stable(feature = "neon_intrinsics", since = "1.59.0")
7794)]
7795#[cfg_attr(
7796 target_arch = "arm",
7797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7798)]
7799pub fn vcreate_f32(a: u64) -> float32x2_t {
7800 unsafe { transmute(a) }
7801}
7802#[doc = "Insert vector element from another vector element"]
7803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
7804#[inline]
7805#[cfg(target_endian = "big")]
7806#[target_feature(enable = "neon")]
7807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7809#[cfg_attr(
7810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7811 assert_instr(nop)
7812)]
7813#[cfg_attr(
7814 not(target_arch = "arm"),
7815 stable(feature = "neon_intrinsics", since = "1.59.0")
7816)]
7817#[cfg_attr(
7818 target_arch = "arm",
7819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7820)]
7821pub fn vcreate_f32(a: u64) -> float32x2_t {
7822 unsafe {
7823 let ret_val: float32x2_t = transmute(a);
7824 simd_shuffle!(ret_val, ret_val, [1, 0])
7825 }
7826}
7827#[doc = "Insert vector element from another vector element"]
7828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7829#[inline]
7830#[cfg(target_endian = "little")]
7831#[target_feature(enable = "neon")]
7832#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7833#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7834#[cfg_attr(
7835 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7836 assert_instr(nop)
7837)]
7838#[cfg_attr(
7839 not(target_arch = "arm"),
7840 stable(feature = "neon_intrinsics", since = "1.59.0")
7841)]
7842#[cfg_attr(
7843 target_arch = "arm",
7844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7845)]
7846pub fn vcreate_s8(a: u64) -> int8x8_t {
7847 unsafe { transmute(a) }
7848}
7849#[doc = "Insert vector element from another vector element"]
7850#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
7851#[inline]
7852#[cfg(target_endian = "big")]
7853#[target_feature(enable = "neon")]
7854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7856#[cfg_attr(
7857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7858 assert_instr(nop)
7859)]
7860#[cfg_attr(
7861 not(target_arch = "arm"),
7862 stable(feature = "neon_intrinsics", since = "1.59.0")
7863)]
7864#[cfg_attr(
7865 target_arch = "arm",
7866 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7867)]
7868pub fn vcreate_s8(a: u64) -> int8x8_t {
7869 unsafe {
7870 let ret_val: int8x8_t = transmute(a);
7871 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
7872 }
7873}
7874#[doc = "Insert vector element from another vector element"]
7875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7876#[inline]
7877#[cfg(target_endian = "little")]
7878#[target_feature(enable = "neon")]
7879#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7881#[cfg_attr(
7882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7883 assert_instr(nop)
7884)]
7885#[cfg_attr(
7886 not(target_arch = "arm"),
7887 stable(feature = "neon_intrinsics", since = "1.59.0")
7888)]
7889#[cfg_attr(
7890 target_arch = "arm",
7891 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7892)]
7893pub fn vcreate_s16(a: u64) -> int16x4_t {
7894 unsafe { transmute(a) }
7895}
7896#[doc = "Insert vector element from another vector element"]
7897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
7898#[inline]
7899#[cfg(target_endian = "big")]
7900#[target_feature(enable = "neon")]
7901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7903#[cfg_attr(
7904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7905 assert_instr(nop)
7906)]
7907#[cfg_attr(
7908 not(target_arch = "arm"),
7909 stable(feature = "neon_intrinsics", since = "1.59.0")
7910)]
7911#[cfg_attr(
7912 target_arch = "arm",
7913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7914)]
7915pub fn vcreate_s16(a: u64) -> int16x4_t {
7916 unsafe {
7917 let ret_val: int16x4_t = transmute(a);
7918 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
7919 }
7920}
7921#[doc = "Insert vector element from another vector element"]
7922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
7923#[inline]
7924#[cfg(target_endian = "little")]
7925#[target_feature(enable = "neon")]
7926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7928#[cfg_attr(
7929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7930 assert_instr(nop)
7931)]
7932#[cfg_attr(
7933 not(target_arch = "arm"),
7934 stable(feature = "neon_intrinsics", since = "1.59.0")
7935)]
7936#[cfg_attr(
7937 target_arch = "arm",
7938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7939)]
7940pub fn vcreate_s32(a: u64) -> int32x2_t {
7941 unsafe { transmute(a) }
7942}
7943#[doc = "Insert vector element from another vector element"]
7944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
7945#[inline]
7946#[cfg(target_endian = "big")]
7947#[target_feature(enable = "neon")]
7948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7950#[cfg_attr(
7951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7952 assert_instr(nop)
7953)]
7954#[cfg_attr(
7955 not(target_arch = "arm"),
7956 stable(feature = "neon_intrinsics", since = "1.59.0")
7957)]
7958#[cfg_attr(
7959 target_arch = "arm",
7960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7961)]
7962pub fn vcreate_s32(a: u64) -> int32x2_t {
7963 unsafe {
7964 let ret_val: int32x2_t = transmute(a);
7965 simd_shuffle!(ret_val, ret_val, [1, 0])
7966 }
7967}
7968#[doc = "Insert vector element from another vector element"]
7969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
7970#[inline]
7971#[target_feature(enable = "neon")]
7972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7974#[cfg_attr(
7975 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7976 assert_instr(nop)
7977)]
7978#[cfg_attr(
7979 not(target_arch = "arm"),
7980 stable(feature = "neon_intrinsics", since = "1.59.0")
7981)]
7982#[cfg_attr(
7983 target_arch = "arm",
7984 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
7985)]
7986pub fn vcreate_s64(a: u64) -> int64x1_t {
7987 unsafe { transmute(a) }
7988}
7989#[doc = "Insert vector element from another vector element"]
7990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
7991#[inline]
7992#[cfg(target_endian = "little")]
7993#[target_feature(enable = "neon")]
7994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
7995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
7996#[cfg_attr(
7997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
7998 assert_instr(nop)
7999)]
8000#[cfg_attr(
8001 not(target_arch = "arm"),
8002 stable(feature = "neon_intrinsics", since = "1.59.0")
8003)]
8004#[cfg_attr(
8005 target_arch = "arm",
8006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8007)]
8008pub fn vcreate_u8(a: u64) -> uint8x8_t {
8009 unsafe { transmute(a) }
8010}
8011#[doc = "Insert vector element from another vector element"]
8012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
8013#[inline]
8014#[cfg(target_endian = "big")]
8015#[target_feature(enable = "neon")]
8016#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8017#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8018#[cfg_attr(
8019 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8020 assert_instr(nop)
8021)]
8022#[cfg_attr(
8023 not(target_arch = "arm"),
8024 stable(feature = "neon_intrinsics", since = "1.59.0")
8025)]
8026#[cfg_attr(
8027 target_arch = "arm",
8028 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8029)]
8030pub fn vcreate_u8(a: u64) -> uint8x8_t {
8031 unsafe {
8032 let ret_val: uint8x8_t = transmute(a);
8033 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8034 }
8035}
8036#[doc = "Insert vector element from another vector element"]
8037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8038#[inline]
8039#[cfg(target_endian = "little")]
8040#[target_feature(enable = "neon")]
8041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8043#[cfg_attr(
8044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8045 assert_instr(nop)
8046)]
8047#[cfg_attr(
8048 not(target_arch = "arm"),
8049 stable(feature = "neon_intrinsics", since = "1.59.0")
8050)]
8051#[cfg_attr(
8052 target_arch = "arm",
8053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8054)]
8055pub fn vcreate_u16(a: u64) -> uint16x4_t {
8056 unsafe { transmute(a) }
8057}
8058#[doc = "Insert vector element from another vector element"]
8059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
8060#[inline]
8061#[cfg(target_endian = "big")]
8062#[target_feature(enable = "neon")]
8063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8065#[cfg_attr(
8066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8067 assert_instr(nop)
8068)]
8069#[cfg_attr(
8070 not(target_arch = "arm"),
8071 stable(feature = "neon_intrinsics", since = "1.59.0")
8072)]
8073#[cfg_attr(
8074 target_arch = "arm",
8075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8076)]
8077pub fn vcreate_u16(a: u64) -> uint16x4_t {
8078 unsafe {
8079 let ret_val: uint16x4_t = transmute(a);
8080 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8081 }
8082}
8083#[doc = "Insert vector element from another vector element"]
8084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8085#[inline]
8086#[cfg(target_endian = "little")]
8087#[target_feature(enable = "neon")]
8088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8090#[cfg_attr(
8091 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8092 assert_instr(nop)
8093)]
8094#[cfg_attr(
8095 not(target_arch = "arm"),
8096 stable(feature = "neon_intrinsics", since = "1.59.0")
8097)]
8098#[cfg_attr(
8099 target_arch = "arm",
8100 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8101)]
8102pub fn vcreate_u32(a: u64) -> uint32x2_t {
8103 unsafe { transmute(a) }
8104}
8105#[doc = "Insert vector element from another vector element"]
8106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
8107#[inline]
8108#[cfg(target_endian = "big")]
8109#[target_feature(enable = "neon")]
8110#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8111#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8112#[cfg_attr(
8113 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8114 assert_instr(nop)
8115)]
8116#[cfg_attr(
8117 not(target_arch = "arm"),
8118 stable(feature = "neon_intrinsics", since = "1.59.0")
8119)]
8120#[cfg_attr(
8121 target_arch = "arm",
8122 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8123)]
8124pub fn vcreate_u32(a: u64) -> uint32x2_t {
8125 unsafe {
8126 let ret_val: uint32x2_t = transmute(a);
8127 simd_shuffle!(ret_val, ret_val, [1, 0])
8128 }
8129}
8130#[doc = "Insert vector element from another vector element"]
8131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
8132#[inline]
8133#[target_feature(enable = "neon")]
8134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8136#[cfg_attr(
8137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8138 assert_instr(nop)
8139)]
8140#[cfg_attr(
8141 not(target_arch = "arm"),
8142 stable(feature = "neon_intrinsics", since = "1.59.0")
8143)]
8144#[cfg_attr(
8145 target_arch = "arm",
8146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8147)]
8148pub fn vcreate_u64(a: u64) -> uint64x1_t {
8149 unsafe { transmute(a) }
8150}
8151#[doc = "Insert vector element from another vector element"]
8152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8153#[inline]
8154#[cfg(target_endian = "little")]
8155#[target_feature(enable = "neon")]
8156#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8158#[cfg_attr(
8159 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8160 assert_instr(nop)
8161)]
8162#[cfg_attr(
8163 not(target_arch = "arm"),
8164 stable(feature = "neon_intrinsics", since = "1.59.0")
8165)]
8166#[cfg_attr(
8167 target_arch = "arm",
8168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8169)]
8170pub fn vcreate_p8(a: u64) -> poly8x8_t {
8171 unsafe { transmute(a) }
8172}
8173#[doc = "Insert vector element from another vector element"]
8174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
8175#[inline]
8176#[cfg(target_endian = "big")]
8177#[target_feature(enable = "neon")]
8178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8180#[cfg_attr(
8181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8182 assert_instr(nop)
8183)]
8184#[cfg_attr(
8185 not(target_arch = "arm"),
8186 stable(feature = "neon_intrinsics", since = "1.59.0")
8187)]
8188#[cfg_attr(
8189 target_arch = "arm",
8190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8191)]
8192pub fn vcreate_p8(a: u64) -> poly8x8_t {
8193 unsafe {
8194 let ret_val: poly8x8_t = transmute(a);
8195 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
8196 }
8197}
8198#[doc = "Insert vector element from another vector element"]
8199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8200#[inline]
8201#[cfg(target_endian = "little")]
8202#[target_feature(enable = "neon")]
8203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8205#[cfg_attr(
8206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8207 assert_instr(nop)
8208)]
8209#[cfg_attr(
8210 not(target_arch = "arm"),
8211 stable(feature = "neon_intrinsics", since = "1.59.0")
8212)]
8213#[cfg_attr(
8214 target_arch = "arm",
8215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8216)]
8217pub fn vcreate_p16(a: u64) -> poly16x4_t {
8218 unsafe { transmute(a) }
8219}
8220#[doc = "Insert vector element from another vector element"]
8221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
8222#[inline]
8223#[cfg(target_endian = "big")]
8224#[target_feature(enable = "neon")]
8225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8227#[cfg_attr(
8228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8229 assert_instr(nop)
8230)]
8231#[cfg_attr(
8232 not(target_arch = "arm"),
8233 stable(feature = "neon_intrinsics", since = "1.59.0")
8234)]
8235#[cfg_attr(
8236 target_arch = "arm",
8237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8238)]
8239pub fn vcreate_p16(a: u64) -> poly16x4_t {
8240 unsafe {
8241 let ret_val: poly16x4_t = transmute(a);
8242 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
8243 }
8244}
8245#[doc = "Insert vector element from another vector element"]
8246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
8247#[inline]
8248#[target_feature(enable = "neon,aes")]
8249#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
8251#[cfg_attr(
8252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8253 assert_instr(nop)
8254)]
8255#[cfg_attr(
8256 not(target_arch = "arm"),
8257 stable(feature = "neon_intrinsics", since = "1.59.0")
8258)]
8259#[cfg_attr(
8260 target_arch = "arm",
8261 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8262)]
8263pub fn vcreate_p64(a: u64) -> poly64x1_t {
8264 unsafe { transmute(a) }
8265}
8266#[doc = "Floating-point convert to lower precision narrow"]
8267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
8268#[inline]
8269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8270# [cfg_attr (all (test , target_arch = "arm") , assert_instr (vcvt . f16 . f32))]
8271#[cfg_attr(
8272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8273 assert_instr(fcvtn)
8274)]
8275#[target_feature(enable = "neon,fp16")]
8276#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8277pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
8278 unsafe { simd_cast(a) }
8279}
8280#[doc = "Fixed-point convert to floating-point"]
8281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
8282#[inline]
8283#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8284#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8285#[cfg_attr(
8286 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8287 assert_instr(scvtf)
8288)]
8289#[target_feature(enable = "neon,fp16")]
8290#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8291pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
8292 unsafe { simd_cast(a) }
8293}
8294#[doc = "Fixed-point convert to floating-point"]
8295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
8296#[inline]
8297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8299#[cfg_attr(
8300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8301 assert_instr(scvtf)
8302)]
8303#[target_feature(enable = "neon,fp16")]
8304#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8305pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
8306 unsafe { simd_cast(a) }
8307}
8308#[doc = "Fixed-point convert to floating-point"]
8309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
8310#[inline]
8311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8313#[cfg_attr(
8314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8315 assert_instr(ucvtf)
8316)]
8317#[target_feature(enable = "neon,fp16")]
8318#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8319pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
8320 unsafe { simd_cast(a) }
8321}
8322#[doc = "Fixed-point convert to floating-point"]
8323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
8324#[inline]
8325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8327#[cfg_attr(
8328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8329 assert_instr(ucvtf)
8330)]
8331#[target_feature(enable = "neon,fp16")]
8332#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8333pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
8334 unsafe { simd_cast(a) }
8335}
8336#[doc = "Floating-point convert to higher precision long"]
8337#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
8338#[inline]
8339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8341#[cfg_attr(
8342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8343 assert_instr(fcvtl)
8344)]
8345#[target_feature(enable = "neon,fp16")]
8346#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8347pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
8348 unsafe { simd_cast(a) }
8349}
8350#[doc = "Fixed-point convert to floating-point"]
8351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
8352#[inline]
8353#[target_feature(enable = "neon")]
8354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8356#[cfg_attr(
8357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8358 assert_instr(scvtf)
8359)]
8360#[cfg_attr(
8361 not(target_arch = "arm"),
8362 stable(feature = "neon_intrinsics", since = "1.59.0")
8363)]
8364#[cfg_attr(
8365 target_arch = "arm",
8366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8367)]
8368pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
8369 unsafe { simd_cast(a) }
8370}
8371#[doc = "Fixed-point convert to floating-point"]
8372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
8373#[inline]
8374#[target_feature(enable = "neon")]
8375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8377#[cfg_attr(
8378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8379 assert_instr(scvtf)
8380)]
8381#[cfg_attr(
8382 not(target_arch = "arm"),
8383 stable(feature = "neon_intrinsics", since = "1.59.0")
8384)]
8385#[cfg_attr(
8386 target_arch = "arm",
8387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8388)]
8389pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
8390 unsafe { simd_cast(a) }
8391}
8392#[doc = "Fixed-point convert to floating-point"]
8393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
8394#[inline]
8395#[target_feature(enable = "neon")]
8396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8398#[cfg_attr(
8399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8400 assert_instr(ucvtf)
8401)]
8402#[cfg_attr(
8403 not(target_arch = "arm"),
8404 stable(feature = "neon_intrinsics", since = "1.59.0")
8405)]
8406#[cfg_attr(
8407 target_arch = "arm",
8408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8409)]
8410pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
8411 unsafe { simd_cast(a) }
8412}
8413#[doc = "Fixed-point convert to floating-point"]
8414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
8415#[inline]
8416#[target_feature(enable = "neon")]
8417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8419#[cfg_attr(
8420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8421 assert_instr(ucvtf)
8422)]
8423#[cfg_attr(
8424 not(target_arch = "arm"),
8425 stable(feature = "neon_intrinsics", since = "1.59.0")
8426)]
8427#[cfg_attr(
8428 target_arch = "arm",
8429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8430)]
8431pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
8432 unsafe { simd_cast(a) }
8433}
8434#[doc = "Fixed-point convert to floating-point"]
8435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
8436#[inline]
8437#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8438#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8439#[cfg_attr(
8440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8441 assert_instr(scvtf, N = 1)
8442)]
8443#[rustc_legacy_const_generics(1)]
8444#[target_feature(enable = "neon,fp16")]
8445#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8446pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
8447 static_assert!(N >= 1 && N <= 16);
8448 unsafe extern "unadjusted" {
8449 #[cfg_attr(
8450 target_arch = "arm",
8451 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16"
8452 )]
8453 #[cfg_attr(
8454 any(target_arch = "aarch64", target_arch = "arm64ec"),
8455 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16"
8456 )]
8457 fn _vcvt_n_f16_s16(a: int16x4_t, n: i32) -> float16x4_t;
8458 }
8459 unsafe { _vcvt_n_f16_s16(a, N) }
8460}
8461#[doc = "Fixed-point convert to floating-point"]
8462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
8463#[inline]
8464#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8465#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8466#[cfg_attr(
8467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8468 assert_instr(scvtf, N = 1)
8469)]
8470#[rustc_legacy_const_generics(1)]
8471#[target_feature(enable = "neon,fp16")]
8472#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8473pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
8474 static_assert!(N >= 1 && N <= 16);
8475 unsafe extern "unadjusted" {
8476 #[cfg_attr(
8477 target_arch = "arm",
8478 link_name = "llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16"
8479 )]
8480 #[cfg_attr(
8481 any(target_arch = "aarch64", target_arch = "arm64ec"),
8482 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16"
8483 )]
8484 fn _vcvtq_n_f16_s16(a: int16x8_t, n: i32) -> float16x8_t;
8485 }
8486 unsafe { _vcvtq_n_f16_s16(a, N) }
8487}
8488#[doc = "Fixed-point convert to floating-point"]
8489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
8490#[inline]
8491#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8492#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8493#[cfg_attr(
8494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8495 assert_instr(ucvtf, N = 1)
8496)]
8497#[rustc_legacy_const_generics(1)]
8498#[target_feature(enable = "neon,fp16")]
8499#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8500pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
8501 static_assert!(N >= 1 && N <= 16);
8502 unsafe extern "unadjusted" {
8503 #[cfg_attr(
8504 target_arch = "arm",
8505 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16"
8506 )]
8507 #[cfg_attr(
8508 any(target_arch = "aarch64", target_arch = "arm64ec"),
8509 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16"
8510 )]
8511 fn _vcvt_n_f16_u16(a: uint16x4_t, n: i32) -> float16x4_t;
8512 }
8513 unsafe { _vcvt_n_f16_u16(a, N) }
8514}
8515#[doc = "Fixed-point convert to floating-point"]
8516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
8517#[inline]
8518#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8519#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8520#[cfg_attr(
8521 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8522 assert_instr(ucvtf, N = 1)
8523)]
8524#[rustc_legacy_const_generics(1)]
8525#[target_feature(enable = "neon,fp16")]
8526#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8527pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
8528 static_assert!(N >= 1 && N <= 16);
8529 unsafe extern "unadjusted" {
8530 #[cfg_attr(
8531 target_arch = "arm",
8532 link_name = "llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16"
8533 )]
8534 #[cfg_attr(
8535 any(target_arch = "aarch64", target_arch = "arm64ec"),
8536 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16"
8537 )]
8538 fn _vcvtq_n_f16_u16(a: uint16x8_t, n: i32) -> float16x8_t;
8539 }
8540 unsafe { _vcvtq_n_f16_u16(a, N) }
8541}
8542#[doc = "Fixed-point convert to floating-point"]
8543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8544#[inline]
8545#[cfg(target_arch = "arm")]
8546#[target_feature(enable = "neon,v7")]
8547#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8548#[rustc_legacy_const_generics(1)]
8549#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8550pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8551 static_assert!(N >= 1 && N <= 32);
8552 unsafe extern "unadjusted" {
8553 #[cfg_attr(
8554 target_arch = "arm",
8555 link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32"
8556 )]
8557 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8558 }
8559 unsafe { _vcvt_n_f32_s32(a, N) }
8560}
8561#[doc = "Fixed-point convert to floating-point"]
8562#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8563#[inline]
8564#[cfg(target_arch = "arm")]
8565#[target_feature(enable = "neon,v7")]
8566#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8567#[rustc_legacy_const_generics(1)]
8568#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8569pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8570 static_assert!(N >= 1 && N <= 32);
8571 unsafe extern "unadjusted" {
8572 #[cfg_attr(
8573 target_arch = "arm",
8574 link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32"
8575 )]
8576 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8577 }
8578 unsafe { _vcvtq_n_f32_s32(a, N) }
8579}
8580#[doc = "Fixed-point convert to floating-point"]
8581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
8582#[inline]
8583#[target_feature(enable = "neon")]
8584#[cfg(not(target_arch = "arm"))]
8585#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8586#[rustc_legacy_const_generics(1)]
8587#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8588pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
8589 static_assert!(N >= 1 && N <= 32);
8590 unsafe extern "unadjusted" {
8591 #[cfg_attr(
8592 any(target_arch = "aarch64", target_arch = "arm64ec"),
8593 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32"
8594 )]
8595 fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t;
8596 }
8597 unsafe { _vcvt_n_f32_s32(a, N) }
8598}
8599#[doc = "Fixed-point convert to floating-point"]
8600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
8601#[inline]
8602#[target_feature(enable = "neon")]
8603#[cfg(not(target_arch = "arm"))]
8604#[cfg_attr(test, assert_instr(scvtf, N = 2))]
8605#[rustc_legacy_const_generics(1)]
8606#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8607pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
8608 static_assert!(N >= 1 && N <= 32);
8609 unsafe extern "unadjusted" {
8610 #[cfg_attr(
8611 any(target_arch = "aarch64", target_arch = "arm64ec"),
8612 link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32"
8613 )]
8614 fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t;
8615 }
8616 unsafe { _vcvtq_n_f32_s32(a, N) }
8617}
8618#[doc = "Fixed-point convert to floating-point"]
8619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8620#[inline]
8621#[cfg(target_arch = "arm")]
8622#[target_feature(enable = "neon,v7")]
8623#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8624#[rustc_legacy_const_generics(1)]
8625#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8626pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8627 static_assert!(N >= 1 && N <= 32);
8628 unsafe extern "unadjusted" {
8629 #[cfg_attr(
8630 target_arch = "arm",
8631 link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32"
8632 )]
8633 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8634 }
8635 unsafe { _vcvt_n_f32_u32(a, N) }
8636}
8637#[doc = "Fixed-point convert to floating-point"]
8638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8639#[inline]
8640#[cfg(target_arch = "arm")]
8641#[target_feature(enable = "neon,v7")]
8642#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8643#[rustc_legacy_const_generics(1)]
8644#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8645pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8646 static_assert!(N >= 1 && N <= 32);
8647 unsafe extern "unadjusted" {
8648 #[cfg_attr(
8649 target_arch = "arm",
8650 link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32"
8651 )]
8652 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8653 }
8654 unsafe { _vcvtq_n_f32_u32(a, N) }
8655}
8656#[doc = "Fixed-point convert to floating-point"]
8657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
8658#[inline]
8659#[target_feature(enable = "neon")]
8660#[cfg(not(target_arch = "arm"))]
8661#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8662#[rustc_legacy_const_generics(1)]
8663#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8664pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
8665 static_assert!(N >= 1 && N <= 32);
8666 unsafe extern "unadjusted" {
8667 #[cfg_attr(
8668 any(target_arch = "aarch64", target_arch = "arm64ec"),
8669 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32"
8670 )]
8671 fn _vcvt_n_f32_u32(a: uint32x2_t, n: i32) -> float32x2_t;
8672 }
8673 unsafe { _vcvt_n_f32_u32(a, N) }
8674}
8675#[doc = "Fixed-point convert to floating-point"]
8676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
8677#[inline]
8678#[target_feature(enable = "neon")]
8679#[cfg(not(target_arch = "arm"))]
8680#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
8681#[rustc_legacy_const_generics(1)]
8682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8683pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
8684 static_assert!(N >= 1 && N <= 32);
8685 unsafe extern "unadjusted" {
8686 #[cfg_attr(
8687 any(target_arch = "aarch64", target_arch = "arm64ec"),
8688 link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32"
8689 )]
8690 fn _vcvtq_n_f32_u32(a: uint32x4_t, n: i32) -> float32x4_t;
8691 }
8692 unsafe { _vcvtq_n_f32_u32(a, N) }
8693}
8694#[doc = "Floating-point convert to signed fixed-point"]
8695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
8696#[inline]
8697#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8698#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8699#[cfg_attr(
8700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8701 assert_instr(fcvtzs, N = 1)
8702)]
8703#[rustc_legacy_const_generics(1)]
8704#[target_feature(enable = "neon,fp16")]
8705#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8706pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
8707 static_assert!(N >= 1 && N <= 16);
8708 unsafe extern "unadjusted" {
8709 #[cfg_attr(
8710 target_arch = "arm",
8711 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16"
8712 )]
8713 #[cfg_attr(
8714 any(target_arch = "aarch64", target_arch = "arm64ec"),
8715 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16"
8716 )]
8717 fn _vcvt_n_s16_f16(a: float16x4_t, n: i32) -> int16x4_t;
8718 }
8719 unsafe { _vcvt_n_s16_f16(a, N) }
8720}
8721#[doc = "Floating-point convert to signed fixed-point"]
8722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
8723#[inline]
8724#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8725#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8726#[cfg_attr(
8727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8728 assert_instr(fcvtzs, N = 1)
8729)]
8730#[rustc_legacy_const_generics(1)]
8731#[target_feature(enable = "neon,fp16")]
8732#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8733pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
8734 static_assert!(N >= 1 && N <= 16);
8735 unsafe extern "unadjusted" {
8736 #[cfg_attr(
8737 target_arch = "arm",
8738 link_name = "llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16"
8739 )]
8740 #[cfg_attr(
8741 any(target_arch = "aarch64", target_arch = "arm64ec"),
8742 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16"
8743 )]
8744 fn _vcvtq_n_s16_f16(a: float16x8_t, n: i32) -> int16x8_t;
8745 }
8746 unsafe { _vcvtq_n_s16_f16(a, N) }
8747}
8748#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8750#[inline]
8751#[cfg(target_arch = "arm")]
8752#[target_feature(enable = "neon,v7")]
8753#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8754#[rustc_legacy_const_generics(1)]
8755#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8756pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8757 static_assert!(N >= 1 && N <= 32);
8758 unsafe extern "unadjusted" {
8759 #[cfg_attr(
8760 target_arch = "arm",
8761 link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32"
8762 )]
8763 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8764 }
8765 unsafe { _vcvt_n_s32_f32(a, N) }
8766}
8767#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8769#[inline]
8770#[cfg(target_arch = "arm")]
8771#[target_feature(enable = "neon,v7")]
8772#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8773#[rustc_legacy_const_generics(1)]
8774#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8775pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8776 static_assert!(N >= 1 && N <= 32);
8777 unsafe extern "unadjusted" {
8778 #[cfg_attr(
8779 target_arch = "arm",
8780 link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32"
8781 )]
8782 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8783 }
8784 unsafe { _vcvtq_n_s32_f32(a, N) }
8785}
8786#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
8788#[inline]
8789#[target_feature(enable = "neon")]
8790#[cfg(not(target_arch = "arm"))]
8791#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8792#[rustc_legacy_const_generics(1)]
8793#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8794pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
8795 static_assert!(N >= 1 && N <= 32);
8796 unsafe extern "unadjusted" {
8797 #[cfg_attr(
8798 any(target_arch = "aarch64", target_arch = "arm64ec"),
8799 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32"
8800 )]
8801 fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t;
8802 }
8803 unsafe { _vcvt_n_s32_f32(a, N) }
8804}
8805#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
8807#[inline]
8808#[target_feature(enable = "neon")]
8809#[cfg(not(target_arch = "arm"))]
8810#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
8811#[rustc_legacy_const_generics(1)]
8812#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8813pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
8814 static_assert!(N >= 1 && N <= 32);
8815 unsafe extern "unadjusted" {
8816 #[cfg_attr(
8817 any(target_arch = "aarch64", target_arch = "arm64ec"),
8818 link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32"
8819 )]
8820 fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t;
8821 }
8822 unsafe { _vcvtq_n_s32_f32(a, N) }
8823}
8824#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
8826#[inline]
8827#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8828#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8829#[cfg_attr(
8830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8831 assert_instr(fcvtzu, N = 1)
8832)]
8833#[rustc_legacy_const_generics(1)]
8834#[target_feature(enable = "neon,fp16")]
8835#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8836pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
8837 static_assert!(N >= 1 && N <= 16);
8838 unsafe extern "unadjusted" {
8839 #[cfg_attr(
8840 target_arch = "arm",
8841 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16"
8842 )]
8843 #[cfg_attr(
8844 any(target_arch = "aarch64", target_arch = "arm64ec"),
8845 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16"
8846 )]
8847 fn _vcvt_n_u16_f16(a: float16x4_t, n: i32) -> uint16x4_t;
8848 }
8849 unsafe { _vcvt_n_u16_f16(a, N) }
8850}
8851#[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
8852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
8853#[inline]
8854#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
8855#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
8856#[cfg_attr(
8857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8858 assert_instr(fcvtzu, N = 1)
8859)]
8860#[rustc_legacy_const_generics(1)]
8861#[target_feature(enable = "neon,fp16")]
8862#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8863pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
8864 static_assert!(N >= 1 && N <= 16);
8865 unsafe extern "unadjusted" {
8866 #[cfg_attr(
8867 target_arch = "arm",
8868 link_name = "llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16"
8869 )]
8870 #[cfg_attr(
8871 any(target_arch = "aarch64", target_arch = "arm64ec"),
8872 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16"
8873 )]
8874 fn _vcvtq_n_u16_f16(a: float16x8_t, n: i32) -> uint16x8_t;
8875 }
8876 unsafe { _vcvtq_n_u16_f16(a, N) }
8877}
8878#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8880#[inline]
8881#[cfg(target_arch = "arm")]
8882#[target_feature(enable = "neon,v7")]
8883#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8884#[rustc_legacy_const_generics(1)]
8885#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8886pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8887 static_assert!(N >= 1 && N <= 32);
8888 unsafe extern "unadjusted" {
8889 #[cfg_attr(
8890 target_arch = "arm",
8891 link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32"
8892 )]
8893 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8894 }
8895 unsafe { _vcvt_n_u32_f32(a, N) }
8896}
8897#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8899#[inline]
8900#[cfg(target_arch = "arm")]
8901#[target_feature(enable = "neon,v7")]
8902#[cfg_attr(test, assert_instr(vcvt, N = 2))]
8903#[rustc_legacy_const_generics(1)]
8904#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
8905pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8906 static_assert!(N >= 1 && N <= 32);
8907 unsafe extern "unadjusted" {
8908 #[cfg_attr(
8909 target_arch = "arm",
8910 link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32"
8911 )]
8912 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
8913 }
8914 unsafe { _vcvtq_n_u32_f32(a, N) }
8915}
8916#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
8918#[inline]
8919#[target_feature(enable = "neon")]
8920#[cfg(not(target_arch = "arm"))]
8921#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
8922#[rustc_legacy_const_generics(1)]
8923#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8924pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
8925 static_assert!(N >= 1 && N <= 32);
8926 unsafe extern "unadjusted" {
8927 #[cfg_attr(
8928 any(target_arch = "aarch64", target_arch = "arm64ec"),
8929 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32"
8930 )]
8931 fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> uint32x2_t;
8932 }
8933 unsafe { _vcvt_n_u32_f32(a, N) }
8934}
8935#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
8936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
8937#[inline]
8938#[target_feature(enable = "neon")]
8939#[cfg(not(target_arch = "arm"))]
8940#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
8941#[rustc_legacy_const_generics(1)]
8942#[stable(feature = "neon_intrinsics", since = "1.59.0")]
8943pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
8944 static_assert!(N >= 1 && N <= 32);
8945 unsafe extern "unadjusted" {
8946 #[cfg_attr(
8947 any(target_arch = "aarch64", target_arch = "arm64ec"),
8948 link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32"
8949 )]
8950 fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> uint32x4_t;
8951 }
8952 unsafe { _vcvtq_n_u32_f32(a, N) }
8953}
8954#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
8955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
8956#[inline]
8957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8959#[cfg_attr(
8960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8961 assert_instr(fcvtzs)
8962)]
8963#[target_feature(enable = "neon,fp16")]
8964#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8965pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
8966 unsafe { simd_cast(a) }
8967}
8968#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
8969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
8970#[inline]
8971#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8972#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8973#[cfg_attr(
8974 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8975 assert_instr(fcvtzs)
8976)]
8977#[target_feature(enable = "neon,fp16")]
8978#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
8979pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
8980 unsafe { simd_cast(a) }
8981}
8982#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
8983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
8984#[inline]
8985#[target_feature(enable = "neon")]
8986#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
8987#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
8988#[cfg_attr(
8989 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
8990 assert_instr(fcvtzs)
8991)]
8992#[cfg_attr(
8993 not(target_arch = "arm"),
8994 stable(feature = "neon_intrinsics", since = "1.59.0")
8995)]
8996#[cfg_attr(
8997 target_arch = "arm",
8998 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
8999)]
9000pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
9001 unsafe extern "unadjusted" {
9002 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")]
9003 #[cfg_attr(
9004 any(target_arch = "aarch64", target_arch = "arm64ec"),
9005 link_name = "llvm.fptosi.sat.v2i32.v2f32"
9006 )]
9007 fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t;
9008 }
9009 unsafe { _vcvt_s32_f32(a) }
9010}
9011#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
9012#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
9013#[inline]
9014#[target_feature(enable = "neon")]
9015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9017#[cfg_attr(
9018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9019 assert_instr(fcvtzs)
9020)]
9021#[cfg_attr(
9022 not(target_arch = "arm"),
9023 stable(feature = "neon_intrinsics", since = "1.59.0")
9024)]
9025#[cfg_attr(
9026 target_arch = "arm",
9027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9028)]
9029pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
9030 unsafe extern "unadjusted" {
9031 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")]
9032 #[cfg_attr(
9033 any(target_arch = "aarch64", target_arch = "arm64ec"),
9034 link_name = "llvm.fptosi.sat.v4i32.v4f32"
9035 )]
9036 fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t;
9037 }
9038 unsafe { _vcvtq_s32_f32(a) }
9039}
9040#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
9042#[inline]
9043#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9045#[cfg_attr(
9046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9047 assert_instr(fcvtzu)
9048)]
9049#[target_feature(enable = "neon,fp16")]
9050#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9051pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
9052 unsafe { simd_cast(a) }
9053}
9054#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
9056#[inline]
9057#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9059#[cfg_attr(
9060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9061 assert_instr(fcvtzu)
9062)]
9063#[target_feature(enable = "neon,fp16")]
9064#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9065pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
9066 unsafe { simd_cast(a) }
9067}
9068#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
9070#[inline]
9071#[target_feature(enable = "neon")]
9072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9074#[cfg_attr(
9075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9076 assert_instr(fcvtzu)
9077)]
9078#[cfg_attr(
9079 not(target_arch = "arm"),
9080 stable(feature = "neon_intrinsics", since = "1.59.0")
9081)]
9082#[cfg_attr(
9083 target_arch = "arm",
9084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9085)]
9086pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
9087 unsafe extern "unadjusted" {
9088 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")]
9089 #[cfg_attr(
9090 any(target_arch = "aarch64", target_arch = "arm64ec"),
9091 link_name = "llvm.fptoui.sat.v2i32.v2f32"
9092 )]
9093 fn _vcvt_u32_f32(a: float32x2_t) -> uint32x2_t;
9094 }
9095 unsafe { _vcvt_u32_f32(a) }
9096}
9097#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
9098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
9099#[inline]
9100#[target_feature(enable = "neon")]
9101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
9103#[cfg_attr(
9104 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9105 assert_instr(fcvtzu)
9106)]
9107#[cfg_attr(
9108 not(target_arch = "arm"),
9109 stable(feature = "neon_intrinsics", since = "1.59.0")
9110)]
9111#[cfg_attr(
9112 target_arch = "arm",
9113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9114)]
9115pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
9116 unsafe extern "unadjusted" {
9117 #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")]
9118 #[cfg_attr(
9119 any(target_arch = "aarch64", target_arch = "arm64ec"),
9120 link_name = "llvm.fptoui.sat.v4i32.v4f32"
9121 )]
9122 fn _vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t;
9123 }
9124 unsafe { _vcvtq_u32_f32(a) }
9125}
9126#[doc = "Dot product arithmetic (indexed)"]
9127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
9128#[inline]
9129#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9130#[target_feature(enable = "neon,dotprod")]
9131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9132#[cfg_attr(
9133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9134 assert_instr(sdot, LANE = 0)
9135)]
9136#[rustc_legacy_const_generics(3)]
9137#[cfg_attr(
9138 not(target_arch = "arm"),
9139 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9140)]
9141#[cfg_attr(
9142 target_arch = "arm",
9143 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9144)]
9145pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9146 static_assert_uimm_bits!(LANE, 1);
9147 unsafe {
9148 let c: int32x2_t = transmute(c);
9149 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9150 vdot_s32(a, b, transmute(c))
9151 }
9152}
9153#[doc = "Dot product arithmetic (indexed)"]
9154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
9155#[inline]
9156#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9157#[target_feature(enable = "neon,dotprod")]
9158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
9159#[cfg_attr(
9160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9161 assert_instr(sdot, LANE = 0)
9162)]
9163#[rustc_legacy_const_generics(3)]
9164#[cfg_attr(
9165 not(target_arch = "arm"),
9166 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9167)]
9168#[cfg_attr(
9169 target_arch = "arm",
9170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9171)]
9172pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t {
9173 static_assert_uimm_bits!(LANE, 1);
9174 unsafe {
9175 let c: int32x2_t = transmute(c);
9176 let c: int32x4_t =
9177 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9178 vdotq_s32(a, b, transmute(c))
9179 }
9180}
9181#[doc = "Dot product arithmetic (indexed)"]
9182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
9183#[inline]
9184#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9185#[target_feature(enable = "neon,dotprod")]
9186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9187#[cfg_attr(
9188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9189 assert_instr(udot, LANE = 0)
9190)]
9191#[rustc_legacy_const_generics(3)]
9192#[cfg_attr(
9193 not(target_arch = "arm"),
9194 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9195)]
9196#[cfg_attr(
9197 target_arch = "arm",
9198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9199)]
9200pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9201 static_assert_uimm_bits!(LANE, 1);
9202 unsafe {
9203 let c: uint32x2_t = transmute(c);
9204 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
9205 vdot_u32(a, b, transmute(c))
9206 }
9207}
9208#[doc = "Dot product arithmetic (indexed)"]
9209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
9210#[inline]
9211#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9212#[target_feature(enable = "neon,dotprod")]
9213#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
9214#[cfg_attr(
9215 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9216 assert_instr(udot, LANE = 0)
9217)]
9218#[rustc_legacy_const_generics(3)]
9219#[cfg_attr(
9220 not(target_arch = "arm"),
9221 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9222)]
9223#[cfg_attr(
9224 target_arch = "arm",
9225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9226)]
9227pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t {
9228 static_assert_uimm_bits!(LANE, 1);
9229 unsafe {
9230 let c: uint32x2_t = transmute(c);
9231 let c: uint32x4_t =
9232 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
9233 vdotq_u32(a, b, transmute(c))
9234 }
9235}
9236#[doc = "Dot product arithmetic (vector)"]
9237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
9238#[inline]
9239#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9240#[target_feature(enable = "neon,dotprod")]
9241#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9242#[cfg_attr(
9243 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9244 assert_instr(sdot)
9245)]
9246#[cfg_attr(
9247 not(target_arch = "arm"),
9248 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9249)]
9250#[cfg_attr(
9251 target_arch = "arm",
9252 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9253)]
9254pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
9255 unsafe extern "unadjusted" {
9256 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")]
9257 #[cfg_attr(
9258 any(target_arch = "aarch64", target_arch = "arm64ec"),
9259 link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8"
9260 )]
9261 fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t;
9262 }
9263 unsafe { _vdot_s32(a, b, c) }
9264}
9265#[doc = "Dot product arithmetic (vector)"]
9266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
9267#[inline]
9268#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9269#[target_feature(enable = "neon,dotprod")]
9270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
9271#[cfg_attr(
9272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9273 assert_instr(sdot)
9274)]
9275#[cfg_attr(
9276 not(target_arch = "arm"),
9277 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9278)]
9279#[cfg_attr(
9280 target_arch = "arm",
9281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9282)]
9283pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
9284 unsafe extern "unadjusted" {
9285 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")]
9286 #[cfg_attr(
9287 any(target_arch = "aarch64", target_arch = "arm64ec"),
9288 link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8"
9289 )]
9290 fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
9291 }
9292 unsafe { _vdotq_s32(a, b, c) }
9293}
9294#[doc = "Dot product arithmetic (vector)"]
9295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
9296#[inline]
9297#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9298#[target_feature(enable = "neon,dotprod")]
9299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9300#[cfg_attr(
9301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9302 assert_instr(udot)
9303)]
9304#[cfg_attr(
9305 not(target_arch = "arm"),
9306 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9307)]
9308#[cfg_attr(
9309 target_arch = "arm",
9310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9311)]
9312pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
9313 unsafe extern "unadjusted" {
9314 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")]
9315 #[cfg_attr(
9316 any(target_arch = "aarch64", target_arch = "arm64ec"),
9317 link_name = "llvm.aarch64.neon.udot.v2i32.v8i8"
9318 )]
9319 fn _vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t;
9320 }
9321 unsafe { _vdot_u32(a, b, c) }
9322}
9323#[doc = "Dot product arithmetic (vector)"]
9324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
9325#[inline]
9326#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
9327#[target_feature(enable = "neon,dotprod")]
9328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
9329#[cfg_attr(
9330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9331 assert_instr(udot)
9332)]
9333#[cfg_attr(
9334 not(target_arch = "arm"),
9335 unstable(feature = "stdarch_neon_dotprod", issue = "117224")
9336)]
9337#[cfg_attr(
9338 target_arch = "arm",
9339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9340)]
9341pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
9342 unsafe extern "unadjusted" {
9343 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")]
9344 #[cfg_attr(
9345 any(target_arch = "aarch64", target_arch = "arm64ec"),
9346 link_name = "llvm.aarch64.neon.udot.v4i32.v16i8"
9347 )]
9348 fn _vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
9349 }
9350 unsafe { _vdotq_u32(a, b, c) }
9351}
9352#[doc = "Set all vector lanes to the same value"]
9353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
9354#[inline]
9355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9356#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9357#[cfg_attr(
9358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9359 assert_instr(dup, N = 2)
9360)]
9361#[rustc_legacy_const_generics(1)]
9362#[target_feature(enable = "neon,fp16")]
9363#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9364pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
9365 static_assert_uimm_bits!(N, 2);
9366 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9367}
9368#[doc = "Set all vector lanes to the same value"]
9369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
9370#[inline]
9371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9373#[cfg_attr(
9374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9375 assert_instr(dup, N = 2)
9376)]
9377#[rustc_legacy_const_generics(1)]
9378#[target_feature(enable = "neon,fp16")]
9379#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9380pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
9381 static_assert_uimm_bits!(N, 2);
9382 unsafe {
9383 simd_shuffle!(
9384 a,
9385 a,
9386 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9387 )
9388 }
9389}
9390#[doc = "Set all vector lanes to the same value"]
9391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
9392#[inline]
9393#[target_feature(enable = "neon")]
9394#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9395#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9396#[cfg_attr(
9397 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9398 assert_instr(dup, N = 1)
9399)]
9400#[rustc_legacy_const_generics(1)]
9401#[cfg_attr(
9402 not(target_arch = "arm"),
9403 stable(feature = "neon_intrinsics", since = "1.59.0")
9404)]
9405#[cfg_attr(
9406 target_arch = "arm",
9407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9408)]
9409pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
9410 static_assert_uimm_bits!(N, 1);
9411 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9412}
9413#[doc = "Set all vector lanes to the same value"]
9414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
9415#[inline]
9416#[target_feature(enable = "neon")]
9417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9418#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9419#[cfg_attr(
9420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9421 assert_instr(dup, N = 1)
9422)]
9423#[rustc_legacy_const_generics(1)]
9424#[cfg_attr(
9425 not(target_arch = "arm"),
9426 stable(feature = "neon_intrinsics", since = "1.59.0")
9427)]
9428#[cfg_attr(
9429 target_arch = "arm",
9430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9431)]
9432pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
9433 static_assert_uimm_bits!(N, 1);
9434 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9435}
9436#[doc = "Set all vector lanes to the same value"]
9437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
9438#[inline]
9439#[target_feature(enable = "neon")]
9440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9441#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9442#[cfg_attr(
9443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9444 assert_instr(dup, N = 1)
9445)]
9446#[rustc_legacy_const_generics(1)]
9447#[cfg_attr(
9448 not(target_arch = "arm"),
9449 stable(feature = "neon_intrinsics", since = "1.59.0")
9450)]
9451#[cfg_attr(
9452 target_arch = "arm",
9453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9454)]
9455pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
9456 static_assert_uimm_bits!(N, 1);
9457 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9458}
9459#[doc = "Set all vector lanes to the same value"]
9460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
9461#[inline]
9462#[target_feature(enable = "neon")]
9463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9464#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9465#[cfg_attr(
9466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9467 assert_instr(dup, N = 1)
9468)]
9469#[rustc_legacy_const_generics(1)]
9470#[cfg_attr(
9471 not(target_arch = "arm"),
9472 stable(feature = "neon_intrinsics", since = "1.59.0")
9473)]
9474#[cfg_attr(
9475 target_arch = "arm",
9476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9477)]
9478pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
9479 static_assert_uimm_bits!(N, 1);
9480 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9481}
9482#[doc = "Set all vector lanes to the same value"]
9483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
9484#[inline]
9485#[target_feature(enable = "neon")]
9486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9487#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9488#[cfg_attr(
9489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9490 assert_instr(dup, N = 1)
9491)]
9492#[rustc_legacy_const_generics(1)]
9493#[cfg_attr(
9494 not(target_arch = "arm"),
9495 stable(feature = "neon_intrinsics", since = "1.59.0")
9496)]
9497#[cfg_attr(
9498 target_arch = "arm",
9499 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9500)]
9501pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
9502 static_assert_uimm_bits!(N, 1);
9503 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9504}
9505#[doc = "Set all vector lanes to the same value"]
9506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
9507#[inline]
9508#[target_feature(enable = "neon")]
9509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9510#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
9511#[cfg_attr(
9512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9513 assert_instr(dup, N = 1)
9514)]
9515#[rustc_legacy_const_generics(1)]
9516#[cfg_attr(
9517 not(target_arch = "arm"),
9518 stable(feature = "neon_intrinsics", since = "1.59.0")
9519)]
9520#[cfg_attr(
9521 target_arch = "arm",
9522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9523)]
9524pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
9525 static_assert_uimm_bits!(N, 1);
9526 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9527}
9528#[doc = "Set all vector lanes to the same value"]
9529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
9530#[inline]
9531#[target_feature(enable = "neon")]
9532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9533#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9534#[cfg_attr(
9535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9536 assert_instr(dup, N = 2)
9537)]
9538#[rustc_legacy_const_generics(1)]
9539#[cfg_attr(
9540 not(target_arch = "arm"),
9541 stable(feature = "neon_intrinsics", since = "1.59.0")
9542)]
9543#[cfg_attr(
9544 target_arch = "arm",
9545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9546)]
9547pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
9548 static_assert_uimm_bits!(N, 2);
9549 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9550}
9551#[doc = "Set all vector lanes to the same value"]
9552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
9553#[inline]
9554#[target_feature(enable = "neon")]
9555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9556#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9557#[cfg_attr(
9558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9559 assert_instr(dup, N = 2)
9560)]
9561#[rustc_legacy_const_generics(1)]
9562#[cfg_attr(
9563 not(target_arch = "arm"),
9564 stable(feature = "neon_intrinsics", since = "1.59.0")
9565)]
9566#[cfg_attr(
9567 target_arch = "arm",
9568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9569)]
9570pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
9571 static_assert_uimm_bits!(N, 2);
9572 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9573}
9574#[doc = "Set all vector lanes to the same value"]
9575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
9576#[inline]
9577#[target_feature(enable = "neon")]
9578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9579#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9580#[cfg_attr(
9581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9582 assert_instr(dup, N = 2)
9583)]
9584#[rustc_legacy_const_generics(1)]
9585#[cfg_attr(
9586 not(target_arch = "arm"),
9587 stable(feature = "neon_intrinsics", since = "1.59.0")
9588)]
9589#[cfg_attr(
9590 target_arch = "arm",
9591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9592)]
9593pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
9594 static_assert_uimm_bits!(N, 2);
9595 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9596}
9597#[doc = "Set all vector lanes to the same value"]
9598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
9599#[inline]
9600#[target_feature(enable = "neon")]
9601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9602#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9603#[cfg_attr(
9604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9605 assert_instr(dup, N = 2)
9606)]
9607#[rustc_legacy_const_generics(1)]
9608#[cfg_attr(
9609 not(target_arch = "arm"),
9610 stable(feature = "neon_intrinsics", since = "1.59.0")
9611)]
9612#[cfg_attr(
9613 target_arch = "arm",
9614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9615)]
9616pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
9617 static_assert_uimm_bits!(N, 2);
9618 unsafe {
9619 simd_shuffle!(
9620 a,
9621 a,
9622 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9623 )
9624 }
9625}
9626#[doc = "Set all vector lanes to the same value"]
9627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
9628#[inline]
9629#[target_feature(enable = "neon")]
9630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9631#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9632#[cfg_attr(
9633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9634 assert_instr(dup, N = 2)
9635)]
9636#[rustc_legacy_const_generics(1)]
9637#[cfg_attr(
9638 not(target_arch = "arm"),
9639 stable(feature = "neon_intrinsics", since = "1.59.0")
9640)]
9641#[cfg_attr(
9642 target_arch = "arm",
9643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9644)]
9645pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
9646 static_assert_uimm_bits!(N, 2);
9647 unsafe {
9648 simd_shuffle!(
9649 a,
9650 a,
9651 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9652 )
9653 }
9654}
9655#[doc = "Set all vector lanes to the same value"]
9656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
9657#[inline]
9658#[target_feature(enable = "neon")]
9659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
9661#[cfg_attr(
9662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9663 assert_instr(dup, N = 2)
9664)]
9665#[rustc_legacy_const_generics(1)]
9666#[cfg_attr(
9667 not(target_arch = "arm"),
9668 stable(feature = "neon_intrinsics", since = "1.59.0")
9669)]
9670#[cfg_attr(
9671 target_arch = "arm",
9672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9673)]
9674pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
9675 static_assert_uimm_bits!(N, 2);
9676 unsafe {
9677 simd_shuffle!(
9678 a,
9679 a,
9680 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9681 )
9682 }
9683}
9684#[doc = "Set all vector lanes to the same value"]
9685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
9686#[inline]
9687#[target_feature(enable = "neon")]
9688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9689#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9690#[cfg_attr(
9691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9692 assert_instr(dup, N = 4)
9693)]
9694#[rustc_legacy_const_generics(1)]
9695#[cfg_attr(
9696 not(target_arch = "arm"),
9697 stable(feature = "neon_intrinsics", since = "1.59.0")
9698)]
9699#[cfg_attr(
9700 target_arch = "arm",
9701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9702)]
9703pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
9704 static_assert_uimm_bits!(N, 3);
9705 unsafe {
9706 simd_shuffle!(
9707 a,
9708 a,
9709 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9710 )
9711 }
9712}
9713#[doc = "Set all vector lanes to the same value"]
9714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
9715#[inline]
9716#[target_feature(enable = "neon")]
9717#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9718#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9719#[cfg_attr(
9720 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9721 assert_instr(dup, N = 4)
9722)]
9723#[rustc_legacy_const_generics(1)]
9724#[cfg_attr(
9725 not(target_arch = "arm"),
9726 stable(feature = "neon_intrinsics", since = "1.59.0")
9727)]
9728#[cfg_attr(
9729 target_arch = "arm",
9730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9731)]
9732pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
9733 static_assert_uimm_bits!(N, 3);
9734 unsafe {
9735 simd_shuffle!(
9736 a,
9737 a,
9738 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9739 )
9740 }
9741}
9742#[doc = "Set all vector lanes to the same value"]
9743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
9744#[inline]
9745#[target_feature(enable = "neon")]
9746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9747#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9748#[cfg_attr(
9749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9750 assert_instr(dup, N = 4)
9751)]
9752#[rustc_legacy_const_generics(1)]
9753#[cfg_attr(
9754 not(target_arch = "arm"),
9755 stable(feature = "neon_intrinsics", since = "1.59.0")
9756)]
9757#[cfg_attr(
9758 target_arch = "arm",
9759 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9760)]
9761pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
9762 static_assert_uimm_bits!(N, 3);
9763 unsafe {
9764 simd_shuffle!(
9765 a,
9766 a,
9767 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9768 )
9769 }
9770}
9771#[doc = "Set all vector lanes to the same value"]
9772#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
9773#[inline]
9774#[target_feature(enable = "neon")]
9775#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9776#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9777#[cfg_attr(
9778 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9779 assert_instr(dup, N = 4)
9780)]
9781#[rustc_legacy_const_generics(1)]
9782#[cfg_attr(
9783 not(target_arch = "arm"),
9784 stable(feature = "neon_intrinsics", since = "1.59.0")
9785)]
9786#[cfg_attr(
9787 target_arch = "arm",
9788 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9789)]
9790pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
9791 static_assert_uimm_bits!(N, 3);
9792 unsafe {
9793 simd_shuffle!(
9794 a,
9795 a,
9796 [
9797 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9798 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9799 ]
9800 )
9801 }
9802}
9803#[doc = "Set all vector lanes to the same value"]
9804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
9805#[inline]
9806#[target_feature(enable = "neon")]
9807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9809#[cfg_attr(
9810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9811 assert_instr(dup, N = 4)
9812)]
9813#[rustc_legacy_const_generics(1)]
9814#[cfg_attr(
9815 not(target_arch = "arm"),
9816 stable(feature = "neon_intrinsics", since = "1.59.0")
9817)]
9818#[cfg_attr(
9819 target_arch = "arm",
9820 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9821)]
9822pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
9823 static_assert_uimm_bits!(N, 3);
9824 unsafe {
9825 simd_shuffle!(
9826 a,
9827 a,
9828 [
9829 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9830 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9831 ]
9832 )
9833 }
9834}
9835#[doc = "Set all vector lanes to the same value"]
9836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
9837#[inline]
9838#[target_feature(enable = "neon")]
9839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
9841#[cfg_attr(
9842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9843 assert_instr(dup, N = 4)
9844)]
9845#[rustc_legacy_const_generics(1)]
9846#[cfg_attr(
9847 not(target_arch = "arm"),
9848 stable(feature = "neon_intrinsics", since = "1.59.0")
9849)]
9850#[cfg_attr(
9851 target_arch = "arm",
9852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9853)]
9854pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
9855 static_assert_uimm_bits!(N, 3);
9856 unsafe {
9857 simd_shuffle!(
9858 a,
9859 a,
9860 [
9861 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
9862 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
9863 ]
9864 )
9865 }
9866}
9867#[doc = "Set all vector lanes to the same value"]
9868#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
9869#[inline]
9870#[target_feature(enable = "neon")]
9871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9873#[cfg_attr(
9874 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9875 assert_instr(nop, N = 0)
9876)]
9877#[rustc_legacy_const_generics(1)]
9878#[cfg_attr(
9879 not(target_arch = "arm"),
9880 stable(feature = "neon_intrinsics", since = "1.59.0")
9881)]
9882#[cfg_attr(
9883 target_arch = "arm",
9884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9885)]
9886pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
9887 static_assert!(N == 0);
9888 a
9889}
9890#[doc = "Set all vector lanes to the same value"]
9891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
9892#[inline]
9893#[target_feature(enable = "neon")]
9894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
9896#[cfg_attr(
9897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9898 assert_instr(nop, N = 0)
9899)]
9900#[rustc_legacy_const_generics(1)]
9901#[cfg_attr(
9902 not(target_arch = "arm"),
9903 stable(feature = "neon_intrinsics", since = "1.59.0")
9904)]
9905#[cfg_attr(
9906 target_arch = "arm",
9907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9908)]
9909pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
9910 static_assert!(N == 0);
9911 a
9912}
9913#[doc = "Set all vector lanes to the same value"]
9914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
9915#[inline]
9916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9917#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
9918#[cfg_attr(
9919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9920 assert_instr(dup, N = 4)
9921)]
9922#[rustc_legacy_const_generics(1)]
9923#[target_feature(enable = "neon,fp16")]
9924#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9925pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
9926 static_assert_uimm_bits!(N, 3);
9927 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
9928}
9929#[doc = "Set all vector lanes to the same value"]
9930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
9931#[inline]
9932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9933#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
9934#[cfg_attr(
9935 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9936 assert_instr(dup, N = 4)
9937)]
9938#[rustc_legacy_const_generics(1)]
9939#[target_feature(enable = "neon,fp16")]
9940#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
9941pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
9942 static_assert_uimm_bits!(N, 3);
9943 unsafe {
9944 simd_shuffle!(
9945 a,
9946 a,
9947 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
9948 )
9949 }
9950}
9951#[doc = "Set all vector lanes to the same value"]
9952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
9953#[inline]
9954#[target_feature(enable = "neon")]
9955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9956#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
9957#[cfg_attr(
9958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9959 assert_instr(dup, N = 2)
9960)]
9961#[rustc_legacy_const_generics(1)]
9962#[cfg_attr(
9963 not(target_arch = "arm"),
9964 stable(feature = "neon_intrinsics", since = "1.59.0")
9965)]
9966#[cfg_attr(
9967 target_arch = "arm",
9968 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9969)]
9970pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
9971 static_assert_uimm_bits!(N, 2);
9972 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9973}
9974#[doc = "Set all vector lanes to the same value"]
9975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
9976#[inline]
9977#[target_feature(enable = "neon")]
9978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
9979#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
9980#[cfg_attr(
9981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
9982 assert_instr(dup, N = 2)
9983)]
9984#[rustc_legacy_const_generics(1)]
9985#[cfg_attr(
9986 not(target_arch = "arm"),
9987 stable(feature = "neon_intrinsics", since = "1.59.0")
9988)]
9989#[cfg_attr(
9990 target_arch = "arm",
9991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
9992)]
9993pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
9994 static_assert_uimm_bits!(N, 2);
9995 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
9996}
9997#[doc = "Set all vector lanes to the same value"]
9998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
9999#[inline]
10000#[target_feature(enable = "neon")]
10001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10002#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10003#[cfg_attr(
10004 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10005 assert_instr(dup, N = 2)
10006)]
10007#[rustc_legacy_const_generics(1)]
10008#[cfg_attr(
10009 not(target_arch = "arm"),
10010 stable(feature = "neon_intrinsics", since = "1.59.0")
10011)]
10012#[cfg_attr(
10013 target_arch = "arm",
10014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10015)]
10016pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
10017 static_assert_uimm_bits!(N, 2);
10018 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
10019}
10020#[doc = "Set all vector lanes to the same value"]
10021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
10022#[inline]
10023#[target_feature(enable = "neon")]
10024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10025#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10026#[cfg_attr(
10027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10028 assert_instr(dup, N = 2)
10029)]
10030#[rustc_legacy_const_generics(1)]
10031#[cfg_attr(
10032 not(target_arch = "arm"),
10033 stable(feature = "neon_intrinsics", since = "1.59.0")
10034)]
10035#[cfg_attr(
10036 target_arch = "arm",
10037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10038)]
10039pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
10040 static_assert_uimm_bits!(N, 2);
10041 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10042}
10043#[doc = "Set all vector lanes to the same value"]
10044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
10045#[inline]
10046#[target_feature(enable = "neon")]
10047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10048#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10049#[cfg_attr(
10050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10051 assert_instr(dup, N = 2)
10052)]
10053#[rustc_legacy_const_generics(1)]
10054#[cfg_attr(
10055 not(target_arch = "arm"),
10056 stable(feature = "neon_intrinsics", since = "1.59.0")
10057)]
10058#[cfg_attr(
10059 target_arch = "arm",
10060 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10061)]
10062pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
10063 static_assert_uimm_bits!(N, 2);
10064 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10065}
10066#[doc = "Set all vector lanes to the same value"]
10067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
10068#[inline]
10069#[target_feature(enable = "neon")]
10070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10071#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
10072#[cfg_attr(
10073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10074 assert_instr(dup, N = 2)
10075)]
10076#[rustc_legacy_const_generics(1)]
10077#[cfg_attr(
10078 not(target_arch = "arm"),
10079 stable(feature = "neon_intrinsics", since = "1.59.0")
10080)]
10081#[cfg_attr(
10082 target_arch = "arm",
10083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10084)]
10085pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
10086 static_assert_uimm_bits!(N, 2);
10087 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10088}
10089#[doc = "Set all vector lanes to the same value"]
10090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
10091#[inline]
10092#[target_feature(enable = "neon")]
10093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10095#[cfg_attr(
10096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10097 assert_instr(dup, N = 4)
10098)]
10099#[rustc_legacy_const_generics(1)]
10100#[cfg_attr(
10101 not(target_arch = "arm"),
10102 stable(feature = "neon_intrinsics", since = "1.59.0")
10103)]
10104#[cfg_attr(
10105 target_arch = "arm",
10106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10107)]
10108pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
10109 static_assert_uimm_bits!(N, 3);
10110 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10111}
10112#[doc = "Set all vector lanes to the same value"]
10113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
10114#[inline]
10115#[target_feature(enable = "neon")]
10116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10117#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10118#[cfg_attr(
10119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10120 assert_instr(dup, N = 4)
10121)]
10122#[rustc_legacy_const_generics(1)]
10123#[cfg_attr(
10124 not(target_arch = "arm"),
10125 stable(feature = "neon_intrinsics", since = "1.59.0")
10126)]
10127#[cfg_attr(
10128 target_arch = "arm",
10129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10130)]
10131pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
10132 static_assert_uimm_bits!(N, 3);
10133 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10134}
10135#[doc = "Set all vector lanes to the same value"]
10136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
10137#[inline]
10138#[target_feature(enable = "neon")]
10139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10141#[cfg_attr(
10142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10143 assert_instr(dup, N = 4)
10144)]
10145#[rustc_legacy_const_generics(1)]
10146#[cfg_attr(
10147 not(target_arch = "arm"),
10148 stable(feature = "neon_intrinsics", since = "1.59.0")
10149)]
10150#[cfg_attr(
10151 target_arch = "arm",
10152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10153)]
10154pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
10155 static_assert_uimm_bits!(N, 3);
10156 unsafe { simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) }
10157}
10158#[doc = "Set all vector lanes to the same value"]
10159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
10160#[inline]
10161#[target_feature(enable = "neon")]
10162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10163#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10164#[cfg_attr(
10165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10166 assert_instr(dup, N = 4)
10167)]
10168#[rustc_legacy_const_generics(1)]
10169#[cfg_attr(
10170 not(target_arch = "arm"),
10171 stable(feature = "neon_intrinsics", since = "1.59.0")
10172)]
10173#[cfg_attr(
10174 target_arch = "arm",
10175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10176)]
10177pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
10178 static_assert_uimm_bits!(N, 3);
10179 unsafe {
10180 simd_shuffle!(
10181 a,
10182 a,
10183 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10184 )
10185 }
10186}
10187#[doc = "Set all vector lanes to the same value"]
10188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
10189#[inline]
10190#[target_feature(enable = "neon")]
10191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10192#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10193#[cfg_attr(
10194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10195 assert_instr(dup, N = 4)
10196)]
10197#[rustc_legacy_const_generics(1)]
10198#[cfg_attr(
10199 not(target_arch = "arm"),
10200 stable(feature = "neon_intrinsics", since = "1.59.0")
10201)]
10202#[cfg_attr(
10203 target_arch = "arm",
10204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10205)]
10206pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
10207 static_assert_uimm_bits!(N, 3);
10208 unsafe {
10209 simd_shuffle!(
10210 a,
10211 a,
10212 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10213 )
10214 }
10215}
10216#[doc = "Set all vector lanes to the same value"]
10217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
10218#[inline]
10219#[target_feature(enable = "neon")]
10220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10221#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
10222#[cfg_attr(
10223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10224 assert_instr(dup, N = 4)
10225)]
10226#[rustc_legacy_const_generics(1)]
10227#[cfg_attr(
10228 not(target_arch = "arm"),
10229 stable(feature = "neon_intrinsics", since = "1.59.0")
10230)]
10231#[cfg_attr(
10232 target_arch = "arm",
10233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10234)]
10235pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
10236 static_assert_uimm_bits!(N, 3);
10237 unsafe {
10238 simd_shuffle!(
10239 a,
10240 a,
10241 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10242 )
10243 }
10244}
10245#[doc = "Set all vector lanes to the same value"]
10246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
10247#[inline]
10248#[target_feature(enable = "neon")]
10249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10250#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10251#[cfg_attr(
10252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10253 assert_instr(dup, N = 8)
10254)]
10255#[rustc_legacy_const_generics(1)]
10256#[cfg_attr(
10257 not(target_arch = "arm"),
10258 stable(feature = "neon_intrinsics", since = "1.59.0")
10259)]
10260#[cfg_attr(
10261 target_arch = "arm",
10262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10263)]
10264pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
10265 static_assert_uimm_bits!(N, 4);
10266 unsafe {
10267 simd_shuffle!(
10268 a,
10269 a,
10270 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10271 )
10272 }
10273}
10274#[doc = "Set all vector lanes to the same value"]
10275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
10276#[inline]
10277#[target_feature(enable = "neon")]
10278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10280#[cfg_attr(
10281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10282 assert_instr(dup, N = 8)
10283)]
10284#[rustc_legacy_const_generics(1)]
10285#[cfg_attr(
10286 not(target_arch = "arm"),
10287 stable(feature = "neon_intrinsics", since = "1.59.0")
10288)]
10289#[cfg_attr(
10290 target_arch = "arm",
10291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10292)]
10293pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
10294 static_assert_uimm_bits!(N, 4);
10295 unsafe {
10296 simd_shuffle!(
10297 a,
10298 a,
10299 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10300 )
10301 }
10302}
10303#[doc = "Set all vector lanes to the same value"]
10304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
10305#[inline]
10306#[target_feature(enable = "neon")]
10307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10308#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10309#[cfg_attr(
10310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10311 assert_instr(dup, N = 8)
10312)]
10313#[rustc_legacy_const_generics(1)]
10314#[cfg_attr(
10315 not(target_arch = "arm"),
10316 stable(feature = "neon_intrinsics", since = "1.59.0")
10317)]
10318#[cfg_attr(
10319 target_arch = "arm",
10320 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10321)]
10322pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
10323 static_assert_uimm_bits!(N, 4);
10324 unsafe {
10325 simd_shuffle!(
10326 a,
10327 a,
10328 [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]
10329 )
10330 }
10331}
10332#[doc = "Set all vector lanes to the same value"]
10333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
10334#[inline]
10335#[target_feature(enable = "neon")]
10336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10337#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10338#[cfg_attr(
10339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10340 assert_instr(dup, N = 8)
10341)]
10342#[rustc_legacy_const_generics(1)]
10343#[cfg_attr(
10344 not(target_arch = "arm"),
10345 stable(feature = "neon_intrinsics", since = "1.59.0")
10346)]
10347#[cfg_attr(
10348 target_arch = "arm",
10349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10350)]
10351pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
10352 static_assert_uimm_bits!(N, 4);
10353 unsafe {
10354 simd_shuffle!(
10355 a,
10356 a,
10357 [
10358 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10359 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10360 ]
10361 )
10362 }
10363}
10364#[doc = "Set all vector lanes to the same value"]
10365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
10366#[inline]
10367#[target_feature(enable = "neon")]
10368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10369#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10370#[cfg_attr(
10371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10372 assert_instr(dup, N = 8)
10373)]
10374#[rustc_legacy_const_generics(1)]
10375#[cfg_attr(
10376 not(target_arch = "arm"),
10377 stable(feature = "neon_intrinsics", since = "1.59.0")
10378)]
10379#[cfg_attr(
10380 target_arch = "arm",
10381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10382)]
10383pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
10384 static_assert_uimm_bits!(N, 4);
10385 unsafe {
10386 simd_shuffle!(
10387 a,
10388 a,
10389 [
10390 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10391 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10392 ]
10393 )
10394 }
10395}
10396#[doc = "Set all vector lanes to the same value"]
10397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
10398#[inline]
10399#[target_feature(enable = "neon")]
10400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10401#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
10402#[cfg_attr(
10403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10404 assert_instr(dup, N = 8)
10405)]
10406#[rustc_legacy_const_generics(1)]
10407#[cfg_attr(
10408 not(target_arch = "arm"),
10409 stable(feature = "neon_intrinsics", since = "1.59.0")
10410)]
10411#[cfg_attr(
10412 target_arch = "arm",
10413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10414)]
10415pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
10416 static_assert_uimm_bits!(N, 4);
10417 unsafe {
10418 simd_shuffle!(
10419 a,
10420 a,
10421 [
10422 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32,
10423 N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32
10424 ]
10425 )
10426 }
10427}
10428#[doc = "Set all vector lanes to the same value"]
10429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
10430#[inline]
10431#[target_feature(enable = "neon")]
10432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10434#[cfg_attr(
10435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10436 assert_instr(nop, N = 1)
10437)]
10438#[rustc_legacy_const_generics(1)]
10439#[cfg_attr(
10440 not(target_arch = "arm"),
10441 stable(feature = "neon_intrinsics", since = "1.59.0")
10442)]
10443#[cfg_attr(
10444 target_arch = "arm",
10445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10446)]
10447pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
10448 static_assert_uimm_bits!(N, 1);
10449 unsafe { transmute::<i64, _>(simd_extract!(a, N as u32)) }
10450}
10451#[doc = "Set all vector lanes to the same value"]
10452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
10453#[inline]
10454#[target_feature(enable = "neon")]
10455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
10457#[cfg_attr(
10458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10459 assert_instr(nop, N = 1)
10460)]
10461#[rustc_legacy_const_generics(1)]
10462#[cfg_attr(
10463 not(target_arch = "arm"),
10464 stable(feature = "neon_intrinsics", since = "1.59.0")
10465)]
10466#[cfg_attr(
10467 target_arch = "arm",
10468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10469)]
10470pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
10471 static_assert_uimm_bits!(N, 1);
10472 unsafe { transmute::<u64, _>(simd_extract!(a, N as u32)) }
10473}
10474#[doc = "Create a new vector with all lanes set to a value"]
10475#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
10476#[inline]
10477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10478#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10479#[cfg_attr(
10480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10481 assert_instr(dup)
10482)]
10483#[target_feature(enable = "neon,fp16")]
10484#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10485pub fn vdup_n_f16(a: f16) -> float16x4_t {
10486 float16x4_t::splat(a)
10487}
10488#[doc = "Create a new vector with all lanes set to a value"]
10489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
10490#[inline]
10491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10492#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10493#[cfg_attr(
10494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10495 assert_instr(dup)
10496)]
10497#[target_feature(enable = "neon,fp16")]
10498#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
10499pub fn vdupq_n_f16(a: f16) -> float16x8_t {
10500 float16x8_t::splat(a)
10501}
10502#[doc = "Duplicate vector element to vector or scalar"]
10503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
10504#[inline]
10505#[target_feature(enable = "neon")]
10506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10507#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10508#[cfg_attr(
10509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10510 assert_instr(dup)
10511)]
10512#[cfg_attr(
10513 not(target_arch = "arm"),
10514 stable(feature = "neon_intrinsics", since = "1.59.0")
10515)]
10516#[cfg_attr(
10517 target_arch = "arm",
10518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10519)]
10520pub fn vdup_n_f32(value: f32) -> float32x2_t {
10521 float32x2_t::splat(value)
10522}
10523#[doc = "Duplicate vector element to vector or scalar"]
10524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
10525#[inline]
10526#[target_feature(enable = "neon")]
10527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10528#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10529#[cfg_attr(
10530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10531 assert_instr(dup)
10532)]
10533#[cfg_attr(
10534 not(target_arch = "arm"),
10535 stable(feature = "neon_intrinsics", since = "1.59.0")
10536)]
10537#[cfg_attr(
10538 target_arch = "arm",
10539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10540)]
10541pub fn vdup_n_p16(value: p16) -> poly16x4_t {
10542 poly16x4_t::splat(value)
10543}
10544#[doc = "Duplicate vector element to vector or scalar"]
10545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
10546#[inline]
10547#[target_feature(enable = "neon")]
10548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10549#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10550#[cfg_attr(
10551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10552 assert_instr(dup)
10553)]
10554#[cfg_attr(
10555 not(target_arch = "arm"),
10556 stable(feature = "neon_intrinsics", since = "1.59.0")
10557)]
10558#[cfg_attr(
10559 target_arch = "arm",
10560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10561)]
10562pub fn vdup_n_p8(value: p8) -> poly8x8_t {
10563 poly8x8_t::splat(value)
10564}
10565#[doc = "Duplicate vector element to vector or scalar"]
10566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
10567#[inline]
10568#[target_feature(enable = "neon")]
10569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10570#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10571#[cfg_attr(
10572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10573 assert_instr(dup)
10574)]
10575#[cfg_attr(
10576 not(target_arch = "arm"),
10577 stable(feature = "neon_intrinsics", since = "1.59.0")
10578)]
10579#[cfg_attr(
10580 target_arch = "arm",
10581 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10582)]
10583pub fn vdup_n_s16(value: i16) -> int16x4_t {
10584 int16x4_t::splat(value)
10585}
10586#[doc = "Duplicate vector element to vector or scalar"]
10587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
10588#[inline]
10589#[target_feature(enable = "neon")]
10590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10592#[cfg_attr(
10593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10594 assert_instr(dup)
10595)]
10596#[cfg_attr(
10597 not(target_arch = "arm"),
10598 stable(feature = "neon_intrinsics", since = "1.59.0")
10599)]
10600#[cfg_attr(
10601 target_arch = "arm",
10602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10603)]
10604pub fn vdup_n_s32(value: i32) -> int32x2_t {
10605 int32x2_t::splat(value)
10606}
10607#[doc = "Duplicate vector element to vector or scalar"]
10608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
10609#[inline]
10610#[target_feature(enable = "neon")]
10611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10613#[cfg_attr(
10614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10615 assert_instr(fmov)
10616)]
10617#[cfg_attr(
10618 not(target_arch = "arm"),
10619 stable(feature = "neon_intrinsics", since = "1.59.0")
10620)]
10621#[cfg_attr(
10622 target_arch = "arm",
10623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10624)]
10625pub fn vdup_n_s64(value: i64) -> int64x1_t {
10626 int64x1_t::splat(value)
10627}
10628#[doc = "Duplicate vector element to vector or scalar"]
10629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
10630#[inline]
10631#[target_feature(enable = "neon")]
10632#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10633#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10634#[cfg_attr(
10635 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10636 assert_instr(dup)
10637)]
10638#[cfg_attr(
10639 not(target_arch = "arm"),
10640 stable(feature = "neon_intrinsics", since = "1.59.0")
10641)]
10642#[cfg_attr(
10643 target_arch = "arm",
10644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10645)]
10646pub fn vdup_n_s8(value: i8) -> int8x8_t {
10647 int8x8_t::splat(value)
10648}
10649#[doc = "Duplicate vector element to vector or scalar"]
10650#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
10651#[inline]
10652#[target_feature(enable = "neon")]
10653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10654#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10655#[cfg_attr(
10656 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10657 assert_instr(dup)
10658)]
10659#[cfg_attr(
10660 not(target_arch = "arm"),
10661 stable(feature = "neon_intrinsics", since = "1.59.0")
10662)]
10663#[cfg_attr(
10664 target_arch = "arm",
10665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10666)]
10667pub fn vdup_n_u16(value: u16) -> uint16x4_t {
10668 uint16x4_t::splat(value)
10669}
10670#[doc = "Duplicate vector element to vector or scalar"]
10671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
10672#[inline]
10673#[target_feature(enable = "neon")]
10674#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10675#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10676#[cfg_attr(
10677 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10678 assert_instr(dup)
10679)]
10680#[cfg_attr(
10681 not(target_arch = "arm"),
10682 stable(feature = "neon_intrinsics", since = "1.59.0")
10683)]
10684#[cfg_attr(
10685 target_arch = "arm",
10686 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10687)]
10688pub fn vdup_n_u32(value: u32) -> uint32x2_t {
10689 uint32x2_t::splat(value)
10690}
10691#[doc = "Duplicate vector element to vector or scalar"]
10692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
10693#[inline]
10694#[target_feature(enable = "neon")]
10695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10696#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10697#[cfg_attr(
10698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10699 assert_instr(fmov)
10700)]
10701#[cfg_attr(
10702 not(target_arch = "arm"),
10703 stable(feature = "neon_intrinsics", since = "1.59.0")
10704)]
10705#[cfg_attr(
10706 target_arch = "arm",
10707 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10708)]
10709pub fn vdup_n_u64(value: u64) -> uint64x1_t {
10710 uint64x1_t::splat(value)
10711}
10712#[doc = "Duplicate vector element to vector or scalar"]
10713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
10714#[inline]
10715#[target_feature(enable = "neon")]
10716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10717#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10718#[cfg_attr(
10719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10720 assert_instr(dup)
10721)]
10722#[cfg_attr(
10723 not(target_arch = "arm"),
10724 stable(feature = "neon_intrinsics", since = "1.59.0")
10725)]
10726#[cfg_attr(
10727 target_arch = "arm",
10728 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10729)]
10730pub fn vdup_n_u8(value: u8) -> uint8x8_t {
10731 uint8x8_t::splat(value)
10732}
10733#[doc = "Duplicate vector element to vector or scalar"]
10734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
10735#[inline]
10736#[target_feature(enable = "neon")]
10737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10739#[cfg_attr(
10740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10741 assert_instr(dup)
10742)]
10743#[cfg_attr(
10744 not(target_arch = "arm"),
10745 stable(feature = "neon_intrinsics", since = "1.59.0")
10746)]
10747#[cfg_attr(
10748 target_arch = "arm",
10749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10750)]
10751pub fn vdupq_n_f32(value: f32) -> float32x4_t {
10752 float32x4_t::splat(value)
10753}
10754#[doc = "Duplicate vector element to vector or scalar"]
10755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
10756#[inline]
10757#[target_feature(enable = "neon")]
10758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10759#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10760#[cfg_attr(
10761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10762 assert_instr(dup)
10763)]
10764#[cfg_attr(
10765 not(target_arch = "arm"),
10766 stable(feature = "neon_intrinsics", since = "1.59.0")
10767)]
10768#[cfg_attr(
10769 target_arch = "arm",
10770 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10771)]
10772pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
10773 poly16x8_t::splat(value)
10774}
10775#[doc = "Duplicate vector element to vector or scalar"]
10776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
10777#[inline]
10778#[target_feature(enable = "neon")]
10779#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10780#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10781#[cfg_attr(
10782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10783 assert_instr(dup)
10784)]
10785#[cfg_attr(
10786 not(target_arch = "arm"),
10787 stable(feature = "neon_intrinsics", since = "1.59.0")
10788)]
10789#[cfg_attr(
10790 target_arch = "arm",
10791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10792)]
10793pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
10794 poly8x16_t::splat(value)
10795}
10796#[doc = "Duplicate vector element to vector or scalar"]
10797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
10798#[inline]
10799#[target_feature(enable = "neon")]
10800#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10801#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10802#[cfg_attr(
10803 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10804 assert_instr(dup)
10805)]
10806#[cfg_attr(
10807 not(target_arch = "arm"),
10808 stable(feature = "neon_intrinsics", since = "1.59.0")
10809)]
10810#[cfg_attr(
10811 target_arch = "arm",
10812 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10813)]
10814pub fn vdupq_n_s16(value: i16) -> int16x8_t {
10815 int16x8_t::splat(value)
10816}
10817#[doc = "Duplicate vector element to vector or scalar"]
10818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
10819#[inline]
10820#[target_feature(enable = "neon")]
10821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10822#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10823#[cfg_attr(
10824 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10825 assert_instr(dup)
10826)]
10827#[cfg_attr(
10828 not(target_arch = "arm"),
10829 stable(feature = "neon_intrinsics", since = "1.59.0")
10830)]
10831#[cfg_attr(
10832 target_arch = "arm",
10833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10834)]
10835pub fn vdupq_n_s32(value: i32) -> int32x4_t {
10836 int32x4_t::splat(value)
10837}
10838#[doc = "Duplicate vector element to vector or scalar"]
10839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
10840#[inline]
10841#[target_feature(enable = "neon")]
10842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10844#[cfg_attr(
10845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10846 assert_instr(dup)
10847)]
10848#[cfg_attr(
10849 not(target_arch = "arm"),
10850 stable(feature = "neon_intrinsics", since = "1.59.0")
10851)]
10852#[cfg_attr(
10853 target_arch = "arm",
10854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10855)]
10856pub fn vdupq_n_s64(value: i64) -> int64x2_t {
10857 int64x2_t::splat(value)
10858}
10859#[doc = "Duplicate vector element to vector or scalar"]
10860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
10861#[inline]
10862#[target_feature(enable = "neon")]
10863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10864#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10865#[cfg_attr(
10866 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10867 assert_instr(dup)
10868)]
10869#[cfg_attr(
10870 not(target_arch = "arm"),
10871 stable(feature = "neon_intrinsics", since = "1.59.0")
10872)]
10873#[cfg_attr(
10874 target_arch = "arm",
10875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10876)]
10877pub fn vdupq_n_s8(value: i8) -> int8x16_t {
10878 int8x16_t::splat(value)
10879}
10880#[doc = "Duplicate vector element to vector or scalar"]
10881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
10882#[inline]
10883#[target_feature(enable = "neon")]
10884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10885#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
10886#[cfg_attr(
10887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10888 assert_instr(dup)
10889)]
10890#[cfg_attr(
10891 not(target_arch = "arm"),
10892 stable(feature = "neon_intrinsics", since = "1.59.0")
10893)]
10894#[cfg_attr(
10895 target_arch = "arm",
10896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10897)]
10898pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
10899 uint16x8_t::splat(value)
10900}
10901#[doc = "Duplicate vector element to vector or scalar"]
10902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
10903#[inline]
10904#[target_feature(enable = "neon")]
10905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10906#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10907#[cfg_attr(
10908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10909 assert_instr(dup)
10910)]
10911#[cfg_attr(
10912 not(target_arch = "arm"),
10913 stable(feature = "neon_intrinsics", since = "1.59.0")
10914)]
10915#[cfg_attr(
10916 target_arch = "arm",
10917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10918)]
10919pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
10920 uint32x4_t::splat(value)
10921}
10922#[doc = "Duplicate vector element to vector or scalar"]
10923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
10924#[inline]
10925#[target_feature(enable = "neon")]
10926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10927#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
10928#[cfg_attr(
10929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10930 assert_instr(dup)
10931)]
10932#[cfg_attr(
10933 not(target_arch = "arm"),
10934 stable(feature = "neon_intrinsics", since = "1.59.0")
10935)]
10936#[cfg_attr(
10937 target_arch = "arm",
10938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10939)]
10940pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
10941 uint64x2_t::splat(value)
10942}
10943#[doc = "Duplicate vector element to vector or scalar"]
10944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
10945#[inline]
10946#[target_feature(enable = "neon")]
10947#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
10948#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
10949#[cfg_attr(
10950 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10951 assert_instr(dup)
10952)]
10953#[cfg_attr(
10954 not(target_arch = "arm"),
10955 stable(feature = "neon_intrinsics", since = "1.59.0")
10956)]
10957#[cfg_attr(
10958 target_arch = "arm",
10959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10960)]
10961pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
10962 uint8x16_t::splat(value)
10963}
10964#[doc = "Duplicate vector element to vector or scalar"]
10965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
10966#[inline]
10967#[target_feature(enable = "neon")]
10968#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
10969#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10970#[cfg_attr(
10971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10972 assert_instr(dup)
10973)]
10974#[cfg_attr(
10975 not(target_arch = "arm"),
10976 stable(feature = "neon_intrinsics", since = "1.59.0")
10977)]
10978#[cfg_attr(
10979 target_arch = "arm",
10980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
10981)]
10982fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
10983 float32x2_t::splat(value)
10984}
10985#[doc = "Duplicate vector element to vector or scalar"]
10986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
10987#[inline]
10988#[target_feature(enable = "neon")]
10989#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
10990#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
10991#[cfg_attr(
10992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
10993 assert_instr(dup)
10994)]
10995#[cfg_attr(
10996 not(target_arch = "arm"),
10997 stable(feature = "neon_intrinsics", since = "1.59.0")
10998)]
10999#[cfg_attr(
11000 target_arch = "arm",
11001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11002)]
11003fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
11004 float32x4_t::splat(value)
11005}
11006#[doc = "Set all vector lanes to the same value"]
11007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
11008#[inline]
11009#[target_feature(enable = "neon")]
11010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11011#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11012#[cfg_attr(
11013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11014 assert_instr(dup, N = 0)
11015)]
11016#[rustc_legacy_const_generics(1)]
11017#[cfg_attr(
11018 not(target_arch = "arm"),
11019 stable(feature = "neon_intrinsics", since = "1.59.0")
11020)]
11021#[cfg_attr(
11022 target_arch = "arm",
11023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11024)]
11025pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
11026 static_assert!(N == 0);
11027 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11028}
11029#[doc = "Set all vector lanes to the same value"]
11030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
11031#[inline]
11032#[target_feature(enable = "neon")]
11033#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11034#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
11035#[cfg_attr(
11036 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11037 assert_instr(dup, N = 0)
11038)]
11039#[rustc_legacy_const_generics(1)]
11040#[cfg_attr(
11041 not(target_arch = "arm"),
11042 stable(feature = "neon_intrinsics", since = "1.59.0")
11043)]
11044#[cfg_attr(
11045 target_arch = "arm",
11046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11047)]
11048pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
11049 static_assert!(N == 0);
11050 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11051}
11052#[doc = "Set all vector lanes to the same value"]
11053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
11054#[inline]
11055#[target_feature(enable = "neon")]
11056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11058#[cfg_attr(
11059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11060 assert_instr(dup, N = 1)
11061)]
11062#[rustc_legacy_const_generics(1)]
11063#[cfg_attr(
11064 not(target_arch = "arm"),
11065 stable(feature = "neon_intrinsics", since = "1.59.0")
11066)]
11067#[cfg_attr(
11068 target_arch = "arm",
11069 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11070)]
11071pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
11072 static_assert_uimm_bits!(N, 1);
11073 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11074}
11075#[doc = "Set all vector lanes to the same value"]
11076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
11077#[inline]
11078#[target_feature(enable = "neon")]
11079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
11081#[cfg_attr(
11082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11083 assert_instr(dup, N = 1)
11084)]
11085#[rustc_legacy_const_generics(1)]
11086#[cfg_attr(
11087 not(target_arch = "arm"),
11088 stable(feature = "neon_intrinsics", since = "1.59.0")
11089)]
11090#[cfg_attr(
11091 target_arch = "arm",
11092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11093)]
11094pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
11095 static_assert_uimm_bits!(N, 1);
11096 unsafe { simd_shuffle!(a, a, [N as u32, N as u32]) }
11097}
11098#[doc = "Vector bitwise exclusive or (vector)"]
11099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
11100#[inline]
11101#[target_feature(enable = "neon")]
11102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11104#[cfg_attr(
11105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11106 assert_instr(eor)
11107)]
11108#[cfg_attr(
11109 not(target_arch = "arm"),
11110 stable(feature = "neon_intrinsics", since = "1.59.0")
11111)]
11112#[cfg_attr(
11113 target_arch = "arm",
11114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11115)]
11116pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11117 unsafe { simd_xor(a, b) }
11118}
11119#[doc = "Vector bitwise exclusive or (vector)"]
11120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
11121#[inline]
11122#[target_feature(enable = "neon")]
11123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11125#[cfg_attr(
11126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11127 assert_instr(eor)
11128)]
11129#[cfg_attr(
11130 not(target_arch = "arm"),
11131 stable(feature = "neon_intrinsics", since = "1.59.0")
11132)]
11133#[cfg_attr(
11134 target_arch = "arm",
11135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11136)]
11137pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
11138 unsafe { simd_xor(a, b) }
11139}
11140#[doc = "Vector bitwise exclusive or (vector)"]
11141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
11142#[inline]
11143#[target_feature(enable = "neon")]
11144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11145#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11146#[cfg_attr(
11147 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11148 assert_instr(eor)
11149)]
11150#[cfg_attr(
11151 not(target_arch = "arm"),
11152 stable(feature = "neon_intrinsics", since = "1.59.0")
11153)]
11154#[cfg_attr(
11155 target_arch = "arm",
11156 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11157)]
11158pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11159 unsafe { simd_xor(a, b) }
11160}
11161#[doc = "Vector bitwise exclusive or (vector)"]
11162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
11163#[inline]
11164#[target_feature(enable = "neon")]
11165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11167#[cfg_attr(
11168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11169 assert_instr(eor)
11170)]
11171#[cfg_attr(
11172 not(target_arch = "arm"),
11173 stable(feature = "neon_intrinsics", since = "1.59.0")
11174)]
11175#[cfg_attr(
11176 target_arch = "arm",
11177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11178)]
11179pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11180 unsafe { simd_xor(a, b) }
11181}
11182#[doc = "Vector bitwise exclusive or (vector)"]
11183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
11184#[inline]
11185#[target_feature(enable = "neon")]
11186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11188#[cfg_attr(
11189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11190 assert_instr(eor)
11191)]
11192#[cfg_attr(
11193 not(target_arch = "arm"),
11194 stable(feature = "neon_intrinsics", since = "1.59.0")
11195)]
11196#[cfg_attr(
11197 target_arch = "arm",
11198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11199)]
11200pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11201 unsafe { simd_xor(a, b) }
11202}
11203#[doc = "Vector bitwise exclusive or (vector)"]
11204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
11205#[inline]
11206#[target_feature(enable = "neon")]
11207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11209#[cfg_attr(
11210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11211 assert_instr(eor)
11212)]
11213#[cfg_attr(
11214 not(target_arch = "arm"),
11215 stable(feature = "neon_intrinsics", since = "1.59.0")
11216)]
11217#[cfg_attr(
11218 target_arch = "arm",
11219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11220)]
11221pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11222 unsafe { simd_xor(a, b) }
11223}
11224#[doc = "Vector bitwise exclusive or (vector)"]
11225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
11226#[inline]
11227#[target_feature(enable = "neon")]
11228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11230#[cfg_attr(
11231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11232 assert_instr(eor)
11233)]
11234#[cfg_attr(
11235 not(target_arch = "arm"),
11236 stable(feature = "neon_intrinsics", since = "1.59.0")
11237)]
11238#[cfg_attr(
11239 target_arch = "arm",
11240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11241)]
11242pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
11243 unsafe { simd_xor(a, b) }
11244}
11245#[doc = "Vector bitwise exclusive or (vector)"]
11246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
11247#[inline]
11248#[target_feature(enable = "neon")]
11249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11251#[cfg_attr(
11252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11253 assert_instr(eor)
11254)]
11255#[cfg_attr(
11256 not(target_arch = "arm"),
11257 stable(feature = "neon_intrinsics", since = "1.59.0")
11258)]
11259#[cfg_attr(
11260 target_arch = "arm",
11261 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11262)]
11263pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
11264 unsafe { simd_xor(a, b) }
11265}
11266#[doc = "Vector bitwise exclusive or (vector)"]
11267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
11268#[inline]
11269#[target_feature(enable = "neon")]
11270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11272#[cfg_attr(
11273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11274 assert_instr(eor)
11275)]
11276#[cfg_attr(
11277 not(target_arch = "arm"),
11278 stable(feature = "neon_intrinsics", since = "1.59.0")
11279)]
11280#[cfg_attr(
11281 target_arch = "arm",
11282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11283)]
11284pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11285 unsafe { simd_xor(a, b) }
11286}
11287#[doc = "Vector bitwise exclusive or (vector)"]
11288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
11289#[inline]
11290#[target_feature(enable = "neon")]
11291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11293#[cfg_attr(
11294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11295 assert_instr(eor)
11296)]
11297#[cfg_attr(
11298 not(target_arch = "arm"),
11299 stable(feature = "neon_intrinsics", since = "1.59.0")
11300)]
11301#[cfg_attr(
11302 target_arch = "arm",
11303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11304)]
11305pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
11306 unsafe { simd_xor(a, b) }
11307}
11308#[doc = "Vector bitwise exclusive or (vector)"]
11309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
11310#[inline]
11311#[target_feature(enable = "neon")]
11312#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11313#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11314#[cfg_attr(
11315 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11316 assert_instr(eor)
11317)]
11318#[cfg_attr(
11319 not(target_arch = "arm"),
11320 stable(feature = "neon_intrinsics", since = "1.59.0")
11321)]
11322#[cfg_attr(
11323 target_arch = "arm",
11324 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11325)]
11326pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11327 unsafe { simd_xor(a, b) }
11328}
11329#[doc = "Vector bitwise exclusive or (vector)"]
11330#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
11331#[inline]
11332#[target_feature(enable = "neon")]
11333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11335#[cfg_attr(
11336 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11337 assert_instr(eor)
11338)]
11339#[cfg_attr(
11340 not(target_arch = "arm"),
11341 stable(feature = "neon_intrinsics", since = "1.59.0")
11342)]
11343#[cfg_attr(
11344 target_arch = "arm",
11345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11346)]
11347pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11348 unsafe { simd_xor(a, b) }
11349}
11350#[doc = "Vector bitwise exclusive or (vector)"]
11351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
11352#[inline]
11353#[target_feature(enable = "neon")]
11354#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11355#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11356#[cfg_attr(
11357 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11358 assert_instr(eor)
11359)]
11360#[cfg_attr(
11361 not(target_arch = "arm"),
11362 stable(feature = "neon_intrinsics", since = "1.59.0")
11363)]
11364#[cfg_attr(
11365 target_arch = "arm",
11366 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11367)]
11368pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11369 unsafe { simd_xor(a, b) }
11370}
11371#[doc = "Vector bitwise exclusive or (vector)"]
11372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
11373#[inline]
11374#[target_feature(enable = "neon")]
11375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11377#[cfg_attr(
11378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11379 assert_instr(eor)
11380)]
11381#[cfg_attr(
11382 not(target_arch = "arm"),
11383 stable(feature = "neon_intrinsics", since = "1.59.0")
11384)]
11385#[cfg_attr(
11386 target_arch = "arm",
11387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11388)]
11389pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
11390 unsafe { simd_xor(a, b) }
11391}
11392#[doc = "Vector bitwise exclusive or (vector)"]
11393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
11394#[inline]
11395#[target_feature(enable = "neon")]
11396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11398#[cfg_attr(
11399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11400 assert_instr(eor)
11401)]
11402#[cfg_attr(
11403 not(target_arch = "arm"),
11404 stable(feature = "neon_intrinsics", since = "1.59.0")
11405)]
11406#[cfg_attr(
11407 target_arch = "arm",
11408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11409)]
11410pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
11411 unsafe { simd_xor(a, b) }
11412}
11413#[doc = "Vector bitwise exclusive or (vector)"]
11414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
11415#[inline]
11416#[target_feature(enable = "neon")]
11417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
11419#[cfg_attr(
11420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11421 assert_instr(eor)
11422)]
11423#[cfg_attr(
11424 not(target_arch = "arm"),
11425 stable(feature = "neon_intrinsics", since = "1.59.0")
11426)]
11427#[cfg_attr(
11428 target_arch = "arm",
11429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11430)]
11431pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
11432 unsafe { simd_xor(a, b) }
11433}
11434#[doc = "Extract vector from pair of vectors"]
11435#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
11436#[inline]
11437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11438#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11439#[cfg_attr(
11440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11441 assert_instr(ext, N = 3)
11442)]
11443#[rustc_legacy_const_generics(2)]
11444#[target_feature(enable = "neon,fp16")]
11445#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11446pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
11447 static_assert_uimm_bits!(N, 2);
11448 unsafe {
11449 match N & 0b11 {
11450 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11451 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11452 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11453 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11454 _ => unreachable_unchecked(),
11455 }
11456 }
11457}
11458#[doc = "Extract vector from pair of vectors"]
11459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
11460#[inline]
11461#[target_feature(enable = "neon")]
11462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11463#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11464#[cfg_attr(
11465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11466 assert_instr(ext, N = 1)
11467)]
11468#[rustc_legacy_const_generics(2)]
11469#[cfg_attr(
11470 not(target_arch = "arm"),
11471 stable(feature = "neon_intrinsics", since = "1.59.0")
11472)]
11473#[cfg_attr(
11474 target_arch = "arm",
11475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11476)]
11477pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
11478 static_assert_uimm_bits!(N, 1);
11479 unsafe {
11480 match N & 0b1 {
11481 0 => simd_shuffle!(a, b, [0, 1]),
11482 1 => simd_shuffle!(a, b, [1, 2]),
11483 _ => unreachable_unchecked(),
11484 }
11485 }
11486}
11487#[doc = "Extract vector from pair of vectors"]
11488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
11489#[inline]
11490#[target_feature(enable = "neon")]
11491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11492#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11493#[cfg_attr(
11494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11495 assert_instr(ext, N = 1)
11496)]
11497#[rustc_legacy_const_generics(2)]
11498#[cfg_attr(
11499 not(target_arch = "arm"),
11500 stable(feature = "neon_intrinsics", since = "1.59.0")
11501)]
11502#[cfg_attr(
11503 target_arch = "arm",
11504 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11505)]
11506pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
11507 static_assert_uimm_bits!(N, 1);
11508 unsafe {
11509 match N & 0b1 {
11510 0 => simd_shuffle!(a, b, [0, 1]),
11511 1 => simd_shuffle!(a, b, [1, 2]),
11512 _ => unreachable_unchecked(),
11513 }
11514 }
11515}
11516#[doc = "Extract vector from pair of vectors"]
11517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
11518#[inline]
11519#[target_feature(enable = "neon")]
11520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11521#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
11522#[cfg_attr(
11523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11524 assert_instr(ext, N = 1)
11525)]
11526#[rustc_legacy_const_generics(2)]
11527#[cfg_attr(
11528 not(target_arch = "arm"),
11529 stable(feature = "neon_intrinsics", since = "1.59.0")
11530)]
11531#[cfg_attr(
11532 target_arch = "arm",
11533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11534)]
11535pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
11536 static_assert_uimm_bits!(N, 1);
11537 unsafe {
11538 match N & 0b1 {
11539 0 => simd_shuffle!(a, b, [0, 1]),
11540 1 => simd_shuffle!(a, b, [1, 2]),
11541 _ => unreachable_unchecked(),
11542 }
11543 }
11544}
11545#[doc = "Extract vector from pair of vectors"]
11546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
11547#[doc = "## Safety"]
11548#[doc = " * Neon instrinsic unsafe"]
11549#[inline]
11550#[target_feature(enable = "neon")]
11551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11553#[cfg_attr(
11554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11555 assert_instr(nop, N = 0)
11556)]
11557#[rustc_legacy_const_generics(2)]
11558#[cfg_attr(
11559 not(target_arch = "arm"),
11560 stable(feature = "neon_intrinsics", since = "1.59.0")
11561)]
11562#[cfg_attr(
11563 target_arch = "arm",
11564 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11565)]
11566pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
11567 static_assert!(N == 0);
11568 a
11569}
11570#[doc = "Extract vector from pair of vectors"]
11571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
11572#[doc = "## Safety"]
11573#[doc = " * Neon instrinsic unsafe"]
11574#[inline]
11575#[target_feature(enable = "neon")]
11576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
11578#[cfg_attr(
11579 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11580 assert_instr(nop, N = 0)
11581)]
11582#[rustc_legacy_const_generics(2)]
11583#[cfg_attr(
11584 not(target_arch = "arm"),
11585 stable(feature = "neon_intrinsics", since = "1.59.0")
11586)]
11587#[cfg_attr(
11588 target_arch = "arm",
11589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11590)]
11591pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_t {
11592 static_assert!(N == 0);
11593 a
11594}
11595#[doc = "Extract vector from pair of vectors"]
11596#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
11597#[inline]
11598#[target_feature(enable = "neon")]
11599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11600#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11601#[cfg_attr(
11602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11603 assert_instr(ext, N = 7)
11604)]
11605#[rustc_legacy_const_generics(2)]
11606#[cfg_attr(
11607 not(target_arch = "arm"),
11608 stable(feature = "neon_intrinsics", since = "1.59.0")
11609)]
11610#[cfg_attr(
11611 target_arch = "arm",
11612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11613)]
11614pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
11615 static_assert_uimm_bits!(N, 3);
11616 unsafe {
11617 match N & 0b111 {
11618 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11619 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11620 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11621 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11622 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11623 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11624 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11625 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11626 _ => unreachable_unchecked(),
11627 }
11628 }
11629}
11630#[doc = "Extract vector from pair of vectors"]
11631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
11632#[inline]
11633#[target_feature(enable = "neon")]
11634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11636#[cfg_attr(
11637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11638 assert_instr(ext, N = 7)
11639)]
11640#[rustc_legacy_const_generics(2)]
11641#[cfg_attr(
11642 not(target_arch = "arm"),
11643 stable(feature = "neon_intrinsics", since = "1.59.0")
11644)]
11645#[cfg_attr(
11646 target_arch = "arm",
11647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11648)]
11649pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
11650 static_assert_uimm_bits!(N, 3);
11651 unsafe {
11652 match N & 0b111 {
11653 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11654 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11655 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11656 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11657 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11658 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11659 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11660 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11661 _ => unreachable_unchecked(),
11662 }
11663 }
11664}
11665#[doc = "Extract vector from pair of vectors"]
11666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
11667#[inline]
11668#[target_feature(enable = "neon")]
11669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11670#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11671#[cfg_attr(
11672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11673 assert_instr(ext, N = 7)
11674)]
11675#[rustc_legacy_const_generics(2)]
11676#[cfg_attr(
11677 not(target_arch = "arm"),
11678 stable(feature = "neon_intrinsics", since = "1.59.0")
11679)]
11680#[cfg_attr(
11681 target_arch = "arm",
11682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11683)]
11684pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
11685 static_assert_uimm_bits!(N, 3);
11686 unsafe {
11687 match N & 0b111 {
11688 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11689 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11690 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11691 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11692 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11693 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11694 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11695 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11696 _ => unreachable_unchecked(),
11697 }
11698 }
11699}
11700#[doc = "Extract vector from pair of vectors"]
11701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
11702#[inline]
11703#[target_feature(enable = "neon")]
11704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11705#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11706#[cfg_attr(
11707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11708 assert_instr(ext, N = 7)
11709)]
11710#[rustc_legacy_const_generics(2)]
11711#[cfg_attr(
11712 not(target_arch = "arm"),
11713 stable(feature = "neon_intrinsics", since = "1.59.0")
11714)]
11715#[cfg_attr(
11716 target_arch = "arm",
11717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11718)]
11719pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
11720 static_assert_uimm_bits!(N, 3);
11721 unsafe {
11722 match N & 0b111 {
11723 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11724 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11725 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11726 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11727 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11728 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11729 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11730 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11731 _ => unreachable_unchecked(),
11732 }
11733 }
11734}
11735#[doc = "Extract vector from pair of vectors"]
11736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
11737#[inline]
11738#[target_feature(enable = "neon")]
11739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11740#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11741#[cfg_attr(
11742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11743 assert_instr(ext, N = 7)
11744)]
11745#[rustc_legacy_const_generics(2)]
11746#[cfg_attr(
11747 not(target_arch = "arm"),
11748 stable(feature = "neon_intrinsics", since = "1.59.0")
11749)]
11750#[cfg_attr(
11751 target_arch = "arm",
11752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11753)]
11754pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
11755 static_assert_uimm_bits!(N, 3);
11756 unsafe {
11757 match N & 0b111 {
11758 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11759 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11760 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11761 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11762 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11763 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11764 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11765 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11766 _ => unreachable_unchecked(),
11767 }
11768 }
11769}
11770#[doc = "Extract vector from pair of vectors"]
11771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
11772#[inline]
11773#[target_feature(enable = "neon")]
11774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11775#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11776#[cfg_attr(
11777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11778 assert_instr(ext, N = 7)
11779)]
11780#[rustc_legacy_const_generics(2)]
11781#[cfg_attr(
11782 not(target_arch = "arm"),
11783 stable(feature = "neon_intrinsics", since = "1.59.0")
11784)]
11785#[cfg_attr(
11786 target_arch = "arm",
11787 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11788)]
11789pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
11790 static_assert_uimm_bits!(N, 3);
11791 unsafe {
11792 match N & 0b111 {
11793 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11794 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11795 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11796 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11797 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11798 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11799 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11800 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11801 _ => unreachable_unchecked(),
11802 }
11803 }
11804}
11805#[doc = "Extract vector from pair of vectors"]
11806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
11807#[inline]
11808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11809#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
11810#[cfg_attr(
11811 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11812 assert_instr(ext, N = 7)
11813)]
11814#[rustc_legacy_const_generics(2)]
11815#[target_feature(enable = "neon,fp16")]
11816#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
11817pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
11818 static_assert_uimm_bits!(N, 3);
11819 unsafe {
11820 match N & 0b111 {
11821 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]),
11822 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]),
11823 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]),
11824 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]),
11825 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]),
11826 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]),
11827 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]),
11828 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]),
11829 _ => unreachable_unchecked(),
11830 }
11831 }
11832}
11833#[doc = "Extract vector from pair of vectors"]
11834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
11835#[inline]
11836#[target_feature(enable = "neon")]
11837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11838#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11839#[cfg_attr(
11840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11841 assert_instr(ext, N = 3)
11842)]
11843#[rustc_legacy_const_generics(2)]
11844#[cfg_attr(
11845 not(target_arch = "arm"),
11846 stable(feature = "neon_intrinsics", since = "1.59.0")
11847)]
11848#[cfg_attr(
11849 target_arch = "arm",
11850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11851)]
11852pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
11853 static_assert_uimm_bits!(N, 2);
11854 unsafe {
11855 match N & 0b11 {
11856 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11857 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11858 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11859 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11860 _ => unreachable_unchecked(),
11861 }
11862 }
11863}
11864#[doc = "Extract vector from pair of vectors"]
11865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
11866#[inline]
11867#[target_feature(enable = "neon")]
11868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11869#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11870#[cfg_attr(
11871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11872 assert_instr(ext, N = 3)
11873)]
11874#[rustc_legacy_const_generics(2)]
11875#[cfg_attr(
11876 not(target_arch = "arm"),
11877 stable(feature = "neon_intrinsics", since = "1.59.0")
11878)]
11879#[cfg_attr(
11880 target_arch = "arm",
11881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11882)]
11883pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
11884 static_assert_uimm_bits!(N, 2);
11885 unsafe {
11886 match N & 0b11 {
11887 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11888 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11889 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11890 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11891 _ => unreachable_unchecked(),
11892 }
11893 }
11894}
11895#[doc = "Extract vector from pair of vectors"]
11896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
11897#[inline]
11898#[target_feature(enable = "neon")]
11899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11900#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11901#[cfg_attr(
11902 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11903 assert_instr(ext, N = 3)
11904)]
11905#[rustc_legacy_const_generics(2)]
11906#[cfg_attr(
11907 not(target_arch = "arm"),
11908 stable(feature = "neon_intrinsics", since = "1.59.0")
11909)]
11910#[cfg_attr(
11911 target_arch = "arm",
11912 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11913)]
11914pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
11915 static_assert_uimm_bits!(N, 2);
11916 unsafe {
11917 match N & 0b11 {
11918 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11919 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11920 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11921 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11922 _ => unreachable_unchecked(),
11923 }
11924 }
11925}
11926#[doc = "Extract vector from pair of vectors"]
11927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
11928#[inline]
11929#[target_feature(enable = "neon")]
11930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11931#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11932#[cfg_attr(
11933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11934 assert_instr(ext, N = 3)
11935)]
11936#[rustc_legacy_const_generics(2)]
11937#[cfg_attr(
11938 not(target_arch = "arm"),
11939 stable(feature = "neon_intrinsics", since = "1.59.0")
11940)]
11941#[cfg_attr(
11942 target_arch = "arm",
11943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11944)]
11945pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
11946 static_assert_uimm_bits!(N, 2);
11947 unsafe {
11948 match N & 0b11 {
11949 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11950 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11951 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11952 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11953 _ => unreachable_unchecked(),
11954 }
11955 }
11956}
11957#[doc = "Extract vector from pair of vectors"]
11958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
11959#[inline]
11960#[target_feature(enable = "neon")]
11961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11962#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11963#[cfg_attr(
11964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11965 assert_instr(ext, N = 3)
11966)]
11967#[rustc_legacy_const_generics(2)]
11968#[cfg_attr(
11969 not(target_arch = "arm"),
11970 stable(feature = "neon_intrinsics", since = "1.59.0")
11971)]
11972#[cfg_attr(
11973 target_arch = "arm",
11974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
11975)]
11976pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
11977 static_assert_uimm_bits!(N, 2);
11978 unsafe {
11979 match N & 0b11 {
11980 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
11981 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
11982 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
11983 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
11984 _ => unreachable_unchecked(),
11985 }
11986 }
11987}
11988#[doc = "Extract vector from pair of vectors"]
11989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
11990#[inline]
11991#[target_feature(enable = "neon")]
11992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
11993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
11994#[cfg_attr(
11995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
11996 assert_instr(ext, N = 3)
11997)]
11998#[rustc_legacy_const_generics(2)]
11999#[cfg_attr(
12000 not(target_arch = "arm"),
12001 stable(feature = "neon_intrinsics", since = "1.59.0")
12002)]
12003#[cfg_attr(
12004 target_arch = "arm",
12005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12006)]
12007pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
12008 static_assert_uimm_bits!(N, 2);
12009 unsafe {
12010 match N & 0b11 {
12011 0 => simd_shuffle!(a, b, [0, 1, 2, 3]),
12012 1 => simd_shuffle!(a, b, [1, 2, 3, 4]),
12013 2 => simd_shuffle!(a, b, [2, 3, 4, 5]),
12014 3 => simd_shuffle!(a, b, [3, 4, 5, 6]),
12015 _ => unreachable_unchecked(),
12016 }
12017 }
12018}
12019#[doc = "Extract vector from pair of vectors"]
12020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
12021#[inline]
12022#[target_feature(enable = "neon")]
12023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12025#[cfg_attr(
12026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12027 assert_instr(ext, N = 1)
12028)]
12029#[rustc_legacy_const_generics(2)]
12030#[cfg_attr(
12031 not(target_arch = "arm"),
12032 stable(feature = "neon_intrinsics", since = "1.59.0")
12033)]
12034#[cfg_attr(
12035 target_arch = "arm",
12036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12037)]
12038pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
12039 static_assert_uimm_bits!(N, 1);
12040 unsafe {
12041 match N & 0b1 {
12042 0 => simd_shuffle!(a, b, [0, 1]),
12043 1 => simd_shuffle!(a, b, [1, 2]),
12044 _ => unreachable_unchecked(),
12045 }
12046 }
12047}
12048#[doc = "Extract vector from pair of vectors"]
12049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
12050#[inline]
12051#[target_feature(enable = "neon")]
12052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
12054#[cfg_attr(
12055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12056 assert_instr(ext, N = 1)
12057)]
12058#[rustc_legacy_const_generics(2)]
12059#[cfg_attr(
12060 not(target_arch = "arm"),
12061 stable(feature = "neon_intrinsics", since = "1.59.0")
12062)]
12063#[cfg_attr(
12064 target_arch = "arm",
12065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12066)]
12067pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
12068 static_assert_uimm_bits!(N, 1);
12069 unsafe {
12070 match N & 0b1 {
12071 0 => simd_shuffle!(a, b, [0, 1]),
12072 1 => simd_shuffle!(a, b, [1, 2]),
12073 _ => unreachable_unchecked(),
12074 }
12075 }
12076}
12077#[doc = "Extract vector from pair of vectors"]
12078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
12079#[inline]
12080#[target_feature(enable = "neon")]
12081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12082#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12083#[cfg_attr(
12084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12085 assert_instr(ext, N = 15)
12086)]
12087#[rustc_legacy_const_generics(2)]
12088#[cfg_attr(
12089 not(target_arch = "arm"),
12090 stable(feature = "neon_intrinsics", since = "1.59.0")
12091)]
12092#[cfg_attr(
12093 target_arch = "arm",
12094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12095)]
12096pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
12097 static_assert_uimm_bits!(N, 4);
12098 unsafe {
12099 match N & 0b1111 {
12100 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12101 1 => simd_shuffle!(
12102 a,
12103 b,
12104 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12105 ),
12106 2 => simd_shuffle!(
12107 a,
12108 b,
12109 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12110 ),
12111 3 => simd_shuffle!(
12112 a,
12113 b,
12114 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12115 ),
12116 4 => simd_shuffle!(
12117 a,
12118 b,
12119 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12120 ),
12121 5 => simd_shuffle!(
12122 a,
12123 b,
12124 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12125 ),
12126 6 => simd_shuffle!(
12127 a,
12128 b,
12129 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12130 ),
12131 7 => simd_shuffle!(
12132 a,
12133 b,
12134 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12135 ),
12136 8 => simd_shuffle!(
12137 a,
12138 b,
12139 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12140 ),
12141 9 => simd_shuffle!(
12142 a,
12143 b,
12144 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12145 ),
12146 10 => simd_shuffle!(
12147 a,
12148 b,
12149 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12150 ),
12151 11 => simd_shuffle!(
12152 a,
12153 b,
12154 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12155 ),
12156 12 => simd_shuffle!(
12157 a,
12158 b,
12159 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12160 ),
12161 13 => simd_shuffle!(
12162 a,
12163 b,
12164 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12165 ),
12166 14 => simd_shuffle!(
12167 a,
12168 b,
12169 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12170 ),
12171 15 => simd_shuffle!(
12172 a,
12173 b,
12174 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12175 ),
12176 _ => unreachable_unchecked(),
12177 }
12178 }
12179}
12180#[doc = "Extract vector from pair of vectors"]
12181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
12182#[inline]
12183#[target_feature(enable = "neon")]
12184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12186#[cfg_attr(
12187 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12188 assert_instr(ext, N = 15)
12189)]
12190#[rustc_legacy_const_generics(2)]
12191#[cfg_attr(
12192 not(target_arch = "arm"),
12193 stable(feature = "neon_intrinsics", since = "1.59.0")
12194)]
12195#[cfg_attr(
12196 target_arch = "arm",
12197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12198)]
12199pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
12200 static_assert_uimm_bits!(N, 4);
12201 unsafe {
12202 match N & 0b1111 {
12203 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12204 1 => simd_shuffle!(
12205 a,
12206 b,
12207 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12208 ),
12209 2 => simd_shuffle!(
12210 a,
12211 b,
12212 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12213 ),
12214 3 => simd_shuffle!(
12215 a,
12216 b,
12217 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12218 ),
12219 4 => simd_shuffle!(
12220 a,
12221 b,
12222 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12223 ),
12224 5 => simd_shuffle!(
12225 a,
12226 b,
12227 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12228 ),
12229 6 => simd_shuffle!(
12230 a,
12231 b,
12232 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12233 ),
12234 7 => simd_shuffle!(
12235 a,
12236 b,
12237 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12238 ),
12239 8 => simd_shuffle!(
12240 a,
12241 b,
12242 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12243 ),
12244 9 => simd_shuffle!(
12245 a,
12246 b,
12247 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12248 ),
12249 10 => simd_shuffle!(
12250 a,
12251 b,
12252 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12253 ),
12254 11 => simd_shuffle!(
12255 a,
12256 b,
12257 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12258 ),
12259 12 => simd_shuffle!(
12260 a,
12261 b,
12262 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12263 ),
12264 13 => simd_shuffle!(
12265 a,
12266 b,
12267 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12268 ),
12269 14 => simd_shuffle!(
12270 a,
12271 b,
12272 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12273 ),
12274 15 => simd_shuffle!(
12275 a,
12276 b,
12277 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12278 ),
12279 _ => unreachable_unchecked(),
12280 }
12281 }
12282}
12283#[doc = "Extract vector from pair of vectors"]
12284#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
12285#[inline]
12286#[target_feature(enable = "neon")]
12287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12288#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
12289#[cfg_attr(
12290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12291 assert_instr(ext, N = 15)
12292)]
12293#[rustc_legacy_const_generics(2)]
12294#[cfg_attr(
12295 not(target_arch = "arm"),
12296 stable(feature = "neon_intrinsics", since = "1.59.0")
12297)]
12298#[cfg_attr(
12299 target_arch = "arm",
12300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12301)]
12302pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
12303 static_assert_uimm_bits!(N, 4);
12304 unsafe {
12305 match N & 0b1111 {
12306 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
12307 1 => simd_shuffle!(
12308 a,
12309 b,
12310 [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
12311 ),
12312 2 => simd_shuffle!(
12313 a,
12314 b,
12315 [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]
12316 ),
12317 3 => simd_shuffle!(
12318 a,
12319 b,
12320 [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]
12321 ),
12322 4 => simd_shuffle!(
12323 a,
12324 b,
12325 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]
12326 ),
12327 5 => simd_shuffle!(
12328 a,
12329 b,
12330 [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]
12331 ),
12332 6 => simd_shuffle!(
12333 a,
12334 b,
12335 [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]
12336 ),
12337 7 => simd_shuffle!(
12338 a,
12339 b,
12340 [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]
12341 ),
12342 8 => simd_shuffle!(
12343 a,
12344 b,
12345 [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]
12346 ),
12347 9 => simd_shuffle!(
12348 a,
12349 b,
12350 [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]
12351 ),
12352 10 => simd_shuffle!(
12353 a,
12354 b,
12355 [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
12356 ),
12357 11 => simd_shuffle!(
12358 a,
12359 b,
12360 [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]
12361 ),
12362 12 => simd_shuffle!(
12363 a,
12364 b,
12365 [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]
12366 ),
12367 13 => simd_shuffle!(
12368 a,
12369 b,
12370 [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]
12371 ),
12372 14 => simd_shuffle!(
12373 a,
12374 b,
12375 [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]
12376 ),
12377 15 => simd_shuffle!(
12378 a,
12379 b,
12380 [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]
12381 ),
12382 _ => unreachable_unchecked(),
12383 }
12384 }
12385}
12386#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
12388#[inline]
12389#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12390#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12391#[cfg_attr(
12392 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12393 assert_instr(fmla)
12394)]
12395#[target_feature(enable = "neon,fp16")]
12396#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12397pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12398 unsafe { simd_fma(b, c, a) }
12399}
12400#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
12401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
12402#[inline]
12403#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12405#[cfg_attr(
12406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12407 assert_instr(fmla)
12408)]
12409#[target_feature(enable = "neon,fp16")]
12410#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12411pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12412 unsafe { simd_fma(b, c, a) }
12413}
12414#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
12416#[inline]
12417#[target_feature(enable = "neon")]
12418#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12419#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12420#[cfg_attr(
12421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12422 assert_instr(fmla)
12423)]
12424#[cfg_attr(
12425 not(target_arch = "arm"),
12426 stable(feature = "neon_intrinsics", since = "1.59.0")
12427)]
12428#[cfg_attr(
12429 target_arch = "arm",
12430 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12431)]
12432pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12433 unsafe { simd_fma(b, c, a) }
12434}
12435#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
12437#[inline]
12438#[target_feature(enable = "neon")]
12439#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12441#[cfg_attr(
12442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12443 assert_instr(fmla)
12444)]
12445#[cfg_attr(
12446 not(target_arch = "arm"),
12447 stable(feature = "neon_intrinsics", since = "1.59.0")
12448)]
12449#[cfg_attr(
12450 target_arch = "arm",
12451 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12452)]
12453pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12454 unsafe { simd_fma(b, c, a) }
12455}
12456#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
12458#[inline]
12459#[target_feature(enable = "neon")]
12460#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12462#[cfg_attr(
12463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12464 assert_instr(fmla)
12465)]
12466#[cfg_attr(
12467 not(target_arch = "arm"),
12468 stable(feature = "neon_intrinsics", since = "1.59.0")
12469)]
12470#[cfg_attr(
12471 target_arch = "arm",
12472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12473)]
12474pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12475 vfma_f32(a, b, vdup_n_f32_vfp4(c))
12476}
12477#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
12478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
12479#[inline]
12480#[target_feature(enable = "neon")]
12481#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
12483#[cfg_attr(
12484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12485 assert_instr(fmla)
12486)]
12487#[cfg_attr(
12488 not(target_arch = "arm"),
12489 stable(feature = "neon_intrinsics", since = "1.59.0")
12490)]
12491#[cfg_attr(
12492 target_arch = "arm",
12493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12494)]
12495pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12496 vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
12497}
12498#[doc = "Floating-point fused multiply-subtract from accumulator"]
12499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
12500#[inline]
12501#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12502#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12504#[cfg_attr(
12505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12506 assert_instr(fmls)
12507)]
12508#[target_feature(enable = "neon,fp16")]
12509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12510pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
12511 unsafe {
12512 let b: float16x4_t = simd_neg(b);
12513 vfma_f16(a, b, c)
12514 }
12515}
12516#[doc = "Floating-point fused multiply-subtract from accumulator"]
12517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
12518#[inline]
12519#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
12520#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
12522#[cfg_attr(
12523 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12524 assert_instr(fmls)
12525)]
12526#[target_feature(enable = "neon,fp16")]
12527#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12528pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
12529 unsafe {
12530 let b: float16x8_t = simd_neg(b);
12531 vfmaq_f16(a, b, c)
12532 }
12533}
12534#[doc = "Floating-point fused multiply-subtract from accumulator"]
12535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
12536#[inline]
12537#[target_feature(enable = "neon")]
12538#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12540#[cfg_attr(
12541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12542 assert_instr(fmls)
12543)]
12544#[cfg_attr(
12545 not(target_arch = "arm"),
12546 stable(feature = "neon_intrinsics", since = "1.59.0")
12547)]
12548#[cfg_attr(
12549 target_arch = "arm",
12550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12551)]
12552pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
12553 unsafe {
12554 let b: float32x2_t = simd_neg(b);
12555 vfma_f32(a, b, c)
12556 }
12557}
12558#[doc = "Floating-point fused multiply-subtract from accumulator"]
12559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
12560#[inline]
12561#[target_feature(enable = "neon")]
12562#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12564#[cfg_attr(
12565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12566 assert_instr(fmls)
12567)]
12568#[cfg_attr(
12569 not(target_arch = "arm"),
12570 stable(feature = "neon_intrinsics", since = "1.59.0")
12571)]
12572#[cfg_attr(
12573 target_arch = "arm",
12574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12575)]
12576pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
12577 unsafe {
12578 let b: float32x4_t = simd_neg(b);
12579 vfmaq_f32(a, b, c)
12580 }
12581}
12582#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12583#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
12584#[inline]
12585#[target_feature(enable = "neon")]
12586#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12587#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12588#[cfg_attr(
12589 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12590 assert_instr(fmls)
12591)]
12592#[cfg_attr(
12593 not(target_arch = "arm"),
12594 stable(feature = "neon_intrinsics", since = "1.59.0")
12595)]
12596#[cfg_attr(
12597 target_arch = "arm",
12598 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12599)]
12600pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
12601 vfms_f32(a, b, vdup_n_f32_vfp4(c))
12602}
12603#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
12604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
12605#[inline]
12606#[target_feature(enable = "neon")]
12607#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
12608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
12609#[cfg_attr(
12610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12611 assert_instr(fmls)
12612)]
12613#[cfg_attr(
12614 not(target_arch = "arm"),
12615 stable(feature = "neon_intrinsics", since = "1.59.0")
12616)]
12617#[cfg_attr(
12618 target_arch = "arm",
12619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12620)]
12621pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
12622 vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
12623}
12624#[doc = "Duplicate vector element to vector"]
12625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
12626#[inline]
12627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12628#[target_feature(enable = "neon,fp16")]
12629#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12630#[cfg_attr(test, assert_instr(nop))]
12631pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
12632 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12633}
12634#[doc = "Duplicate vector element to vector"]
12635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
12636#[inline]
12637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12638#[target_feature(enable = "neon,fp16")]
12639#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12640#[cfg_attr(test, assert_instr(nop))]
12641pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
12642 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
12643}
12644#[doc = "Duplicate vector element to vector or scalar"]
12645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
12646#[inline]
12647#[target_feature(enable = "neon")]
12648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12649#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12650#[cfg_attr(
12651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12652 assert_instr(ext)
12653)]
12654#[cfg_attr(
12655 not(target_arch = "arm"),
12656 stable(feature = "neon_intrinsics", since = "1.59.0")
12657)]
12658#[cfg_attr(
12659 target_arch = "arm",
12660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12661)]
12662pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
12663 unsafe { simd_shuffle!(a, a, [2, 3]) }
12664}
12665#[doc = "Duplicate vector element to vector or scalar"]
12666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
12667#[inline]
12668#[target_feature(enable = "neon")]
12669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12670#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12671#[cfg_attr(
12672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12673 assert_instr(ext)
12674)]
12675#[cfg_attr(
12676 not(target_arch = "arm"),
12677 stable(feature = "neon_intrinsics", since = "1.59.0")
12678)]
12679#[cfg_attr(
12680 target_arch = "arm",
12681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12682)]
12683pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
12684 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12685}
12686#[doc = "Duplicate vector element to vector or scalar"]
12687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
12688#[inline]
12689#[target_feature(enable = "neon")]
12690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12691#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12692#[cfg_attr(
12693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12694 assert_instr(ext)
12695)]
12696#[cfg_attr(
12697 not(target_arch = "arm"),
12698 stable(feature = "neon_intrinsics", since = "1.59.0")
12699)]
12700#[cfg_attr(
12701 target_arch = "arm",
12702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12703)]
12704pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
12705 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12706}
12707#[doc = "Duplicate vector element to vector or scalar"]
12708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
12709#[inline]
12710#[target_feature(enable = "neon")]
12711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12712#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12713#[cfg_attr(
12714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12715 assert_instr(ext)
12716)]
12717#[cfg_attr(
12718 not(target_arch = "arm"),
12719 stable(feature = "neon_intrinsics", since = "1.59.0")
12720)]
12721#[cfg_attr(
12722 target_arch = "arm",
12723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12724)]
12725pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
12726 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12727}
12728#[doc = "Duplicate vector element to vector or scalar"]
12729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
12730#[inline]
12731#[target_feature(enable = "neon")]
12732#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12733#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12734#[cfg_attr(
12735 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12736 assert_instr(ext)
12737)]
12738#[cfg_attr(
12739 not(target_arch = "arm"),
12740 stable(feature = "neon_intrinsics", since = "1.59.0")
12741)]
12742#[cfg_attr(
12743 target_arch = "arm",
12744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12745)]
12746pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
12747 unsafe { simd_shuffle!(a, a, [2, 3]) }
12748}
12749#[doc = "Duplicate vector element to vector or scalar"]
12750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
12751#[inline]
12752#[target_feature(enable = "neon")]
12753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12754#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12755#[cfg_attr(
12756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12757 assert_instr(ext)
12758)]
12759#[cfg_attr(
12760 not(target_arch = "arm"),
12761 stable(feature = "neon_intrinsics", since = "1.59.0")
12762)]
12763#[cfg_attr(
12764 target_arch = "arm",
12765 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12766)]
12767pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
12768 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12769}
12770#[doc = "Duplicate vector element to vector or scalar"]
12771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
12772#[inline]
12773#[target_feature(enable = "neon")]
12774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12775#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12776#[cfg_attr(
12777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12778 assert_instr(ext)
12779)]
12780#[cfg_attr(
12781 not(target_arch = "arm"),
12782 stable(feature = "neon_intrinsics", since = "1.59.0")
12783)]
12784#[cfg_attr(
12785 target_arch = "arm",
12786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12787)]
12788pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
12789 unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
12790}
12791#[doc = "Duplicate vector element to vector or scalar"]
12792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
12793#[inline]
12794#[target_feature(enable = "neon")]
12795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12796#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12797#[cfg_attr(
12798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12799 assert_instr(ext)
12800)]
12801#[cfg_attr(
12802 not(target_arch = "arm"),
12803 stable(feature = "neon_intrinsics", since = "1.59.0")
12804)]
12805#[cfg_attr(
12806 target_arch = "arm",
12807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12808)]
12809pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
12810 unsafe { simd_shuffle!(a, a, [2, 3]) }
12811}
12812#[doc = "Duplicate vector element to vector or scalar"]
12813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
12814#[inline]
12815#[target_feature(enable = "neon")]
12816#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12817#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12818#[cfg_attr(
12819 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12820 assert_instr(ext)
12821)]
12822#[cfg_attr(
12823 not(target_arch = "arm"),
12824 stable(feature = "neon_intrinsics", since = "1.59.0")
12825)]
12826#[cfg_attr(
12827 target_arch = "arm",
12828 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12829)]
12830pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
12831 unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
12832}
12833#[doc = "Duplicate vector element to vector or scalar"]
12834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
12835#[inline]
12836#[target_feature(enable = "neon")]
12837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12838#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12839#[cfg_attr(
12840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12841 assert_instr(ext)
12842)]
12843#[cfg_attr(
12844 not(target_arch = "arm"),
12845 stable(feature = "neon_intrinsics", since = "1.59.0")
12846)]
12847#[cfg_attr(
12848 target_arch = "arm",
12849 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12850)]
12851pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
12852 unsafe { int64x1_t([simd_extract!(a, 1)]) }
12853}
12854#[doc = "Duplicate vector element to vector or scalar"]
12855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
12856#[inline]
12857#[target_feature(enable = "neon")]
12858#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12859#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
12860#[cfg_attr(
12861 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12862 assert_instr(ext)
12863)]
12864#[cfg_attr(
12865 not(target_arch = "arm"),
12866 stable(feature = "neon_intrinsics", since = "1.59.0")
12867)]
12868#[cfg_attr(
12869 target_arch = "arm",
12870 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12871)]
12872pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
12873 unsafe { uint64x1_t([simd_extract!(a, 1)]) }
12874}
12875#[doc = "Duplicate vector element to scalar"]
12876#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
12877#[inline]
12878#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12879#[target_feature(enable = "neon,fp16")]
12880#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12881#[cfg_attr(
12882 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12883 assert_instr(nop, LANE = 0)
12884)]
12885#[rustc_legacy_const_generics(1)]
12886#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12887pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
12888 static_assert_uimm_bits!(LANE, 2);
12889 unsafe { simd_extract!(a, LANE as u32) }
12890}
12891#[doc = "Duplicate vector element to scalar"]
12892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
12893#[inline]
12894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12895#[target_feature(enable = "neon,fp16")]
12896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
12897#[cfg_attr(
12898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
12899 assert_instr(nop, LANE = 0)
12900)]
12901#[rustc_legacy_const_generics(1)]
12902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
12903pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
12904 static_assert_uimm_bits!(LANE, 3);
12905 unsafe { simd_extract!(a, LANE as u32) }
12906}
12907#[doc = "Move vector element to general-purpose register"]
12908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
12909#[inline]
12910#[target_feature(enable = "neon")]
12911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12912#[rustc_legacy_const_generics(1)]
12913#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
12914#[cfg_attr(
12915 not(target_arch = "arm"),
12916 stable(feature = "neon_intrinsics", since = "1.59.0")
12917)]
12918#[cfg_attr(
12919 target_arch = "arm",
12920 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12921)]
12922pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
12923 static_assert_uimm_bits!(IMM5, 1);
12924 unsafe { simd_extract!(v, IMM5 as u32) }
12925}
12926#[doc = "Move vector element to general-purpose register"]
12927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
12928#[inline]
12929#[target_feature(enable = "neon")]
12930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12931#[rustc_legacy_const_generics(1)]
12932#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12933#[cfg_attr(
12934 not(target_arch = "arm"),
12935 stable(feature = "neon_intrinsics", since = "1.59.0")
12936)]
12937#[cfg_attr(
12938 target_arch = "arm",
12939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12940)]
12941pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
12942 static_assert_uimm_bits!(IMM5, 2);
12943 unsafe { simd_extract!(v, IMM5 as u32) }
12944}
12945#[doc = "Move vector element to general-purpose register"]
12946#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
12947#[inline]
12948#[target_feature(enable = "neon")]
12949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12950#[rustc_legacy_const_generics(1)]
12951#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12952#[cfg_attr(
12953 not(target_arch = "arm"),
12954 stable(feature = "neon_intrinsics", since = "1.59.0")
12955)]
12956#[cfg_attr(
12957 target_arch = "arm",
12958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12959)]
12960pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
12961 static_assert_uimm_bits!(IMM5, 3);
12962 unsafe { simd_extract!(v, IMM5 as u32) }
12963}
12964#[doc = "Move vector element to general-purpose register"]
12965#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
12966#[inline]
12967#[target_feature(enable = "neon")]
12968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12969#[rustc_legacy_const_generics(1)]
12970#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
12971#[cfg_attr(
12972 not(target_arch = "arm"),
12973 stable(feature = "neon_intrinsics", since = "1.59.0")
12974)]
12975#[cfg_attr(
12976 target_arch = "arm",
12977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12978)]
12979pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
12980 static_assert_uimm_bits!(IMM5, 2);
12981 unsafe { simd_extract!(v, IMM5 as u32) }
12982}
12983#[doc = "Move vector element to general-purpose register"]
12984#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
12985#[inline]
12986#[target_feature(enable = "neon")]
12987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
12988#[rustc_legacy_const_generics(1)]
12989#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
12990#[cfg_attr(
12991 not(target_arch = "arm"),
12992 stable(feature = "neon_intrinsics", since = "1.59.0")
12993)]
12994#[cfg_attr(
12995 target_arch = "arm",
12996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
12997)]
12998pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
12999 static_assert_uimm_bits!(IMM5, 1);
13000 unsafe { simd_extract!(v, IMM5 as u32) }
13001}
13002#[doc = "Move vector element to general-purpose register"]
13003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
13004#[inline]
13005#[target_feature(enable = "neon")]
13006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13007#[rustc_legacy_const_generics(1)]
13008#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13009#[cfg_attr(
13010 not(target_arch = "arm"),
13011 stable(feature = "neon_intrinsics", since = "1.59.0")
13012)]
13013#[cfg_attr(
13014 target_arch = "arm",
13015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13016)]
13017pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
13018 static_assert_uimm_bits!(IMM5, 3);
13019 unsafe { simd_extract!(v, IMM5 as u32) }
13020}
13021#[doc = "Move vector element to general-purpose register"]
13022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
13023#[inline]
13024#[target_feature(enable = "neon")]
13025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13026#[rustc_legacy_const_generics(1)]
13027#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13028#[cfg_attr(
13029 not(target_arch = "arm"),
13030 stable(feature = "neon_intrinsics", since = "1.59.0")
13031)]
13032#[cfg_attr(
13033 target_arch = "arm",
13034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13035)]
13036pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
13037 static_assert_uimm_bits!(IMM5, 2);
13038 unsafe { simd_extract!(v, IMM5 as u32) }
13039}
13040#[doc = "Move vector element to general-purpose register"]
13041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
13042#[inline]
13043#[target_feature(enable = "neon")]
13044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13045#[rustc_legacy_const_generics(1)]
13046#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13047#[cfg_attr(
13048 not(target_arch = "arm"),
13049 stable(feature = "neon_intrinsics", since = "1.59.0")
13050)]
13051#[cfg_attr(
13052 target_arch = "arm",
13053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13054)]
13055pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
13056 static_assert_uimm_bits!(IMM5, 1);
13057 unsafe { simd_extract!(v, IMM5 as u32) }
13058}
13059#[doc = "Move vector element to general-purpose register"]
13060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
13061#[inline]
13062#[target_feature(enable = "neon")]
13063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13064#[rustc_legacy_const_generics(1)]
13065#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13066#[cfg_attr(
13067 not(target_arch = "arm"),
13068 stable(feature = "neon_intrinsics", since = "1.59.0")
13069)]
13070#[cfg_attr(
13071 target_arch = "arm",
13072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13073)]
13074pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
13075 static_assert_uimm_bits!(IMM5, 3);
13076 unsafe { simd_extract!(v, IMM5 as u32) }
13077}
13078#[doc = "Move vector element to general-purpose register"]
13079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
13080#[inline]
13081#[target_feature(enable = "neon")]
13082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13083#[rustc_legacy_const_generics(1)]
13084#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13085#[cfg_attr(
13086 not(target_arch = "arm"),
13087 stable(feature = "neon_intrinsics", since = "1.59.0")
13088)]
13089#[cfg_attr(
13090 target_arch = "arm",
13091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13092)]
13093pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
13094 static_assert_uimm_bits!(IMM5, 2);
13095 unsafe { simd_extract!(v, IMM5 as u32) }
13096}
13097#[doc = "Move vector element to general-purpose register"]
13098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
13099#[inline]
13100#[target_feature(enable = "neon")]
13101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13102#[rustc_legacy_const_generics(1)]
13103#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13104#[cfg_attr(
13105 not(target_arch = "arm"),
13106 stable(feature = "neon_intrinsics", since = "1.59.0")
13107)]
13108#[cfg_attr(
13109 target_arch = "arm",
13110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13111)]
13112pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
13113 static_assert_uimm_bits!(IMM5, 3);
13114 unsafe { simd_extract!(v, IMM5 as u32) }
13115}
13116#[doc = "Move vector element to general-purpose register"]
13117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
13118#[inline]
13119#[target_feature(enable = "neon")]
13120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13121#[rustc_legacy_const_generics(1)]
13122#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13123#[cfg_attr(
13124 not(target_arch = "arm"),
13125 stable(feature = "neon_intrinsics", since = "1.59.0")
13126)]
13127#[cfg_attr(
13128 target_arch = "arm",
13129 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13130)]
13131pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
13132 static_assert_uimm_bits!(IMM5, 1);
13133 unsafe { simd_extract!(v, IMM5 as u32) }
13134}
13135#[doc = "Move vector element to general-purpose register"]
13136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
13137#[inline]
13138#[target_feature(enable = "neon")]
13139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13140#[rustc_legacy_const_generics(1)]
13141#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13142#[cfg_attr(
13143 not(target_arch = "arm"),
13144 stable(feature = "neon_intrinsics", since = "1.59.0")
13145)]
13146#[cfg_attr(
13147 target_arch = "arm",
13148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13149)]
13150pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
13151 static_assert_uimm_bits!(IMM5, 4);
13152 unsafe { simd_extract!(v, IMM5 as u32) }
13153}
13154#[doc = "Move vector element to general-purpose register"]
13155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
13156#[inline]
13157#[target_feature(enable = "neon")]
13158#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13159#[rustc_legacy_const_generics(1)]
13160#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13161#[cfg_attr(
13162 not(target_arch = "arm"),
13163 stable(feature = "neon_intrinsics", since = "1.59.0")
13164)]
13165#[cfg_attr(
13166 target_arch = "arm",
13167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13168)]
13169pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
13170 static_assert_uimm_bits!(IMM5, 3);
13171 unsafe { simd_extract!(v, IMM5 as u32) }
13172}
13173#[doc = "Move vector element to general-purpose register"]
13174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
13175#[inline]
13176#[target_feature(enable = "neon")]
13177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13178#[rustc_legacy_const_generics(1)]
13179#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13180#[cfg_attr(
13181 not(target_arch = "arm"),
13182 stable(feature = "neon_intrinsics", since = "1.59.0")
13183)]
13184#[cfg_attr(
13185 target_arch = "arm",
13186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13187)]
13188pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
13189 static_assert_uimm_bits!(IMM5, 2);
13190 unsafe { simd_extract!(v, IMM5 as u32) }
13191}
13192#[doc = "Move vector element to general-purpose register"]
13193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
13194#[inline]
13195#[target_feature(enable = "neon")]
13196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13197#[rustc_legacy_const_generics(1)]
13198#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13199#[cfg_attr(
13200 not(target_arch = "arm"),
13201 stable(feature = "neon_intrinsics", since = "1.59.0")
13202)]
13203#[cfg_attr(
13204 target_arch = "arm",
13205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13206)]
13207pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
13208 static_assert_uimm_bits!(IMM5, 1);
13209 unsafe { simd_extract!(v, IMM5 as u32) }
13210}
13211#[doc = "Move vector element to general-purpose register"]
13212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
13213#[inline]
13214#[target_feature(enable = "neon")]
13215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13216#[rustc_legacy_const_generics(1)]
13217#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13218#[cfg_attr(
13219 not(target_arch = "arm"),
13220 stable(feature = "neon_intrinsics", since = "1.59.0")
13221)]
13222#[cfg_attr(
13223 target_arch = "arm",
13224 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13225)]
13226pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
13227 static_assert_uimm_bits!(IMM5, 4);
13228 unsafe { simd_extract!(v, IMM5 as u32) }
13229}
13230#[doc = "Move vector element to general-purpose register"]
13231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
13232#[inline]
13233#[target_feature(enable = "neon")]
13234#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13235#[rustc_legacy_const_generics(1)]
13236#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13237#[cfg_attr(
13238 not(target_arch = "arm"),
13239 stable(feature = "neon_intrinsics", since = "1.59.0")
13240)]
13241#[cfg_attr(
13242 target_arch = "arm",
13243 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13244)]
13245pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
13246 static_assert_uimm_bits!(IMM5, 3);
13247 unsafe { simd_extract!(v, IMM5 as u32) }
13248}
13249#[doc = "Move vector element to general-purpose register"]
13250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
13251#[inline]
13252#[target_feature(enable = "neon")]
13253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13254#[rustc_legacy_const_generics(1)]
13255#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13256#[cfg_attr(
13257 not(target_arch = "arm"),
13258 stable(feature = "neon_intrinsics", since = "1.59.0")
13259)]
13260#[cfg_attr(
13261 target_arch = "arm",
13262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13263)]
13264pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
13265 static_assert_uimm_bits!(IMM5, 2);
13266 unsafe { simd_extract!(v, IMM5 as u32) }
13267}
13268#[doc = "Move vector element to general-purpose register"]
13269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
13270#[inline]
13271#[target_feature(enable = "neon")]
13272#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13273#[rustc_legacy_const_generics(1)]
13274#[cfg_attr(test, assert_instr(nop, IMM5 = 1))]
13275#[cfg_attr(
13276 not(target_arch = "arm"),
13277 stable(feature = "neon_intrinsics", since = "1.59.0")
13278)]
13279#[cfg_attr(
13280 target_arch = "arm",
13281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13282)]
13283pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
13284 static_assert_uimm_bits!(IMM5, 2);
13285 unsafe { simd_extract!(v, IMM5 as u32) }
13286}
13287#[doc = "Move vector element to general-purpose register"]
13288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
13289#[inline]
13290#[target_feature(enable = "neon")]
13291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13292#[rustc_legacy_const_generics(1)]
13293#[cfg_attr(test, assert_instr(nop, IMM5 = 2))]
13294#[cfg_attr(
13295 not(target_arch = "arm"),
13296 stable(feature = "neon_intrinsics", since = "1.59.0")
13297)]
13298#[cfg_attr(
13299 target_arch = "arm",
13300 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13301)]
13302pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
13303 static_assert_uimm_bits!(IMM5, 4);
13304 unsafe { simd_extract!(v, IMM5 as u32) }
13305}
13306#[doc = "Move vector element to general-purpose register"]
13307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
13308#[inline]
13309#[target_feature(enable = "neon")]
13310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13311#[rustc_legacy_const_generics(1)]
13312#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13313#[cfg_attr(
13314 not(target_arch = "arm"),
13315 stable(feature = "neon_intrinsics", since = "1.59.0")
13316)]
13317#[cfg_attr(
13318 target_arch = "arm",
13319 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13320)]
13321pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
13322 static_assert!(IMM5 == 0);
13323 unsafe { simd_extract!(v, IMM5 as u32) }
13324}
13325#[doc = "Move vector element to general-purpose register"]
13326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
13327#[inline]
13328#[target_feature(enable = "neon")]
13329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13330#[rustc_legacy_const_generics(1)]
13331#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13332#[cfg_attr(
13333 not(target_arch = "arm"),
13334 stable(feature = "neon_intrinsics", since = "1.59.0")
13335)]
13336#[cfg_attr(
13337 target_arch = "arm",
13338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13339)]
13340pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
13341 static_assert!(IMM5 == 0);
13342 unsafe { simd_extract!(v, IMM5 as u32) }
13343}
13344#[doc = "Move vector element to general-purpose register"]
13345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
13346#[inline]
13347#[target_feature(enable = "neon")]
13348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13349#[rustc_legacy_const_generics(1)]
13350#[cfg_attr(test, assert_instr(nop, IMM5 = 0))]
13351#[cfg_attr(
13352 not(target_arch = "arm"),
13353 stable(feature = "neon_intrinsics", since = "1.59.0")
13354)]
13355#[cfg_attr(
13356 target_arch = "arm",
13357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13358)]
13359pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
13360 static_assert!(IMM5 == 0);
13361 unsafe { simd_extract!(v, 0) }
13362}
13363#[doc = "Duplicate vector element to vector or scalar"]
13364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
13365#[inline]
13366#[target_feature(enable = "neon")]
13367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13368#[cfg_attr(test, assert_instr(nop))]
13369#[cfg_attr(
13370 not(target_arch = "arm"),
13371 stable(feature = "neon_intrinsics", since = "1.59.0")
13372)]
13373#[cfg_attr(
13374 target_arch = "arm",
13375 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13376)]
13377pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
13378 unsafe { simd_shuffle!(a, a, [0, 1]) }
13379}
13380#[doc = "Duplicate vector element to vector or scalar"]
13381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
13382#[inline]
13383#[target_feature(enable = "neon")]
13384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13385#[cfg_attr(test, assert_instr(nop))]
13386#[cfg_attr(
13387 not(target_arch = "arm"),
13388 stable(feature = "neon_intrinsics", since = "1.59.0")
13389)]
13390#[cfg_attr(
13391 target_arch = "arm",
13392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13393)]
13394pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
13395 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13396}
13397#[doc = "Duplicate vector element to vector or scalar"]
13398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
13399#[inline]
13400#[target_feature(enable = "neon")]
13401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13402#[cfg_attr(test, assert_instr(nop))]
13403#[cfg_attr(
13404 not(target_arch = "arm"),
13405 stable(feature = "neon_intrinsics", since = "1.59.0")
13406)]
13407#[cfg_attr(
13408 target_arch = "arm",
13409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13410)]
13411pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
13412 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13413}
13414#[doc = "Duplicate vector element to vector or scalar"]
13415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
13416#[inline]
13417#[target_feature(enable = "neon")]
13418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13419#[cfg_attr(test, assert_instr(nop))]
13420#[cfg_attr(
13421 not(target_arch = "arm"),
13422 stable(feature = "neon_intrinsics", since = "1.59.0")
13423)]
13424#[cfg_attr(
13425 target_arch = "arm",
13426 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13427)]
13428pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
13429 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13430}
13431#[doc = "Duplicate vector element to vector or scalar"]
13432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
13433#[inline]
13434#[target_feature(enable = "neon")]
13435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13436#[cfg_attr(test, assert_instr(nop))]
13437#[cfg_attr(
13438 not(target_arch = "arm"),
13439 stable(feature = "neon_intrinsics", since = "1.59.0")
13440)]
13441#[cfg_attr(
13442 target_arch = "arm",
13443 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13444)]
13445pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
13446 unsafe { simd_shuffle!(a, a, [0, 1]) }
13447}
13448#[doc = "Duplicate vector element to vector or scalar"]
13449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
13450#[inline]
13451#[target_feature(enable = "neon")]
13452#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13453#[cfg_attr(test, assert_instr(nop))]
13454#[cfg_attr(
13455 not(target_arch = "arm"),
13456 stable(feature = "neon_intrinsics", since = "1.59.0")
13457)]
13458#[cfg_attr(
13459 target_arch = "arm",
13460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13461)]
13462pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
13463 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13464}
13465#[doc = "Duplicate vector element to vector or scalar"]
13466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
13467#[inline]
13468#[target_feature(enable = "neon")]
13469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13470#[cfg_attr(test, assert_instr(nop))]
13471#[cfg_attr(
13472 not(target_arch = "arm"),
13473 stable(feature = "neon_intrinsics", since = "1.59.0")
13474)]
13475#[cfg_attr(
13476 target_arch = "arm",
13477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13478)]
13479pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
13480 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
13481}
13482#[doc = "Duplicate vector element to vector or scalar"]
13483#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
13484#[inline]
13485#[target_feature(enable = "neon")]
13486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13487#[cfg_attr(test, assert_instr(nop))]
13488#[cfg_attr(
13489 not(target_arch = "arm"),
13490 stable(feature = "neon_intrinsics", since = "1.59.0")
13491)]
13492#[cfg_attr(
13493 target_arch = "arm",
13494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13495)]
13496pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
13497 unsafe { simd_shuffle!(a, a, [0, 1]) }
13498}
13499#[doc = "Duplicate vector element to vector or scalar"]
13500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
13501#[inline]
13502#[target_feature(enable = "neon")]
13503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13504#[cfg_attr(test, assert_instr(nop))]
13505#[cfg_attr(
13506 not(target_arch = "arm"),
13507 stable(feature = "neon_intrinsics", since = "1.59.0")
13508)]
13509#[cfg_attr(
13510 target_arch = "arm",
13511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13512)]
13513pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
13514 unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) }
13515}
13516#[doc = "Duplicate vector element to vector or scalar"]
13517#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
13518#[inline]
13519#[target_feature(enable = "neon")]
13520#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13521#[cfg_attr(test, assert_instr(nop))]
13522#[cfg_attr(
13523 not(target_arch = "arm"),
13524 stable(feature = "neon_intrinsics", since = "1.59.0")
13525)]
13526#[cfg_attr(
13527 target_arch = "arm",
13528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13529)]
13530pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
13531 unsafe { int64x1_t([simd_extract!(a, 0)]) }
13532}
13533#[doc = "Duplicate vector element to vector or scalar"]
13534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
13535#[inline]
13536#[target_feature(enable = "neon")]
13537#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13538#[cfg_attr(test, assert_instr(nop))]
13539#[cfg_attr(
13540 not(target_arch = "arm"),
13541 stable(feature = "neon_intrinsics", since = "1.59.0")
13542)]
13543#[cfg_attr(
13544 target_arch = "arm",
13545 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13546)]
13547pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
13548 unsafe { uint64x1_t([simd_extract!(a, 0)]) }
13549}
13550#[doc = "Halving add"]
13551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
13552#[inline]
13553#[target_feature(enable = "neon")]
13554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13556#[cfg_attr(
13557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13558 assert_instr(shadd)
13559)]
13560#[cfg_attr(
13561 not(target_arch = "arm"),
13562 stable(feature = "neon_intrinsics", since = "1.59.0")
13563)]
13564#[cfg_attr(
13565 target_arch = "arm",
13566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13567)]
13568pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
13569 unsafe extern "unadjusted" {
13570 #[cfg_attr(
13571 any(target_arch = "aarch64", target_arch = "arm64ec"),
13572 link_name = "llvm.aarch64.neon.shadd.v8i8"
13573 )]
13574 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")]
13575 fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
13576 }
13577 unsafe { _vhadd_s8(a, b) }
13578}
13579#[doc = "Halving add"]
13580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
13581#[inline]
13582#[target_feature(enable = "neon")]
13583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13584#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
13585#[cfg_attr(
13586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13587 assert_instr(shadd)
13588)]
13589#[cfg_attr(
13590 not(target_arch = "arm"),
13591 stable(feature = "neon_intrinsics", since = "1.59.0")
13592)]
13593#[cfg_attr(
13594 target_arch = "arm",
13595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13596)]
13597pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
13598 unsafe extern "unadjusted" {
13599 #[cfg_attr(
13600 any(target_arch = "aarch64", target_arch = "arm64ec"),
13601 link_name = "llvm.aarch64.neon.shadd.v16i8"
13602 )]
13603 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")]
13604 fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
13605 }
13606 unsafe { _vhaddq_s8(a, b) }
13607}
13608#[doc = "Halving add"]
13609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
13610#[inline]
13611#[target_feature(enable = "neon")]
13612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13613#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13614#[cfg_attr(
13615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13616 assert_instr(shadd)
13617)]
13618#[cfg_attr(
13619 not(target_arch = "arm"),
13620 stable(feature = "neon_intrinsics", since = "1.59.0")
13621)]
13622#[cfg_attr(
13623 target_arch = "arm",
13624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13625)]
13626pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13627 unsafe extern "unadjusted" {
13628 #[cfg_attr(
13629 any(target_arch = "aarch64", target_arch = "arm64ec"),
13630 link_name = "llvm.aarch64.neon.shadd.v4i16"
13631 )]
13632 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")]
13633 fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13634 }
13635 unsafe { _vhadd_s16(a, b) }
13636}
13637#[doc = "Halving add"]
13638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
13639#[inline]
13640#[target_feature(enable = "neon")]
13641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13642#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
13643#[cfg_attr(
13644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13645 assert_instr(shadd)
13646)]
13647#[cfg_attr(
13648 not(target_arch = "arm"),
13649 stable(feature = "neon_intrinsics", since = "1.59.0")
13650)]
13651#[cfg_attr(
13652 target_arch = "arm",
13653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13654)]
13655pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13656 unsafe extern "unadjusted" {
13657 #[cfg_attr(
13658 any(target_arch = "aarch64", target_arch = "arm64ec"),
13659 link_name = "llvm.aarch64.neon.shadd.v8i16"
13660 )]
13661 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")]
13662 fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13663 }
13664 unsafe { _vhaddq_s16(a, b) }
13665}
13666#[doc = "Halving add"]
13667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
13668#[inline]
13669#[target_feature(enable = "neon")]
13670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13671#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13672#[cfg_attr(
13673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13674 assert_instr(shadd)
13675)]
13676#[cfg_attr(
13677 not(target_arch = "arm"),
13678 stable(feature = "neon_intrinsics", since = "1.59.0")
13679)]
13680#[cfg_attr(
13681 target_arch = "arm",
13682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13683)]
13684pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13685 unsafe extern "unadjusted" {
13686 #[cfg_attr(
13687 any(target_arch = "aarch64", target_arch = "arm64ec"),
13688 link_name = "llvm.aarch64.neon.shadd.v2i32"
13689 )]
13690 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")]
13691 fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
13692 }
13693 unsafe { _vhadd_s32(a, b) }
13694}
13695#[doc = "Halving add"]
13696#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
13697#[inline]
13698#[target_feature(enable = "neon")]
13699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13700#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
13701#[cfg_attr(
13702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13703 assert_instr(shadd)
13704)]
13705#[cfg_attr(
13706 not(target_arch = "arm"),
13707 stable(feature = "neon_intrinsics", since = "1.59.0")
13708)]
13709#[cfg_attr(
13710 target_arch = "arm",
13711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13712)]
13713pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
13714 unsafe extern "unadjusted" {
13715 #[cfg_attr(
13716 any(target_arch = "aarch64", target_arch = "arm64ec"),
13717 link_name = "llvm.aarch64.neon.shadd.v4i32"
13718 )]
13719 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")]
13720 fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
13721 }
13722 unsafe { _vhaddq_s32(a, b) }
13723}
13724#[doc = "Halving add"]
13725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
13726#[inline]
13727#[target_feature(enable = "neon")]
13728#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13729#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13730#[cfg_attr(
13731 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13732 assert_instr(uhadd)
13733)]
13734#[cfg_attr(
13735 not(target_arch = "arm"),
13736 stable(feature = "neon_intrinsics", since = "1.59.0")
13737)]
13738#[cfg_attr(
13739 target_arch = "arm",
13740 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13741)]
13742pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
13743 unsafe extern "unadjusted" {
13744 #[cfg_attr(
13745 any(target_arch = "aarch64", target_arch = "arm64ec"),
13746 link_name = "llvm.aarch64.neon.uhadd.v8i8"
13747 )]
13748 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")]
13749 fn _vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
13750 }
13751 unsafe { _vhadd_u8(a, b) }
13752}
13753#[doc = "Halving add"]
13754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
13755#[inline]
13756#[target_feature(enable = "neon")]
13757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
13759#[cfg_attr(
13760 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13761 assert_instr(uhadd)
13762)]
13763#[cfg_attr(
13764 not(target_arch = "arm"),
13765 stable(feature = "neon_intrinsics", since = "1.59.0")
13766)]
13767#[cfg_attr(
13768 target_arch = "arm",
13769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13770)]
13771pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
13772 unsafe extern "unadjusted" {
13773 #[cfg_attr(
13774 any(target_arch = "aarch64", target_arch = "arm64ec"),
13775 link_name = "llvm.aarch64.neon.uhadd.v16i8"
13776 )]
13777 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")]
13778 fn _vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
13779 }
13780 unsafe { _vhaddq_u8(a, b) }
13781}
13782#[doc = "Halving add"]
13783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
13784#[inline]
13785#[target_feature(enable = "neon")]
13786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13788#[cfg_attr(
13789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13790 assert_instr(uhadd)
13791)]
13792#[cfg_attr(
13793 not(target_arch = "arm"),
13794 stable(feature = "neon_intrinsics", since = "1.59.0")
13795)]
13796#[cfg_attr(
13797 target_arch = "arm",
13798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13799)]
13800pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
13801 unsafe extern "unadjusted" {
13802 #[cfg_attr(
13803 any(target_arch = "aarch64", target_arch = "arm64ec"),
13804 link_name = "llvm.aarch64.neon.uhadd.v4i16"
13805 )]
13806 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")]
13807 fn _vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
13808 }
13809 unsafe { _vhadd_u16(a, b) }
13810}
13811#[doc = "Halving add"]
13812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
13813#[inline]
13814#[target_feature(enable = "neon")]
13815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
13817#[cfg_attr(
13818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13819 assert_instr(uhadd)
13820)]
13821#[cfg_attr(
13822 not(target_arch = "arm"),
13823 stable(feature = "neon_intrinsics", since = "1.59.0")
13824)]
13825#[cfg_attr(
13826 target_arch = "arm",
13827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13828)]
13829pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
13830 unsafe extern "unadjusted" {
13831 #[cfg_attr(
13832 any(target_arch = "aarch64", target_arch = "arm64ec"),
13833 link_name = "llvm.aarch64.neon.uhadd.v8i16"
13834 )]
13835 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")]
13836 fn _vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
13837 }
13838 unsafe { _vhaddq_u16(a, b) }
13839}
13840#[doc = "Halving add"]
13841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
13842#[inline]
13843#[target_feature(enable = "neon")]
13844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13845#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13846#[cfg_attr(
13847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13848 assert_instr(uhadd)
13849)]
13850#[cfg_attr(
13851 not(target_arch = "arm"),
13852 stable(feature = "neon_intrinsics", since = "1.59.0")
13853)]
13854#[cfg_attr(
13855 target_arch = "arm",
13856 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13857)]
13858pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
13859 unsafe extern "unadjusted" {
13860 #[cfg_attr(
13861 any(target_arch = "aarch64", target_arch = "arm64ec"),
13862 link_name = "llvm.aarch64.neon.uhadd.v2i32"
13863 )]
13864 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")]
13865 fn _vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
13866 }
13867 unsafe { _vhadd_u32(a, b) }
13868}
13869#[doc = "Halving add"]
13870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
13871#[inline]
13872#[target_feature(enable = "neon")]
13873#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13874#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
13875#[cfg_attr(
13876 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13877 assert_instr(uhadd)
13878)]
13879#[cfg_attr(
13880 not(target_arch = "arm"),
13881 stable(feature = "neon_intrinsics", since = "1.59.0")
13882)]
13883#[cfg_attr(
13884 target_arch = "arm",
13885 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13886)]
13887pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
13888 unsafe extern "unadjusted" {
13889 #[cfg_attr(
13890 any(target_arch = "aarch64", target_arch = "arm64ec"),
13891 link_name = "llvm.aarch64.neon.uhadd.v4i32"
13892 )]
13893 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")]
13894 fn _vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
13895 }
13896 unsafe { _vhaddq_u32(a, b) }
13897}
13898#[doc = "Signed halving subtract"]
13899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
13900#[inline]
13901#[target_feature(enable = "neon")]
13902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13903#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
13904#[cfg_attr(
13905 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13906 assert_instr(shsub)
13907)]
13908#[cfg_attr(
13909 not(target_arch = "arm"),
13910 stable(feature = "neon_intrinsics", since = "1.59.0")
13911)]
13912#[cfg_attr(
13913 target_arch = "arm",
13914 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13915)]
13916pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
13917 unsafe extern "unadjusted" {
13918 #[cfg_attr(
13919 any(target_arch = "aarch64", target_arch = "arm64ec"),
13920 link_name = "llvm.aarch64.neon.shsub.v4i16"
13921 )]
13922 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")]
13923 fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
13924 }
13925 unsafe { _vhsub_s16(a, b) }
13926}
13927#[doc = "Signed halving subtract"]
13928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
13929#[inline]
13930#[target_feature(enable = "neon")]
13931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13932#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
13933#[cfg_attr(
13934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13935 assert_instr(shsub)
13936)]
13937#[cfg_attr(
13938 not(target_arch = "arm"),
13939 stable(feature = "neon_intrinsics", since = "1.59.0")
13940)]
13941#[cfg_attr(
13942 target_arch = "arm",
13943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13944)]
13945pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
13946 unsafe extern "unadjusted" {
13947 #[cfg_attr(
13948 any(target_arch = "aarch64", target_arch = "arm64ec"),
13949 link_name = "llvm.aarch64.neon.shsub.v8i16"
13950 )]
13951 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")]
13952 fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
13953 }
13954 unsafe { _vhsubq_s16(a, b) }
13955}
13956#[doc = "Signed halving subtract"]
13957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
13958#[inline]
13959#[target_feature(enable = "neon")]
13960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13961#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
13962#[cfg_attr(
13963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13964 assert_instr(shsub)
13965)]
13966#[cfg_attr(
13967 not(target_arch = "arm"),
13968 stable(feature = "neon_intrinsics", since = "1.59.0")
13969)]
13970#[cfg_attr(
13971 target_arch = "arm",
13972 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
13973)]
13974pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
13975 unsafe extern "unadjusted" {
13976 #[cfg_attr(
13977 any(target_arch = "aarch64", target_arch = "arm64ec"),
13978 link_name = "llvm.aarch64.neon.shsub.v2i32"
13979 )]
13980 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")]
13981 fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
13982 }
13983 unsafe { _vhsub_s32(a, b) }
13984}
13985#[doc = "Signed halving subtract"]
13986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
13987#[inline]
13988#[target_feature(enable = "neon")]
13989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
13990#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
13991#[cfg_attr(
13992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
13993 assert_instr(shsub)
13994)]
13995#[cfg_attr(
13996 not(target_arch = "arm"),
13997 stable(feature = "neon_intrinsics", since = "1.59.0")
13998)]
13999#[cfg_attr(
14000 target_arch = "arm",
14001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14002)]
14003pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
14004 unsafe extern "unadjusted" {
14005 #[cfg_attr(
14006 any(target_arch = "aarch64", target_arch = "arm64ec"),
14007 link_name = "llvm.aarch64.neon.shsub.v4i32"
14008 )]
14009 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")]
14010 fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
14011 }
14012 unsafe { _vhsubq_s32(a, b) }
14013}
14014#[doc = "Signed halving subtract"]
14015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
14016#[inline]
14017#[target_feature(enable = "neon")]
14018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14019#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14020#[cfg_attr(
14021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14022 assert_instr(shsub)
14023)]
14024#[cfg_attr(
14025 not(target_arch = "arm"),
14026 stable(feature = "neon_intrinsics", since = "1.59.0")
14027)]
14028#[cfg_attr(
14029 target_arch = "arm",
14030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14031)]
14032pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
14033 unsafe extern "unadjusted" {
14034 #[cfg_attr(
14035 any(target_arch = "aarch64", target_arch = "arm64ec"),
14036 link_name = "llvm.aarch64.neon.shsub.v8i8"
14037 )]
14038 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")]
14039 fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
14040 }
14041 unsafe { _vhsub_s8(a, b) }
14042}
14043#[doc = "Signed halving subtract"]
14044#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
14045#[inline]
14046#[target_feature(enable = "neon")]
14047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14048#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
14049#[cfg_attr(
14050 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14051 assert_instr(shsub)
14052)]
14053#[cfg_attr(
14054 not(target_arch = "arm"),
14055 stable(feature = "neon_intrinsics", since = "1.59.0")
14056)]
14057#[cfg_attr(
14058 target_arch = "arm",
14059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14060)]
14061pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
14062 unsafe extern "unadjusted" {
14063 #[cfg_attr(
14064 any(target_arch = "aarch64", target_arch = "arm64ec"),
14065 link_name = "llvm.aarch64.neon.shsub.v16i8"
14066 )]
14067 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")]
14068 fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
14069 }
14070 unsafe { _vhsubq_s8(a, b) }
14071}
14072#[doc = "Signed halving subtract"]
14073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
14074#[inline]
14075#[target_feature(enable = "neon")]
14076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14077#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14078#[cfg_attr(
14079 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14080 assert_instr(uhsub)
14081)]
14082#[cfg_attr(
14083 not(target_arch = "arm"),
14084 stable(feature = "neon_intrinsics", since = "1.59.0")
14085)]
14086#[cfg_attr(
14087 target_arch = "arm",
14088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14089)]
14090pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
14091 unsafe extern "unadjusted" {
14092 #[cfg_attr(
14093 any(target_arch = "aarch64", target_arch = "arm64ec"),
14094 link_name = "llvm.aarch64.neon.uhsub.v8i8"
14095 )]
14096 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")]
14097 fn _vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
14098 }
14099 unsafe { _vhsub_u8(a, b) }
14100}
14101#[doc = "Signed halving subtract"]
14102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
14103#[inline]
14104#[target_feature(enable = "neon")]
14105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14106#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
14107#[cfg_attr(
14108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14109 assert_instr(uhsub)
14110)]
14111#[cfg_attr(
14112 not(target_arch = "arm"),
14113 stable(feature = "neon_intrinsics", since = "1.59.0")
14114)]
14115#[cfg_attr(
14116 target_arch = "arm",
14117 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14118)]
14119pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
14120 unsafe extern "unadjusted" {
14121 #[cfg_attr(
14122 any(target_arch = "aarch64", target_arch = "arm64ec"),
14123 link_name = "llvm.aarch64.neon.uhsub.v16i8"
14124 )]
14125 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")]
14126 fn _vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
14127 }
14128 unsafe { _vhsubq_u8(a, b) }
14129}
14130#[doc = "Signed halving subtract"]
14131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
14132#[inline]
14133#[target_feature(enable = "neon")]
14134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14135#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14136#[cfg_attr(
14137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14138 assert_instr(uhsub)
14139)]
14140#[cfg_attr(
14141 not(target_arch = "arm"),
14142 stable(feature = "neon_intrinsics", since = "1.59.0")
14143)]
14144#[cfg_attr(
14145 target_arch = "arm",
14146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14147)]
14148pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
14149 unsafe extern "unadjusted" {
14150 #[cfg_attr(
14151 any(target_arch = "aarch64", target_arch = "arm64ec"),
14152 link_name = "llvm.aarch64.neon.uhsub.v4i16"
14153 )]
14154 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")]
14155 fn _vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
14156 }
14157 unsafe { _vhsub_u16(a, b) }
14158}
14159#[doc = "Signed halving subtract"]
14160#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
14161#[inline]
14162#[target_feature(enable = "neon")]
14163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14164#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
14165#[cfg_attr(
14166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14167 assert_instr(uhsub)
14168)]
14169#[cfg_attr(
14170 not(target_arch = "arm"),
14171 stable(feature = "neon_intrinsics", since = "1.59.0")
14172)]
14173#[cfg_attr(
14174 target_arch = "arm",
14175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14176)]
14177pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
14178 unsafe extern "unadjusted" {
14179 #[cfg_attr(
14180 any(target_arch = "aarch64", target_arch = "arm64ec"),
14181 link_name = "llvm.aarch64.neon.uhsub.v8i16"
14182 )]
14183 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")]
14184 fn _vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
14185 }
14186 unsafe { _vhsubq_u16(a, b) }
14187}
14188#[doc = "Signed halving subtract"]
14189#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
14190#[inline]
14191#[target_feature(enable = "neon")]
14192#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14193#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14194#[cfg_attr(
14195 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14196 assert_instr(uhsub)
14197)]
14198#[cfg_attr(
14199 not(target_arch = "arm"),
14200 stable(feature = "neon_intrinsics", since = "1.59.0")
14201)]
14202#[cfg_attr(
14203 target_arch = "arm",
14204 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14205)]
14206pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
14207 unsafe extern "unadjusted" {
14208 #[cfg_attr(
14209 any(target_arch = "aarch64", target_arch = "arm64ec"),
14210 link_name = "llvm.aarch64.neon.uhsub.v2i32"
14211 )]
14212 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")]
14213 fn _vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
14214 }
14215 unsafe { _vhsub_u32(a, b) }
14216}
14217#[doc = "Signed halving subtract"]
14218#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
14219#[inline]
14220#[target_feature(enable = "neon")]
14221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14222#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
14223#[cfg_attr(
14224 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14225 assert_instr(uhsub)
14226)]
14227#[cfg_attr(
14228 not(target_arch = "arm"),
14229 stable(feature = "neon_intrinsics", since = "1.59.0")
14230)]
14231#[cfg_attr(
14232 target_arch = "arm",
14233 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14234)]
14235pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
14236 unsafe extern "unadjusted" {
14237 #[cfg_attr(
14238 any(target_arch = "aarch64", target_arch = "arm64ec"),
14239 link_name = "llvm.aarch64.neon.uhsub.v4i32"
14240 )]
14241 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")]
14242 fn _vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
14243 }
14244 unsafe { _vhsubq_u32(a, b) }
14245}
14246#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
14248#[doc = "## Safety"]
14249#[doc = " * Neon instrinsic unsafe"]
14250#[inline]
14251#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14252#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14253#[cfg_attr(
14254 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14255 assert_instr(ld1r)
14256)]
14257#[target_feature(enable = "neon,fp16")]
14258#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14259pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
14260 let x: float16x4_t = vld1_lane_f16::<0>(ptr, transmute(f16x4::splat(0.0)));
14261 simd_shuffle!(x, x, [0, 0, 0, 0])
14262}
14263#[doc = "Load one single-element structure and replicate to all lanes of one register"]
14264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
14265#[doc = "## Safety"]
14266#[doc = " * Neon instrinsic unsafe"]
14267#[inline]
14268#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14270#[cfg_attr(
14271 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14272 assert_instr(ld1r)
14273)]
14274#[target_feature(enable = "neon,fp16")]
14275#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14276pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
14277 let x: float16x8_t = vld1q_lane_f16::<0>(ptr, transmute(f16x8::splat(0.0)));
14278 simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
14279}
14280#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
14282#[doc = "## Safety"]
14283#[doc = " * Neon instrinsic unsafe"]
14284#[inline]
14285#[target_feature(enable = "neon")]
14286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14287#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14288#[cfg_attr(
14289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14290 assert_instr(ld1r)
14291)]
14292#[cfg_attr(
14293 not(target_arch = "arm"),
14294 stable(feature = "neon_intrinsics", since = "1.59.0")
14295)]
14296#[cfg_attr(
14297 target_arch = "arm",
14298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14299)]
14300pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
14301 transmute(f32x2::splat(*ptr))
14302}
14303#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
14305#[doc = "## Safety"]
14306#[doc = " * Neon instrinsic unsafe"]
14307#[inline]
14308#[target_feature(enable = "neon")]
14309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14311#[cfg_attr(
14312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14313 assert_instr(ld1r)
14314)]
14315#[cfg_attr(
14316 not(target_arch = "arm"),
14317 stable(feature = "neon_intrinsics", since = "1.59.0")
14318)]
14319#[cfg_attr(
14320 target_arch = "arm",
14321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14322)]
14323pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
14324 transmute(u16x4::splat(*ptr))
14325}
14326#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
14328#[doc = "## Safety"]
14329#[doc = " * Neon instrinsic unsafe"]
14330#[inline]
14331#[target_feature(enable = "neon")]
14332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14333#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14334#[cfg_attr(
14335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14336 assert_instr(ld1r)
14337)]
14338#[cfg_attr(
14339 not(target_arch = "arm"),
14340 stable(feature = "neon_intrinsics", since = "1.59.0")
14341)]
14342#[cfg_attr(
14343 target_arch = "arm",
14344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14345)]
14346pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
14347 transmute(u8x8::splat(*ptr))
14348}
14349#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
14351#[doc = "## Safety"]
14352#[doc = " * Neon instrinsic unsafe"]
14353#[inline]
14354#[target_feature(enable = "neon")]
14355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14356#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14357#[cfg_attr(
14358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14359 assert_instr(ld1r)
14360)]
14361#[cfg_attr(
14362 not(target_arch = "arm"),
14363 stable(feature = "neon_intrinsics", since = "1.59.0")
14364)]
14365#[cfg_attr(
14366 target_arch = "arm",
14367 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14368)]
14369pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
14370 transmute(i16x4::splat(*ptr))
14371}
14372#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
14374#[doc = "## Safety"]
14375#[doc = " * Neon instrinsic unsafe"]
14376#[inline]
14377#[target_feature(enable = "neon")]
14378#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14379#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14380#[cfg_attr(
14381 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14382 assert_instr(ld1r)
14383)]
14384#[cfg_attr(
14385 not(target_arch = "arm"),
14386 stable(feature = "neon_intrinsics", since = "1.59.0")
14387)]
14388#[cfg_attr(
14389 target_arch = "arm",
14390 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14391)]
14392pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
14393 transmute(i32x2::splat(*ptr))
14394}
14395#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
14397#[doc = "## Safety"]
14398#[doc = " * Neon instrinsic unsafe"]
14399#[inline]
14400#[target_feature(enable = "neon")]
14401#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14402#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14403#[cfg_attr(
14404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14405 assert_instr(ld1r)
14406)]
14407#[cfg_attr(
14408 not(target_arch = "arm"),
14409 stable(feature = "neon_intrinsics", since = "1.59.0")
14410)]
14411#[cfg_attr(
14412 target_arch = "arm",
14413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14414)]
14415pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
14416 transmute(i8x8::splat(*ptr))
14417}
14418#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
14420#[doc = "## Safety"]
14421#[doc = " * Neon instrinsic unsafe"]
14422#[inline]
14423#[target_feature(enable = "neon")]
14424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14425#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14426#[cfg_attr(
14427 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14428 assert_instr(ld1r)
14429)]
14430#[cfg_attr(
14431 not(target_arch = "arm"),
14432 stable(feature = "neon_intrinsics", since = "1.59.0")
14433)]
14434#[cfg_attr(
14435 target_arch = "arm",
14436 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14437)]
14438pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
14439 transmute(u16x4::splat(*ptr))
14440}
14441#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
14443#[doc = "## Safety"]
14444#[doc = " * Neon instrinsic unsafe"]
14445#[inline]
14446#[target_feature(enable = "neon")]
14447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14448#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14449#[cfg_attr(
14450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14451 assert_instr(ld1r)
14452)]
14453#[cfg_attr(
14454 not(target_arch = "arm"),
14455 stable(feature = "neon_intrinsics", since = "1.59.0")
14456)]
14457#[cfg_attr(
14458 target_arch = "arm",
14459 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14460)]
14461pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
14462 transmute(u32x2::splat(*ptr))
14463}
14464#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
14466#[doc = "## Safety"]
14467#[doc = " * Neon instrinsic unsafe"]
14468#[inline]
14469#[target_feature(enable = "neon")]
14470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14472#[cfg_attr(
14473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14474 assert_instr(ld1r)
14475)]
14476#[cfg_attr(
14477 not(target_arch = "arm"),
14478 stable(feature = "neon_intrinsics", since = "1.59.0")
14479)]
14480#[cfg_attr(
14481 target_arch = "arm",
14482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14483)]
14484pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
14485 transmute(u8x8::splat(*ptr))
14486}
14487#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
14489#[doc = "## Safety"]
14490#[doc = " * Neon instrinsic unsafe"]
14491#[inline]
14492#[target_feature(enable = "neon")]
14493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14494#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14495#[cfg_attr(
14496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14497 assert_instr(ld1r)
14498)]
14499#[cfg_attr(
14500 not(target_arch = "arm"),
14501 stable(feature = "neon_intrinsics", since = "1.59.0")
14502)]
14503#[cfg_attr(
14504 target_arch = "arm",
14505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14506)]
14507pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
14508 transmute(f32x4::splat(*ptr))
14509}
14510#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
14512#[doc = "## Safety"]
14513#[doc = " * Neon instrinsic unsafe"]
14514#[inline]
14515#[target_feature(enable = "neon")]
14516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14517#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14518#[cfg_attr(
14519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14520 assert_instr(ld1r)
14521)]
14522#[cfg_attr(
14523 not(target_arch = "arm"),
14524 stable(feature = "neon_intrinsics", since = "1.59.0")
14525)]
14526#[cfg_attr(
14527 target_arch = "arm",
14528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14529)]
14530pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
14531 transmute(u16x8::splat(*ptr))
14532}
14533#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
14535#[doc = "## Safety"]
14536#[doc = " * Neon instrinsic unsafe"]
14537#[inline]
14538#[target_feature(enable = "neon")]
14539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14541#[cfg_attr(
14542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14543 assert_instr(ld1r)
14544)]
14545#[cfg_attr(
14546 not(target_arch = "arm"),
14547 stable(feature = "neon_intrinsics", since = "1.59.0")
14548)]
14549#[cfg_attr(
14550 target_arch = "arm",
14551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14552)]
14553pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
14554 transmute(u8x16::splat(*ptr))
14555}
14556#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
14558#[doc = "## Safety"]
14559#[doc = " * Neon instrinsic unsafe"]
14560#[inline]
14561#[target_feature(enable = "neon")]
14562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14563#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14564#[cfg_attr(
14565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14566 assert_instr(ld1r)
14567)]
14568#[cfg_attr(
14569 not(target_arch = "arm"),
14570 stable(feature = "neon_intrinsics", since = "1.59.0")
14571)]
14572#[cfg_attr(
14573 target_arch = "arm",
14574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14575)]
14576pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
14577 transmute(i16x8::splat(*ptr))
14578}
14579#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
14581#[doc = "## Safety"]
14582#[doc = " * Neon instrinsic unsafe"]
14583#[inline]
14584#[target_feature(enable = "neon")]
14585#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14586#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14587#[cfg_attr(
14588 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14589 assert_instr(ld1r)
14590)]
14591#[cfg_attr(
14592 not(target_arch = "arm"),
14593 stable(feature = "neon_intrinsics", since = "1.59.0")
14594)]
14595#[cfg_attr(
14596 target_arch = "arm",
14597 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14598)]
14599pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
14600 transmute(i32x4::splat(*ptr))
14601}
14602#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
14604#[doc = "## Safety"]
14605#[doc = " * Neon instrinsic unsafe"]
14606#[inline]
14607#[target_feature(enable = "neon")]
14608#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14609#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14610#[cfg_attr(
14611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14612 assert_instr(ld1r)
14613)]
14614#[cfg_attr(
14615 not(target_arch = "arm"),
14616 stable(feature = "neon_intrinsics", since = "1.59.0")
14617)]
14618#[cfg_attr(
14619 target_arch = "arm",
14620 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14621)]
14622pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
14623 transmute(i64x2::splat(*ptr))
14624}
14625#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
14627#[doc = "## Safety"]
14628#[doc = " * Neon instrinsic unsafe"]
14629#[inline]
14630#[target_feature(enable = "neon")]
14631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14632#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14633#[cfg_attr(
14634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14635 assert_instr(ld1r)
14636)]
14637#[cfg_attr(
14638 not(target_arch = "arm"),
14639 stable(feature = "neon_intrinsics", since = "1.59.0")
14640)]
14641#[cfg_attr(
14642 target_arch = "arm",
14643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14644)]
14645pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
14646 transmute(i8x16::splat(*ptr))
14647}
14648#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
14650#[doc = "## Safety"]
14651#[doc = " * Neon instrinsic unsafe"]
14652#[inline]
14653#[target_feature(enable = "neon")]
14654#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14655#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14656#[cfg_attr(
14657 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14658 assert_instr(ld1r)
14659)]
14660#[cfg_attr(
14661 not(target_arch = "arm"),
14662 stable(feature = "neon_intrinsics", since = "1.59.0")
14663)]
14664#[cfg_attr(
14665 target_arch = "arm",
14666 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14667)]
14668pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
14669 transmute(u16x8::splat(*ptr))
14670}
14671#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
14673#[doc = "## Safety"]
14674#[doc = " * Neon instrinsic unsafe"]
14675#[inline]
14676#[target_feature(enable = "neon")]
14677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
14679#[cfg_attr(
14680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14681 assert_instr(ld1r)
14682)]
14683#[cfg_attr(
14684 not(target_arch = "arm"),
14685 stable(feature = "neon_intrinsics", since = "1.59.0")
14686)]
14687#[cfg_attr(
14688 target_arch = "arm",
14689 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14690)]
14691pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
14692 transmute(u32x4::splat(*ptr))
14693}
14694#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
14696#[doc = "## Safety"]
14697#[doc = " * Neon instrinsic unsafe"]
14698#[inline]
14699#[target_feature(enable = "neon")]
14700#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14701#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
14702#[cfg_attr(
14703 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14704 assert_instr(ld1r)
14705)]
14706#[cfg_attr(
14707 not(target_arch = "arm"),
14708 stable(feature = "neon_intrinsics", since = "1.59.0")
14709)]
14710#[cfg_attr(
14711 target_arch = "arm",
14712 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14713)]
14714pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
14715 transmute(u64x2::splat(*ptr))
14716}
14717#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
14719#[doc = "## Safety"]
14720#[doc = " * Neon instrinsic unsafe"]
14721#[inline]
14722#[target_feature(enable = "neon")]
14723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
14725#[cfg_attr(
14726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14727 assert_instr(ld1r)
14728)]
14729#[cfg_attr(
14730 not(target_arch = "arm"),
14731 stable(feature = "neon_intrinsics", since = "1.59.0")
14732)]
14733#[cfg_attr(
14734 target_arch = "arm",
14735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14736)]
14737pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
14738 transmute(u8x16::splat(*ptr))
14739}
14740#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
14742#[doc = "## Safety"]
14743#[doc = " * Neon instrinsic unsafe"]
14744#[inline]
14745#[target_feature(enable = "neon,aes")]
14746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14748#[cfg_attr(
14749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14750 assert_instr(ldr)
14751)]
14752#[cfg_attr(
14753 not(target_arch = "arm"),
14754 stable(feature = "neon_intrinsics", since = "1.59.0")
14755)]
14756#[cfg_attr(
14757 target_arch = "arm",
14758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14759)]
14760pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
14761 let x: poly64x1_t;
14762 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14763 {
14764 x = crate::core_arch::aarch64::vld1_p64(ptr);
14765 }
14766 #[cfg(target_arch = "arm")]
14767 {
14768 x = crate::core_arch::arm::vld1_p64(ptr);
14769 };
14770 x
14771}
14772#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
14774#[doc = "## Safety"]
14775#[doc = " * Neon instrinsic unsafe"]
14776#[inline]
14777#[target_feature(enable = "neon")]
14778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14780#[cfg_attr(
14781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14782 assert_instr(ldr)
14783)]
14784#[cfg_attr(
14785 not(target_arch = "arm"),
14786 stable(feature = "neon_intrinsics", since = "1.59.0")
14787)]
14788#[cfg_attr(
14789 target_arch = "arm",
14790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14791)]
14792pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
14793 let x: int64x1_t;
14794 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14795 {
14796 x = crate::core_arch::aarch64::vld1_s64(ptr);
14797 }
14798 #[cfg(target_arch = "arm")]
14799 {
14800 x = crate::core_arch::arm::vld1_s64(ptr);
14801 };
14802 x
14803}
14804#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
14805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
14806#[doc = "## Safety"]
14807#[doc = " * Neon instrinsic unsafe"]
14808#[inline]
14809#[target_feature(enable = "neon")]
14810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
14812#[cfg_attr(
14813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14814 assert_instr(ldr)
14815)]
14816#[cfg_attr(
14817 not(target_arch = "arm"),
14818 stable(feature = "neon_intrinsics", since = "1.59.0")
14819)]
14820#[cfg_attr(
14821 target_arch = "arm",
14822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
14823)]
14824pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
14825 let x: uint64x1_t;
14826 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
14827 {
14828 x = crate::core_arch::aarch64::vld1_u64(ptr);
14829 }
14830 #[cfg(target_arch = "arm")]
14831 {
14832 x = crate::core_arch::arm::vld1_u64(ptr);
14833 };
14834 x
14835}
14836#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14838#[doc = "## Safety"]
14839#[doc = " * Neon instrinsic unsafe"]
14840#[inline]
14841#[cfg(target_endian = "little")]
14842#[cfg(target_arch = "arm")]
14843#[target_feature(enable = "neon,v7")]
14844#[target_feature(enable = "neon,fp16")]
14845#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14846#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14847pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14848 transmute(vld1_v4f16(
14849 ptr as *const i8,
14850 crate::mem::align_of::<f16>() as i32,
14851 ))
14852}
14853#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
14855#[doc = "## Safety"]
14856#[doc = " * Neon instrinsic unsafe"]
14857#[inline]
14858#[cfg(target_endian = "big")]
14859#[cfg(target_arch = "arm")]
14860#[target_feature(enable = "neon,v7")]
14861#[target_feature(enable = "neon,fp16")]
14862#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14864pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
14865 let ret_val: float16x4_t = transmute(vld1_v4f16(
14866 ptr as *const i8,
14867 crate::mem::align_of::<f16>() as i32,
14868 ));
14869 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
14870}
14871#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
14873#[doc = "## Safety"]
14874#[doc = " * Neon instrinsic unsafe"]
14875#[inline]
14876#[cfg(target_endian = "little")]
14877#[cfg(target_arch = "arm")]
14878#[target_feature(enable = "neon,v7")]
14879#[target_feature(enable = "neon,fp16")]
14880#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14882pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
14883 transmute(vld1q_v8f16(
14884 ptr as *const i8,
14885 crate::mem::align_of::<f16>() as i32,
14886 ))
14887}
14888#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
14889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
14890#[doc = "## Safety"]
14891#[doc = " * Neon instrinsic unsafe"]
14892#[inline]
14893#[cfg(target_endian = "big")]
14894#[cfg(target_arch = "arm")]
14895#[target_feature(enable = "neon,v7")]
14896#[target_feature(enable = "neon,fp16")]
14897#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14898#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
14899pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
14900 let ret_val: float16x8_t = transmute(vld1q_v8f16(
14901 ptr as *const i8,
14902 crate::mem::align_of::<f16>() as i32,
14903 ));
14904 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
14905}
14906#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
14908#[doc = "## Safety"]
14909#[doc = " * Neon instrinsic unsafe"]
14910#[inline]
14911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14913#[cfg_attr(
14914 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14915 assert_instr(ld1)
14916)]
14917#[target_feature(enable = "neon,fp16")]
14918#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14919pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
14920 unsafe extern "unadjusted" {
14921 #[cfg_attr(
14922 any(target_arch = "aarch64", target_arch = "arm64ec"),
14923 link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0"
14924 )]
14925 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")]
14926 fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t;
14927 }
14928 _vld1_f16_x2(a)
14929}
14930#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
14932#[doc = "## Safety"]
14933#[doc = " * Neon instrinsic unsafe"]
14934#[inline]
14935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14937#[cfg_attr(
14938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14939 assert_instr(ld1)
14940)]
14941#[target_feature(enable = "neon,fp16")]
14942#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14943pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
14944 unsafe extern "unadjusted" {
14945 #[cfg_attr(
14946 any(target_arch = "aarch64", target_arch = "arm64ec"),
14947 link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0"
14948 )]
14949 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")]
14950 fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t;
14951 }
14952 _vld1_f16_x3(a)
14953}
14954#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
14956#[doc = "## Safety"]
14957#[doc = " * Neon instrinsic unsafe"]
14958#[inline]
14959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14961#[cfg_attr(
14962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14963 assert_instr(ld1)
14964)]
14965#[target_feature(enable = "neon,fp16")]
14966#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14967pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
14968 unsafe extern "unadjusted" {
14969 #[cfg_attr(
14970 any(target_arch = "aarch64", target_arch = "arm64ec"),
14971 link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0"
14972 )]
14973 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")]
14974 fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t;
14975 }
14976 _vld1_f16_x4(a)
14977}
14978#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
14979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
14980#[doc = "## Safety"]
14981#[doc = " * Neon instrinsic unsafe"]
14982#[inline]
14983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
14984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
14985#[cfg_attr(
14986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
14987 assert_instr(ld1)
14988)]
14989#[target_feature(enable = "neon,fp16")]
14990#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
14991pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
14992 unsafe extern "unadjusted" {
14993 #[cfg_attr(
14994 any(target_arch = "aarch64", target_arch = "arm64ec"),
14995 link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0"
14996 )]
14997 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")]
14998 fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t;
14999 }
15000 _vld1q_f16_x2(a)
15001}
15002#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
15004#[doc = "## Safety"]
15005#[doc = " * Neon instrinsic unsafe"]
15006#[inline]
15007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15009#[cfg_attr(
15010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15011 assert_instr(ld1)
15012)]
15013#[target_feature(enable = "neon,fp16")]
15014#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15015pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
15016 unsafe extern "unadjusted" {
15017 #[cfg_attr(
15018 any(target_arch = "aarch64", target_arch = "arm64ec"),
15019 link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0"
15020 )]
15021 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")]
15022 fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t;
15023 }
15024 _vld1q_f16_x3(a)
15025}
15026#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
15028#[doc = "## Safety"]
15029#[doc = " * Neon instrinsic unsafe"]
15030#[inline]
15031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15033#[cfg_attr(
15034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15035 assert_instr(ld1)
15036)]
15037#[target_feature(enable = "neon,fp16")]
15038#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15039pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
15040 unsafe extern "unadjusted" {
15041 #[cfg_attr(
15042 any(target_arch = "aarch64", target_arch = "arm64ec"),
15043 link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0"
15044 )]
15045 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")]
15046 fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t;
15047 }
15048 _vld1q_f16_x4(a)
15049}
15050#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15052#[doc = "## Safety"]
15053#[doc = " * Neon instrinsic unsafe"]
15054#[inline]
15055#[cfg(target_endian = "little")]
15056#[cfg(target_arch = "arm")]
15057#[target_feature(enable = "neon,v7")]
15058#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15060pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15061 transmute(vld1_v2f32(
15062 ptr as *const i8,
15063 crate::mem::align_of::<f32>() as i32,
15064 ))
15065}
15066#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
15068#[doc = "## Safety"]
15069#[doc = " * Neon instrinsic unsafe"]
15070#[inline]
15071#[cfg(target_endian = "big")]
15072#[cfg(target_arch = "arm")]
15073#[target_feature(enable = "neon,v7")]
15074#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15076pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
15077 let ret_val: float32x2_t = transmute(vld1_v2f32(
15078 ptr as *const i8,
15079 crate::mem::align_of::<f32>() as i32,
15080 ));
15081 simd_shuffle!(ret_val, ret_val, [1, 0])
15082}
15083#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15085#[doc = "## Safety"]
15086#[doc = " * Neon instrinsic unsafe"]
15087#[inline]
15088#[cfg(target_endian = "little")]
15089#[cfg(target_arch = "arm")]
15090#[target_feature(enable = "neon,v7")]
15091#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15092#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15093pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15094 transmute(vld1q_v4f32(
15095 ptr as *const i8,
15096 crate::mem::align_of::<f32>() as i32,
15097 ))
15098}
15099#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
15101#[doc = "## Safety"]
15102#[doc = " * Neon instrinsic unsafe"]
15103#[inline]
15104#[cfg(target_endian = "big")]
15105#[cfg(target_arch = "arm")]
15106#[target_feature(enable = "neon,v7")]
15107#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15108#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15109pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
15110 let ret_val: float32x4_t = transmute(vld1q_v4f32(
15111 ptr as *const i8,
15112 crate::mem::align_of::<f32>() as i32,
15113 ));
15114 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15115}
15116#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15118#[doc = "## Safety"]
15119#[doc = " * Neon instrinsic unsafe"]
15120#[inline]
15121#[cfg(target_endian = "little")]
15122#[cfg(target_arch = "arm")]
15123#[target_feature(enable = "neon,v7")]
15124#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15125#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15126pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15127 transmute(vld1_v8i8(
15128 ptr as *const i8,
15129 crate::mem::align_of::<u8>() as i32,
15130 ))
15131}
15132#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
15134#[doc = "## Safety"]
15135#[doc = " * Neon instrinsic unsafe"]
15136#[inline]
15137#[cfg(target_endian = "big")]
15138#[cfg(target_arch = "arm")]
15139#[target_feature(enable = "neon,v7")]
15140#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15142pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
15143 let ret_val: uint8x8_t = transmute(vld1_v8i8(
15144 ptr as *const i8,
15145 crate::mem::align_of::<u8>() as i32,
15146 ));
15147 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15148}
15149#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15151#[doc = "## Safety"]
15152#[doc = " * Neon instrinsic unsafe"]
15153#[inline]
15154#[cfg(target_endian = "little")]
15155#[cfg(target_arch = "arm")]
15156#[target_feature(enable = "neon,v7")]
15157#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15159pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15160 transmute(vld1q_v16i8(
15161 ptr as *const i8,
15162 crate::mem::align_of::<u8>() as i32,
15163 ))
15164}
15165#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
15167#[doc = "## Safety"]
15168#[doc = " * Neon instrinsic unsafe"]
15169#[inline]
15170#[cfg(target_endian = "big")]
15171#[cfg(target_arch = "arm")]
15172#[target_feature(enable = "neon,v7")]
15173#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15174#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15175pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
15176 let ret_val: uint8x16_t = transmute(vld1q_v16i8(
15177 ptr as *const i8,
15178 crate::mem::align_of::<u8>() as i32,
15179 ));
15180 simd_shuffle!(
15181 ret_val,
15182 ret_val,
15183 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15184 )
15185}
15186#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15188#[doc = "## Safety"]
15189#[doc = " * Neon instrinsic unsafe"]
15190#[inline]
15191#[cfg(target_endian = "little")]
15192#[cfg(target_arch = "arm")]
15193#[target_feature(enable = "neon,v7")]
15194#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15195#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15196pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15197 transmute(vld1_v4i16(
15198 ptr as *const i8,
15199 crate::mem::align_of::<u16>() as i32,
15200 ))
15201}
15202#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
15204#[doc = "## Safety"]
15205#[doc = " * Neon instrinsic unsafe"]
15206#[inline]
15207#[cfg(target_endian = "big")]
15208#[cfg(target_arch = "arm")]
15209#[target_feature(enable = "neon,v7")]
15210#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15211#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15212pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
15213 let ret_val: uint16x4_t = transmute(vld1_v4i16(
15214 ptr as *const i8,
15215 crate::mem::align_of::<u16>() as i32,
15216 ));
15217 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15218}
15219#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15221#[doc = "## Safety"]
15222#[doc = " * Neon instrinsic unsafe"]
15223#[inline]
15224#[cfg(target_endian = "little")]
15225#[cfg(target_arch = "arm")]
15226#[target_feature(enable = "neon,v7")]
15227#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15229pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15230 transmute(vld1q_v8i16(
15231 ptr as *const i8,
15232 crate::mem::align_of::<u16>() as i32,
15233 ))
15234}
15235#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15236#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
15237#[doc = "## Safety"]
15238#[doc = " * Neon instrinsic unsafe"]
15239#[inline]
15240#[cfg(target_endian = "big")]
15241#[cfg(target_arch = "arm")]
15242#[target_feature(enable = "neon,v7")]
15243#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15244#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15245pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
15246 let ret_val: uint16x8_t = transmute(vld1q_v8i16(
15247 ptr as *const i8,
15248 crate::mem::align_of::<u16>() as i32,
15249 ));
15250 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15251}
15252#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15254#[doc = "## Safety"]
15255#[doc = " * Neon instrinsic unsafe"]
15256#[inline]
15257#[cfg(target_endian = "little")]
15258#[cfg(target_arch = "arm")]
15259#[target_feature(enable = "neon,v7")]
15260#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15261#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15262pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15263 transmute(vld1_v2i32(
15264 ptr as *const i8,
15265 crate::mem::align_of::<u32>() as i32,
15266 ))
15267}
15268#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
15270#[doc = "## Safety"]
15271#[doc = " * Neon instrinsic unsafe"]
15272#[inline]
15273#[cfg(target_endian = "big")]
15274#[cfg(target_arch = "arm")]
15275#[target_feature(enable = "neon,v7")]
15276#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15278pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
15279 let ret_val: uint32x2_t = transmute(vld1_v2i32(
15280 ptr as *const i8,
15281 crate::mem::align_of::<u32>() as i32,
15282 ));
15283 simd_shuffle!(ret_val, ret_val, [1, 0])
15284}
15285#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15287#[doc = "## Safety"]
15288#[doc = " * Neon instrinsic unsafe"]
15289#[inline]
15290#[cfg(target_endian = "little")]
15291#[cfg(target_arch = "arm")]
15292#[target_feature(enable = "neon,v7")]
15293#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15294#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15295pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15296 transmute(vld1q_v4i32(
15297 ptr as *const i8,
15298 crate::mem::align_of::<u32>() as i32,
15299 ))
15300}
15301#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
15303#[doc = "## Safety"]
15304#[doc = " * Neon instrinsic unsafe"]
15305#[inline]
15306#[cfg(target_endian = "big")]
15307#[cfg(target_arch = "arm")]
15308#[target_feature(enable = "neon,v7")]
15309#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
15311pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
15312 let ret_val: uint32x4_t = transmute(vld1q_v4i32(
15313 ptr as *const i8,
15314 crate::mem::align_of::<u32>() as i32,
15315 ));
15316 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15317}
15318#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
15320#[doc = "## Safety"]
15321#[doc = " * Neon instrinsic unsafe"]
15322#[inline]
15323#[cfg(target_arch = "arm")]
15324#[target_feature(enable = "neon,v7")]
15325#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
15327pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
15328 transmute(vld1_v1i64(
15329 ptr as *const i8,
15330 crate::mem::align_of::<u64>() as i32,
15331 ))
15332}
15333#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15335#[doc = "## Safety"]
15336#[doc = " * Neon instrinsic unsafe"]
15337#[inline]
15338#[cfg(target_endian = "little")]
15339#[cfg(target_arch = "arm")]
15340#[target_feature(enable = "neon,v7")]
15341#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15342#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15343pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15344 transmute(vld1q_v2i64(
15345 ptr as *const i8,
15346 crate::mem::align_of::<u64>() as i32,
15347 ))
15348}
15349#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
15351#[doc = "## Safety"]
15352#[doc = " * Neon instrinsic unsafe"]
15353#[inline]
15354#[cfg(target_endian = "big")]
15355#[cfg(target_arch = "arm")]
15356#[target_feature(enable = "neon,v7")]
15357#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15358#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15359pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
15360 let ret_val: uint64x2_t = transmute(vld1q_v2i64(
15361 ptr as *const i8,
15362 crate::mem::align_of::<u64>() as i32,
15363 ));
15364 simd_shuffle!(ret_val, ret_val, [1, 0])
15365}
15366#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15368#[doc = "## Safety"]
15369#[doc = " * Neon instrinsic unsafe"]
15370#[inline]
15371#[cfg(target_endian = "little")]
15372#[cfg(target_arch = "arm")]
15373#[target_feature(enable = "neon,v7")]
15374#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15375#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15376pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15377 transmute(vld1_v8i8(
15378 ptr as *const i8,
15379 crate::mem::align_of::<p8>() as i32,
15380 ))
15381}
15382#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15383#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
15384#[doc = "## Safety"]
15385#[doc = " * Neon instrinsic unsafe"]
15386#[inline]
15387#[cfg(target_endian = "big")]
15388#[cfg(target_arch = "arm")]
15389#[target_feature(enable = "neon,v7")]
15390#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15391#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15392pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
15393 let ret_val: poly8x8_t = transmute(vld1_v8i8(
15394 ptr as *const i8,
15395 crate::mem::align_of::<p8>() as i32,
15396 ));
15397 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15398}
15399#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15401#[doc = "## Safety"]
15402#[doc = " * Neon instrinsic unsafe"]
15403#[inline]
15404#[cfg(target_endian = "little")]
15405#[cfg(target_arch = "arm")]
15406#[target_feature(enable = "neon,v7")]
15407#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15408#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15409pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15410 transmute(vld1q_v16i8(
15411 ptr as *const i8,
15412 crate::mem::align_of::<p8>() as i32,
15413 ))
15414}
15415#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
15417#[doc = "## Safety"]
15418#[doc = " * Neon instrinsic unsafe"]
15419#[inline]
15420#[cfg(target_endian = "big")]
15421#[cfg(target_arch = "arm")]
15422#[target_feature(enable = "neon,v7")]
15423#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15424#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
15425pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
15426 let ret_val: poly8x16_t = transmute(vld1q_v16i8(
15427 ptr as *const i8,
15428 crate::mem::align_of::<p8>() as i32,
15429 ));
15430 simd_shuffle!(
15431 ret_val,
15432 ret_val,
15433 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
15434 )
15435}
15436#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15438#[doc = "## Safety"]
15439#[doc = " * Neon instrinsic unsafe"]
15440#[inline]
15441#[cfg(target_endian = "little")]
15442#[cfg(target_arch = "arm")]
15443#[target_feature(enable = "neon,v7")]
15444#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15445#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15446pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15447 transmute(vld1_v4i16(
15448 ptr as *const i8,
15449 crate::mem::align_of::<p16>() as i32,
15450 ))
15451}
15452#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
15454#[doc = "## Safety"]
15455#[doc = " * Neon instrinsic unsafe"]
15456#[inline]
15457#[cfg(target_endian = "big")]
15458#[cfg(target_arch = "arm")]
15459#[target_feature(enable = "neon,v7")]
15460#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15461#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15462pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
15463 let ret_val: poly16x4_t = transmute(vld1_v4i16(
15464 ptr as *const i8,
15465 crate::mem::align_of::<p16>() as i32,
15466 ));
15467 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
15468}
15469#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15471#[doc = "## Safety"]
15472#[doc = " * Neon instrinsic unsafe"]
15473#[inline]
15474#[cfg(target_endian = "little")]
15475#[cfg(target_arch = "arm")]
15476#[target_feature(enable = "neon,v7")]
15477#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15478#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15479pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15480 transmute(vld1q_v8i16(
15481 ptr as *const i8,
15482 crate::mem::align_of::<p16>() as i32,
15483 ))
15484}
15485#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
15487#[doc = "## Safety"]
15488#[doc = " * Neon instrinsic unsafe"]
15489#[inline]
15490#[cfg(target_endian = "big")]
15491#[cfg(target_arch = "arm")]
15492#[target_feature(enable = "neon,v7")]
15493#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15494#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
15495pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
15496 let ret_val: poly16x8_t = transmute(vld1q_v8i16(
15497 ptr as *const i8,
15498 crate::mem::align_of::<p16>() as i32,
15499 ));
15500 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
15501}
15502#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15504#[doc = "## Safety"]
15505#[doc = " * Neon instrinsic unsafe"]
15506#[inline]
15507#[cfg(target_endian = "little")]
15508#[cfg(target_arch = "arm")]
15509#[target_feature(enable = "neon,aes")]
15510#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15511#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15512pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15513 transmute(vld1q_v2i64(
15514 ptr as *const i8,
15515 crate::mem::align_of::<p64>() as i32,
15516 ))
15517}
15518#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
15519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
15520#[doc = "## Safety"]
15521#[doc = " * Neon instrinsic unsafe"]
15522#[inline]
15523#[cfg(target_endian = "big")]
15524#[cfg(target_arch = "arm")]
15525#[target_feature(enable = "neon,aes")]
15526#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
15527#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
15528pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
15529 let ret_val: poly64x2_t = transmute(vld1q_v2i64(
15530 ptr as *const i8,
15531 crate::mem::align_of::<p64>() as i32,
15532 ));
15533 simd_shuffle!(ret_val, ret_val, [1, 0])
15534}
15535#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
15537#[doc = "## Safety"]
15538#[doc = " * Neon instrinsic unsafe"]
15539#[inline]
15540#[target_feature(enable = "neon")]
15541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15543#[cfg_attr(
15544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15545 assert_instr(ld1)
15546)]
15547#[cfg_attr(
15548 not(target_arch = "arm"),
15549 stable(feature = "neon_intrinsics", since = "1.59.0")
15550)]
15551#[cfg_attr(
15552 target_arch = "arm",
15553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15554)]
15555pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
15556 unsafe extern "unadjusted" {
15557 #[cfg_attr(
15558 any(target_arch = "aarch64", target_arch = "arm64ec"),
15559 link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0"
15560 )]
15561 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")]
15562 fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t;
15563 }
15564 _vld1_f32_x2(a)
15565}
15566#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
15568#[doc = "## Safety"]
15569#[doc = " * Neon instrinsic unsafe"]
15570#[inline]
15571#[target_feature(enable = "neon")]
15572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15574#[cfg_attr(
15575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15576 assert_instr(ld1)
15577)]
15578#[cfg_attr(
15579 not(target_arch = "arm"),
15580 stable(feature = "neon_intrinsics", since = "1.59.0")
15581)]
15582#[cfg_attr(
15583 target_arch = "arm",
15584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15585)]
15586pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
15587 unsafe extern "unadjusted" {
15588 #[cfg_attr(
15589 any(target_arch = "aarch64", target_arch = "arm64ec"),
15590 link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0"
15591 )]
15592 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")]
15593 fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t;
15594 }
15595 _vld1_f32_x3(a)
15596}
15597#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
15599#[doc = "## Safety"]
15600#[doc = " * Neon instrinsic unsafe"]
15601#[inline]
15602#[target_feature(enable = "neon")]
15603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15605#[cfg_attr(
15606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15607 assert_instr(ld1)
15608)]
15609#[cfg_attr(
15610 not(target_arch = "arm"),
15611 stable(feature = "neon_intrinsics", since = "1.59.0")
15612)]
15613#[cfg_attr(
15614 target_arch = "arm",
15615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15616)]
15617pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
15618 unsafe extern "unadjusted" {
15619 #[cfg_attr(
15620 any(target_arch = "aarch64", target_arch = "arm64ec"),
15621 link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0"
15622 )]
15623 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")]
15624 fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t;
15625 }
15626 _vld1_f32_x4(a)
15627}
15628#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
15630#[doc = "## Safety"]
15631#[doc = " * Neon instrinsic unsafe"]
15632#[inline]
15633#[target_feature(enable = "neon")]
15634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15636#[cfg_attr(
15637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15638 assert_instr(ld1)
15639)]
15640#[cfg_attr(
15641 not(target_arch = "arm"),
15642 stable(feature = "neon_intrinsics", since = "1.59.0")
15643)]
15644#[cfg_attr(
15645 target_arch = "arm",
15646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15647)]
15648pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
15649 unsafe extern "unadjusted" {
15650 #[cfg_attr(
15651 any(target_arch = "aarch64", target_arch = "arm64ec"),
15652 link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0"
15653 )]
15654 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")]
15655 fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t;
15656 }
15657 _vld1q_f32_x2(a)
15658}
15659#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
15661#[doc = "## Safety"]
15662#[doc = " * Neon instrinsic unsafe"]
15663#[inline]
15664#[target_feature(enable = "neon")]
15665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15667#[cfg_attr(
15668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15669 assert_instr(ld1)
15670)]
15671#[cfg_attr(
15672 not(target_arch = "arm"),
15673 stable(feature = "neon_intrinsics", since = "1.59.0")
15674)]
15675#[cfg_attr(
15676 target_arch = "arm",
15677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15678)]
15679pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
15680 unsafe extern "unadjusted" {
15681 #[cfg_attr(
15682 any(target_arch = "aarch64", target_arch = "arm64ec"),
15683 link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0"
15684 )]
15685 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")]
15686 fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t;
15687 }
15688 _vld1q_f32_x3(a)
15689}
15690#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
15691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
15692#[doc = "## Safety"]
15693#[doc = " * Neon instrinsic unsafe"]
15694#[inline]
15695#[target_feature(enable = "neon")]
15696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
15698#[cfg_attr(
15699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15700 assert_instr(ld1)
15701)]
15702#[cfg_attr(
15703 not(target_arch = "arm"),
15704 stable(feature = "neon_intrinsics", since = "1.59.0")
15705)]
15706#[cfg_attr(
15707 target_arch = "arm",
15708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15709)]
15710pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
15711 unsafe extern "unadjusted" {
15712 #[cfg_attr(
15713 any(target_arch = "aarch64", target_arch = "arm64ec"),
15714 link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0"
15715 )]
15716 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")]
15717 fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t;
15718 }
15719 _vld1q_f32_x4(a)
15720}
15721#[doc = "Load one single-element structure to one lane of one register"]
15722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
15723#[doc = "## Safety"]
15724#[doc = " * Neon instrinsic unsafe"]
15725#[inline]
15726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15728#[cfg_attr(
15729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15730 assert_instr(ld1, LANE = 0)
15731)]
15732#[rustc_legacy_const_generics(2)]
15733#[target_feature(enable = "neon,fp16")]
15734#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15735pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t) -> float16x4_t {
15736 static_assert_uimm_bits!(LANE, 2);
15737 simd_insert!(src, LANE as u32, *ptr)
15738}
15739#[doc = "Load one single-element structure to one lane of one register"]
15740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
15741#[doc = "## Safety"]
15742#[doc = " * Neon instrinsic unsafe"]
15743#[inline]
15744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
15746#[cfg_attr(
15747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15748 assert_instr(ld1, LANE = 0)
15749)]
15750#[rustc_legacy_const_generics(2)]
15751#[target_feature(enable = "neon,fp16")]
15752#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
15753pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t) -> float16x8_t {
15754 static_assert_uimm_bits!(LANE, 3);
15755 simd_insert!(src, LANE as u32, *ptr)
15756}
15757#[doc = "Load one single-element structure to one lane of one register."]
15758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
15759#[doc = "## Safety"]
15760#[doc = " * Neon instrinsic unsafe"]
15761#[inline]
15762#[target_feature(enable = "neon")]
15763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15764#[rustc_legacy_const_generics(2)]
15765#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15766#[cfg_attr(
15767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15768 assert_instr(ld1, LANE = 1)
15769)]
15770#[cfg_attr(
15771 not(target_arch = "arm"),
15772 stable(feature = "neon_intrinsics", since = "1.59.0")
15773)]
15774#[cfg_attr(
15775 target_arch = "arm",
15776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15777)]
15778pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t) -> float32x2_t {
15779 static_assert_uimm_bits!(LANE, 1);
15780 simd_insert!(src, LANE as u32, *ptr)
15781}
15782#[doc = "Load one single-element structure to one lane of one register."]
15783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
15784#[doc = "## Safety"]
15785#[doc = " * Neon instrinsic unsafe"]
15786#[inline]
15787#[target_feature(enable = "neon")]
15788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15789#[rustc_legacy_const_generics(2)]
15790#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15791#[cfg_attr(
15792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15793 assert_instr(ld1, LANE = 3)
15794)]
15795#[cfg_attr(
15796 not(target_arch = "arm"),
15797 stable(feature = "neon_intrinsics", since = "1.59.0")
15798)]
15799#[cfg_attr(
15800 target_arch = "arm",
15801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15802)]
15803pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -> poly16x4_t {
15804 static_assert_uimm_bits!(LANE, 2);
15805 simd_insert!(src, LANE as u32, *ptr)
15806}
15807#[doc = "Load one single-element structure to one lane of one register."]
15808#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
15809#[doc = "## Safety"]
15810#[doc = " * Neon instrinsic unsafe"]
15811#[inline]
15812#[target_feature(enable = "neon")]
15813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15814#[rustc_legacy_const_generics(2)]
15815#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15816#[cfg_attr(
15817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15818 assert_instr(ld1, LANE = 7)
15819)]
15820#[cfg_attr(
15821 not(target_arch = "arm"),
15822 stable(feature = "neon_intrinsics", since = "1.59.0")
15823)]
15824#[cfg_attr(
15825 target_arch = "arm",
15826 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15827)]
15828pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> poly8x8_t {
15829 static_assert_uimm_bits!(LANE, 3);
15830 simd_insert!(src, LANE as u32, *ptr)
15831}
15832#[doc = "Load one single-element structure to one lane of one register."]
15833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
15834#[doc = "## Safety"]
15835#[doc = " * Neon instrinsic unsafe"]
15836#[inline]
15837#[target_feature(enable = "neon")]
15838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15839#[rustc_legacy_const_generics(2)]
15840#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15841#[cfg_attr(
15842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15843 assert_instr(ld1, LANE = 3)
15844)]
15845#[cfg_attr(
15846 not(target_arch = "arm"),
15847 stable(feature = "neon_intrinsics", since = "1.59.0")
15848)]
15849#[cfg_attr(
15850 target_arch = "arm",
15851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15852)]
15853pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) -> int16x4_t {
15854 static_assert_uimm_bits!(LANE, 2);
15855 simd_insert!(src, LANE as u32, *ptr)
15856}
15857#[doc = "Load one single-element structure to one lane of one register."]
15858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
15859#[doc = "## Safety"]
15860#[doc = " * Neon instrinsic unsafe"]
15861#[inline]
15862#[target_feature(enable = "neon")]
15863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15864#[rustc_legacy_const_generics(2)]
15865#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15866#[cfg_attr(
15867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15868 assert_instr(ld1, LANE = 1)
15869)]
15870#[cfg_attr(
15871 not(target_arch = "arm"),
15872 stable(feature = "neon_intrinsics", since = "1.59.0")
15873)]
15874#[cfg_attr(
15875 target_arch = "arm",
15876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15877)]
15878pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) -> int32x2_t {
15879 static_assert_uimm_bits!(LANE, 1);
15880 simd_insert!(src, LANE as u32, *ptr)
15881}
15882#[doc = "Load one single-element structure to one lane of one register."]
15883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
15884#[doc = "## Safety"]
15885#[doc = " * Neon instrinsic unsafe"]
15886#[inline]
15887#[target_feature(enable = "neon")]
15888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15889#[rustc_legacy_const_generics(2)]
15890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
15891#[cfg_attr(
15892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15893 assert_instr(ldr, LANE = 0)
15894)]
15895#[cfg_attr(
15896 not(target_arch = "arm"),
15897 stable(feature = "neon_intrinsics", since = "1.59.0")
15898)]
15899#[cfg_attr(
15900 target_arch = "arm",
15901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15902)]
15903pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
15904 static_assert!(LANE == 0);
15905 simd_insert!(src, LANE as u32, *ptr)
15906}
15907#[doc = "Load one single-element structure to one lane of one register."]
15908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
15909#[doc = "## Safety"]
15910#[doc = " * Neon instrinsic unsafe"]
15911#[inline]
15912#[target_feature(enable = "neon")]
15913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15914#[rustc_legacy_const_generics(2)]
15915#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
15916#[cfg_attr(
15917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15918 assert_instr(ld1, LANE = 7)
15919)]
15920#[cfg_attr(
15921 not(target_arch = "arm"),
15922 stable(feature = "neon_intrinsics", since = "1.59.0")
15923)]
15924#[cfg_attr(
15925 target_arch = "arm",
15926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15927)]
15928pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> int8x8_t {
15929 static_assert_uimm_bits!(LANE, 3);
15930 simd_insert!(src, LANE as u32, *ptr)
15931}
15932#[doc = "Load one single-element structure to one lane of one register."]
15933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
15934#[doc = "## Safety"]
15935#[doc = " * Neon instrinsic unsafe"]
15936#[inline]
15937#[target_feature(enable = "neon")]
15938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15939#[rustc_legacy_const_generics(2)]
15940#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 3))]
15941#[cfg_attr(
15942 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15943 assert_instr(ld1, LANE = 3)
15944)]
15945#[cfg_attr(
15946 not(target_arch = "arm"),
15947 stable(feature = "neon_intrinsics", since = "1.59.0")
15948)]
15949#[cfg_attr(
15950 target_arch = "arm",
15951 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15952)]
15953pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -> uint16x4_t {
15954 static_assert_uimm_bits!(LANE, 2);
15955 simd_insert!(src, LANE as u32, *ptr)
15956}
15957#[doc = "Load one single-element structure to one lane of one register."]
15958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
15959#[doc = "## Safety"]
15960#[doc = " * Neon instrinsic unsafe"]
15961#[inline]
15962#[target_feature(enable = "neon")]
15963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15964#[rustc_legacy_const_generics(2)]
15965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 1))]
15966#[cfg_attr(
15967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15968 assert_instr(ld1, LANE = 1)
15969)]
15970#[cfg_attr(
15971 not(target_arch = "arm"),
15972 stable(feature = "neon_intrinsics", since = "1.59.0")
15973)]
15974#[cfg_attr(
15975 target_arch = "arm",
15976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
15977)]
15978pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -> uint32x2_t {
15979 static_assert_uimm_bits!(LANE, 1);
15980 simd_insert!(src, LANE as u32, *ptr)
15981}
15982#[doc = "Load one single-element structure to one lane of one register."]
15983#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
15984#[doc = "## Safety"]
15985#[doc = " * Neon instrinsic unsafe"]
15986#[inline]
15987#[target_feature(enable = "neon")]
15988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
15989#[rustc_legacy_const_generics(2)]
15990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
15991#[cfg_attr(
15992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
15993 assert_instr(ldr, LANE = 0)
15994)]
15995#[cfg_attr(
15996 not(target_arch = "arm"),
15997 stable(feature = "neon_intrinsics", since = "1.59.0")
15998)]
15999#[cfg_attr(
16000 target_arch = "arm",
16001 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16002)]
16003pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
16004 static_assert!(LANE == 0);
16005 simd_insert!(src, LANE as u32, *ptr)
16006}
16007#[doc = "Load one single-element structure to one lane of one register."]
16008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
16009#[doc = "## Safety"]
16010#[doc = " * Neon instrinsic unsafe"]
16011#[inline]
16012#[target_feature(enable = "neon")]
16013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16014#[rustc_legacy_const_generics(2)]
16015#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 7))]
16016#[cfg_attr(
16017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16018 assert_instr(ld1, LANE = 7)
16019)]
16020#[cfg_attr(
16021 not(target_arch = "arm"),
16022 stable(feature = "neon_intrinsics", since = "1.59.0")
16023)]
16024#[cfg_attr(
16025 target_arch = "arm",
16026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16027)]
16028pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> uint8x8_t {
16029 static_assert_uimm_bits!(LANE, 3);
16030 simd_insert!(src, LANE as u32, *ptr)
16031}
16032#[doc = "Load one single-element structure to one lane of one register."]
16033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
16034#[doc = "## Safety"]
16035#[doc = " * Neon instrinsic unsafe"]
16036#[inline]
16037#[target_feature(enable = "neon")]
16038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16039#[rustc_legacy_const_generics(2)]
16040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16041#[cfg_attr(
16042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16043 assert_instr(ld1, LANE = 3)
16044)]
16045#[cfg_attr(
16046 not(target_arch = "arm"),
16047 stable(feature = "neon_intrinsics", since = "1.59.0")
16048)]
16049#[cfg_attr(
16050 target_arch = "arm",
16051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16052)]
16053pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t) -> float32x4_t {
16054 static_assert_uimm_bits!(LANE, 2);
16055 simd_insert!(src, LANE as u32, *ptr)
16056}
16057#[doc = "Load one single-element structure to one lane of one register."]
16058#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
16059#[doc = "## Safety"]
16060#[doc = " * Neon instrinsic unsafe"]
16061#[inline]
16062#[target_feature(enable = "neon")]
16063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16064#[rustc_legacy_const_generics(2)]
16065#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16066#[cfg_attr(
16067 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16068 assert_instr(ld1, LANE = 7)
16069)]
16070#[cfg_attr(
16071 not(target_arch = "arm"),
16072 stable(feature = "neon_intrinsics", since = "1.59.0")
16073)]
16074#[cfg_attr(
16075 target_arch = "arm",
16076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16077)]
16078pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t) -> poly16x8_t {
16079 static_assert_uimm_bits!(LANE, 3);
16080 simd_insert!(src, LANE as u32, *ptr)
16081}
16082#[doc = "Load one single-element structure to one lane of one register."]
16083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
16084#[doc = "## Safety"]
16085#[doc = " * Neon instrinsic unsafe"]
16086#[inline]
16087#[target_feature(enable = "neon")]
16088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16089#[rustc_legacy_const_generics(2)]
16090#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16091#[cfg_attr(
16092 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16093 assert_instr(ld1, LANE = 15)
16094)]
16095#[cfg_attr(
16096 not(target_arch = "arm"),
16097 stable(feature = "neon_intrinsics", since = "1.59.0")
16098)]
16099#[cfg_attr(
16100 target_arch = "arm",
16101 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16102)]
16103pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) -> poly8x16_t {
16104 static_assert_uimm_bits!(LANE, 4);
16105 simd_insert!(src, LANE as u32, *ptr)
16106}
16107#[doc = "Load one single-element structure to one lane of one register."]
16108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
16109#[doc = "## Safety"]
16110#[doc = " * Neon instrinsic unsafe"]
16111#[inline]
16112#[target_feature(enable = "neon")]
16113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16114#[rustc_legacy_const_generics(2)]
16115#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16116#[cfg_attr(
16117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16118 assert_instr(ld1, LANE = 7)
16119)]
16120#[cfg_attr(
16121 not(target_arch = "arm"),
16122 stable(feature = "neon_intrinsics", since = "1.59.0")
16123)]
16124#[cfg_attr(
16125 target_arch = "arm",
16126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16127)]
16128pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -> int16x8_t {
16129 static_assert_uimm_bits!(LANE, 3);
16130 simd_insert!(src, LANE as u32, *ptr)
16131}
16132#[doc = "Load one single-element structure to one lane of one register."]
16133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
16134#[doc = "## Safety"]
16135#[doc = " * Neon instrinsic unsafe"]
16136#[inline]
16137#[target_feature(enable = "neon")]
16138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16139#[rustc_legacy_const_generics(2)]
16140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16141#[cfg_attr(
16142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16143 assert_instr(ld1, LANE = 3)
16144)]
16145#[cfg_attr(
16146 not(target_arch = "arm"),
16147 stable(feature = "neon_intrinsics", since = "1.59.0")
16148)]
16149#[cfg_attr(
16150 target_arch = "arm",
16151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16152)]
16153pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -> int32x4_t {
16154 static_assert_uimm_bits!(LANE, 2);
16155 simd_insert!(src, LANE as u32, *ptr)
16156}
16157#[doc = "Load one single-element structure to one lane of one register."]
16158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
16159#[doc = "## Safety"]
16160#[doc = " * Neon instrinsic unsafe"]
16161#[inline]
16162#[target_feature(enable = "neon")]
16163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16164#[rustc_legacy_const_generics(2)]
16165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16166#[cfg_attr(
16167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16168 assert_instr(ld1, LANE = 1)
16169)]
16170#[cfg_attr(
16171 not(target_arch = "arm"),
16172 stable(feature = "neon_intrinsics", since = "1.59.0")
16173)]
16174#[cfg_attr(
16175 target_arch = "arm",
16176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16177)]
16178pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
16179 static_assert_uimm_bits!(LANE, 1);
16180 simd_insert!(src, LANE as u32, *ptr)
16181}
16182#[doc = "Load one single-element structure to one lane of one register."]
16183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
16184#[doc = "## Safety"]
16185#[doc = " * Neon instrinsic unsafe"]
16186#[inline]
16187#[target_feature(enable = "neon")]
16188#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16189#[rustc_legacy_const_generics(2)]
16190#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16191#[cfg_attr(
16192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16193 assert_instr(ld1, LANE = 15)
16194)]
16195#[cfg_attr(
16196 not(target_arch = "arm"),
16197 stable(feature = "neon_intrinsics", since = "1.59.0")
16198)]
16199#[cfg_attr(
16200 target_arch = "arm",
16201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16202)]
16203pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) -> int8x16_t {
16204 static_assert_uimm_bits!(LANE, 4);
16205 simd_insert!(src, LANE as u32, *ptr)
16206}
16207#[doc = "Load one single-element structure to one lane of one register."]
16208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
16209#[doc = "## Safety"]
16210#[doc = " * Neon instrinsic unsafe"]
16211#[inline]
16212#[target_feature(enable = "neon")]
16213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16214#[rustc_legacy_const_generics(2)]
16215#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16", LANE = 7))]
16216#[cfg_attr(
16217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16218 assert_instr(ld1, LANE = 7)
16219)]
16220#[cfg_attr(
16221 not(target_arch = "arm"),
16222 stable(feature = "neon_intrinsics", since = "1.59.0")
16223)]
16224#[cfg_attr(
16225 target_arch = "arm",
16226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16227)]
16228pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t) -> uint16x8_t {
16229 static_assert_uimm_bits!(LANE, 3);
16230 simd_insert!(src, LANE as u32, *ptr)
16231}
16232#[doc = "Load one single-element structure to one lane of one register."]
16233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
16234#[doc = "## Safety"]
16235#[doc = " * Neon instrinsic unsafe"]
16236#[inline]
16237#[target_feature(enable = "neon")]
16238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16239#[rustc_legacy_const_generics(2)]
16240#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32", LANE = 3))]
16241#[cfg_attr(
16242 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16243 assert_instr(ld1, LANE = 3)
16244)]
16245#[cfg_attr(
16246 not(target_arch = "arm"),
16247 stable(feature = "neon_intrinsics", since = "1.59.0")
16248)]
16249#[cfg_attr(
16250 target_arch = "arm",
16251 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16252)]
16253pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t) -> uint32x4_t {
16254 static_assert_uimm_bits!(LANE, 2);
16255 simd_insert!(src, LANE as u32, *ptr)
16256}
16257#[doc = "Load one single-element structure to one lane of one register."]
16258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
16259#[doc = "## Safety"]
16260#[doc = " * Neon instrinsic unsafe"]
16261#[inline]
16262#[target_feature(enable = "neon")]
16263#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16264#[rustc_legacy_const_generics(2)]
16265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16266#[cfg_attr(
16267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16268 assert_instr(ld1, LANE = 1)
16269)]
16270#[cfg_attr(
16271 not(target_arch = "arm"),
16272 stable(feature = "neon_intrinsics", since = "1.59.0")
16273)]
16274#[cfg_attr(
16275 target_arch = "arm",
16276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16277)]
16278pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
16279 static_assert_uimm_bits!(LANE, 1);
16280 simd_insert!(src, LANE as u32, *ptr)
16281}
16282#[doc = "Load one single-element structure to one lane of one register."]
16283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
16284#[doc = "## Safety"]
16285#[doc = " * Neon instrinsic unsafe"]
16286#[inline]
16287#[target_feature(enable = "neon")]
16288#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16289#[rustc_legacy_const_generics(2)]
16290#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8", LANE = 15))]
16291#[cfg_attr(
16292 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16293 assert_instr(ld1, LANE = 15)
16294)]
16295#[cfg_attr(
16296 not(target_arch = "arm"),
16297 stable(feature = "neon_intrinsics", since = "1.59.0")
16298)]
16299#[cfg_attr(
16300 target_arch = "arm",
16301 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16302)]
16303pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) -> uint8x16_t {
16304 static_assert_uimm_bits!(LANE, 4);
16305 simd_insert!(src, LANE as u32, *ptr)
16306}
16307#[doc = "Load one single-element structure to one lane of one register."]
16308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
16309#[doc = "## Safety"]
16310#[doc = " * Neon instrinsic unsafe"]
16311#[inline]
16312#[target_feature(enable = "neon,aes")]
16313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16314#[rustc_legacy_const_generics(2)]
16315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))]
16316#[cfg_attr(
16317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16318 assert_instr(ldr, LANE = 0)
16319)]
16320#[cfg_attr(
16321 not(target_arch = "arm"),
16322 stable(feature = "neon_intrinsics", since = "1.59.0")
16323)]
16324#[cfg_attr(
16325 target_arch = "arm",
16326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16327)]
16328pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
16329 static_assert!(LANE == 0);
16330 simd_insert!(src, LANE as u32, *ptr)
16331}
16332#[doc = "Load one single-element structure to one lane of one register."]
16333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
16334#[doc = "## Safety"]
16335#[doc = " * Neon instrinsic unsafe"]
16336#[inline]
16337#[target_feature(enable = "neon,aes")]
16338#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16339#[rustc_legacy_const_generics(2)]
16340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))]
16341#[cfg_attr(
16342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16343 assert_instr(ld1, LANE = 1)
16344)]
16345#[cfg_attr(
16346 not(target_arch = "arm"),
16347 stable(feature = "neon_intrinsics", since = "1.59.0")
16348)]
16349#[cfg_attr(
16350 target_arch = "arm",
16351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16352)]
16353pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
16354 static_assert_uimm_bits!(LANE, 1);
16355 simd_insert!(src, LANE as u32, *ptr)
16356}
16357#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
16359#[doc = "## Safety"]
16360#[doc = " * Neon instrinsic unsafe"]
16361#[inline]
16362#[cfg(target_arch = "arm")]
16363#[target_feature(enable = "neon,aes")]
16364#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16366pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
16367 let a: *const i8 = ptr as *const i8;
16368 let b: i32 = crate::mem::align_of::<p64>() as i32;
16369 unsafe extern "unadjusted" {
16370 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
16371 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
16372 }
16373 transmute(_vld1_v1i64(a, b))
16374}
16375#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
16377#[doc = "## Safety"]
16378#[doc = " * Neon instrinsic unsafe"]
16379#[inline]
16380#[target_feature(enable = "neon,aes")]
16381#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16383#[cfg_attr(
16384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16385 assert_instr(ld1)
16386)]
16387#[cfg_attr(
16388 not(target_arch = "arm"),
16389 stable(feature = "neon_intrinsics", since = "1.59.0")
16390)]
16391#[cfg_attr(
16392 target_arch = "arm",
16393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16394)]
16395pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
16396 transmute(vld1_s64_x2(transmute(a)))
16397}
16398#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
16400#[doc = "## Safety"]
16401#[doc = " * Neon instrinsic unsafe"]
16402#[inline]
16403#[target_feature(enable = "neon,aes")]
16404#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16405#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16406#[cfg_attr(
16407 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16408 assert_instr(ld1)
16409)]
16410#[cfg_attr(
16411 not(target_arch = "arm"),
16412 stable(feature = "neon_intrinsics", since = "1.59.0")
16413)]
16414#[cfg_attr(
16415 target_arch = "arm",
16416 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16417)]
16418pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
16419 transmute(vld1_s64_x3(transmute(a)))
16420}
16421#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16422#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
16423#[doc = "## Safety"]
16424#[doc = " * Neon instrinsic unsafe"]
16425#[inline]
16426#[target_feature(enable = "neon,aes")]
16427#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16429#[cfg_attr(
16430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16431 assert_instr(ld1)
16432)]
16433#[cfg_attr(
16434 not(target_arch = "arm"),
16435 stable(feature = "neon_intrinsics", since = "1.59.0")
16436)]
16437#[cfg_attr(
16438 target_arch = "arm",
16439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16440)]
16441pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
16442 transmute(vld1_s64_x4(transmute(a)))
16443}
16444#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16446#[doc = "## Safety"]
16447#[doc = " * Neon instrinsic unsafe"]
16448#[inline]
16449#[cfg(target_endian = "little")]
16450#[target_feature(enable = "neon,aes")]
16451#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16453#[cfg_attr(
16454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16455 assert_instr(ld1)
16456)]
16457#[cfg_attr(
16458 not(target_arch = "arm"),
16459 stable(feature = "neon_intrinsics", since = "1.59.0")
16460)]
16461#[cfg_attr(
16462 target_arch = "arm",
16463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16464)]
16465pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16466 transmute(vld1q_s64_x2(transmute(a)))
16467}
16468#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
16470#[doc = "## Safety"]
16471#[doc = " * Neon instrinsic unsafe"]
16472#[inline]
16473#[cfg(target_endian = "big")]
16474#[target_feature(enable = "neon,aes")]
16475#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16477#[cfg_attr(
16478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16479 assert_instr(ld1)
16480)]
16481#[cfg_attr(
16482 not(target_arch = "arm"),
16483 stable(feature = "neon_intrinsics", since = "1.59.0")
16484)]
16485#[cfg_attr(
16486 target_arch = "arm",
16487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16488)]
16489pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
16490 let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
16491 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16492 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16493 ret_val
16494}
16495#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16497#[doc = "## Safety"]
16498#[doc = " * Neon instrinsic unsafe"]
16499#[inline]
16500#[cfg(target_endian = "little")]
16501#[target_feature(enable = "neon,aes")]
16502#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16504#[cfg_attr(
16505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16506 assert_instr(ld1)
16507)]
16508#[cfg_attr(
16509 not(target_arch = "arm"),
16510 stable(feature = "neon_intrinsics", since = "1.59.0")
16511)]
16512#[cfg_attr(
16513 target_arch = "arm",
16514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16515)]
16516pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16517 transmute(vld1q_s64_x3(transmute(a)))
16518}
16519#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
16521#[doc = "## Safety"]
16522#[doc = " * Neon instrinsic unsafe"]
16523#[inline]
16524#[cfg(target_endian = "big")]
16525#[target_feature(enable = "neon,aes")]
16526#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16528#[cfg_attr(
16529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16530 assert_instr(ld1)
16531)]
16532#[cfg_attr(
16533 not(target_arch = "arm"),
16534 stable(feature = "neon_intrinsics", since = "1.59.0")
16535)]
16536#[cfg_attr(
16537 target_arch = "arm",
16538 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16539)]
16540pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
16541 let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
16542 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16543 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16544 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16545 ret_val
16546}
16547#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16549#[doc = "## Safety"]
16550#[doc = " * Neon instrinsic unsafe"]
16551#[inline]
16552#[cfg(target_endian = "little")]
16553#[target_feature(enable = "neon,aes")]
16554#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16556#[cfg_attr(
16557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16558 assert_instr(ld1)
16559)]
16560#[cfg_attr(
16561 not(target_arch = "arm"),
16562 stable(feature = "neon_intrinsics", since = "1.59.0")
16563)]
16564#[cfg_attr(
16565 target_arch = "arm",
16566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16567)]
16568pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16569 transmute(vld1q_s64_x4(transmute(a)))
16570}
16571#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
16573#[doc = "## Safety"]
16574#[doc = " * Neon instrinsic unsafe"]
16575#[inline]
16576#[cfg(target_endian = "big")]
16577#[target_feature(enable = "neon,aes")]
16578#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
16579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
16580#[cfg_attr(
16581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16582 assert_instr(ld1)
16583)]
16584#[cfg_attr(
16585 not(target_arch = "arm"),
16586 stable(feature = "neon_intrinsics", since = "1.59.0")
16587)]
16588#[cfg_attr(
16589 target_arch = "arm",
16590 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16591)]
16592pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
16593 let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
16594 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
16595 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
16596 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
16597 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
16598 ret_val
16599}
16600#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
16602#[doc = "## Safety"]
16603#[doc = " * Neon instrinsic unsafe"]
16604#[inline]
16605#[cfg(target_arch = "arm")]
16606#[target_feature(enable = "neon,v7")]
16607#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16608#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16609pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
16610 vld1_v8i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16611}
16612#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
16614#[doc = "## Safety"]
16615#[doc = " * Neon instrinsic unsafe"]
16616#[inline]
16617#[cfg(target_arch = "arm")]
16618#[target_feature(enable = "neon,v7")]
16619#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16620#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
16621pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
16622 vld1q_v16i8(ptr as *const i8, crate::mem::align_of::<i8>() as i32)
16623}
16624#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
16626#[doc = "## Safety"]
16627#[doc = " * Neon instrinsic unsafe"]
16628#[inline]
16629#[cfg(target_arch = "arm")]
16630#[target_feature(enable = "neon,v7")]
16631#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16632#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16633pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
16634 vld1_v4i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16635}
16636#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
16638#[doc = "## Safety"]
16639#[doc = " * Neon instrinsic unsafe"]
16640#[inline]
16641#[cfg(target_arch = "arm")]
16642#[target_feature(enable = "neon,v7")]
16643#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16644#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
16645pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
16646 vld1q_v8i16(ptr as *const i8, crate::mem::align_of::<i16>() as i32)
16647}
16648#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
16650#[doc = "## Safety"]
16651#[doc = " * Neon instrinsic unsafe"]
16652#[inline]
16653#[cfg(target_arch = "arm")]
16654#[target_feature(enable = "neon,v7")]
16655#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16657pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
16658 vld1_v2i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16659}
16660#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16661#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
16662#[doc = "## Safety"]
16663#[doc = " * Neon instrinsic unsafe"]
16664#[inline]
16665#[cfg(target_arch = "arm")]
16666#[target_feature(enable = "neon,v7")]
16667#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16668#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
16669pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
16670 vld1q_v4i32(ptr as *const i8, crate::mem::align_of::<i32>() as i32)
16671}
16672#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
16674#[doc = "## Safety"]
16675#[doc = " * Neon instrinsic unsafe"]
16676#[inline]
16677#[cfg(target_arch = "arm")]
16678#[target_feature(enable = "neon,v7")]
16679#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16680#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
16681pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
16682 vld1_v1i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16683}
16684#[doc = "Load multiple single-element structures to one, two, three, or four registers."]
16685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
16686#[doc = "## Safety"]
16687#[doc = " * Neon instrinsic unsafe"]
16688#[inline]
16689#[cfg(target_arch = "arm")]
16690#[target_feature(enable = "neon,v7")]
16691#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
16692#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))]
16693pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
16694 vld1q_v2i64(ptr as *const i8, crate::mem::align_of::<i64>() as i32)
16695}
16696#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
16698#[doc = "## Safety"]
16699#[doc = " * Neon instrinsic unsafe"]
16700#[inline]
16701#[target_feature(enable = "neon")]
16702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16704#[cfg_attr(
16705 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16706 assert_instr(ld1)
16707)]
16708#[cfg_attr(
16709 not(target_arch = "arm"),
16710 stable(feature = "neon_intrinsics", since = "1.59.0")
16711)]
16712#[cfg_attr(
16713 target_arch = "arm",
16714 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16715)]
16716pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
16717 unsafe extern "unadjusted" {
16718 #[cfg_attr(
16719 any(target_arch = "aarch64", target_arch = "arm64ec"),
16720 link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0"
16721 )]
16722 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")]
16723 fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t;
16724 }
16725 _vld1_s8_x2(a)
16726}
16727#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
16729#[doc = "## Safety"]
16730#[doc = " * Neon instrinsic unsafe"]
16731#[inline]
16732#[target_feature(enable = "neon")]
16733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16735#[cfg_attr(
16736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16737 assert_instr(ld1)
16738)]
16739#[cfg_attr(
16740 not(target_arch = "arm"),
16741 stable(feature = "neon_intrinsics", since = "1.59.0")
16742)]
16743#[cfg_attr(
16744 target_arch = "arm",
16745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16746)]
16747pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
16748 unsafe extern "unadjusted" {
16749 #[cfg_attr(
16750 any(target_arch = "aarch64", target_arch = "arm64ec"),
16751 link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0"
16752 )]
16753 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")]
16754 fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t;
16755 }
16756 _vld1_s8_x3(a)
16757}
16758#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
16760#[doc = "## Safety"]
16761#[doc = " * Neon instrinsic unsafe"]
16762#[inline]
16763#[target_feature(enable = "neon")]
16764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16766#[cfg_attr(
16767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16768 assert_instr(ld1)
16769)]
16770#[cfg_attr(
16771 not(target_arch = "arm"),
16772 stable(feature = "neon_intrinsics", since = "1.59.0")
16773)]
16774#[cfg_attr(
16775 target_arch = "arm",
16776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16777)]
16778pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
16779 unsafe extern "unadjusted" {
16780 #[cfg_attr(
16781 any(target_arch = "aarch64", target_arch = "arm64ec"),
16782 link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0"
16783 )]
16784 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")]
16785 fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t;
16786 }
16787 _vld1_s8_x4(a)
16788}
16789#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
16791#[doc = "## Safety"]
16792#[doc = " * Neon instrinsic unsafe"]
16793#[inline]
16794#[target_feature(enable = "neon")]
16795#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16796#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16797#[cfg_attr(
16798 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16799 assert_instr(ld1)
16800)]
16801#[cfg_attr(
16802 not(target_arch = "arm"),
16803 stable(feature = "neon_intrinsics", since = "1.59.0")
16804)]
16805#[cfg_attr(
16806 target_arch = "arm",
16807 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16808)]
16809pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
16810 unsafe extern "unadjusted" {
16811 #[cfg_attr(
16812 any(target_arch = "aarch64", target_arch = "arm64ec"),
16813 link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0"
16814 )]
16815 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")]
16816 fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t;
16817 }
16818 _vld1q_s8_x2(a)
16819}
16820#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
16822#[doc = "## Safety"]
16823#[doc = " * Neon instrinsic unsafe"]
16824#[inline]
16825#[target_feature(enable = "neon")]
16826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16828#[cfg_attr(
16829 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16830 assert_instr(ld1)
16831)]
16832#[cfg_attr(
16833 not(target_arch = "arm"),
16834 stable(feature = "neon_intrinsics", since = "1.59.0")
16835)]
16836#[cfg_attr(
16837 target_arch = "arm",
16838 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16839)]
16840pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
16841 unsafe extern "unadjusted" {
16842 #[cfg_attr(
16843 any(target_arch = "aarch64", target_arch = "arm64ec"),
16844 link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0"
16845 )]
16846 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")]
16847 fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t;
16848 }
16849 _vld1q_s8_x3(a)
16850}
16851#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
16853#[doc = "## Safety"]
16854#[doc = " * Neon instrinsic unsafe"]
16855#[inline]
16856#[target_feature(enable = "neon")]
16857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16858#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16859#[cfg_attr(
16860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16861 assert_instr(ld1)
16862)]
16863#[cfg_attr(
16864 not(target_arch = "arm"),
16865 stable(feature = "neon_intrinsics", since = "1.59.0")
16866)]
16867#[cfg_attr(
16868 target_arch = "arm",
16869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16870)]
16871pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
16872 unsafe extern "unadjusted" {
16873 #[cfg_attr(
16874 any(target_arch = "aarch64", target_arch = "arm64ec"),
16875 link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0"
16876 )]
16877 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")]
16878 fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t;
16879 }
16880 _vld1q_s8_x4(a)
16881}
16882#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
16884#[doc = "## Safety"]
16885#[doc = " * Neon instrinsic unsafe"]
16886#[inline]
16887#[target_feature(enable = "neon")]
16888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16890#[cfg_attr(
16891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16892 assert_instr(ld1)
16893)]
16894#[cfg_attr(
16895 not(target_arch = "arm"),
16896 stable(feature = "neon_intrinsics", since = "1.59.0")
16897)]
16898#[cfg_attr(
16899 target_arch = "arm",
16900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16901)]
16902pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
16903 unsafe extern "unadjusted" {
16904 #[cfg_attr(
16905 any(target_arch = "aarch64", target_arch = "arm64ec"),
16906 link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0"
16907 )]
16908 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")]
16909 fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t;
16910 }
16911 _vld1_s16_x2(a)
16912}
16913#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
16915#[doc = "## Safety"]
16916#[doc = " * Neon instrinsic unsafe"]
16917#[inline]
16918#[target_feature(enable = "neon")]
16919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16921#[cfg_attr(
16922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16923 assert_instr(ld1)
16924)]
16925#[cfg_attr(
16926 not(target_arch = "arm"),
16927 stable(feature = "neon_intrinsics", since = "1.59.0")
16928)]
16929#[cfg_attr(
16930 target_arch = "arm",
16931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16932)]
16933pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
16934 unsafe extern "unadjusted" {
16935 #[cfg_attr(
16936 any(target_arch = "aarch64", target_arch = "arm64ec"),
16937 link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0"
16938 )]
16939 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")]
16940 fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t;
16941 }
16942 _vld1_s16_x3(a)
16943}
16944#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
16946#[doc = "## Safety"]
16947#[doc = " * Neon instrinsic unsafe"]
16948#[inline]
16949#[target_feature(enable = "neon")]
16950#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16951#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16952#[cfg_attr(
16953 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16954 assert_instr(ld1)
16955)]
16956#[cfg_attr(
16957 not(target_arch = "arm"),
16958 stable(feature = "neon_intrinsics", since = "1.59.0")
16959)]
16960#[cfg_attr(
16961 target_arch = "arm",
16962 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16963)]
16964pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
16965 unsafe extern "unadjusted" {
16966 #[cfg_attr(
16967 any(target_arch = "aarch64", target_arch = "arm64ec"),
16968 link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0"
16969 )]
16970 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")]
16971 fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t;
16972 }
16973 _vld1_s16_x4(a)
16974}
16975#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
16976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
16977#[doc = "## Safety"]
16978#[doc = " * Neon instrinsic unsafe"]
16979#[inline]
16980#[target_feature(enable = "neon")]
16981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
16982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
16983#[cfg_attr(
16984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
16985 assert_instr(ld1)
16986)]
16987#[cfg_attr(
16988 not(target_arch = "arm"),
16989 stable(feature = "neon_intrinsics", since = "1.59.0")
16990)]
16991#[cfg_attr(
16992 target_arch = "arm",
16993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
16994)]
16995pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
16996 unsafe extern "unadjusted" {
16997 #[cfg_attr(
16998 any(target_arch = "aarch64", target_arch = "arm64ec"),
16999 link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0"
17000 )]
17001 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")]
17002 fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t;
17003 }
17004 _vld1q_s16_x2(a)
17005}
17006#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
17008#[doc = "## Safety"]
17009#[doc = " * Neon instrinsic unsafe"]
17010#[inline]
17011#[target_feature(enable = "neon")]
17012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17014#[cfg_attr(
17015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17016 assert_instr(ld1)
17017)]
17018#[cfg_attr(
17019 not(target_arch = "arm"),
17020 stable(feature = "neon_intrinsics", since = "1.59.0")
17021)]
17022#[cfg_attr(
17023 target_arch = "arm",
17024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17025)]
17026pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
17027 unsafe extern "unadjusted" {
17028 #[cfg_attr(
17029 any(target_arch = "aarch64", target_arch = "arm64ec"),
17030 link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0"
17031 )]
17032 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")]
17033 fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t;
17034 }
17035 _vld1q_s16_x3(a)
17036}
17037#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
17039#[doc = "## Safety"]
17040#[doc = " * Neon instrinsic unsafe"]
17041#[inline]
17042#[target_feature(enable = "neon")]
17043#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17044#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17045#[cfg_attr(
17046 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17047 assert_instr(ld1)
17048)]
17049#[cfg_attr(
17050 not(target_arch = "arm"),
17051 stable(feature = "neon_intrinsics", since = "1.59.0")
17052)]
17053#[cfg_attr(
17054 target_arch = "arm",
17055 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17056)]
17057pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
17058 unsafe extern "unadjusted" {
17059 #[cfg_attr(
17060 any(target_arch = "aarch64", target_arch = "arm64ec"),
17061 link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0"
17062 )]
17063 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")]
17064 fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t;
17065 }
17066 _vld1q_s16_x4(a)
17067}
17068#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
17070#[doc = "## Safety"]
17071#[doc = " * Neon instrinsic unsafe"]
17072#[inline]
17073#[target_feature(enable = "neon")]
17074#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17075#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17076#[cfg_attr(
17077 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17078 assert_instr(ld1)
17079)]
17080#[cfg_attr(
17081 not(target_arch = "arm"),
17082 stable(feature = "neon_intrinsics", since = "1.59.0")
17083)]
17084#[cfg_attr(
17085 target_arch = "arm",
17086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17087)]
17088pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
17089 unsafe extern "unadjusted" {
17090 #[cfg_attr(
17091 any(target_arch = "aarch64", target_arch = "arm64ec"),
17092 link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0"
17093 )]
17094 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")]
17095 fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t;
17096 }
17097 _vld1_s32_x2(a)
17098}
17099#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
17101#[doc = "## Safety"]
17102#[doc = " * Neon instrinsic unsafe"]
17103#[inline]
17104#[target_feature(enable = "neon")]
17105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17106#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17107#[cfg_attr(
17108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17109 assert_instr(ld1)
17110)]
17111#[cfg_attr(
17112 not(target_arch = "arm"),
17113 stable(feature = "neon_intrinsics", since = "1.59.0")
17114)]
17115#[cfg_attr(
17116 target_arch = "arm",
17117 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17118)]
17119pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
17120 unsafe extern "unadjusted" {
17121 #[cfg_attr(
17122 any(target_arch = "aarch64", target_arch = "arm64ec"),
17123 link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0"
17124 )]
17125 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")]
17126 fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t;
17127 }
17128 _vld1_s32_x3(a)
17129}
17130#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
17132#[doc = "## Safety"]
17133#[doc = " * Neon instrinsic unsafe"]
17134#[inline]
17135#[target_feature(enable = "neon")]
17136#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17137#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17138#[cfg_attr(
17139 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17140 assert_instr(ld1)
17141)]
17142#[cfg_attr(
17143 not(target_arch = "arm"),
17144 stable(feature = "neon_intrinsics", since = "1.59.0")
17145)]
17146#[cfg_attr(
17147 target_arch = "arm",
17148 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17149)]
17150pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
17151 unsafe extern "unadjusted" {
17152 #[cfg_attr(
17153 any(target_arch = "aarch64", target_arch = "arm64ec"),
17154 link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0"
17155 )]
17156 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")]
17157 fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t;
17158 }
17159 _vld1_s32_x4(a)
17160}
17161#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
17163#[doc = "## Safety"]
17164#[doc = " * Neon instrinsic unsafe"]
17165#[inline]
17166#[target_feature(enable = "neon")]
17167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17169#[cfg_attr(
17170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17171 assert_instr(ld1)
17172)]
17173#[cfg_attr(
17174 not(target_arch = "arm"),
17175 stable(feature = "neon_intrinsics", since = "1.59.0")
17176)]
17177#[cfg_attr(
17178 target_arch = "arm",
17179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17180)]
17181pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
17182 unsafe extern "unadjusted" {
17183 #[cfg_attr(
17184 any(target_arch = "aarch64", target_arch = "arm64ec"),
17185 link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0"
17186 )]
17187 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")]
17188 fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t;
17189 }
17190 _vld1q_s32_x2(a)
17191}
17192#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
17194#[doc = "## Safety"]
17195#[doc = " * Neon instrinsic unsafe"]
17196#[inline]
17197#[target_feature(enable = "neon")]
17198#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17199#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17200#[cfg_attr(
17201 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17202 assert_instr(ld1)
17203)]
17204#[cfg_attr(
17205 not(target_arch = "arm"),
17206 stable(feature = "neon_intrinsics", since = "1.59.0")
17207)]
17208#[cfg_attr(
17209 target_arch = "arm",
17210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17211)]
17212pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
17213 unsafe extern "unadjusted" {
17214 #[cfg_attr(
17215 any(target_arch = "aarch64", target_arch = "arm64ec"),
17216 link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0"
17217 )]
17218 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")]
17219 fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t;
17220 }
17221 _vld1q_s32_x3(a)
17222}
17223#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
17225#[doc = "## Safety"]
17226#[doc = " * Neon instrinsic unsafe"]
17227#[inline]
17228#[target_feature(enable = "neon")]
17229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17231#[cfg_attr(
17232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17233 assert_instr(ld1)
17234)]
17235#[cfg_attr(
17236 not(target_arch = "arm"),
17237 stable(feature = "neon_intrinsics", since = "1.59.0")
17238)]
17239#[cfg_attr(
17240 target_arch = "arm",
17241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17242)]
17243pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
17244 unsafe extern "unadjusted" {
17245 #[cfg_attr(
17246 any(target_arch = "aarch64", target_arch = "arm64ec"),
17247 link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0"
17248 )]
17249 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")]
17250 fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t;
17251 }
17252 _vld1q_s32_x4(a)
17253}
17254#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
17256#[doc = "## Safety"]
17257#[doc = " * Neon instrinsic unsafe"]
17258#[inline]
17259#[target_feature(enable = "neon")]
17260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17261#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17262#[cfg_attr(
17263 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17264 assert_instr(ld1)
17265)]
17266#[cfg_attr(
17267 not(target_arch = "arm"),
17268 stable(feature = "neon_intrinsics", since = "1.59.0")
17269)]
17270#[cfg_attr(
17271 target_arch = "arm",
17272 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17273)]
17274pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
17275 unsafe extern "unadjusted" {
17276 #[cfg_attr(
17277 any(target_arch = "aarch64", target_arch = "arm64ec"),
17278 link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0"
17279 )]
17280 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")]
17281 fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t;
17282 }
17283 _vld1_s64_x2(a)
17284}
17285#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17286#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
17287#[doc = "## Safety"]
17288#[doc = " * Neon instrinsic unsafe"]
17289#[inline]
17290#[target_feature(enable = "neon")]
17291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17293#[cfg_attr(
17294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17295 assert_instr(ld1)
17296)]
17297#[cfg_attr(
17298 not(target_arch = "arm"),
17299 stable(feature = "neon_intrinsics", since = "1.59.0")
17300)]
17301#[cfg_attr(
17302 target_arch = "arm",
17303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17304)]
17305pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
17306 unsafe extern "unadjusted" {
17307 #[cfg_attr(
17308 any(target_arch = "aarch64", target_arch = "arm64ec"),
17309 link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0"
17310 )]
17311 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")]
17312 fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t;
17313 }
17314 _vld1_s64_x3(a)
17315}
17316#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17317#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
17318#[doc = "## Safety"]
17319#[doc = " * Neon instrinsic unsafe"]
17320#[inline]
17321#[target_feature(enable = "neon")]
17322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17324#[cfg_attr(
17325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17326 assert_instr(ld1)
17327)]
17328#[cfg_attr(
17329 not(target_arch = "arm"),
17330 stable(feature = "neon_intrinsics", since = "1.59.0")
17331)]
17332#[cfg_attr(
17333 target_arch = "arm",
17334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17335)]
17336pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
17337 unsafe extern "unadjusted" {
17338 #[cfg_attr(
17339 any(target_arch = "aarch64", target_arch = "arm64ec"),
17340 link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0"
17341 )]
17342 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")]
17343 fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t;
17344 }
17345 _vld1_s64_x4(a)
17346}
17347#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17348#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
17349#[doc = "## Safety"]
17350#[doc = " * Neon instrinsic unsafe"]
17351#[inline]
17352#[target_feature(enable = "neon")]
17353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17355#[cfg_attr(
17356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17357 assert_instr(ld1)
17358)]
17359#[cfg_attr(
17360 not(target_arch = "arm"),
17361 stable(feature = "neon_intrinsics", since = "1.59.0")
17362)]
17363#[cfg_attr(
17364 target_arch = "arm",
17365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17366)]
17367pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
17368 unsafe extern "unadjusted" {
17369 #[cfg_attr(
17370 any(target_arch = "aarch64", target_arch = "arm64ec"),
17371 link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0"
17372 )]
17373 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")]
17374 fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t;
17375 }
17376 _vld1q_s64_x2(a)
17377}
17378#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
17380#[doc = "## Safety"]
17381#[doc = " * Neon instrinsic unsafe"]
17382#[inline]
17383#[target_feature(enable = "neon")]
17384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17386#[cfg_attr(
17387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17388 assert_instr(ld1)
17389)]
17390#[cfg_attr(
17391 not(target_arch = "arm"),
17392 stable(feature = "neon_intrinsics", since = "1.59.0")
17393)]
17394#[cfg_attr(
17395 target_arch = "arm",
17396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17397)]
17398pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
17399 unsafe extern "unadjusted" {
17400 #[cfg_attr(
17401 any(target_arch = "aarch64", target_arch = "arm64ec"),
17402 link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0"
17403 )]
17404 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")]
17405 fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t;
17406 }
17407 _vld1q_s64_x3(a)
17408}
17409#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
17411#[doc = "## Safety"]
17412#[doc = " * Neon instrinsic unsafe"]
17413#[inline]
17414#[target_feature(enable = "neon")]
17415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17417#[cfg_attr(
17418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17419 assert_instr(ld1)
17420)]
17421#[cfg_attr(
17422 not(target_arch = "arm"),
17423 stable(feature = "neon_intrinsics", since = "1.59.0")
17424)]
17425#[cfg_attr(
17426 target_arch = "arm",
17427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17428)]
17429pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
17430 unsafe extern "unadjusted" {
17431 #[cfg_attr(
17432 any(target_arch = "aarch64", target_arch = "arm64ec"),
17433 link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0"
17434 )]
17435 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")]
17436 fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t;
17437 }
17438 _vld1q_s64_x4(a)
17439}
17440#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17441#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17442#[doc = "## Safety"]
17443#[doc = " * Neon instrinsic unsafe"]
17444#[inline]
17445#[cfg(target_endian = "little")]
17446#[target_feature(enable = "neon")]
17447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17449#[cfg_attr(
17450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17451 assert_instr(ld1)
17452)]
17453#[cfg_attr(
17454 not(target_arch = "arm"),
17455 stable(feature = "neon_intrinsics", since = "1.59.0")
17456)]
17457#[cfg_attr(
17458 target_arch = "arm",
17459 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17460)]
17461pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17462 transmute(vld1_s8_x2(transmute(a)))
17463}
17464#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
17466#[doc = "## Safety"]
17467#[doc = " * Neon instrinsic unsafe"]
17468#[inline]
17469#[cfg(target_endian = "big")]
17470#[target_feature(enable = "neon")]
17471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17473#[cfg_attr(
17474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17475 assert_instr(ld1)
17476)]
17477#[cfg_attr(
17478 not(target_arch = "arm"),
17479 stable(feature = "neon_intrinsics", since = "1.59.0")
17480)]
17481#[cfg_attr(
17482 target_arch = "arm",
17483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17484)]
17485pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
17486 let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
17487 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17488 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17489 ret_val
17490}
17491#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17493#[doc = "## Safety"]
17494#[doc = " * Neon instrinsic unsafe"]
17495#[inline]
17496#[cfg(target_endian = "little")]
17497#[target_feature(enable = "neon")]
17498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17499#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17500#[cfg_attr(
17501 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17502 assert_instr(ld1)
17503)]
17504#[cfg_attr(
17505 not(target_arch = "arm"),
17506 stable(feature = "neon_intrinsics", since = "1.59.0")
17507)]
17508#[cfg_attr(
17509 target_arch = "arm",
17510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17511)]
17512pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17513 transmute(vld1_s8_x3(transmute(a)))
17514}
17515#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
17517#[doc = "## Safety"]
17518#[doc = " * Neon instrinsic unsafe"]
17519#[inline]
17520#[cfg(target_endian = "big")]
17521#[target_feature(enable = "neon")]
17522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17524#[cfg_attr(
17525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17526 assert_instr(ld1)
17527)]
17528#[cfg_attr(
17529 not(target_arch = "arm"),
17530 stable(feature = "neon_intrinsics", since = "1.59.0")
17531)]
17532#[cfg_attr(
17533 target_arch = "arm",
17534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17535)]
17536pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
17537 let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
17538 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17539 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17540 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17541 ret_val
17542}
17543#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17545#[doc = "## Safety"]
17546#[doc = " * Neon instrinsic unsafe"]
17547#[inline]
17548#[cfg(target_endian = "little")]
17549#[target_feature(enable = "neon")]
17550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17552#[cfg_attr(
17553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17554 assert_instr(ld1)
17555)]
17556#[cfg_attr(
17557 not(target_arch = "arm"),
17558 stable(feature = "neon_intrinsics", since = "1.59.0")
17559)]
17560#[cfg_attr(
17561 target_arch = "arm",
17562 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17563)]
17564pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17565 transmute(vld1_s8_x4(transmute(a)))
17566}
17567#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
17569#[doc = "## Safety"]
17570#[doc = " * Neon instrinsic unsafe"]
17571#[inline]
17572#[cfg(target_endian = "big")]
17573#[target_feature(enable = "neon")]
17574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17576#[cfg_attr(
17577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17578 assert_instr(ld1)
17579)]
17580#[cfg_attr(
17581 not(target_arch = "arm"),
17582 stable(feature = "neon_intrinsics", since = "1.59.0")
17583)]
17584#[cfg_attr(
17585 target_arch = "arm",
17586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17587)]
17588pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
17589 let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
17590 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
17591 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
17592 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
17593 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
17594 ret_val
17595}
17596#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17598#[doc = "## Safety"]
17599#[doc = " * Neon instrinsic unsafe"]
17600#[inline]
17601#[cfg(target_endian = "little")]
17602#[target_feature(enable = "neon")]
17603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17605#[cfg_attr(
17606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17607 assert_instr(ld1)
17608)]
17609#[cfg_attr(
17610 not(target_arch = "arm"),
17611 stable(feature = "neon_intrinsics", since = "1.59.0")
17612)]
17613#[cfg_attr(
17614 target_arch = "arm",
17615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17616)]
17617pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17618 transmute(vld1q_s8_x2(transmute(a)))
17619}
17620#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
17622#[doc = "## Safety"]
17623#[doc = " * Neon instrinsic unsafe"]
17624#[inline]
17625#[cfg(target_endian = "big")]
17626#[target_feature(enable = "neon")]
17627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17629#[cfg_attr(
17630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17631 assert_instr(ld1)
17632)]
17633#[cfg_attr(
17634 not(target_arch = "arm"),
17635 stable(feature = "neon_intrinsics", since = "1.59.0")
17636)]
17637#[cfg_attr(
17638 target_arch = "arm",
17639 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17640)]
17641pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
17642 let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
17643 ret_val.0 = unsafe {
17644 simd_shuffle!(
17645 ret_val.0,
17646 ret_val.0,
17647 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17648 )
17649 };
17650 ret_val.1 = unsafe {
17651 simd_shuffle!(
17652 ret_val.1,
17653 ret_val.1,
17654 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17655 )
17656 };
17657 ret_val
17658}
17659#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17661#[doc = "## Safety"]
17662#[doc = " * Neon instrinsic unsafe"]
17663#[inline]
17664#[cfg(target_endian = "little")]
17665#[target_feature(enable = "neon")]
17666#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17667#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17668#[cfg_attr(
17669 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17670 assert_instr(ld1)
17671)]
17672#[cfg_attr(
17673 not(target_arch = "arm"),
17674 stable(feature = "neon_intrinsics", since = "1.59.0")
17675)]
17676#[cfg_attr(
17677 target_arch = "arm",
17678 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17679)]
17680pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17681 transmute(vld1q_s8_x3(transmute(a)))
17682}
17683#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
17685#[doc = "## Safety"]
17686#[doc = " * Neon instrinsic unsafe"]
17687#[inline]
17688#[cfg(target_endian = "big")]
17689#[target_feature(enable = "neon")]
17690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17692#[cfg_attr(
17693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17694 assert_instr(ld1)
17695)]
17696#[cfg_attr(
17697 not(target_arch = "arm"),
17698 stable(feature = "neon_intrinsics", since = "1.59.0")
17699)]
17700#[cfg_attr(
17701 target_arch = "arm",
17702 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17703)]
17704pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
17705 let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
17706 ret_val.0 = unsafe {
17707 simd_shuffle!(
17708 ret_val.0,
17709 ret_val.0,
17710 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17711 )
17712 };
17713 ret_val.1 = unsafe {
17714 simd_shuffle!(
17715 ret_val.1,
17716 ret_val.1,
17717 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17718 )
17719 };
17720 ret_val.2 = unsafe {
17721 simd_shuffle!(
17722 ret_val.2,
17723 ret_val.2,
17724 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17725 )
17726 };
17727 ret_val
17728}
17729#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17731#[doc = "## Safety"]
17732#[doc = " * Neon instrinsic unsafe"]
17733#[inline]
17734#[cfg(target_endian = "little")]
17735#[target_feature(enable = "neon")]
17736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17737#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17738#[cfg_attr(
17739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17740 assert_instr(ld1)
17741)]
17742#[cfg_attr(
17743 not(target_arch = "arm"),
17744 stable(feature = "neon_intrinsics", since = "1.59.0")
17745)]
17746#[cfg_attr(
17747 target_arch = "arm",
17748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17749)]
17750pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17751 transmute(vld1q_s8_x4(transmute(a)))
17752}
17753#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
17755#[doc = "## Safety"]
17756#[doc = " * Neon instrinsic unsafe"]
17757#[inline]
17758#[cfg(target_endian = "big")]
17759#[target_feature(enable = "neon")]
17760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17762#[cfg_attr(
17763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17764 assert_instr(ld1)
17765)]
17766#[cfg_attr(
17767 not(target_arch = "arm"),
17768 stable(feature = "neon_intrinsics", since = "1.59.0")
17769)]
17770#[cfg_attr(
17771 target_arch = "arm",
17772 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17773)]
17774pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
17775 let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
17776 ret_val.0 = unsafe {
17777 simd_shuffle!(
17778 ret_val.0,
17779 ret_val.0,
17780 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17781 )
17782 };
17783 ret_val.1 = unsafe {
17784 simd_shuffle!(
17785 ret_val.1,
17786 ret_val.1,
17787 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17788 )
17789 };
17790 ret_val.2 = unsafe {
17791 simd_shuffle!(
17792 ret_val.2,
17793 ret_val.2,
17794 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17795 )
17796 };
17797 ret_val.3 = unsafe {
17798 simd_shuffle!(
17799 ret_val.3,
17800 ret_val.3,
17801 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
17802 )
17803 };
17804 ret_val
17805}
17806#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17808#[doc = "## Safety"]
17809#[doc = " * Neon instrinsic unsafe"]
17810#[inline]
17811#[cfg(target_endian = "little")]
17812#[target_feature(enable = "neon")]
17813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17815#[cfg_attr(
17816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17817 assert_instr(ld1)
17818)]
17819#[cfg_attr(
17820 not(target_arch = "arm"),
17821 stable(feature = "neon_intrinsics", since = "1.59.0")
17822)]
17823#[cfg_attr(
17824 target_arch = "arm",
17825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17826)]
17827pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17828 transmute(vld1_s16_x2(transmute(a)))
17829}
17830#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
17832#[doc = "## Safety"]
17833#[doc = " * Neon instrinsic unsafe"]
17834#[inline]
17835#[cfg(target_endian = "big")]
17836#[target_feature(enable = "neon")]
17837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17839#[cfg_attr(
17840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17841 assert_instr(ld1)
17842)]
17843#[cfg_attr(
17844 not(target_arch = "arm"),
17845 stable(feature = "neon_intrinsics", since = "1.59.0")
17846)]
17847#[cfg_attr(
17848 target_arch = "arm",
17849 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17850)]
17851pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
17852 let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
17853 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17854 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17855 ret_val
17856}
17857#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17858#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17859#[doc = "## Safety"]
17860#[doc = " * Neon instrinsic unsafe"]
17861#[inline]
17862#[cfg(target_endian = "little")]
17863#[target_feature(enable = "neon")]
17864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17866#[cfg_attr(
17867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17868 assert_instr(ld1)
17869)]
17870#[cfg_attr(
17871 not(target_arch = "arm"),
17872 stable(feature = "neon_intrinsics", since = "1.59.0")
17873)]
17874#[cfg_attr(
17875 target_arch = "arm",
17876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17877)]
17878pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
17879 transmute(vld1_s16_x3(transmute(a)))
17880}
17881#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
17883#[doc = "## Safety"]
17884#[doc = " * Neon instrinsic unsafe"]
17885#[inline]
17886#[cfg(target_endian = "big")]
17887#[target_feature(enable = "neon")]
17888#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17889#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17890#[cfg_attr(
17891 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17892 assert_instr(ld1)
17893)]
17894#[cfg_attr(
17895 not(target_arch = "arm"),
17896 stable(feature = "neon_intrinsics", since = "1.59.0")
17897)]
17898#[cfg_attr(
17899 target_arch = "arm",
17900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17901)]
17902pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
17903 let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
17904 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17905 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17906 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
17907 ret_val
17908}
17909#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
17911#[doc = "## Safety"]
17912#[doc = " * Neon instrinsic unsafe"]
17913#[inline]
17914#[cfg(target_endian = "little")]
17915#[target_feature(enable = "neon")]
17916#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17917#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17918#[cfg_attr(
17919 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17920 assert_instr(ld1)
17921)]
17922#[cfg_attr(
17923 not(target_arch = "arm"),
17924 stable(feature = "neon_intrinsics", since = "1.59.0")
17925)]
17926#[cfg_attr(
17927 target_arch = "arm",
17928 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17929)]
17930pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
17931 transmute(vld1_s16_x4(transmute(a)))
17932}
17933#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
17935#[doc = "## Safety"]
17936#[doc = " * Neon instrinsic unsafe"]
17937#[inline]
17938#[cfg(target_endian = "big")]
17939#[target_feature(enable = "neon")]
17940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17942#[cfg_attr(
17943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17944 assert_instr(ld1)
17945)]
17946#[cfg_attr(
17947 not(target_arch = "arm"),
17948 stable(feature = "neon_intrinsics", since = "1.59.0")
17949)]
17950#[cfg_attr(
17951 target_arch = "arm",
17952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17953)]
17954pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
17955 let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
17956 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
17957 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
17958 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
17959 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
17960 ret_val
17961}
17962#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
17964#[doc = "## Safety"]
17965#[doc = " * Neon instrinsic unsafe"]
17966#[inline]
17967#[cfg(target_endian = "little")]
17968#[target_feature(enable = "neon")]
17969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17971#[cfg_attr(
17972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17973 assert_instr(ld1)
17974)]
17975#[cfg_attr(
17976 not(target_arch = "arm"),
17977 stable(feature = "neon_intrinsics", since = "1.59.0")
17978)]
17979#[cfg_attr(
17980 target_arch = "arm",
17981 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
17982)]
17983pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
17984 transmute(vld1q_s16_x2(transmute(a)))
17985}
17986#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
17987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
17988#[doc = "## Safety"]
17989#[doc = " * Neon instrinsic unsafe"]
17990#[inline]
17991#[cfg(target_endian = "big")]
17992#[target_feature(enable = "neon")]
17993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
17994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
17995#[cfg_attr(
17996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
17997 assert_instr(ld1)
17998)]
17999#[cfg_attr(
18000 not(target_arch = "arm"),
18001 stable(feature = "neon_intrinsics", since = "1.59.0")
18002)]
18003#[cfg_attr(
18004 target_arch = "arm",
18005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18006)]
18007pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
18008 let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
18009 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18010 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18011 ret_val
18012}
18013#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18015#[doc = "## Safety"]
18016#[doc = " * Neon instrinsic unsafe"]
18017#[inline]
18018#[cfg(target_endian = "little")]
18019#[target_feature(enable = "neon")]
18020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18022#[cfg_attr(
18023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18024 assert_instr(ld1)
18025)]
18026#[cfg_attr(
18027 not(target_arch = "arm"),
18028 stable(feature = "neon_intrinsics", since = "1.59.0")
18029)]
18030#[cfg_attr(
18031 target_arch = "arm",
18032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18033)]
18034pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18035 transmute(vld1q_s16_x3(transmute(a)))
18036}
18037#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
18039#[doc = "## Safety"]
18040#[doc = " * Neon instrinsic unsafe"]
18041#[inline]
18042#[cfg(target_endian = "big")]
18043#[target_feature(enable = "neon")]
18044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18046#[cfg_attr(
18047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18048 assert_instr(ld1)
18049)]
18050#[cfg_attr(
18051 not(target_arch = "arm"),
18052 stable(feature = "neon_intrinsics", since = "1.59.0")
18053)]
18054#[cfg_attr(
18055 target_arch = "arm",
18056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18057)]
18058pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
18059 let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
18060 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18061 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18062 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18063 ret_val
18064}
18065#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18067#[doc = "## Safety"]
18068#[doc = " * Neon instrinsic unsafe"]
18069#[inline]
18070#[cfg(target_endian = "little")]
18071#[target_feature(enable = "neon")]
18072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18074#[cfg_attr(
18075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18076 assert_instr(ld1)
18077)]
18078#[cfg_attr(
18079 not(target_arch = "arm"),
18080 stable(feature = "neon_intrinsics", since = "1.59.0")
18081)]
18082#[cfg_attr(
18083 target_arch = "arm",
18084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18085)]
18086pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18087 transmute(vld1q_s16_x4(transmute(a)))
18088}
18089#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
18091#[doc = "## Safety"]
18092#[doc = " * Neon instrinsic unsafe"]
18093#[inline]
18094#[cfg(target_endian = "big")]
18095#[target_feature(enable = "neon")]
18096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18098#[cfg_attr(
18099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18100 assert_instr(ld1)
18101)]
18102#[cfg_attr(
18103 not(target_arch = "arm"),
18104 stable(feature = "neon_intrinsics", since = "1.59.0")
18105)]
18106#[cfg_attr(
18107 target_arch = "arm",
18108 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18109)]
18110pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
18111 let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
18112 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18113 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18114 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18115 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18116 ret_val
18117}
18118#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18120#[doc = "## Safety"]
18121#[doc = " * Neon instrinsic unsafe"]
18122#[inline]
18123#[cfg(target_endian = "little")]
18124#[target_feature(enable = "neon")]
18125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18127#[cfg_attr(
18128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18129 assert_instr(ld1)
18130)]
18131#[cfg_attr(
18132 not(target_arch = "arm"),
18133 stable(feature = "neon_intrinsics", since = "1.59.0")
18134)]
18135#[cfg_attr(
18136 target_arch = "arm",
18137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18138)]
18139pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18140 transmute(vld1_s32_x2(transmute(a)))
18141}
18142#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
18144#[doc = "## Safety"]
18145#[doc = " * Neon instrinsic unsafe"]
18146#[inline]
18147#[cfg(target_endian = "big")]
18148#[target_feature(enable = "neon")]
18149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18151#[cfg_attr(
18152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18153 assert_instr(ld1)
18154)]
18155#[cfg_attr(
18156 not(target_arch = "arm"),
18157 stable(feature = "neon_intrinsics", since = "1.59.0")
18158)]
18159#[cfg_attr(
18160 target_arch = "arm",
18161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18162)]
18163pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
18164 let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a)));
18165 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18166 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18167 ret_val
18168}
18169#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18171#[doc = "## Safety"]
18172#[doc = " * Neon instrinsic unsafe"]
18173#[inline]
18174#[cfg(target_endian = "little")]
18175#[target_feature(enable = "neon")]
18176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18178#[cfg_attr(
18179 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18180 assert_instr(ld1)
18181)]
18182#[cfg_attr(
18183 not(target_arch = "arm"),
18184 stable(feature = "neon_intrinsics", since = "1.59.0")
18185)]
18186#[cfg_attr(
18187 target_arch = "arm",
18188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18189)]
18190pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18191 transmute(vld1_s32_x3(transmute(a)))
18192}
18193#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
18195#[doc = "## Safety"]
18196#[doc = " * Neon instrinsic unsafe"]
18197#[inline]
18198#[cfg(target_endian = "big")]
18199#[target_feature(enable = "neon")]
18200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18201#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18202#[cfg_attr(
18203 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18204 assert_instr(ld1)
18205)]
18206#[cfg_attr(
18207 not(target_arch = "arm"),
18208 stable(feature = "neon_intrinsics", since = "1.59.0")
18209)]
18210#[cfg_attr(
18211 target_arch = "arm",
18212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18213)]
18214pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
18215 let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a)));
18216 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18217 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18218 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18219 ret_val
18220}
18221#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18223#[doc = "## Safety"]
18224#[doc = " * Neon instrinsic unsafe"]
18225#[inline]
18226#[cfg(target_endian = "little")]
18227#[target_feature(enable = "neon")]
18228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18230#[cfg_attr(
18231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18232 assert_instr(ld1)
18233)]
18234#[cfg_attr(
18235 not(target_arch = "arm"),
18236 stable(feature = "neon_intrinsics", since = "1.59.0")
18237)]
18238#[cfg_attr(
18239 target_arch = "arm",
18240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18241)]
18242pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18243 transmute(vld1_s32_x4(transmute(a)))
18244}
18245#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
18247#[doc = "## Safety"]
18248#[doc = " * Neon instrinsic unsafe"]
18249#[inline]
18250#[cfg(target_endian = "big")]
18251#[target_feature(enable = "neon")]
18252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18254#[cfg_attr(
18255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18256 assert_instr(ld1)
18257)]
18258#[cfg_attr(
18259 not(target_arch = "arm"),
18260 stable(feature = "neon_intrinsics", since = "1.59.0")
18261)]
18262#[cfg_attr(
18263 target_arch = "arm",
18264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18265)]
18266pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
18267 let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a)));
18268 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18269 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18270 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18271 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18272 ret_val
18273}
18274#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18276#[doc = "## Safety"]
18277#[doc = " * Neon instrinsic unsafe"]
18278#[inline]
18279#[cfg(target_endian = "little")]
18280#[target_feature(enable = "neon")]
18281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18283#[cfg_attr(
18284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18285 assert_instr(ld1)
18286)]
18287#[cfg_attr(
18288 not(target_arch = "arm"),
18289 stable(feature = "neon_intrinsics", since = "1.59.0")
18290)]
18291#[cfg_attr(
18292 target_arch = "arm",
18293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18294)]
18295pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18296 transmute(vld1q_s32_x2(transmute(a)))
18297}
18298#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
18300#[doc = "## Safety"]
18301#[doc = " * Neon instrinsic unsafe"]
18302#[inline]
18303#[cfg(target_endian = "big")]
18304#[target_feature(enable = "neon")]
18305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18307#[cfg_attr(
18308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18309 assert_instr(ld1)
18310)]
18311#[cfg_attr(
18312 not(target_arch = "arm"),
18313 stable(feature = "neon_intrinsics", since = "1.59.0")
18314)]
18315#[cfg_attr(
18316 target_arch = "arm",
18317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18318)]
18319pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
18320 let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a)));
18321 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18322 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18323 ret_val
18324}
18325#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18327#[doc = "## Safety"]
18328#[doc = " * Neon instrinsic unsafe"]
18329#[inline]
18330#[cfg(target_endian = "little")]
18331#[target_feature(enable = "neon")]
18332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18334#[cfg_attr(
18335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18336 assert_instr(ld1)
18337)]
18338#[cfg_attr(
18339 not(target_arch = "arm"),
18340 stable(feature = "neon_intrinsics", since = "1.59.0")
18341)]
18342#[cfg_attr(
18343 target_arch = "arm",
18344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18345)]
18346pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18347 transmute(vld1q_s32_x3(transmute(a)))
18348}
18349#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
18351#[doc = "## Safety"]
18352#[doc = " * Neon instrinsic unsafe"]
18353#[inline]
18354#[cfg(target_endian = "big")]
18355#[target_feature(enable = "neon")]
18356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18358#[cfg_attr(
18359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18360 assert_instr(ld1)
18361)]
18362#[cfg_attr(
18363 not(target_arch = "arm"),
18364 stable(feature = "neon_intrinsics", since = "1.59.0")
18365)]
18366#[cfg_attr(
18367 target_arch = "arm",
18368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18369)]
18370pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
18371 let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a)));
18372 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18373 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18374 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18375 ret_val
18376}
18377#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18379#[doc = "## Safety"]
18380#[doc = " * Neon instrinsic unsafe"]
18381#[inline]
18382#[cfg(target_endian = "little")]
18383#[target_feature(enable = "neon")]
18384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18386#[cfg_attr(
18387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18388 assert_instr(ld1)
18389)]
18390#[cfg_attr(
18391 not(target_arch = "arm"),
18392 stable(feature = "neon_intrinsics", since = "1.59.0")
18393)]
18394#[cfg_attr(
18395 target_arch = "arm",
18396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18397)]
18398pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18399 transmute(vld1q_s32_x4(transmute(a)))
18400}
18401#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
18403#[doc = "## Safety"]
18404#[doc = " * Neon instrinsic unsafe"]
18405#[inline]
18406#[cfg(target_endian = "big")]
18407#[target_feature(enable = "neon")]
18408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18409#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18410#[cfg_attr(
18411 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18412 assert_instr(ld1)
18413)]
18414#[cfg_attr(
18415 not(target_arch = "arm"),
18416 stable(feature = "neon_intrinsics", since = "1.59.0")
18417)]
18418#[cfg_attr(
18419 target_arch = "arm",
18420 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18421)]
18422pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
18423 let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a)));
18424 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
18425 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
18426 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
18427 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
18428 ret_val
18429}
18430#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
18432#[doc = "## Safety"]
18433#[doc = " * Neon instrinsic unsafe"]
18434#[inline]
18435#[target_feature(enable = "neon")]
18436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18438#[cfg_attr(
18439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18440 assert_instr(ld1)
18441)]
18442#[cfg_attr(
18443 not(target_arch = "arm"),
18444 stable(feature = "neon_intrinsics", since = "1.59.0")
18445)]
18446#[cfg_attr(
18447 target_arch = "arm",
18448 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18449)]
18450pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
18451 transmute(vld1_s64_x2(transmute(a)))
18452}
18453#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
18455#[doc = "## Safety"]
18456#[doc = " * Neon instrinsic unsafe"]
18457#[inline]
18458#[target_feature(enable = "neon")]
18459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18461#[cfg_attr(
18462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18463 assert_instr(ld1)
18464)]
18465#[cfg_attr(
18466 not(target_arch = "arm"),
18467 stable(feature = "neon_intrinsics", since = "1.59.0")
18468)]
18469#[cfg_attr(
18470 target_arch = "arm",
18471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18472)]
18473pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
18474 transmute(vld1_s64_x3(transmute(a)))
18475}
18476#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
18478#[doc = "## Safety"]
18479#[doc = " * Neon instrinsic unsafe"]
18480#[inline]
18481#[target_feature(enable = "neon")]
18482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18484#[cfg_attr(
18485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18486 assert_instr(ld1)
18487)]
18488#[cfg_attr(
18489 not(target_arch = "arm"),
18490 stable(feature = "neon_intrinsics", since = "1.59.0")
18491)]
18492#[cfg_attr(
18493 target_arch = "arm",
18494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18495)]
18496pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
18497 transmute(vld1_s64_x4(transmute(a)))
18498}
18499#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18501#[doc = "## Safety"]
18502#[doc = " * Neon instrinsic unsafe"]
18503#[inline]
18504#[cfg(target_endian = "little")]
18505#[target_feature(enable = "neon")]
18506#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18508#[cfg_attr(
18509 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18510 assert_instr(ld1)
18511)]
18512#[cfg_attr(
18513 not(target_arch = "arm"),
18514 stable(feature = "neon_intrinsics", since = "1.59.0")
18515)]
18516#[cfg_attr(
18517 target_arch = "arm",
18518 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18519)]
18520pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18521 transmute(vld1q_s64_x2(transmute(a)))
18522}
18523#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
18525#[doc = "## Safety"]
18526#[doc = " * Neon instrinsic unsafe"]
18527#[inline]
18528#[cfg(target_endian = "big")]
18529#[target_feature(enable = "neon")]
18530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18532#[cfg_attr(
18533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18534 assert_instr(ld1)
18535)]
18536#[cfg_attr(
18537 not(target_arch = "arm"),
18538 stable(feature = "neon_intrinsics", since = "1.59.0")
18539)]
18540#[cfg_attr(
18541 target_arch = "arm",
18542 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18543)]
18544pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
18545 let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a)));
18546 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18547 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18548 ret_val
18549}
18550#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18552#[doc = "## Safety"]
18553#[doc = " * Neon instrinsic unsafe"]
18554#[inline]
18555#[cfg(target_endian = "little")]
18556#[target_feature(enable = "neon")]
18557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18559#[cfg_attr(
18560 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18561 assert_instr(ld1)
18562)]
18563#[cfg_attr(
18564 not(target_arch = "arm"),
18565 stable(feature = "neon_intrinsics", since = "1.59.0")
18566)]
18567#[cfg_attr(
18568 target_arch = "arm",
18569 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18570)]
18571pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18572 transmute(vld1q_s64_x3(transmute(a)))
18573}
18574#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
18576#[doc = "## Safety"]
18577#[doc = " * Neon instrinsic unsafe"]
18578#[inline]
18579#[cfg(target_endian = "big")]
18580#[target_feature(enable = "neon")]
18581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18583#[cfg_attr(
18584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18585 assert_instr(ld1)
18586)]
18587#[cfg_attr(
18588 not(target_arch = "arm"),
18589 stable(feature = "neon_intrinsics", since = "1.59.0")
18590)]
18591#[cfg_attr(
18592 target_arch = "arm",
18593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18594)]
18595pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
18596 let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a)));
18597 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18598 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18599 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18600 ret_val
18601}
18602#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18604#[doc = "## Safety"]
18605#[doc = " * Neon instrinsic unsafe"]
18606#[inline]
18607#[cfg(target_endian = "little")]
18608#[target_feature(enable = "neon")]
18609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18611#[cfg_attr(
18612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18613 assert_instr(ld1)
18614)]
18615#[cfg_attr(
18616 not(target_arch = "arm"),
18617 stable(feature = "neon_intrinsics", since = "1.59.0")
18618)]
18619#[cfg_attr(
18620 target_arch = "arm",
18621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18622)]
18623pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18624 transmute(vld1q_s64_x4(transmute(a)))
18625}
18626#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
18628#[doc = "## Safety"]
18629#[doc = " * Neon instrinsic unsafe"]
18630#[inline]
18631#[cfg(target_endian = "big")]
18632#[target_feature(enable = "neon")]
18633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18635#[cfg_attr(
18636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18637 assert_instr(ld1)
18638)]
18639#[cfg_attr(
18640 not(target_arch = "arm"),
18641 stable(feature = "neon_intrinsics", since = "1.59.0")
18642)]
18643#[cfg_attr(
18644 target_arch = "arm",
18645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18646)]
18647pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
18648 let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a)));
18649 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
18650 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
18651 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
18652 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
18653 ret_val
18654}
18655#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18657#[doc = "## Safety"]
18658#[doc = " * Neon instrinsic unsafe"]
18659#[inline]
18660#[cfg(target_endian = "little")]
18661#[target_feature(enable = "neon")]
18662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18664#[cfg_attr(
18665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18666 assert_instr(ld1)
18667)]
18668#[cfg_attr(
18669 not(target_arch = "arm"),
18670 stable(feature = "neon_intrinsics", since = "1.59.0")
18671)]
18672#[cfg_attr(
18673 target_arch = "arm",
18674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18675)]
18676pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18677 transmute(vld1_s8_x2(transmute(a)))
18678}
18679#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
18681#[doc = "## Safety"]
18682#[doc = " * Neon instrinsic unsafe"]
18683#[inline]
18684#[cfg(target_endian = "big")]
18685#[target_feature(enable = "neon")]
18686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18688#[cfg_attr(
18689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18690 assert_instr(ld1)
18691)]
18692#[cfg_attr(
18693 not(target_arch = "arm"),
18694 stable(feature = "neon_intrinsics", since = "1.59.0")
18695)]
18696#[cfg_attr(
18697 target_arch = "arm",
18698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18699)]
18700pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
18701 let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a)));
18702 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18703 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18704 ret_val
18705}
18706#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18708#[doc = "## Safety"]
18709#[doc = " * Neon instrinsic unsafe"]
18710#[inline]
18711#[cfg(target_endian = "little")]
18712#[target_feature(enable = "neon")]
18713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18715#[cfg_attr(
18716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18717 assert_instr(ld1)
18718)]
18719#[cfg_attr(
18720 not(target_arch = "arm"),
18721 stable(feature = "neon_intrinsics", since = "1.59.0")
18722)]
18723#[cfg_attr(
18724 target_arch = "arm",
18725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18726)]
18727pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18728 transmute(vld1_s8_x3(transmute(a)))
18729}
18730#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
18732#[doc = "## Safety"]
18733#[doc = " * Neon instrinsic unsafe"]
18734#[inline]
18735#[cfg(target_endian = "big")]
18736#[target_feature(enable = "neon")]
18737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18739#[cfg_attr(
18740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18741 assert_instr(ld1)
18742)]
18743#[cfg_attr(
18744 not(target_arch = "arm"),
18745 stable(feature = "neon_intrinsics", since = "1.59.0")
18746)]
18747#[cfg_attr(
18748 target_arch = "arm",
18749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18750)]
18751pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
18752 let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a)));
18753 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18754 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18755 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18756 ret_val
18757}
18758#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18760#[doc = "## Safety"]
18761#[doc = " * Neon instrinsic unsafe"]
18762#[inline]
18763#[cfg(target_endian = "little")]
18764#[target_feature(enable = "neon")]
18765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18766#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18767#[cfg_attr(
18768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18769 assert_instr(ld1)
18770)]
18771#[cfg_attr(
18772 not(target_arch = "arm"),
18773 stable(feature = "neon_intrinsics", since = "1.59.0")
18774)]
18775#[cfg_attr(
18776 target_arch = "arm",
18777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18778)]
18779pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18780 transmute(vld1_s8_x4(transmute(a)))
18781}
18782#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
18784#[doc = "## Safety"]
18785#[doc = " * Neon instrinsic unsafe"]
18786#[inline]
18787#[cfg(target_endian = "big")]
18788#[target_feature(enable = "neon")]
18789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18791#[cfg_attr(
18792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18793 assert_instr(ld1)
18794)]
18795#[cfg_attr(
18796 not(target_arch = "arm"),
18797 stable(feature = "neon_intrinsics", since = "1.59.0")
18798)]
18799#[cfg_attr(
18800 target_arch = "arm",
18801 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18802)]
18803pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
18804 let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a)));
18805 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
18806 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
18807 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
18808 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
18809 ret_val
18810}
18811#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18813#[doc = "## Safety"]
18814#[doc = " * Neon instrinsic unsafe"]
18815#[inline]
18816#[cfg(target_endian = "little")]
18817#[target_feature(enable = "neon")]
18818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18820#[cfg_attr(
18821 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18822 assert_instr(ld1)
18823)]
18824#[cfg_attr(
18825 not(target_arch = "arm"),
18826 stable(feature = "neon_intrinsics", since = "1.59.0")
18827)]
18828#[cfg_attr(
18829 target_arch = "arm",
18830 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18831)]
18832pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18833 transmute(vld1q_s8_x2(transmute(a)))
18834}
18835#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
18837#[doc = "## Safety"]
18838#[doc = " * Neon instrinsic unsafe"]
18839#[inline]
18840#[cfg(target_endian = "big")]
18841#[target_feature(enable = "neon")]
18842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18844#[cfg_attr(
18845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18846 assert_instr(ld1)
18847)]
18848#[cfg_attr(
18849 not(target_arch = "arm"),
18850 stable(feature = "neon_intrinsics", since = "1.59.0")
18851)]
18852#[cfg_attr(
18853 target_arch = "arm",
18854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18855)]
18856pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
18857 let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a)));
18858 ret_val.0 = unsafe {
18859 simd_shuffle!(
18860 ret_val.0,
18861 ret_val.0,
18862 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18863 )
18864 };
18865 ret_val.1 = unsafe {
18866 simd_shuffle!(
18867 ret_val.1,
18868 ret_val.1,
18869 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18870 )
18871 };
18872 ret_val
18873}
18874#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
18876#[doc = "## Safety"]
18877#[doc = " * Neon instrinsic unsafe"]
18878#[inline]
18879#[cfg(target_endian = "little")]
18880#[target_feature(enable = "neon")]
18881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18883#[cfg_attr(
18884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18885 assert_instr(ld1)
18886)]
18887#[cfg_attr(
18888 not(target_arch = "arm"),
18889 stable(feature = "neon_intrinsics", since = "1.59.0")
18890)]
18891#[cfg_attr(
18892 target_arch = "arm",
18893 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18894)]
18895pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
18896 transmute(vld1q_s8_x3(transmute(a)))
18897}
18898#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
18900#[doc = "## Safety"]
18901#[doc = " * Neon instrinsic unsafe"]
18902#[inline]
18903#[cfg(target_endian = "big")]
18904#[target_feature(enable = "neon")]
18905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18907#[cfg_attr(
18908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18909 assert_instr(ld1)
18910)]
18911#[cfg_attr(
18912 not(target_arch = "arm"),
18913 stable(feature = "neon_intrinsics", since = "1.59.0")
18914)]
18915#[cfg_attr(
18916 target_arch = "arm",
18917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18918)]
18919pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
18920 let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a)));
18921 ret_val.0 = unsafe {
18922 simd_shuffle!(
18923 ret_val.0,
18924 ret_val.0,
18925 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18926 )
18927 };
18928 ret_val.1 = unsafe {
18929 simd_shuffle!(
18930 ret_val.1,
18931 ret_val.1,
18932 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18933 )
18934 };
18935 ret_val.2 = unsafe {
18936 simd_shuffle!(
18937 ret_val.2,
18938 ret_val.2,
18939 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18940 )
18941 };
18942 ret_val
18943}
18944#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
18946#[doc = "## Safety"]
18947#[doc = " * Neon instrinsic unsafe"]
18948#[inline]
18949#[cfg(target_endian = "little")]
18950#[target_feature(enable = "neon")]
18951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18953#[cfg_attr(
18954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18955 assert_instr(ld1)
18956)]
18957#[cfg_attr(
18958 not(target_arch = "arm"),
18959 stable(feature = "neon_intrinsics", since = "1.59.0")
18960)]
18961#[cfg_attr(
18962 target_arch = "arm",
18963 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18964)]
18965pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
18966 transmute(vld1q_s8_x4(transmute(a)))
18967}
18968#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
18969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
18970#[doc = "## Safety"]
18971#[doc = " * Neon instrinsic unsafe"]
18972#[inline]
18973#[cfg(target_endian = "big")]
18974#[target_feature(enable = "neon")]
18975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
18976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
18977#[cfg_attr(
18978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
18979 assert_instr(ld1)
18980)]
18981#[cfg_attr(
18982 not(target_arch = "arm"),
18983 stable(feature = "neon_intrinsics", since = "1.59.0")
18984)]
18985#[cfg_attr(
18986 target_arch = "arm",
18987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
18988)]
18989pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
18990 let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a)));
18991 ret_val.0 = unsafe {
18992 simd_shuffle!(
18993 ret_val.0,
18994 ret_val.0,
18995 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
18996 )
18997 };
18998 ret_val.1 = unsafe {
18999 simd_shuffle!(
19000 ret_val.1,
19001 ret_val.1,
19002 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19003 )
19004 };
19005 ret_val.2 = unsafe {
19006 simd_shuffle!(
19007 ret_val.2,
19008 ret_val.2,
19009 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19010 )
19011 };
19012 ret_val.3 = unsafe {
19013 simd_shuffle!(
19014 ret_val.3,
19015 ret_val.3,
19016 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
19017 )
19018 };
19019 ret_val
19020}
19021#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19023#[doc = "## Safety"]
19024#[doc = " * Neon instrinsic unsafe"]
19025#[inline]
19026#[cfg(target_endian = "little")]
19027#[target_feature(enable = "neon")]
19028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19030#[cfg_attr(
19031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19032 assert_instr(ld1)
19033)]
19034#[cfg_attr(
19035 not(target_arch = "arm"),
19036 stable(feature = "neon_intrinsics", since = "1.59.0")
19037)]
19038#[cfg_attr(
19039 target_arch = "arm",
19040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19041)]
19042pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19043 transmute(vld1_s16_x2(transmute(a)))
19044}
19045#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
19047#[doc = "## Safety"]
19048#[doc = " * Neon instrinsic unsafe"]
19049#[inline]
19050#[cfg(target_endian = "big")]
19051#[target_feature(enable = "neon")]
19052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19054#[cfg_attr(
19055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19056 assert_instr(ld1)
19057)]
19058#[cfg_attr(
19059 not(target_arch = "arm"),
19060 stable(feature = "neon_intrinsics", since = "1.59.0")
19061)]
19062#[cfg_attr(
19063 target_arch = "arm",
19064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19065)]
19066pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
19067 let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a)));
19068 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19069 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19070 ret_val
19071}
19072#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19074#[doc = "## Safety"]
19075#[doc = " * Neon instrinsic unsafe"]
19076#[inline]
19077#[cfg(target_endian = "little")]
19078#[target_feature(enable = "neon")]
19079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19081#[cfg_attr(
19082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19083 assert_instr(ld1)
19084)]
19085#[cfg_attr(
19086 not(target_arch = "arm"),
19087 stable(feature = "neon_intrinsics", since = "1.59.0")
19088)]
19089#[cfg_attr(
19090 target_arch = "arm",
19091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19092)]
19093pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19094 transmute(vld1_s16_x3(transmute(a)))
19095}
19096#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
19098#[doc = "## Safety"]
19099#[doc = " * Neon instrinsic unsafe"]
19100#[inline]
19101#[cfg(target_endian = "big")]
19102#[target_feature(enable = "neon")]
19103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19105#[cfg_attr(
19106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19107 assert_instr(ld1)
19108)]
19109#[cfg_attr(
19110 not(target_arch = "arm"),
19111 stable(feature = "neon_intrinsics", since = "1.59.0")
19112)]
19113#[cfg_attr(
19114 target_arch = "arm",
19115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19116)]
19117pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
19118 let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a)));
19119 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19120 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19121 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19122 ret_val
19123}
19124#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19126#[doc = "## Safety"]
19127#[doc = " * Neon instrinsic unsafe"]
19128#[inline]
19129#[cfg(target_endian = "little")]
19130#[target_feature(enable = "neon")]
19131#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19132#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19133#[cfg_attr(
19134 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19135 assert_instr(ld1)
19136)]
19137#[cfg_attr(
19138 not(target_arch = "arm"),
19139 stable(feature = "neon_intrinsics", since = "1.59.0")
19140)]
19141#[cfg_attr(
19142 target_arch = "arm",
19143 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19144)]
19145pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19146 transmute(vld1_s16_x4(transmute(a)))
19147}
19148#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
19150#[doc = "## Safety"]
19151#[doc = " * Neon instrinsic unsafe"]
19152#[inline]
19153#[cfg(target_endian = "big")]
19154#[target_feature(enable = "neon")]
19155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19157#[cfg_attr(
19158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19159 assert_instr(ld1)
19160)]
19161#[cfg_attr(
19162 not(target_arch = "arm"),
19163 stable(feature = "neon_intrinsics", since = "1.59.0")
19164)]
19165#[cfg_attr(
19166 target_arch = "arm",
19167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19168)]
19169pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
19170 let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a)));
19171 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
19172 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
19173 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
19174 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
19175 ret_val
19176}
19177#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19179#[doc = "## Safety"]
19180#[doc = " * Neon instrinsic unsafe"]
19181#[inline]
19182#[cfg(target_endian = "little")]
19183#[target_feature(enable = "neon")]
19184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19186#[cfg_attr(
19187 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19188 assert_instr(ld1)
19189)]
19190#[cfg_attr(
19191 not(target_arch = "arm"),
19192 stable(feature = "neon_intrinsics", since = "1.59.0")
19193)]
19194#[cfg_attr(
19195 target_arch = "arm",
19196 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19197)]
19198pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19199 transmute(vld1q_s16_x2(transmute(a)))
19200}
19201#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
19203#[doc = "## Safety"]
19204#[doc = " * Neon instrinsic unsafe"]
19205#[inline]
19206#[cfg(target_endian = "big")]
19207#[target_feature(enable = "neon")]
19208#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19210#[cfg_attr(
19211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19212 assert_instr(ld1)
19213)]
19214#[cfg_attr(
19215 not(target_arch = "arm"),
19216 stable(feature = "neon_intrinsics", since = "1.59.0")
19217)]
19218#[cfg_attr(
19219 target_arch = "arm",
19220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19221)]
19222pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
19223 let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a)));
19224 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19225 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19226 ret_val
19227}
19228#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19230#[doc = "## Safety"]
19231#[doc = " * Neon instrinsic unsafe"]
19232#[inline]
19233#[cfg(target_endian = "little")]
19234#[target_feature(enable = "neon")]
19235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19237#[cfg_attr(
19238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19239 assert_instr(ld1)
19240)]
19241#[cfg_attr(
19242 not(target_arch = "arm"),
19243 stable(feature = "neon_intrinsics", since = "1.59.0")
19244)]
19245#[cfg_attr(
19246 target_arch = "arm",
19247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19248)]
19249pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19250 transmute(vld1q_s16_x3(transmute(a)))
19251}
19252#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
19254#[doc = "## Safety"]
19255#[doc = " * Neon instrinsic unsafe"]
19256#[inline]
19257#[cfg(target_endian = "big")]
19258#[target_feature(enable = "neon")]
19259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19261#[cfg_attr(
19262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19263 assert_instr(ld1)
19264)]
19265#[cfg_attr(
19266 not(target_arch = "arm"),
19267 stable(feature = "neon_intrinsics", since = "1.59.0")
19268)]
19269#[cfg_attr(
19270 target_arch = "arm",
19271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19272)]
19273pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
19274 let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a)));
19275 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19276 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19277 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19278 ret_val
19279}
19280#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19282#[doc = "## Safety"]
19283#[doc = " * Neon instrinsic unsafe"]
19284#[inline]
19285#[cfg(target_endian = "little")]
19286#[target_feature(enable = "neon")]
19287#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19288#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19289#[cfg_attr(
19290 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19291 assert_instr(ld1)
19292)]
19293#[cfg_attr(
19294 not(target_arch = "arm"),
19295 stable(feature = "neon_intrinsics", since = "1.59.0")
19296)]
19297#[cfg_attr(
19298 target_arch = "arm",
19299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19300)]
19301pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19302 transmute(vld1q_s16_x4(transmute(a)))
19303}
19304#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
19306#[doc = "## Safety"]
19307#[doc = " * Neon instrinsic unsafe"]
19308#[inline]
19309#[cfg(target_endian = "big")]
19310#[target_feature(enable = "neon")]
19311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
19313#[cfg_attr(
19314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19315 assert_instr(ld1)
19316)]
19317#[cfg_attr(
19318 not(target_arch = "arm"),
19319 stable(feature = "neon_intrinsics", since = "1.59.0")
19320)]
19321#[cfg_attr(
19322 target_arch = "arm",
19323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19324)]
19325pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
19326 let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a)));
19327 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
19328 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
19329 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
19330 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
19331 ret_val
19332}
19333#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v1i64)"]
19335#[doc = "## Safety"]
19336#[doc = " * Neon instrinsic unsafe"]
19337#[inline]
19338#[cfg(target_arch = "arm")]
19339#[target_feature(enable = "neon,v7")]
19340#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19341unsafe fn vld1_v1i64(a: *const i8, b: i32) -> int64x1_t {
19342 unsafe extern "unadjusted" {
19343 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v1i64")]
19344 fn _vld1_v1i64(a: *const i8, b: i32) -> int64x1_t;
19345 }
19346 _vld1_v1i64(a, b)
19347}
19348#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2f32)"]
19350#[doc = "## Safety"]
19351#[doc = " * Neon instrinsic unsafe"]
19352#[inline]
19353#[cfg(target_arch = "arm")]
19354#[target_feature(enable = "neon,v7")]
19355#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19356unsafe fn vld1_v2f32(a: *const i8, b: i32) -> float32x2_t {
19357 unsafe extern "unadjusted" {
19358 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2f32")]
19359 fn _vld1_v2f32(a: *const i8, b: i32) -> float32x2_t;
19360 }
19361 _vld1_v2f32(a, b)
19362}
19363#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19364#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v2i32)"]
19365#[doc = "## Safety"]
19366#[doc = " * Neon instrinsic unsafe"]
19367#[inline]
19368#[cfg(target_arch = "arm")]
19369#[target_feature(enable = "neon,v7")]
19370#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19371unsafe fn vld1_v2i32(a: *const i8, b: i32) -> int32x2_t {
19372 unsafe extern "unadjusted" {
19373 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i32")]
19374 fn _vld1_v2i32(a: *const i8, b: i32) -> int32x2_t;
19375 }
19376 _vld1_v2i32(a, b)
19377}
19378#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4i16)"]
19380#[doc = "## Safety"]
19381#[doc = " * Neon instrinsic unsafe"]
19382#[inline]
19383#[cfg(target_arch = "arm")]
19384#[target_feature(enable = "neon,v7")]
19385#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19386unsafe fn vld1_v4i16(a: *const i8, b: i32) -> int16x4_t {
19387 unsafe extern "unadjusted" {
19388 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i16")]
19389 fn _vld1_v4i16(a: *const i8, b: i32) -> int16x4_t;
19390 }
19391 _vld1_v4i16(a, b)
19392}
19393#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v8i8)"]
19395#[doc = "## Safety"]
19396#[doc = " * Neon instrinsic unsafe"]
19397#[inline]
19398#[cfg(target_arch = "arm")]
19399#[target_feature(enable = "neon,v7")]
19400#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19401unsafe fn vld1_v8i8(a: *const i8, b: i32) -> int8x8_t {
19402 unsafe extern "unadjusted" {
19403 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i8")]
19404 fn _vld1_v8i8(a: *const i8, b: i32) -> int8x8_t;
19405 }
19406 _vld1_v8i8(a, b)
19407}
19408#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v16i8)"]
19410#[doc = "## Safety"]
19411#[doc = " * Neon instrinsic unsafe"]
19412#[inline]
19413#[cfg(target_arch = "arm")]
19414#[target_feature(enable = "neon,v7")]
19415#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19416unsafe fn vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t {
19417 unsafe extern "unadjusted" {
19418 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v16i8")]
19419 fn _vld1q_v16i8(a: *const i8, b: i32) -> int8x16_t;
19420 }
19421 _vld1q_v16i8(a, b)
19422}
19423#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v2i64)"]
19425#[doc = "## Safety"]
19426#[doc = " * Neon instrinsic unsafe"]
19427#[inline]
19428#[cfg(target_arch = "arm")]
19429#[target_feature(enable = "neon,v7")]
19430#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19431unsafe fn vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t {
19432 unsafe extern "unadjusted" {
19433 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v2i64")]
19434 fn _vld1q_v2i64(a: *const i8, b: i32) -> int64x2_t;
19435 }
19436 _vld1q_v2i64(a, b)
19437}
19438#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4f32)"]
19440#[doc = "## Safety"]
19441#[doc = " * Neon instrinsic unsafe"]
19442#[inline]
19443#[cfg(target_arch = "arm")]
19444#[target_feature(enable = "neon,v7")]
19445#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19446unsafe fn vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t {
19447 unsafe extern "unadjusted" {
19448 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f32")]
19449 fn _vld1q_v4f32(a: *const i8, b: i32) -> float32x4_t;
19450 }
19451 _vld1q_v4f32(a, b)
19452}
19453#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v4i32)"]
19455#[doc = "## Safety"]
19456#[doc = " * Neon instrinsic unsafe"]
19457#[inline]
19458#[cfg(target_arch = "arm")]
19459#[target_feature(enable = "neon,v7")]
19460#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19461unsafe fn vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t {
19462 unsafe extern "unadjusted" {
19463 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4i32")]
19464 fn _vld1q_v4i32(a: *const i8, b: i32) -> int32x4_t;
19465 }
19466 _vld1q_v4i32(a, b)
19467}
19468#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8i16)"]
19470#[doc = "## Safety"]
19471#[doc = " * Neon instrinsic unsafe"]
19472#[inline]
19473#[cfg(target_arch = "arm")]
19474#[target_feature(enable = "neon,v7")]
19475#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19476unsafe fn vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t {
19477 unsafe extern "unadjusted" {
19478 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8i16")]
19479 fn _vld1q_v8i16(a: *const i8, b: i32) -> int16x8_t;
19480 }
19481 _vld1q_v8i16(a, b)
19482}
19483#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19484#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_v4f16)"]
19485#[doc = "## Safety"]
19486#[doc = " * Neon instrinsic unsafe"]
19487#[inline]
19488#[cfg(target_arch = "arm")]
19489#[target_feature(enable = "neon,v7")]
19490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19491#[target_feature(enable = "neon,fp16")]
19492#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19493unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
19494 unsafe extern "unadjusted" {
19495 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v4f16")]
19496 fn _vld1_v4f16(a: *const i8, b: i32) -> float16x4_t;
19497 }
19498 _vld1_v4f16(a, b)
19499}
19500#[doc = "Load multiple single-element structures to one, two, three, or four registers"]
19501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_v8f16)"]
19502#[doc = "## Safety"]
19503#[doc = " * Neon instrinsic unsafe"]
19504#[inline]
19505#[cfg(target_arch = "arm")]
19506#[target_feature(enable = "neon,v7")]
19507#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19508#[target_feature(enable = "neon,fp16")]
19509#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19510unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
19511 unsafe extern "unadjusted" {
19512 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1.v8f16")]
19513 fn _vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t;
19514 }
19515 _vld1q_v8f16(a, b)
19516}
19517#[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
19518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
19519#[doc = "## Safety"]
19520#[doc = " * Neon instrinsic unsafe"]
19521#[inline]
19522#[target_feature(enable = "neon,aes")]
19523#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19524#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
19525#[cfg_attr(
19526 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19527 assert_instr(ld1r)
19528)]
19529#[cfg_attr(
19530 not(target_arch = "arm"),
19531 stable(feature = "neon_intrinsics", since = "1.59.0")
19532)]
19533#[cfg_attr(
19534 target_arch = "arm",
19535 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19536)]
19537pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
19538 let x = vld1q_lane_p64::<0>(ptr, transmute(u64x2::splat(0)));
19539 simd_shuffle!(x, x, [0, 0])
19540}
19541#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19543#[doc = "## Safety"]
19544#[doc = " * Neon instrinsic unsafe"]
19545#[inline]
19546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19547#[cfg(target_arch = "arm")]
19548#[target_feature(enable = "neon,fp16")]
19549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19551pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19552 unsafe extern "unadjusted" {
19553 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f16.p0")]
19554 fn _vld2_dup_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
19555 }
19556 _vld2_dup_f16(a as _, 2)
19557}
19558#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19560#[doc = "## Safety"]
19561#[doc = " * Neon instrinsic unsafe"]
19562#[inline]
19563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19564#[cfg(target_arch = "arm")]
19565#[target_feature(enable = "neon,fp16")]
19566#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19567#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19568pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19569 unsafe extern "unadjusted" {
19570 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8f16.p0")]
19571 fn _vld2q_dup_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
19572 }
19573 _vld2q_dup_f16(a as _, 2)
19574}
19575#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
19577#[doc = "## Safety"]
19578#[doc = " * Neon instrinsic unsafe"]
19579#[inline]
19580#[cfg(not(target_arch = "arm"))]
19581#[cfg_attr(
19582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19583 assert_instr(ld2r)
19584)]
19585#[target_feature(enable = "neon,fp16")]
19586#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19587pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
19588 unsafe extern "unadjusted" {
19589 #[cfg_attr(
19590 any(target_arch = "aarch64", target_arch = "arm64ec"),
19591 link_name = "llvm.aarch64.neon.ld2r.v4f16.p0"
19592 )]
19593 fn _vld2_dup_f16(ptr: *const f16) -> float16x4x2_t;
19594 }
19595 _vld2_dup_f16(a as _)
19596}
19597#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
19599#[doc = "## Safety"]
19600#[doc = " * Neon instrinsic unsafe"]
19601#[inline]
19602#[cfg(not(target_arch = "arm"))]
19603#[cfg_attr(
19604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19605 assert_instr(ld2r)
19606)]
19607#[target_feature(enable = "neon,fp16")]
19608#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
19609pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
19610 unsafe extern "unadjusted" {
19611 #[cfg_attr(
19612 any(target_arch = "aarch64", target_arch = "arm64ec"),
19613 link_name = "llvm.aarch64.neon.ld2r.v8f16.p0"
19614 )]
19615 fn _vld2q_dup_f16(ptr: *const f16) -> float16x8x2_t;
19616 }
19617 _vld2q_dup_f16(a as _)
19618}
19619#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19621#[doc = "## Safety"]
19622#[doc = " * Neon instrinsic unsafe"]
19623#[inline]
19624#[target_feature(enable = "neon,v7")]
19625#[cfg(target_arch = "arm")]
19626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19627#[cfg_attr(test, assert_instr(vld2))]
19628pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19629 unsafe extern "unadjusted" {
19630 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0")]
19631 fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
19632 }
19633 _vld2_dup_f32(a as *const i8, 4)
19634}
19635#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19637#[doc = "## Safety"]
19638#[doc = " * Neon instrinsic unsafe"]
19639#[inline]
19640#[target_feature(enable = "neon,v7")]
19641#[cfg(target_arch = "arm")]
19642#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19643#[cfg_attr(test, assert_instr(vld2))]
19644pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19645 unsafe extern "unadjusted" {
19646 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0")]
19647 fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
19648 }
19649 _vld2q_dup_f32(a as *const i8, 4)
19650}
19651#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19652#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19653#[doc = "## Safety"]
19654#[doc = " * Neon instrinsic unsafe"]
19655#[inline]
19656#[target_feature(enable = "neon,v7")]
19657#[cfg(target_arch = "arm")]
19658#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19659#[cfg_attr(test, assert_instr(vld2))]
19660pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19661 unsafe extern "unadjusted" {
19662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0")]
19663 fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
19664 }
19665 _vld2_dup_s8(a as *const i8, 1)
19666}
19667#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19669#[doc = "## Safety"]
19670#[doc = " * Neon instrinsic unsafe"]
19671#[inline]
19672#[target_feature(enable = "neon,v7")]
19673#[cfg(target_arch = "arm")]
19674#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19675#[cfg_attr(test, assert_instr(vld2))]
19676pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19677 unsafe extern "unadjusted" {
19678 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0")]
19679 fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
19680 }
19681 _vld2q_dup_s8(a as *const i8, 1)
19682}
19683#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19685#[doc = "## Safety"]
19686#[doc = " * Neon instrinsic unsafe"]
19687#[inline]
19688#[target_feature(enable = "neon,v7")]
19689#[cfg(target_arch = "arm")]
19690#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19691#[cfg_attr(test, assert_instr(vld2))]
19692pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19693 unsafe extern "unadjusted" {
19694 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0")]
19695 fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
19696 }
19697 _vld2_dup_s16(a as *const i8, 2)
19698}
19699#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19701#[doc = "## Safety"]
19702#[doc = " * Neon instrinsic unsafe"]
19703#[inline]
19704#[target_feature(enable = "neon,v7")]
19705#[cfg(target_arch = "arm")]
19706#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19707#[cfg_attr(test, assert_instr(vld2))]
19708pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19709 unsafe extern "unadjusted" {
19710 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0")]
19711 fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
19712 }
19713 _vld2q_dup_s16(a as *const i8, 2)
19714}
19715#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19717#[doc = "## Safety"]
19718#[doc = " * Neon instrinsic unsafe"]
19719#[inline]
19720#[target_feature(enable = "neon,v7")]
19721#[cfg(target_arch = "arm")]
19722#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19723#[cfg_attr(test, assert_instr(vld2))]
19724pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19725 unsafe extern "unadjusted" {
19726 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0")]
19727 fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
19728 }
19729 _vld2_dup_s32(a as *const i8, 4)
19730}
19731#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19733#[doc = "## Safety"]
19734#[doc = " * Neon instrinsic unsafe"]
19735#[inline]
19736#[target_feature(enable = "neon,v7")]
19737#[cfg(target_arch = "arm")]
19738#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19739#[cfg_attr(test, assert_instr(vld2))]
19740pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19741 unsafe extern "unadjusted" {
19742 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0")]
19743 fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
19744 }
19745 _vld2q_dup_s32(a as *const i8, 4)
19746}
19747#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
19749#[doc = "## Safety"]
19750#[doc = " * Neon instrinsic unsafe"]
19751#[inline]
19752#[target_feature(enable = "neon")]
19753#[cfg(not(target_arch = "arm"))]
19754#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19755#[cfg_attr(test, assert_instr(ld2r))]
19756pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
19757 unsafe extern "unadjusted" {
19758 #[cfg_attr(
19759 any(target_arch = "aarch64", target_arch = "arm64ec"),
19760 link_name = "llvm.aarch64.neon.ld2r.v2f32.p0"
19761 )]
19762 fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t;
19763 }
19764 _vld2_dup_f32(a as _)
19765}
19766#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
19768#[doc = "## Safety"]
19769#[doc = " * Neon instrinsic unsafe"]
19770#[inline]
19771#[target_feature(enable = "neon")]
19772#[cfg(not(target_arch = "arm"))]
19773#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19774#[cfg_attr(test, assert_instr(ld2r))]
19775pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
19776 unsafe extern "unadjusted" {
19777 #[cfg_attr(
19778 any(target_arch = "aarch64", target_arch = "arm64ec"),
19779 link_name = "llvm.aarch64.neon.ld2r.v4f32.p0"
19780 )]
19781 fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t;
19782 }
19783 _vld2q_dup_f32(a as _)
19784}
19785#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
19787#[doc = "## Safety"]
19788#[doc = " * Neon instrinsic unsafe"]
19789#[inline]
19790#[target_feature(enable = "neon")]
19791#[cfg(not(target_arch = "arm"))]
19792#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19793#[cfg_attr(test, assert_instr(ld2r))]
19794pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
19795 unsafe extern "unadjusted" {
19796 #[cfg_attr(
19797 any(target_arch = "aarch64", target_arch = "arm64ec"),
19798 link_name = "llvm.aarch64.neon.ld2r.v8i8.p0"
19799 )]
19800 fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t;
19801 }
19802 _vld2_dup_s8(a as _)
19803}
19804#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
19806#[doc = "## Safety"]
19807#[doc = " * Neon instrinsic unsafe"]
19808#[inline]
19809#[target_feature(enable = "neon")]
19810#[cfg(not(target_arch = "arm"))]
19811#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19812#[cfg_attr(test, assert_instr(ld2r))]
19813pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
19814 unsafe extern "unadjusted" {
19815 #[cfg_attr(
19816 any(target_arch = "aarch64", target_arch = "arm64ec"),
19817 link_name = "llvm.aarch64.neon.ld2r.v16i8.p0"
19818 )]
19819 fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t;
19820 }
19821 _vld2q_dup_s8(a as _)
19822}
19823#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19824#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
19825#[doc = "## Safety"]
19826#[doc = " * Neon instrinsic unsafe"]
19827#[inline]
19828#[target_feature(enable = "neon")]
19829#[cfg(not(target_arch = "arm"))]
19830#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19831#[cfg_attr(test, assert_instr(ld2r))]
19832pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
19833 unsafe extern "unadjusted" {
19834 #[cfg_attr(
19835 any(target_arch = "aarch64", target_arch = "arm64ec"),
19836 link_name = "llvm.aarch64.neon.ld2r.v4i16.p0"
19837 )]
19838 fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t;
19839 }
19840 _vld2_dup_s16(a as _)
19841}
19842#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
19844#[doc = "## Safety"]
19845#[doc = " * Neon instrinsic unsafe"]
19846#[inline]
19847#[target_feature(enable = "neon")]
19848#[cfg(not(target_arch = "arm"))]
19849#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19850#[cfg_attr(test, assert_instr(ld2r))]
19851pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
19852 unsafe extern "unadjusted" {
19853 #[cfg_attr(
19854 any(target_arch = "aarch64", target_arch = "arm64ec"),
19855 link_name = "llvm.aarch64.neon.ld2r.v8i16.p0"
19856 )]
19857 fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t;
19858 }
19859 _vld2q_dup_s16(a as _)
19860}
19861#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
19863#[doc = "## Safety"]
19864#[doc = " * Neon instrinsic unsafe"]
19865#[inline]
19866#[target_feature(enable = "neon")]
19867#[cfg(not(target_arch = "arm"))]
19868#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19869#[cfg_attr(test, assert_instr(ld2r))]
19870pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
19871 unsafe extern "unadjusted" {
19872 #[cfg_attr(
19873 any(target_arch = "aarch64", target_arch = "arm64ec"),
19874 link_name = "llvm.aarch64.neon.ld2r.v2i32.p0"
19875 )]
19876 fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t;
19877 }
19878 _vld2_dup_s32(a as _)
19879}
19880#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
19882#[doc = "## Safety"]
19883#[doc = " * Neon instrinsic unsafe"]
19884#[inline]
19885#[target_feature(enable = "neon")]
19886#[cfg(not(target_arch = "arm"))]
19887#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19888#[cfg_attr(test, assert_instr(ld2r))]
19889pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
19890 unsafe extern "unadjusted" {
19891 #[cfg_attr(
19892 any(target_arch = "aarch64", target_arch = "arm64ec"),
19893 link_name = "llvm.aarch64.neon.ld2r.v4i32.p0"
19894 )]
19895 fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t;
19896 }
19897 _vld2q_dup_s32(a as _)
19898}
19899#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
19901#[doc = "## Safety"]
19902#[doc = " * Neon instrinsic unsafe"]
19903#[inline]
19904#[target_feature(enable = "neon,aes")]
19905#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
19906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19907#[cfg_attr(
19908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19909 assert_instr(ld2r)
19910)]
19911#[cfg_attr(
19912 not(target_arch = "arm"),
19913 stable(feature = "neon_intrinsics", since = "1.59.0")
19914)]
19915#[cfg_attr(
19916 target_arch = "arm",
19917 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19918)]
19919pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
19920 transmute(vld2_dup_s64(transmute(a)))
19921}
19922#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
19924#[doc = "## Safety"]
19925#[doc = " * Neon instrinsic unsafe"]
19926#[inline]
19927#[target_feature(enable = "neon,v7")]
19928#[cfg(target_arch = "arm")]
19929#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
19930#[cfg_attr(test, assert_instr(nop))]
19931pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
19932 unsafe extern "unadjusted" {
19933 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0")]
19934 fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
19935 }
19936 _vld2_dup_s64(a as *const i8, 8)
19937}
19938#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
19940#[doc = "## Safety"]
19941#[doc = " * Neon instrinsic unsafe"]
19942#[inline]
19943#[target_feature(enable = "neon")]
19944#[cfg(not(target_arch = "arm"))]
19945#[stable(feature = "neon_intrinsics", since = "1.59.0")]
19946#[cfg_attr(test, assert_instr(ld2r))]
19947pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
19948 unsafe extern "unadjusted" {
19949 #[cfg_attr(
19950 any(target_arch = "aarch64", target_arch = "arm64ec"),
19951 link_name = "llvm.aarch64.neon.ld2r.v1i64.p0"
19952 )]
19953 fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t;
19954 }
19955 _vld2_dup_s64(a as _)
19956}
19957#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
19959#[doc = "## Safety"]
19960#[doc = " * Neon instrinsic unsafe"]
19961#[inline]
19962#[target_feature(enable = "neon")]
19963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
19965#[cfg_attr(
19966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19967 assert_instr(ld2r)
19968)]
19969#[cfg_attr(
19970 not(target_arch = "arm"),
19971 stable(feature = "neon_intrinsics", since = "1.59.0")
19972)]
19973#[cfg_attr(
19974 target_arch = "arm",
19975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
19976)]
19977pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
19978 transmute(vld2_dup_s64(transmute(a)))
19979}
19980#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
19981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
19982#[doc = "## Safety"]
19983#[doc = " * Neon instrinsic unsafe"]
19984#[inline]
19985#[cfg(target_endian = "little")]
19986#[target_feature(enable = "neon")]
19987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
19988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
19989#[cfg_attr(
19990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
19991 assert_instr(ld2r)
19992)]
19993#[cfg_attr(
19994 not(target_arch = "arm"),
19995 stable(feature = "neon_intrinsics", since = "1.59.0")
19996)]
19997#[cfg_attr(
19998 target_arch = "arm",
19999 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20000)]
20001pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20002 transmute(vld2_dup_s8(transmute(a)))
20003}
20004#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20005#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
20006#[doc = "## Safety"]
20007#[doc = " * Neon instrinsic unsafe"]
20008#[inline]
20009#[cfg(target_endian = "big")]
20010#[target_feature(enable = "neon")]
20011#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20013#[cfg_attr(
20014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20015 assert_instr(ld2r)
20016)]
20017#[cfg_attr(
20018 not(target_arch = "arm"),
20019 stable(feature = "neon_intrinsics", since = "1.59.0")
20020)]
20021#[cfg_attr(
20022 target_arch = "arm",
20023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20024)]
20025pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
20026 let mut ret_val: uint8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20027 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20028 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20029 ret_val
20030}
20031#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20033#[doc = "## Safety"]
20034#[doc = " * Neon instrinsic unsafe"]
20035#[inline]
20036#[cfg(target_endian = "little")]
20037#[target_feature(enable = "neon")]
20038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20040#[cfg_attr(
20041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20042 assert_instr(ld2r)
20043)]
20044#[cfg_attr(
20045 not(target_arch = "arm"),
20046 stable(feature = "neon_intrinsics", since = "1.59.0")
20047)]
20048#[cfg_attr(
20049 target_arch = "arm",
20050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20051)]
20052pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20053 transmute(vld2q_dup_s8(transmute(a)))
20054}
20055#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
20057#[doc = "## Safety"]
20058#[doc = " * Neon instrinsic unsafe"]
20059#[inline]
20060#[cfg(target_endian = "big")]
20061#[target_feature(enable = "neon")]
20062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20064#[cfg_attr(
20065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20066 assert_instr(ld2r)
20067)]
20068#[cfg_attr(
20069 not(target_arch = "arm"),
20070 stable(feature = "neon_intrinsics", since = "1.59.0")
20071)]
20072#[cfg_attr(
20073 target_arch = "arm",
20074 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20075)]
20076pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
20077 let mut ret_val: uint8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20078 ret_val.0 = unsafe {
20079 simd_shuffle!(
20080 ret_val.0,
20081 ret_val.0,
20082 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20083 )
20084 };
20085 ret_val.1 = unsafe {
20086 simd_shuffle!(
20087 ret_val.1,
20088 ret_val.1,
20089 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20090 )
20091 };
20092 ret_val
20093}
20094#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20096#[doc = "## Safety"]
20097#[doc = " * Neon instrinsic unsafe"]
20098#[inline]
20099#[cfg(target_endian = "little")]
20100#[target_feature(enable = "neon")]
20101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20103#[cfg_attr(
20104 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20105 assert_instr(ld2r)
20106)]
20107#[cfg_attr(
20108 not(target_arch = "arm"),
20109 stable(feature = "neon_intrinsics", since = "1.59.0")
20110)]
20111#[cfg_attr(
20112 target_arch = "arm",
20113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20114)]
20115pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20116 transmute(vld2_dup_s16(transmute(a)))
20117}
20118#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
20120#[doc = "## Safety"]
20121#[doc = " * Neon instrinsic unsafe"]
20122#[inline]
20123#[cfg(target_endian = "big")]
20124#[target_feature(enable = "neon")]
20125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20127#[cfg_attr(
20128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20129 assert_instr(ld2r)
20130)]
20131#[cfg_attr(
20132 not(target_arch = "arm"),
20133 stable(feature = "neon_intrinsics", since = "1.59.0")
20134)]
20135#[cfg_attr(
20136 target_arch = "arm",
20137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20138)]
20139pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
20140 let mut ret_val: uint16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20141 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20142 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20143 ret_val
20144}
20145#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20147#[doc = "## Safety"]
20148#[doc = " * Neon instrinsic unsafe"]
20149#[inline]
20150#[cfg(target_endian = "little")]
20151#[target_feature(enable = "neon")]
20152#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20153#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20154#[cfg_attr(
20155 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20156 assert_instr(ld2r)
20157)]
20158#[cfg_attr(
20159 not(target_arch = "arm"),
20160 stable(feature = "neon_intrinsics", since = "1.59.0")
20161)]
20162#[cfg_attr(
20163 target_arch = "arm",
20164 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20165)]
20166pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20167 transmute(vld2q_dup_s16(transmute(a)))
20168}
20169#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20170#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
20171#[doc = "## Safety"]
20172#[doc = " * Neon instrinsic unsafe"]
20173#[inline]
20174#[cfg(target_endian = "big")]
20175#[target_feature(enable = "neon")]
20176#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20178#[cfg_attr(
20179 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20180 assert_instr(ld2r)
20181)]
20182#[cfg_attr(
20183 not(target_arch = "arm"),
20184 stable(feature = "neon_intrinsics", since = "1.59.0")
20185)]
20186#[cfg_attr(
20187 target_arch = "arm",
20188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20189)]
20190pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
20191 let mut ret_val: uint16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20192 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20193 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20194 ret_val
20195}
20196#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20198#[doc = "## Safety"]
20199#[doc = " * Neon instrinsic unsafe"]
20200#[inline]
20201#[cfg(target_endian = "little")]
20202#[target_feature(enable = "neon")]
20203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20205#[cfg_attr(
20206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20207 assert_instr(ld2r)
20208)]
20209#[cfg_attr(
20210 not(target_arch = "arm"),
20211 stable(feature = "neon_intrinsics", since = "1.59.0")
20212)]
20213#[cfg_attr(
20214 target_arch = "arm",
20215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20216)]
20217pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20218 transmute(vld2_dup_s32(transmute(a)))
20219}
20220#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
20222#[doc = "## Safety"]
20223#[doc = " * Neon instrinsic unsafe"]
20224#[inline]
20225#[cfg(target_endian = "big")]
20226#[target_feature(enable = "neon")]
20227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20229#[cfg_attr(
20230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20231 assert_instr(ld2r)
20232)]
20233#[cfg_attr(
20234 not(target_arch = "arm"),
20235 stable(feature = "neon_intrinsics", since = "1.59.0")
20236)]
20237#[cfg_attr(
20238 target_arch = "arm",
20239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20240)]
20241pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
20242 let mut ret_val: uint32x2x2_t = transmute(vld2_dup_s32(transmute(a)));
20243 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
20244 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
20245 ret_val
20246}
20247#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20249#[doc = "## Safety"]
20250#[doc = " * Neon instrinsic unsafe"]
20251#[inline]
20252#[cfg(target_endian = "little")]
20253#[target_feature(enable = "neon")]
20254#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20256#[cfg_attr(
20257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20258 assert_instr(ld2r)
20259)]
20260#[cfg_attr(
20261 not(target_arch = "arm"),
20262 stable(feature = "neon_intrinsics", since = "1.59.0")
20263)]
20264#[cfg_attr(
20265 target_arch = "arm",
20266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20267)]
20268pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20269 transmute(vld2q_dup_s32(transmute(a)))
20270}
20271#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
20273#[doc = "## Safety"]
20274#[doc = " * Neon instrinsic unsafe"]
20275#[inline]
20276#[cfg(target_endian = "big")]
20277#[target_feature(enable = "neon")]
20278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20280#[cfg_attr(
20281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20282 assert_instr(ld2r)
20283)]
20284#[cfg_attr(
20285 not(target_arch = "arm"),
20286 stable(feature = "neon_intrinsics", since = "1.59.0")
20287)]
20288#[cfg_attr(
20289 target_arch = "arm",
20290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20291)]
20292pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
20293 let mut ret_val: uint32x4x2_t = transmute(vld2q_dup_s32(transmute(a)));
20294 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20295 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20296 ret_val
20297}
20298#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20300#[doc = "## Safety"]
20301#[doc = " * Neon instrinsic unsafe"]
20302#[inline]
20303#[cfg(target_endian = "little")]
20304#[target_feature(enable = "neon")]
20305#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20306#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20307#[cfg_attr(
20308 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20309 assert_instr(ld2r)
20310)]
20311#[cfg_attr(
20312 not(target_arch = "arm"),
20313 stable(feature = "neon_intrinsics", since = "1.59.0")
20314)]
20315#[cfg_attr(
20316 target_arch = "arm",
20317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20318)]
20319pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20320 transmute(vld2_dup_s8(transmute(a)))
20321}
20322#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20323#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
20324#[doc = "## Safety"]
20325#[doc = " * Neon instrinsic unsafe"]
20326#[inline]
20327#[cfg(target_endian = "big")]
20328#[target_feature(enable = "neon")]
20329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20331#[cfg_attr(
20332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20333 assert_instr(ld2r)
20334)]
20335#[cfg_attr(
20336 not(target_arch = "arm"),
20337 stable(feature = "neon_intrinsics", since = "1.59.0")
20338)]
20339#[cfg_attr(
20340 target_arch = "arm",
20341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20342)]
20343pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
20344 let mut ret_val: poly8x8x2_t = transmute(vld2_dup_s8(transmute(a)));
20345 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20346 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20347 ret_val
20348}
20349#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20351#[doc = "## Safety"]
20352#[doc = " * Neon instrinsic unsafe"]
20353#[inline]
20354#[cfg(target_endian = "little")]
20355#[target_feature(enable = "neon")]
20356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20358#[cfg_attr(
20359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20360 assert_instr(ld2r)
20361)]
20362#[cfg_attr(
20363 not(target_arch = "arm"),
20364 stable(feature = "neon_intrinsics", since = "1.59.0")
20365)]
20366#[cfg_attr(
20367 target_arch = "arm",
20368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20369)]
20370pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20371 transmute(vld2q_dup_s8(transmute(a)))
20372}
20373#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
20375#[doc = "## Safety"]
20376#[doc = " * Neon instrinsic unsafe"]
20377#[inline]
20378#[cfg(target_endian = "big")]
20379#[target_feature(enable = "neon")]
20380#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20382#[cfg_attr(
20383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20384 assert_instr(ld2r)
20385)]
20386#[cfg_attr(
20387 not(target_arch = "arm"),
20388 stable(feature = "neon_intrinsics", since = "1.59.0")
20389)]
20390#[cfg_attr(
20391 target_arch = "arm",
20392 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20393)]
20394pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
20395 let mut ret_val: poly8x16x2_t = transmute(vld2q_dup_s8(transmute(a)));
20396 ret_val.0 = unsafe {
20397 simd_shuffle!(
20398 ret_val.0,
20399 ret_val.0,
20400 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20401 )
20402 };
20403 ret_val.1 = unsafe {
20404 simd_shuffle!(
20405 ret_val.1,
20406 ret_val.1,
20407 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
20408 )
20409 };
20410 ret_val
20411}
20412#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20414#[doc = "## Safety"]
20415#[doc = " * Neon instrinsic unsafe"]
20416#[inline]
20417#[cfg(target_endian = "little")]
20418#[target_feature(enable = "neon")]
20419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20421#[cfg_attr(
20422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20423 assert_instr(ld2r)
20424)]
20425#[cfg_attr(
20426 not(target_arch = "arm"),
20427 stable(feature = "neon_intrinsics", since = "1.59.0")
20428)]
20429#[cfg_attr(
20430 target_arch = "arm",
20431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20432)]
20433pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20434 transmute(vld2_dup_s16(transmute(a)))
20435}
20436#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
20438#[doc = "## Safety"]
20439#[doc = " * Neon instrinsic unsafe"]
20440#[inline]
20441#[cfg(target_endian = "big")]
20442#[target_feature(enable = "neon")]
20443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20445#[cfg_attr(
20446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20447 assert_instr(ld2r)
20448)]
20449#[cfg_attr(
20450 not(target_arch = "arm"),
20451 stable(feature = "neon_intrinsics", since = "1.59.0")
20452)]
20453#[cfg_attr(
20454 target_arch = "arm",
20455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20456)]
20457pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
20458 let mut ret_val: poly16x4x2_t = transmute(vld2_dup_s16(transmute(a)));
20459 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
20460 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
20461 ret_val
20462}
20463#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20465#[doc = "## Safety"]
20466#[doc = " * Neon instrinsic unsafe"]
20467#[inline]
20468#[cfg(target_endian = "little")]
20469#[target_feature(enable = "neon")]
20470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20472#[cfg_attr(
20473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20474 assert_instr(ld2r)
20475)]
20476#[cfg_attr(
20477 not(target_arch = "arm"),
20478 stable(feature = "neon_intrinsics", since = "1.59.0")
20479)]
20480#[cfg_attr(
20481 target_arch = "arm",
20482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20483)]
20484pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20485 transmute(vld2q_dup_s16(transmute(a)))
20486}
20487#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
20489#[doc = "## Safety"]
20490#[doc = " * Neon instrinsic unsafe"]
20491#[inline]
20492#[cfg(target_endian = "big")]
20493#[target_feature(enable = "neon")]
20494#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20496#[cfg_attr(
20497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20498 assert_instr(ld2r)
20499)]
20500#[cfg_attr(
20501 not(target_arch = "arm"),
20502 stable(feature = "neon_intrinsics", since = "1.59.0")
20503)]
20504#[cfg_attr(
20505 target_arch = "arm",
20506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
20507)]
20508pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
20509 let mut ret_val: poly16x8x2_t = transmute(vld2q_dup_s16(transmute(a)));
20510 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
20511 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
20512 ret_val
20513}
20514#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20516#[doc = "## Safety"]
20517#[doc = " * Neon instrinsic unsafe"]
20518#[inline]
20519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20520#[cfg(target_arch = "arm")]
20521#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20522#[target_feature(enable = "neon,fp16")]
20523#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20524pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20525 unsafe extern "unadjusted" {
20526 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f16.p0")]
20527 fn _vld2_f16(ptr: *const f16, size: i32) -> float16x4x2_t;
20528 }
20529 _vld2_f16(a as _, 2)
20530}
20531#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20533#[doc = "## Safety"]
20534#[doc = " * Neon instrinsic unsafe"]
20535#[inline]
20536#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
20537#[cfg(target_arch = "arm")]
20538#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
20539#[target_feature(enable = "neon,fp16")]
20540#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20541pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20542 unsafe extern "unadjusted" {
20543 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8f16.p0")]
20544 fn _vld2q_f16(ptr: *const f16, size: i32) -> float16x8x2_t;
20545 }
20546 _vld2q_f16(a as _, 2)
20547}
20548#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
20550#[doc = "## Safety"]
20551#[doc = " * Neon instrinsic unsafe"]
20552#[inline]
20553#[cfg(not(target_arch = "arm"))]
20554#[cfg_attr(
20555 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20556 assert_instr(ld2)
20557)]
20558#[target_feature(enable = "neon,fp16")]
20559#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20560pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
20561 unsafe extern "unadjusted" {
20562 #[cfg_attr(
20563 any(target_arch = "aarch64", target_arch = "arm64ec"),
20564 link_name = "llvm.aarch64.neon.ld2.v4f16.p0"
20565 )]
20566 fn _vld2_f16(ptr: *const f16) -> float16x4x2_t;
20567 }
20568 _vld2_f16(a as _)
20569}
20570#[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
20571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
20572#[doc = "## Safety"]
20573#[doc = " * Neon instrinsic unsafe"]
20574#[inline]
20575#[cfg(not(target_arch = "arm"))]
20576#[cfg_attr(
20577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20578 assert_instr(ld2)
20579)]
20580#[target_feature(enable = "neon,fp16")]
20581#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20582pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
20583 unsafe extern "unadjusted" {
20584 #[cfg_attr(
20585 any(target_arch = "aarch64", target_arch = "arm64ec"),
20586 link_name = "llvm.aarch64.neon.ld2.v8f16.p0"
20587 )]
20588 fn _vld2q_f16(ptr: *const f16) -> float16x8x2_t;
20589 }
20590 _vld2q_f16(a as _)
20591}
20592#[doc = "Load multiple 2-element structures to two registers"]
20593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20594#[doc = "## Safety"]
20595#[doc = " * Neon instrinsic unsafe"]
20596#[inline]
20597#[target_feature(enable = "neon,v7")]
20598#[cfg(target_arch = "arm")]
20599#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20600#[cfg_attr(test, assert_instr(vld2))]
20601pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20602 unsafe extern "unadjusted" {
20603 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32")]
20604 fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t;
20605 }
20606 _vld2_f32(a as *const i8, 4)
20607}
20608#[doc = "Load multiple 2-element structures to two registers"]
20609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20610#[doc = "## Safety"]
20611#[doc = " * Neon instrinsic unsafe"]
20612#[inline]
20613#[target_feature(enable = "neon,v7")]
20614#[cfg(target_arch = "arm")]
20615#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20616#[cfg_attr(test, assert_instr(vld2))]
20617pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20618 unsafe extern "unadjusted" {
20619 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32")]
20620 fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t;
20621 }
20622 _vld2q_f32(a as *const i8, 4)
20623}
20624#[doc = "Load multiple 2-element structures to two registers"]
20625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20626#[doc = "## Safety"]
20627#[doc = " * Neon instrinsic unsafe"]
20628#[inline]
20629#[target_feature(enable = "neon,v7")]
20630#[cfg(target_arch = "arm")]
20631#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20632#[cfg_attr(test, assert_instr(vld2))]
20633pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20634 unsafe extern "unadjusted" {
20635 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8")]
20636 fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t;
20637 }
20638 _vld2_s8(a as *const i8, 1)
20639}
20640#[doc = "Load multiple 2-element structures to two registers"]
20641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20642#[doc = "## Safety"]
20643#[doc = " * Neon instrinsic unsafe"]
20644#[inline]
20645#[target_feature(enable = "neon,v7")]
20646#[cfg(target_arch = "arm")]
20647#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20648#[cfg_attr(test, assert_instr(vld2))]
20649pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20650 unsafe extern "unadjusted" {
20651 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8")]
20652 fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t;
20653 }
20654 _vld2q_s8(a as *const i8, 1)
20655}
20656#[doc = "Load multiple 2-element structures to two registers"]
20657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20658#[doc = "## Safety"]
20659#[doc = " * Neon instrinsic unsafe"]
20660#[inline]
20661#[target_feature(enable = "neon,v7")]
20662#[cfg(target_arch = "arm")]
20663#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20664#[cfg_attr(test, assert_instr(vld2))]
20665pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20666 unsafe extern "unadjusted" {
20667 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16")]
20668 fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t;
20669 }
20670 _vld2_s16(a as *const i8, 2)
20671}
20672#[doc = "Load multiple 2-element structures to two registers"]
20673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20674#[doc = "## Safety"]
20675#[doc = " * Neon instrinsic unsafe"]
20676#[inline]
20677#[target_feature(enable = "neon,v7")]
20678#[cfg(target_arch = "arm")]
20679#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20680#[cfg_attr(test, assert_instr(vld2))]
20681pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20682 unsafe extern "unadjusted" {
20683 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16")]
20684 fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t;
20685 }
20686 _vld2q_s16(a as *const i8, 2)
20687}
20688#[doc = "Load multiple 2-element structures to two registers"]
20689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20690#[doc = "## Safety"]
20691#[doc = " * Neon instrinsic unsafe"]
20692#[inline]
20693#[target_feature(enable = "neon,v7")]
20694#[cfg(target_arch = "arm")]
20695#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20696#[cfg_attr(test, assert_instr(vld2))]
20697pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20698 unsafe extern "unadjusted" {
20699 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32")]
20700 fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t;
20701 }
20702 _vld2_s32(a as *const i8, 4)
20703}
20704#[doc = "Load multiple 2-element structures to two registers"]
20705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20706#[doc = "## Safety"]
20707#[doc = " * Neon instrinsic unsafe"]
20708#[inline]
20709#[target_feature(enable = "neon,v7")]
20710#[cfg(target_arch = "arm")]
20711#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
20712#[cfg_attr(test, assert_instr(vld2))]
20713pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20714 unsafe extern "unadjusted" {
20715 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32")]
20716 fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t;
20717 }
20718 _vld2q_s32(a as *const i8, 4)
20719}
20720#[doc = "Load multiple 2-element structures to two registers"]
20721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
20722#[doc = "## Safety"]
20723#[doc = " * Neon instrinsic unsafe"]
20724#[inline]
20725#[target_feature(enable = "neon")]
20726#[cfg(not(target_arch = "arm"))]
20727#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20728#[cfg_attr(test, assert_instr(ld2))]
20729pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
20730 unsafe extern "unadjusted" {
20731 #[cfg_attr(
20732 any(target_arch = "aarch64", target_arch = "arm64ec"),
20733 link_name = "llvm.aarch64.neon.ld2.v2f32.p0"
20734 )]
20735 fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t;
20736 }
20737 _vld2_f32(a as _)
20738}
20739#[doc = "Load multiple 2-element structures to two registers"]
20740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
20741#[doc = "## Safety"]
20742#[doc = " * Neon instrinsic unsafe"]
20743#[inline]
20744#[target_feature(enable = "neon")]
20745#[cfg(not(target_arch = "arm"))]
20746#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20747#[cfg_attr(test, assert_instr(ld2))]
20748pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
20749 unsafe extern "unadjusted" {
20750 #[cfg_attr(
20751 any(target_arch = "aarch64", target_arch = "arm64ec"),
20752 link_name = "llvm.aarch64.neon.ld2.v4f32.p0"
20753 )]
20754 fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t;
20755 }
20756 _vld2q_f32(a as _)
20757}
20758#[doc = "Load multiple 2-element structures to two registers"]
20759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
20760#[doc = "## Safety"]
20761#[doc = " * Neon instrinsic unsafe"]
20762#[inline]
20763#[target_feature(enable = "neon")]
20764#[cfg(not(target_arch = "arm"))]
20765#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20766#[cfg_attr(test, assert_instr(ld2))]
20767pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
20768 unsafe extern "unadjusted" {
20769 #[cfg_attr(
20770 any(target_arch = "aarch64", target_arch = "arm64ec"),
20771 link_name = "llvm.aarch64.neon.ld2.v8i8.p0"
20772 )]
20773 fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t;
20774 }
20775 _vld2_s8(a as _)
20776}
20777#[doc = "Load multiple 2-element structures to two registers"]
20778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
20779#[doc = "## Safety"]
20780#[doc = " * Neon instrinsic unsafe"]
20781#[inline]
20782#[target_feature(enable = "neon")]
20783#[cfg(not(target_arch = "arm"))]
20784#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20785#[cfg_attr(test, assert_instr(ld2))]
20786pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
20787 unsafe extern "unadjusted" {
20788 #[cfg_attr(
20789 any(target_arch = "aarch64", target_arch = "arm64ec"),
20790 link_name = "llvm.aarch64.neon.ld2.v16i8.p0"
20791 )]
20792 fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t;
20793 }
20794 _vld2q_s8(a as _)
20795}
20796#[doc = "Load multiple 2-element structures to two registers"]
20797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
20798#[doc = "## Safety"]
20799#[doc = " * Neon instrinsic unsafe"]
20800#[inline]
20801#[target_feature(enable = "neon")]
20802#[cfg(not(target_arch = "arm"))]
20803#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20804#[cfg_attr(test, assert_instr(ld2))]
20805pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
20806 unsafe extern "unadjusted" {
20807 #[cfg_attr(
20808 any(target_arch = "aarch64", target_arch = "arm64ec"),
20809 link_name = "llvm.aarch64.neon.ld2.v4i16.p0"
20810 )]
20811 fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t;
20812 }
20813 _vld2_s16(a as _)
20814}
20815#[doc = "Load multiple 2-element structures to two registers"]
20816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
20817#[doc = "## Safety"]
20818#[doc = " * Neon instrinsic unsafe"]
20819#[inline]
20820#[target_feature(enable = "neon")]
20821#[cfg(not(target_arch = "arm"))]
20822#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20823#[cfg_attr(test, assert_instr(ld2))]
20824pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
20825 unsafe extern "unadjusted" {
20826 #[cfg_attr(
20827 any(target_arch = "aarch64", target_arch = "arm64ec"),
20828 link_name = "llvm.aarch64.neon.ld2.v8i16.p0"
20829 )]
20830 fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t;
20831 }
20832 _vld2q_s16(a as _)
20833}
20834#[doc = "Load multiple 2-element structures to two registers"]
20835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
20836#[doc = "## Safety"]
20837#[doc = " * Neon instrinsic unsafe"]
20838#[inline]
20839#[target_feature(enable = "neon")]
20840#[cfg(not(target_arch = "arm"))]
20841#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20842#[cfg_attr(test, assert_instr(ld2))]
20843pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
20844 unsafe extern "unadjusted" {
20845 #[cfg_attr(
20846 any(target_arch = "aarch64", target_arch = "arm64ec"),
20847 link_name = "llvm.aarch64.neon.ld2.v2i32.p0"
20848 )]
20849 fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t;
20850 }
20851 _vld2_s32(a as _)
20852}
20853#[doc = "Load multiple 2-element structures to two registers"]
20854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
20855#[doc = "## Safety"]
20856#[doc = " * Neon instrinsic unsafe"]
20857#[inline]
20858#[target_feature(enable = "neon")]
20859#[cfg(not(target_arch = "arm"))]
20860#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20861#[cfg_attr(test, assert_instr(ld2))]
20862pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
20863 unsafe extern "unadjusted" {
20864 #[cfg_attr(
20865 any(target_arch = "aarch64", target_arch = "arm64ec"),
20866 link_name = "llvm.aarch64.neon.ld2.v4i32.p0"
20867 )]
20868 fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t;
20869 }
20870 _vld2q_s32(a as _)
20871}
20872#[doc = "Load multiple 2-element structures to two registers"]
20873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
20874#[doc = "## Safety"]
20875#[doc = " * Neon instrinsic unsafe"]
20876#[inline]
20877#[target_feature(enable = "neon,v7")]
20878#[cfg(target_arch = "arm")]
20879#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
20880#[rustc_legacy_const_generics(2)]
20881#[target_feature(enable = "neon,fp16")]
20882#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20883pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
20884 static_assert_uimm_bits!(LANE, 2);
20885 unsafe extern "unadjusted" {
20886 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f16.p0")]
20887 fn _vld2_lane_f16(
20888 ptr: *const f16,
20889 a: float16x4_t,
20890 b: float16x4_t,
20891 n: i32,
20892 size: i32,
20893 ) -> float16x4x2_t;
20894 }
20895 _vld2_lane_f16(a as _, b.0, b.1, LANE, 2)
20896}
20897#[doc = "Load multiple 2-element structures to two registers"]
20898#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
20899#[doc = "## Safety"]
20900#[doc = " * Neon instrinsic unsafe"]
20901#[inline]
20902#[target_feature(enable = "neon,v7")]
20903#[cfg(target_arch = "arm")]
20904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
20905#[rustc_legacy_const_generics(2)]
20906#[target_feature(enable = "neon,fp16")]
20907#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20908pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
20909 static_assert_uimm_bits!(LANE, 3);
20910 unsafe extern "unadjusted" {
20911 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8f16.p0")]
20912 fn _vld2q_lane_f16(
20913 ptr: *const f16,
20914 a: float16x8_t,
20915 b: float16x8_t,
20916 n: i32,
20917 size: i32,
20918 ) -> float16x8x2_t;
20919 }
20920 _vld2q_lane_f16(a as _, b.0, b.1, LANE, 2)
20921}
20922#[doc = "Load multiple 2-element structures to two registers"]
20923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
20924#[doc = "## Safety"]
20925#[doc = " * Neon instrinsic unsafe"]
20926#[inline]
20927#[cfg(not(target_arch = "arm"))]
20928#[cfg_attr(
20929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20930 assert_instr(ld2, LANE = 0)
20931)]
20932#[rustc_legacy_const_generics(2)]
20933#[target_feature(enable = "neon,fp16")]
20934#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20935pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) -> float16x4x2_t {
20936 static_assert_uimm_bits!(LANE, 2);
20937 unsafe extern "unadjusted" {
20938 #[cfg_attr(
20939 any(target_arch = "aarch64", target_arch = "arm64ec"),
20940 link_name = "llvm.aarch64.neon.ld2lane.v4f16.p0"
20941 )]
20942 fn _vld2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *const f16)
20943 -> float16x4x2_t;
20944 }
20945 _vld2_lane_f16(b.0, b.1, LANE as i64, a as _)
20946}
20947#[doc = "Load multiple 2-element structures to two registers"]
20948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
20949#[doc = "## Safety"]
20950#[doc = " * Neon instrinsic unsafe"]
20951#[inline]
20952#[cfg(not(target_arch = "arm"))]
20953#[cfg_attr(
20954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
20955 assert_instr(ld2, LANE = 0)
20956)]
20957#[rustc_legacy_const_generics(2)]
20958#[target_feature(enable = "neon,fp16")]
20959#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
20960pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -> float16x8x2_t {
20961 static_assert_uimm_bits!(LANE, 3);
20962 unsafe extern "unadjusted" {
20963 #[cfg_attr(
20964 any(target_arch = "aarch64", target_arch = "arm64ec"),
20965 link_name = "llvm.aarch64.neon.ld2lane.v8f16.p0"
20966 )]
20967 fn _vld2q_lane_f16(
20968 a: float16x8_t,
20969 b: float16x8_t,
20970 n: i64,
20971 ptr: *const f16,
20972 ) -> float16x8x2_t;
20973 }
20974 _vld2q_lane_f16(b.0, b.1, LANE as i64, a as _)
20975}
20976#[doc = "Load multiple 2-element structures to two registers"]
20977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
20978#[doc = "## Safety"]
20979#[doc = " * Neon instrinsic unsafe"]
20980#[inline]
20981#[target_feature(enable = "neon")]
20982#[cfg(not(target_arch = "arm"))]
20983#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
20984#[rustc_legacy_const_generics(2)]
20985#[stable(feature = "neon_intrinsics", since = "1.59.0")]
20986pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
20987 static_assert_uimm_bits!(LANE, 2);
20988 unsafe extern "unadjusted" {
20989 #[cfg_attr(
20990 any(target_arch = "aarch64", target_arch = "arm64ec"),
20991 link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0"
20992 )]
20993 fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t;
20994 }
20995 _vld2_lane_f32(b.0, b.1, LANE as i64, a as _)
20996}
20997#[doc = "Load multiple 2-element structures to two registers"]
20998#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
20999#[doc = "## Safety"]
21000#[doc = " * Neon instrinsic unsafe"]
21001#[inline]
21002#[target_feature(enable = "neon")]
21003#[cfg(not(target_arch = "arm"))]
21004#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21005#[rustc_legacy_const_generics(2)]
21006#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21007pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21008 static_assert_uimm_bits!(LANE, 2);
21009 unsafe extern "unadjusted" {
21010 #[cfg_attr(
21011 any(target_arch = "aarch64", target_arch = "arm64ec"),
21012 link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0"
21013 )]
21014 fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8)
21015 -> float32x4x2_t;
21016 }
21017 _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _)
21018}
21019#[doc = "Load multiple 2-element structures to two registers"]
21020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21021#[doc = "## Safety"]
21022#[doc = " * Neon instrinsic unsafe"]
21023#[inline]
21024#[target_feature(enable = "neon")]
21025#[cfg(not(target_arch = "arm"))]
21026#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21027#[rustc_legacy_const_generics(2)]
21028#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21029pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21030 static_assert_uimm_bits!(LANE, 3);
21031 unsafe extern "unadjusted" {
21032 #[cfg_attr(
21033 any(target_arch = "aarch64", target_arch = "arm64ec"),
21034 link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0"
21035 )]
21036 fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t;
21037 }
21038 _vld2_lane_s8(b.0, b.1, LANE as i64, a as _)
21039}
21040#[doc = "Load multiple 2-element structures to two registers"]
21041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21042#[doc = "## Safety"]
21043#[doc = " * Neon instrinsic unsafe"]
21044#[inline]
21045#[target_feature(enable = "neon")]
21046#[cfg(not(target_arch = "arm"))]
21047#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21048#[rustc_legacy_const_generics(2)]
21049#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21050pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21051 static_assert_uimm_bits!(LANE, 2);
21052 unsafe extern "unadjusted" {
21053 #[cfg_attr(
21054 any(target_arch = "aarch64", target_arch = "arm64ec"),
21055 link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0"
21056 )]
21057 fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t;
21058 }
21059 _vld2_lane_s16(b.0, b.1, LANE as i64, a as _)
21060}
21061#[doc = "Load multiple 2-element structures to two registers"]
21062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21063#[doc = "## Safety"]
21064#[doc = " * Neon instrinsic unsafe"]
21065#[inline]
21066#[target_feature(enable = "neon")]
21067#[cfg(not(target_arch = "arm"))]
21068#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21069#[rustc_legacy_const_generics(2)]
21070#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21071pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21072 static_assert_uimm_bits!(LANE, 3);
21073 unsafe extern "unadjusted" {
21074 #[cfg_attr(
21075 any(target_arch = "aarch64", target_arch = "arm64ec"),
21076 link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0"
21077 )]
21078 fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t;
21079 }
21080 _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _)
21081}
21082#[doc = "Load multiple 2-element structures to two registers"]
21083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21084#[doc = "## Safety"]
21085#[doc = " * Neon instrinsic unsafe"]
21086#[inline]
21087#[target_feature(enable = "neon")]
21088#[cfg(not(target_arch = "arm"))]
21089#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21090#[rustc_legacy_const_generics(2)]
21091#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21092pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21093 static_assert_uimm_bits!(LANE, 1);
21094 unsafe extern "unadjusted" {
21095 #[cfg_attr(
21096 any(target_arch = "aarch64", target_arch = "arm64ec"),
21097 link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0"
21098 )]
21099 fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t;
21100 }
21101 _vld2_lane_s32(b.0, b.1, LANE as i64, a as _)
21102}
21103#[doc = "Load multiple 2-element structures to two registers"]
21104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21105#[doc = "## Safety"]
21106#[doc = " * Neon instrinsic unsafe"]
21107#[inline]
21108#[target_feature(enable = "neon")]
21109#[cfg(not(target_arch = "arm"))]
21110#[cfg_attr(test, assert_instr(ld2, LANE = 0))]
21111#[rustc_legacy_const_generics(2)]
21112#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21113pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21114 static_assert_uimm_bits!(LANE, 2);
21115 unsafe extern "unadjusted" {
21116 #[cfg_attr(
21117 any(target_arch = "aarch64", target_arch = "arm64ec"),
21118 link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0"
21119 )]
21120 fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t;
21121 }
21122 _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _)
21123}
21124#[doc = "Load multiple 2-element structures to two registers"]
21125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
21126#[doc = "## Safety"]
21127#[doc = " * Neon instrinsic unsafe"]
21128#[inline]
21129#[target_feature(enable = "neon,v7")]
21130#[cfg(target_arch = "arm")]
21131#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21132#[rustc_legacy_const_generics(2)]
21133#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21134pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) -> float32x2x2_t {
21135 static_assert_uimm_bits!(LANE, 1);
21136 unsafe extern "unadjusted" {
21137 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0")]
21138 fn _vld2_lane_f32(
21139 ptr: *const i8,
21140 a: float32x2_t,
21141 b: float32x2_t,
21142 n: i32,
21143 size: i32,
21144 ) -> float32x2x2_t;
21145 }
21146 _vld2_lane_f32(a as _, b.0, b.1, LANE, 4)
21147}
21148#[doc = "Load multiple 2-element structures to two registers"]
21149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
21150#[doc = "## Safety"]
21151#[doc = " * Neon instrinsic unsafe"]
21152#[inline]
21153#[target_feature(enable = "neon,v7")]
21154#[cfg(target_arch = "arm")]
21155#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21156#[rustc_legacy_const_generics(2)]
21157#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21158pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -> float32x4x2_t {
21159 static_assert_uimm_bits!(LANE, 2);
21160 unsafe extern "unadjusted" {
21161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0")]
21162 fn _vld2q_lane_f32(
21163 ptr: *const i8,
21164 a: float32x4_t,
21165 b: float32x4_t,
21166 n: i32,
21167 size: i32,
21168 ) -> float32x4x2_t;
21169 }
21170 _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4)
21171}
21172#[doc = "Load multiple 2-element structures to two registers"]
21173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
21174#[doc = "## Safety"]
21175#[doc = " * Neon instrinsic unsafe"]
21176#[inline]
21177#[target_feature(enable = "neon,v7")]
21178#[cfg(target_arch = "arm")]
21179#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21180#[rustc_legacy_const_generics(2)]
21181#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21182pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) -> int16x8x2_t {
21183 static_assert_uimm_bits!(LANE, 3);
21184 unsafe extern "unadjusted" {
21185 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0")]
21186 fn _vld2q_lane_s16(
21187 ptr: *const i8,
21188 a: int16x8_t,
21189 b: int16x8_t,
21190 n: i32,
21191 size: i32,
21192 ) -> int16x8x2_t;
21193 }
21194 _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2)
21195}
21196#[doc = "Load multiple 2-element structures to two registers"]
21197#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
21198#[doc = "## Safety"]
21199#[doc = " * Neon instrinsic unsafe"]
21200#[inline]
21201#[target_feature(enable = "neon,v7")]
21202#[cfg(target_arch = "arm")]
21203#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21204#[rustc_legacy_const_generics(2)]
21205#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21206pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) -> int32x4x2_t {
21207 static_assert_uimm_bits!(LANE, 2);
21208 unsafe extern "unadjusted" {
21209 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0")]
21210 fn _vld2q_lane_s32(
21211 ptr: *const i8,
21212 a: int32x4_t,
21213 b: int32x4_t,
21214 n: i32,
21215 size: i32,
21216 ) -> int32x4x2_t;
21217 }
21218 _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4)
21219}
21220#[doc = "Load multiple 2-element structures to two registers"]
21221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
21222#[doc = "## Safety"]
21223#[doc = " * Neon instrinsic unsafe"]
21224#[inline]
21225#[target_feature(enable = "neon,v7")]
21226#[cfg(target_arch = "arm")]
21227#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21228#[rustc_legacy_const_generics(2)]
21229#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21230pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8x8x2_t {
21231 static_assert_uimm_bits!(LANE, 3);
21232 unsafe extern "unadjusted" {
21233 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0")]
21234 fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32)
21235 -> int8x8x2_t;
21236 }
21237 _vld2_lane_s8(a as _, b.0, b.1, LANE, 1)
21238}
21239#[doc = "Load multiple 2-element structures to two registers"]
21240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
21241#[doc = "## Safety"]
21242#[doc = " * Neon instrinsic unsafe"]
21243#[inline]
21244#[target_feature(enable = "neon,v7")]
21245#[cfg(target_arch = "arm")]
21246#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21247#[rustc_legacy_const_generics(2)]
21248#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21249pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> int16x4x2_t {
21250 static_assert_uimm_bits!(LANE, 2);
21251 unsafe extern "unadjusted" {
21252 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0")]
21253 fn _vld2_lane_s16(
21254 ptr: *const i8,
21255 a: int16x4_t,
21256 b: int16x4_t,
21257 n: i32,
21258 size: i32,
21259 ) -> int16x4x2_t;
21260 }
21261 _vld2_lane_s16(a as _, b.0, b.1, LANE, 2)
21262}
21263#[doc = "Load multiple 2-element structures to two registers"]
21264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
21265#[doc = "## Safety"]
21266#[doc = " * Neon instrinsic unsafe"]
21267#[inline]
21268#[target_feature(enable = "neon,v7")]
21269#[cfg(target_arch = "arm")]
21270#[cfg_attr(test, assert_instr(vld2, LANE = 0))]
21271#[rustc_legacy_const_generics(2)]
21272#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21273pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> int32x2x2_t {
21274 static_assert_uimm_bits!(LANE, 1);
21275 unsafe extern "unadjusted" {
21276 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0")]
21277 fn _vld2_lane_s32(
21278 ptr: *const i8,
21279 a: int32x2_t,
21280 b: int32x2_t,
21281 n: i32,
21282 size: i32,
21283 ) -> int32x2x2_t;
21284 }
21285 _vld2_lane_s32(a as _, b.0, b.1, LANE, 4)
21286}
21287#[doc = "Load multiple 2-element structures to two registers"]
21288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
21289#[doc = "## Safety"]
21290#[doc = " * Neon instrinsic unsafe"]
21291#[inline]
21292#[target_feature(enable = "neon")]
21293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21295#[cfg_attr(
21296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21297 assert_instr(ld2, LANE = 0)
21298)]
21299#[rustc_legacy_const_generics(2)]
21300#[cfg_attr(
21301 not(target_arch = "arm"),
21302 stable(feature = "neon_intrinsics", since = "1.59.0")
21303)]
21304#[cfg_attr(
21305 target_arch = "arm",
21306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21307)]
21308pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t {
21309 static_assert_uimm_bits!(LANE, 3);
21310 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21311}
21312#[doc = "Load multiple 2-element structures to two registers"]
21313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
21314#[doc = "## Safety"]
21315#[doc = " * Neon instrinsic unsafe"]
21316#[inline]
21317#[target_feature(enable = "neon")]
21318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21320#[cfg_attr(
21321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21322 assert_instr(ld2, LANE = 0)
21323)]
21324#[rustc_legacy_const_generics(2)]
21325#[cfg_attr(
21326 not(target_arch = "arm"),
21327 stable(feature = "neon_intrinsics", since = "1.59.0")
21328)]
21329#[cfg_attr(
21330 target_arch = "arm",
21331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21332)]
21333pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t {
21334 static_assert_uimm_bits!(LANE, 2);
21335 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21336}
21337#[doc = "Load multiple 2-element structures to two registers"]
21338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
21339#[doc = "## Safety"]
21340#[doc = " * Neon instrinsic unsafe"]
21341#[inline]
21342#[target_feature(enable = "neon")]
21343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21345#[cfg_attr(
21346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21347 assert_instr(ld2, LANE = 0)
21348)]
21349#[rustc_legacy_const_generics(2)]
21350#[cfg_attr(
21351 not(target_arch = "arm"),
21352 stable(feature = "neon_intrinsics", since = "1.59.0")
21353)]
21354#[cfg_attr(
21355 target_arch = "arm",
21356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21357)]
21358pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t {
21359 static_assert_uimm_bits!(LANE, 3);
21360 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21361}
21362#[doc = "Load multiple 2-element structures to two registers"]
21363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
21364#[doc = "## Safety"]
21365#[doc = " * Neon instrinsic unsafe"]
21366#[inline]
21367#[target_feature(enable = "neon")]
21368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21370#[cfg_attr(
21371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21372 assert_instr(ld2, LANE = 0)
21373)]
21374#[rustc_legacy_const_generics(2)]
21375#[cfg_attr(
21376 not(target_arch = "arm"),
21377 stable(feature = "neon_intrinsics", since = "1.59.0")
21378)]
21379#[cfg_attr(
21380 target_arch = "arm",
21381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21382)]
21383pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t {
21384 static_assert_uimm_bits!(LANE, 1);
21385 transmute(vld2_lane_s32::<LANE>(transmute(a), transmute(b)))
21386}
21387#[doc = "Load multiple 2-element structures to two registers"]
21388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
21389#[doc = "## Safety"]
21390#[doc = " * Neon instrinsic unsafe"]
21391#[inline]
21392#[target_feature(enable = "neon")]
21393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21395#[cfg_attr(
21396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21397 assert_instr(ld2, LANE = 0)
21398)]
21399#[rustc_legacy_const_generics(2)]
21400#[cfg_attr(
21401 not(target_arch = "arm"),
21402 stable(feature = "neon_intrinsics", since = "1.59.0")
21403)]
21404#[cfg_attr(
21405 target_arch = "arm",
21406 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21407)]
21408pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t {
21409 static_assert_uimm_bits!(LANE, 2);
21410 transmute(vld2q_lane_s32::<LANE>(transmute(a), transmute(b)))
21411}
21412#[doc = "Load multiple 2-element structures to two registers"]
21413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
21414#[doc = "## Safety"]
21415#[doc = " * Neon instrinsic unsafe"]
21416#[inline]
21417#[target_feature(enable = "neon")]
21418#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21419#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21420#[cfg_attr(
21421 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21422 assert_instr(ld2, LANE = 0)
21423)]
21424#[rustc_legacy_const_generics(2)]
21425#[cfg_attr(
21426 not(target_arch = "arm"),
21427 stable(feature = "neon_intrinsics", since = "1.59.0")
21428)]
21429#[cfg_attr(
21430 target_arch = "arm",
21431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21432)]
21433pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t {
21434 static_assert_uimm_bits!(LANE, 3);
21435 transmute(vld2_lane_s8::<LANE>(transmute(a), transmute(b)))
21436}
21437#[doc = "Load multiple 2-element structures to two registers"]
21438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
21439#[doc = "## Safety"]
21440#[doc = " * Neon instrinsic unsafe"]
21441#[inline]
21442#[target_feature(enable = "neon")]
21443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21445#[cfg_attr(
21446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21447 assert_instr(ld2, LANE = 0)
21448)]
21449#[rustc_legacy_const_generics(2)]
21450#[cfg_attr(
21451 not(target_arch = "arm"),
21452 stable(feature = "neon_intrinsics", since = "1.59.0")
21453)]
21454#[cfg_attr(
21455 target_arch = "arm",
21456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21457)]
21458pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t {
21459 static_assert_uimm_bits!(LANE, 2);
21460 transmute(vld2_lane_s16::<LANE>(transmute(a), transmute(b)))
21461}
21462#[doc = "Load multiple 2-element structures to two registers"]
21463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
21464#[doc = "## Safety"]
21465#[doc = " * Neon instrinsic unsafe"]
21466#[inline]
21467#[target_feature(enable = "neon")]
21468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
21470#[cfg_attr(
21471 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21472 assert_instr(ld2, LANE = 0)
21473)]
21474#[rustc_legacy_const_generics(2)]
21475#[cfg_attr(
21476 not(target_arch = "arm"),
21477 stable(feature = "neon_intrinsics", since = "1.59.0")
21478)]
21479#[cfg_attr(
21480 target_arch = "arm",
21481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21482)]
21483pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t {
21484 static_assert_uimm_bits!(LANE, 3);
21485 transmute(vld2q_lane_s16::<LANE>(transmute(a), transmute(b)))
21486}
21487#[doc = "Load multiple 2-element structures to two registers"]
21488#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
21489#[doc = "## Safety"]
21490#[doc = " * Neon instrinsic unsafe"]
21491#[inline]
21492#[target_feature(enable = "neon,aes")]
21493#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
21494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21495#[cfg_attr(
21496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21497 assert_instr(nop)
21498)]
21499#[cfg_attr(
21500 not(target_arch = "arm"),
21501 stable(feature = "neon_intrinsics", since = "1.59.0")
21502)]
21503#[cfg_attr(
21504 target_arch = "arm",
21505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21506)]
21507pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
21508 transmute(vld2_s64(transmute(a)))
21509}
21510#[doc = "Load multiple 2-element structures to two registers"]
21511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21512#[doc = "## Safety"]
21513#[doc = " * Neon instrinsic unsafe"]
21514#[inline]
21515#[target_feature(enable = "neon,v7")]
21516#[cfg(target_arch = "arm")]
21517#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
21518#[cfg_attr(test, assert_instr(nop))]
21519pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21520 unsafe extern "unadjusted" {
21521 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64")]
21522 fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t;
21523 }
21524 _vld2_s64(a as *const i8, 8)
21525}
21526#[doc = "Load multiple 2-element structures to two registers"]
21527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
21528#[doc = "## Safety"]
21529#[doc = " * Neon instrinsic unsafe"]
21530#[inline]
21531#[target_feature(enable = "neon")]
21532#[cfg(not(target_arch = "arm"))]
21533#[stable(feature = "neon_intrinsics", since = "1.59.0")]
21534#[cfg_attr(test, assert_instr(nop))]
21535pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
21536 unsafe extern "unadjusted" {
21537 #[cfg_attr(
21538 any(target_arch = "aarch64", target_arch = "arm64ec"),
21539 link_name = "llvm.aarch64.neon.ld2.v1i64.p0"
21540 )]
21541 fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t;
21542 }
21543 _vld2_s64(a as _)
21544}
21545#[doc = "Load multiple 2-element structures to two registers"]
21546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
21547#[doc = "## Safety"]
21548#[doc = " * Neon instrinsic unsafe"]
21549#[inline]
21550#[target_feature(enable = "neon")]
21551#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21552#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
21553#[cfg_attr(
21554 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21555 assert_instr(nop)
21556)]
21557#[cfg_attr(
21558 not(target_arch = "arm"),
21559 stable(feature = "neon_intrinsics", since = "1.59.0")
21560)]
21561#[cfg_attr(
21562 target_arch = "arm",
21563 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21564)]
21565pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
21566 transmute(vld2_s64(transmute(a)))
21567}
21568#[doc = "Load multiple 2-element structures to two registers"]
21569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21570#[doc = "## Safety"]
21571#[doc = " * Neon instrinsic unsafe"]
21572#[inline]
21573#[cfg(target_endian = "little")]
21574#[target_feature(enable = "neon")]
21575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21577#[cfg_attr(
21578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21579 assert_instr(ld2)
21580)]
21581#[cfg_attr(
21582 not(target_arch = "arm"),
21583 stable(feature = "neon_intrinsics", since = "1.59.0")
21584)]
21585#[cfg_attr(
21586 target_arch = "arm",
21587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21588)]
21589pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21590 transmute(vld2_s8(transmute(a)))
21591}
21592#[doc = "Load multiple 2-element structures to two registers"]
21593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
21594#[doc = "## Safety"]
21595#[doc = " * Neon instrinsic unsafe"]
21596#[inline]
21597#[cfg(target_endian = "big")]
21598#[target_feature(enable = "neon")]
21599#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21601#[cfg_attr(
21602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21603 assert_instr(ld2)
21604)]
21605#[cfg_attr(
21606 not(target_arch = "arm"),
21607 stable(feature = "neon_intrinsics", since = "1.59.0")
21608)]
21609#[cfg_attr(
21610 target_arch = "arm",
21611 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21612)]
21613pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
21614 let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a)));
21615 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21616 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21617 ret_val
21618}
21619#[doc = "Load multiple 2-element structures to two registers"]
21620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21621#[doc = "## Safety"]
21622#[doc = " * Neon instrinsic unsafe"]
21623#[inline]
21624#[cfg(target_endian = "little")]
21625#[target_feature(enable = "neon")]
21626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21628#[cfg_attr(
21629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21630 assert_instr(ld2)
21631)]
21632#[cfg_attr(
21633 not(target_arch = "arm"),
21634 stable(feature = "neon_intrinsics", since = "1.59.0")
21635)]
21636#[cfg_attr(
21637 target_arch = "arm",
21638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21639)]
21640pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21641 transmute(vld2q_s8(transmute(a)))
21642}
21643#[doc = "Load multiple 2-element structures to two registers"]
21644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
21645#[doc = "## Safety"]
21646#[doc = " * Neon instrinsic unsafe"]
21647#[inline]
21648#[cfg(target_endian = "big")]
21649#[target_feature(enable = "neon")]
21650#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21652#[cfg_attr(
21653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21654 assert_instr(ld2)
21655)]
21656#[cfg_attr(
21657 not(target_arch = "arm"),
21658 stable(feature = "neon_intrinsics", since = "1.59.0")
21659)]
21660#[cfg_attr(
21661 target_arch = "arm",
21662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21663)]
21664pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
21665 let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a)));
21666 ret_val.0 = unsafe {
21667 simd_shuffle!(
21668 ret_val.0,
21669 ret_val.0,
21670 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21671 )
21672 };
21673 ret_val.1 = unsafe {
21674 simd_shuffle!(
21675 ret_val.1,
21676 ret_val.1,
21677 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21678 )
21679 };
21680 ret_val
21681}
21682#[doc = "Load multiple 2-element structures to two registers"]
21683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21684#[doc = "## Safety"]
21685#[doc = " * Neon instrinsic unsafe"]
21686#[inline]
21687#[cfg(target_endian = "little")]
21688#[target_feature(enable = "neon")]
21689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21691#[cfg_attr(
21692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21693 assert_instr(ld2)
21694)]
21695#[cfg_attr(
21696 not(target_arch = "arm"),
21697 stable(feature = "neon_intrinsics", since = "1.59.0")
21698)]
21699#[cfg_attr(
21700 target_arch = "arm",
21701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21702)]
21703pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21704 transmute(vld2_s16(transmute(a)))
21705}
21706#[doc = "Load multiple 2-element structures to two registers"]
21707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
21708#[doc = "## Safety"]
21709#[doc = " * Neon instrinsic unsafe"]
21710#[inline]
21711#[cfg(target_endian = "big")]
21712#[target_feature(enable = "neon")]
21713#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21714#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21715#[cfg_attr(
21716 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21717 assert_instr(ld2)
21718)]
21719#[cfg_attr(
21720 not(target_arch = "arm"),
21721 stable(feature = "neon_intrinsics", since = "1.59.0")
21722)]
21723#[cfg_attr(
21724 target_arch = "arm",
21725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21726)]
21727pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
21728 let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a)));
21729 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21730 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21731 ret_val
21732}
21733#[doc = "Load multiple 2-element structures to two registers"]
21734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21735#[doc = "## Safety"]
21736#[doc = " * Neon instrinsic unsafe"]
21737#[inline]
21738#[cfg(target_endian = "little")]
21739#[target_feature(enable = "neon")]
21740#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21741#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21742#[cfg_attr(
21743 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21744 assert_instr(ld2)
21745)]
21746#[cfg_attr(
21747 not(target_arch = "arm"),
21748 stable(feature = "neon_intrinsics", since = "1.59.0")
21749)]
21750#[cfg_attr(
21751 target_arch = "arm",
21752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21753)]
21754pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21755 transmute(vld2q_s16(transmute(a)))
21756}
21757#[doc = "Load multiple 2-element structures to two registers"]
21758#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
21759#[doc = "## Safety"]
21760#[doc = " * Neon instrinsic unsafe"]
21761#[inline]
21762#[cfg(target_endian = "big")]
21763#[target_feature(enable = "neon")]
21764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21766#[cfg_attr(
21767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21768 assert_instr(ld2)
21769)]
21770#[cfg_attr(
21771 not(target_arch = "arm"),
21772 stable(feature = "neon_intrinsics", since = "1.59.0")
21773)]
21774#[cfg_attr(
21775 target_arch = "arm",
21776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21777)]
21778pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
21779 let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a)));
21780 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21781 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21782 ret_val
21783}
21784#[doc = "Load multiple 2-element structures to two registers"]
21785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21786#[doc = "## Safety"]
21787#[doc = " * Neon instrinsic unsafe"]
21788#[inline]
21789#[cfg(target_endian = "little")]
21790#[target_feature(enable = "neon")]
21791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21793#[cfg_attr(
21794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21795 assert_instr(ld2)
21796)]
21797#[cfg_attr(
21798 not(target_arch = "arm"),
21799 stable(feature = "neon_intrinsics", since = "1.59.0")
21800)]
21801#[cfg_attr(
21802 target_arch = "arm",
21803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21804)]
21805pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21806 transmute(vld2_s32(transmute(a)))
21807}
21808#[doc = "Load multiple 2-element structures to two registers"]
21809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
21810#[doc = "## Safety"]
21811#[doc = " * Neon instrinsic unsafe"]
21812#[inline]
21813#[cfg(target_endian = "big")]
21814#[target_feature(enable = "neon")]
21815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21817#[cfg_attr(
21818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21819 assert_instr(ld2)
21820)]
21821#[cfg_attr(
21822 not(target_arch = "arm"),
21823 stable(feature = "neon_intrinsics", since = "1.59.0")
21824)]
21825#[cfg_attr(
21826 target_arch = "arm",
21827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21828)]
21829pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
21830 let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a)));
21831 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
21832 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
21833 ret_val
21834}
21835#[doc = "Load multiple 2-element structures to two registers"]
21836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21837#[doc = "## Safety"]
21838#[doc = " * Neon instrinsic unsafe"]
21839#[inline]
21840#[cfg(target_endian = "little")]
21841#[target_feature(enable = "neon")]
21842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21844#[cfg_attr(
21845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21846 assert_instr(ld2)
21847)]
21848#[cfg_attr(
21849 not(target_arch = "arm"),
21850 stable(feature = "neon_intrinsics", since = "1.59.0")
21851)]
21852#[cfg_attr(
21853 target_arch = "arm",
21854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21855)]
21856pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21857 transmute(vld2q_s32(transmute(a)))
21858}
21859#[doc = "Load multiple 2-element structures to two registers"]
21860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
21861#[doc = "## Safety"]
21862#[doc = " * Neon instrinsic unsafe"]
21863#[inline]
21864#[cfg(target_endian = "big")]
21865#[target_feature(enable = "neon")]
21866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21868#[cfg_attr(
21869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21870 assert_instr(ld2)
21871)]
21872#[cfg_attr(
21873 not(target_arch = "arm"),
21874 stable(feature = "neon_intrinsics", since = "1.59.0")
21875)]
21876#[cfg_attr(
21877 target_arch = "arm",
21878 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21879)]
21880pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
21881 let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a)));
21882 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
21883 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
21884 ret_val
21885}
21886#[doc = "Load multiple 2-element structures to two registers"]
21887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
21888#[doc = "## Safety"]
21889#[doc = " * Neon instrinsic unsafe"]
21890#[inline]
21891#[cfg(target_endian = "little")]
21892#[target_feature(enable = "neon")]
21893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21894#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21895#[cfg_attr(
21896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21897 assert_instr(ld2)
21898)]
21899#[cfg_attr(
21900 not(target_arch = "arm"),
21901 stable(feature = "neon_intrinsics", since = "1.59.0")
21902)]
21903#[cfg_attr(
21904 target_arch = "arm",
21905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21906)]
21907pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
21908 transmute(vld2_s8(transmute(a)))
21909}
21910#[doc = "Load multiple 2-element structures to two registers"]
21911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
21912#[doc = "## Safety"]
21913#[doc = " * Neon instrinsic unsafe"]
21914#[inline]
21915#[cfg(target_endian = "big")]
21916#[target_feature(enable = "neon")]
21917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21919#[cfg_attr(
21920 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21921 assert_instr(ld2)
21922)]
21923#[cfg_attr(
21924 not(target_arch = "arm"),
21925 stable(feature = "neon_intrinsics", since = "1.59.0")
21926)]
21927#[cfg_attr(
21928 target_arch = "arm",
21929 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21930)]
21931pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
21932 let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a)));
21933 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
21934 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
21935 ret_val
21936}
21937#[doc = "Load multiple 2-element structures to two registers"]
21938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
21939#[doc = "## Safety"]
21940#[doc = " * Neon instrinsic unsafe"]
21941#[inline]
21942#[cfg(target_endian = "little")]
21943#[target_feature(enable = "neon")]
21944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21946#[cfg_attr(
21947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21948 assert_instr(ld2)
21949)]
21950#[cfg_attr(
21951 not(target_arch = "arm"),
21952 stable(feature = "neon_intrinsics", since = "1.59.0")
21953)]
21954#[cfg_attr(
21955 target_arch = "arm",
21956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21957)]
21958pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
21959 transmute(vld2q_s8(transmute(a)))
21960}
21961#[doc = "Load multiple 2-element structures to two registers"]
21962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
21963#[doc = "## Safety"]
21964#[doc = " * Neon instrinsic unsafe"]
21965#[inline]
21966#[cfg(target_endian = "big")]
21967#[target_feature(enable = "neon")]
21968#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
21969#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
21970#[cfg_attr(
21971 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
21972 assert_instr(ld2)
21973)]
21974#[cfg_attr(
21975 not(target_arch = "arm"),
21976 stable(feature = "neon_intrinsics", since = "1.59.0")
21977)]
21978#[cfg_attr(
21979 target_arch = "arm",
21980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
21981)]
21982pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
21983 let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a)));
21984 ret_val.0 = unsafe {
21985 simd_shuffle!(
21986 ret_val.0,
21987 ret_val.0,
21988 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21989 )
21990 };
21991 ret_val.1 = unsafe {
21992 simd_shuffle!(
21993 ret_val.1,
21994 ret_val.1,
21995 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
21996 )
21997 };
21998 ret_val
21999}
22000#[doc = "Load multiple 2-element structures to two registers"]
22001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22002#[doc = "## Safety"]
22003#[doc = " * Neon instrinsic unsafe"]
22004#[inline]
22005#[cfg(target_endian = "little")]
22006#[target_feature(enable = "neon")]
22007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22009#[cfg_attr(
22010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22011 assert_instr(ld2)
22012)]
22013#[cfg_attr(
22014 not(target_arch = "arm"),
22015 stable(feature = "neon_intrinsics", since = "1.59.0")
22016)]
22017#[cfg_attr(
22018 target_arch = "arm",
22019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22020)]
22021pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22022 transmute(vld2_s16(transmute(a)))
22023}
22024#[doc = "Load multiple 2-element structures to two registers"]
22025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
22026#[doc = "## Safety"]
22027#[doc = " * Neon instrinsic unsafe"]
22028#[inline]
22029#[cfg(target_endian = "big")]
22030#[target_feature(enable = "neon")]
22031#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22033#[cfg_attr(
22034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22035 assert_instr(ld2)
22036)]
22037#[cfg_attr(
22038 not(target_arch = "arm"),
22039 stable(feature = "neon_intrinsics", since = "1.59.0")
22040)]
22041#[cfg_attr(
22042 target_arch = "arm",
22043 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22044)]
22045pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
22046 let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a)));
22047 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22048 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22049 ret_val
22050}
22051#[doc = "Load multiple 2-element structures to two registers"]
22052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22053#[doc = "## Safety"]
22054#[doc = " * Neon instrinsic unsafe"]
22055#[inline]
22056#[cfg(target_endian = "little")]
22057#[target_feature(enable = "neon")]
22058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22060#[cfg_attr(
22061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22062 assert_instr(ld2)
22063)]
22064#[cfg_attr(
22065 not(target_arch = "arm"),
22066 stable(feature = "neon_intrinsics", since = "1.59.0")
22067)]
22068#[cfg_attr(
22069 target_arch = "arm",
22070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22071)]
22072pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22073 transmute(vld2q_s16(transmute(a)))
22074}
22075#[doc = "Load multiple 2-element structures to two registers"]
22076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
22077#[doc = "## Safety"]
22078#[doc = " * Neon instrinsic unsafe"]
22079#[inline]
22080#[cfg(target_endian = "big")]
22081#[target_feature(enable = "neon")]
22082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22083#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))]
22084#[cfg_attr(
22085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22086 assert_instr(ld2)
22087)]
22088#[cfg_attr(
22089 not(target_arch = "arm"),
22090 stable(feature = "neon_intrinsics", since = "1.59.0")
22091)]
22092#[cfg_attr(
22093 target_arch = "arm",
22094 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22095)]
22096pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
22097 let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a)));
22098 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22099 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22100 ret_val
22101}
22102#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22104#[doc = "## Safety"]
22105#[doc = " * Neon instrinsic unsafe"]
22106#[inline]
22107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22108#[cfg(target_arch = "arm")]
22109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22110#[target_feature(enable = "neon,fp16")]
22111#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22112pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22113 unsafe extern "unadjusted" {
22114 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f16.p0")]
22115 fn _vld3_dup_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
22116 }
22117 _vld3_dup_f16(a as _, 2)
22118}
22119#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22121#[doc = "## Safety"]
22122#[doc = " * Neon instrinsic unsafe"]
22123#[inline]
22124#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22125#[cfg(target_arch = "arm")]
22126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22127#[target_feature(enable = "neon,fp16")]
22128#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22129pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22130 unsafe extern "unadjusted" {
22131 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8f16.p0")]
22132 fn _vld3q_dup_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
22133 }
22134 _vld3q_dup_f16(a as _, 2)
22135}
22136#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
22138#[doc = "## Safety"]
22139#[doc = " * Neon instrinsic unsafe"]
22140#[inline]
22141#[cfg(not(target_arch = "arm"))]
22142#[cfg_attr(
22143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22144 assert_instr(ld3r)
22145)]
22146#[target_feature(enable = "neon,fp16")]
22147#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22148pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
22149 unsafe extern "unadjusted" {
22150 #[cfg_attr(
22151 any(target_arch = "aarch64", target_arch = "arm64ec"),
22152 link_name = "llvm.aarch64.neon.ld3r.v4f16.p0"
22153 )]
22154 fn _vld3_dup_f16(ptr: *const f16) -> float16x4x3_t;
22155 }
22156 _vld3_dup_f16(a as _)
22157}
22158#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
22159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
22160#[doc = "## Safety"]
22161#[doc = " * Neon instrinsic unsafe"]
22162#[inline]
22163#[cfg(not(target_arch = "arm"))]
22164#[cfg_attr(
22165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22166 assert_instr(ld3r)
22167)]
22168#[target_feature(enable = "neon,fp16")]
22169#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
22170pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
22171 unsafe extern "unadjusted" {
22172 #[cfg_attr(
22173 any(target_arch = "aarch64", target_arch = "arm64ec"),
22174 link_name = "llvm.aarch64.neon.ld3r.v8f16.p0"
22175 )]
22176 fn _vld3q_dup_f16(ptr: *const f16) -> float16x8x3_t;
22177 }
22178 _vld3q_dup_f16(a as _)
22179}
22180#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22182#[doc = "## Safety"]
22183#[doc = " * Neon instrinsic unsafe"]
22184#[inline]
22185#[target_feature(enable = "neon")]
22186#[cfg(not(target_arch = "arm"))]
22187#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22188#[cfg_attr(test, assert_instr(ld3r))]
22189pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22190 unsafe extern "unadjusted" {
22191 #[cfg_attr(
22192 any(target_arch = "aarch64", target_arch = "arm64ec"),
22193 link_name = "llvm.aarch64.neon.ld3r.v2f32.p0"
22194 )]
22195 fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t;
22196 }
22197 _vld3_dup_f32(a as _)
22198}
22199#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22201#[doc = "## Safety"]
22202#[doc = " * Neon instrinsic unsafe"]
22203#[inline]
22204#[target_feature(enable = "neon")]
22205#[cfg(not(target_arch = "arm"))]
22206#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22207#[cfg_attr(test, assert_instr(ld3r))]
22208pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22209 unsafe extern "unadjusted" {
22210 #[cfg_attr(
22211 any(target_arch = "aarch64", target_arch = "arm64ec"),
22212 link_name = "llvm.aarch64.neon.ld3r.v4f32.p0"
22213 )]
22214 fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t;
22215 }
22216 _vld3q_dup_f32(a as _)
22217}
22218#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22220#[doc = "## Safety"]
22221#[doc = " * Neon instrinsic unsafe"]
22222#[inline]
22223#[target_feature(enable = "neon")]
22224#[cfg(not(target_arch = "arm"))]
22225#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22226#[cfg_attr(test, assert_instr(ld3r))]
22227pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22228 unsafe extern "unadjusted" {
22229 #[cfg_attr(
22230 any(target_arch = "aarch64", target_arch = "arm64ec"),
22231 link_name = "llvm.aarch64.neon.ld3r.v8i8.p0"
22232 )]
22233 fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t;
22234 }
22235 _vld3_dup_s8(a as _)
22236}
22237#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22238#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22239#[doc = "## Safety"]
22240#[doc = " * Neon instrinsic unsafe"]
22241#[inline]
22242#[target_feature(enable = "neon")]
22243#[cfg(not(target_arch = "arm"))]
22244#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22245#[cfg_attr(test, assert_instr(ld3r))]
22246pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22247 unsafe extern "unadjusted" {
22248 #[cfg_attr(
22249 any(target_arch = "aarch64", target_arch = "arm64ec"),
22250 link_name = "llvm.aarch64.neon.ld3r.v16i8.p0"
22251 )]
22252 fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t;
22253 }
22254 _vld3q_dup_s8(a as _)
22255}
22256#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22258#[doc = "## Safety"]
22259#[doc = " * Neon instrinsic unsafe"]
22260#[inline]
22261#[target_feature(enable = "neon")]
22262#[cfg(not(target_arch = "arm"))]
22263#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22264#[cfg_attr(test, assert_instr(ld3r))]
22265pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22266 unsafe extern "unadjusted" {
22267 #[cfg_attr(
22268 any(target_arch = "aarch64", target_arch = "arm64ec"),
22269 link_name = "llvm.aarch64.neon.ld3r.v4i16.p0"
22270 )]
22271 fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t;
22272 }
22273 _vld3_dup_s16(a as _)
22274}
22275#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22277#[doc = "## Safety"]
22278#[doc = " * Neon instrinsic unsafe"]
22279#[inline]
22280#[target_feature(enable = "neon")]
22281#[cfg(not(target_arch = "arm"))]
22282#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22283#[cfg_attr(test, assert_instr(ld3r))]
22284pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22285 unsafe extern "unadjusted" {
22286 #[cfg_attr(
22287 any(target_arch = "aarch64", target_arch = "arm64ec"),
22288 link_name = "llvm.aarch64.neon.ld3r.v8i16.p0"
22289 )]
22290 fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t;
22291 }
22292 _vld3q_dup_s16(a as _)
22293}
22294#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22296#[doc = "## Safety"]
22297#[doc = " * Neon instrinsic unsafe"]
22298#[inline]
22299#[target_feature(enable = "neon")]
22300#[cfg(not(target_arch = "arm"))]
22301#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22302#[cfg_attr(test, assert_instr(ld3r))]
22303pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22304 unsafe extern "unadjusted" {
22305 #[cfg_attr(
22306 any(target_arch = "aarch64", target_arch = "arm64ec"),
22307 link_name = "llvm.aarch64.neon.ld3r.v2i32.p0"
22308 )]
22309 fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t;
22310 }
22311 _vld3_dup_s32(a as _)
22312}
22313#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22315#[doc = "## Safety"]
22316#[doc = " * Neon instrinsic unsafe"]
22317#[inline]
22318#[target_feature(enable = "neon")]
22319#[cfg(not(target_arch = "arm"))]
22320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22321#[cfg_attr(test, assert_instr(ld3r))]
22322pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22323 unsafe extern "unadjusted" {
22324 #[cfg_attr(
22325 any(target_arch = "aarch64", target_arch = "arm64ec"),
22326 link_name = "llvm.aarch64.neon.ld3r.v4i32.p0"
22327 )]
22328 fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t;
22329 }
22330 _vld3q_dup_s32(a as _)
22331}
22332#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22334#[doc = "## Safety"]
22335#[doc = " * Neon instrinsic unsafe"]
22336#[inline]
22337#[target_feature(enable = "neon")]
22338#[cfg(not(target_arch = "arm"))]
22339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
22340#[cfg_attr(test, assert_instr(ld3r))]
22341pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22342 unsafe extern "unadjusted" {
22343 #[cfg_attr(
22344 any(target_arch = "aarch64", target_arch = "arm64ec"),
22345 link_name = "llvm.aarch64.neon.ld3r.v1i64.p0"
22346 )]
22347 fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t;
22348 }
22349 _vld3_dup_s64(a as _)
22350}
22351#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
22353#[doc = "## Safety"]
22354#[doc = " * Neon instrinsic unsafe"]
22355#[inline]
22356#[target_feature(enable = "neon,v7")]
22357#[cfg(target_arch = "arm")]
22358#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22359#[cfg_attr(test, assert_instr(vld3))]
22360pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
22361 unsafe extern "unadjusted" {
22362 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0")]
22363 fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
22364 }
22365 _vld3_dup_f32(a as *const i8, 4)
22366}
22367#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
22369#[doc = "## Safety"]
22370#[doc = " * Neon instrinsic unsafe"]
22371#[inline]
22372#[target_feature(enable = "neon,v7")]
22373#[cfg(target_arch = "arm")]
22374#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22375#[cfg_attr(test, assert_instr(vld3))]
22376pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
22377 unsafe extern "unadjusted" {
22378 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0")]
22379 fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
22380 }
22381 _vld3q_dup_f32(a as *const i8, 4)
22382}
22383#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
22385#[doc = "## Safety"]
22386#[doc = " * Neon instrinsic unsafe"]
22387#[inline]
22388#[target_feature(enable = "neon,v7")]
22389#[cfg(target_arch = "arm")]
22390#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22391#[cfg_attr(test, assert_instr(vld3))]
22392pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
22393 unsafe extern "unadjusted" {
22394 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0")]
22395 fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
22396 }
22397 _vld3_dup_s8(a as *const i8, 1)
22398}
22399#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
22401#[doc = "## Safety"]
22402#[doc = " * Neon instrinsic unsafe"]
22403#[inline]
22404#[target_feature(enable = "neon,v7")]
22405#[cfg(target_arch = "arm")]
22406#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22407#[cfg_attr(test, assert_instr(vld3))]
22408pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
22409 unsafe extern "unadjusted" {
22410 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0")]
22411 fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
22412 }
22413 _vld3q_dup_s8(a as *const i8, 1)
22414}
22415#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
22417#[doc = "## Safety"]
22418#[doc = " * Neon instrinsic unsafe"]
22419#[inline]
22420#[target_feature(enable = "neon,v7")]
22421#[cfg(target_arch = "arm")]
22422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22423#[cfg_attr(test, assert_instr(vld3))]
22424pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
22425 unsafe extern "unadjusted" {
22426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0")]
22427 fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
22428 }
22429 _vld3_dup_s16(a as *const i8, 2)
22430}
22431#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
22433#[doc = "## Safety"]
22434#[doc = " * Neon instrinsic unsafe"]
22435#[inline]
22436#[target_feature(enable = "neon,v7")]
22437#[cfg(target_arch = "arm")]
22438#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22439#[cfg_attr(test, assert_instr(vld3))]
22440pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
22441 unsafe extern "unadjusted" {
22442 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0")]
22443 fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
22444 }
22445 _vld3q_dup_s16(a as *const i8, 2)
22446}
22447#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
22449#[doc = "## Safety"]
22450#[doc = " * Neon instrinsic unsafe"]
22451#[inline]
22452#[target_feature(enable = "neon,v7")]
22453#[cfg(target_arch = "arm")]
22454#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22455#[cfg_attr(test, assert_instr(vld3))]
22456pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
22457 unsafe extern "unadjusted" {
22458 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0")]
22459 fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
22460 }
22461 _vld3_dup_s32(a as *const i8, 4)
22462}
22463#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
22465#[doc = "## Safety"]
22466#[doc = " * Neon instrinsic unsafe"]
22467#[inline]
22468#[target_feature(enable = "neon,v7")]
22469#[cfg(target_arch = "arm")]
22470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22471#[cfg_attr(test, assert_instr(vld3))]
22472pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
22473 unsafe extern "unadjusted" {
22474 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0")]
22475 fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
22476 }
22477 _vld3q_dup_s32(a as *const i8, 4)
22478}
22479#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
22481#[doc = "## Safety"]
22482#[doc = " * Neon instrinsic unsafe"]
22483#[inline]
22484#[target_feature(enable = "neon,aes")]
22485#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
22486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22487#[cfg_attr(
22488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22489 assert_instr(ld3r)
22490)]
22491#[cfg_attr(
22492 not(target_arch = "arm"),
22493 stable(feature = "neon_intrinsics", since = "1.59.0")
22494)]
22495#[cfg_attr(
22496 target_arch = "arm",
22497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22498)]
22499pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
22500 transmute(vld3_dup_s64(transmute(a)))
22501}
22502#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
22504#[doc = "## Safety"]
22505#[doc = " * Neon instrinsic unsafe"]
22506#[inline]
22507#[cfg(target_arch = "arm")]
22508#[target_feature(enable = "neon,v7")]
22509#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
22510#[cfg_attr(test, assert_instr(nop))]
22511pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
22512 unsafe extern "unadjusted" {
22513 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0")]
22514 fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
22515 }
22516 _vld3_dup_s64(a as *const i8, 8)
22517}
22518#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
22520#[doc = "## Safety"]
22521#[doc = " * Neon instrinsic unsafe"]
22522#[inline]
22523#[target_feature(enable = "neon")]
22524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
22526#[cfg_attr(
22527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22528 assert_instr(ld3r)
22529)]
22530#[cfg_attr(
22531 not(target_arch = "arm"),
22532 stable(feature = "neon_intrinsics", since = "1.59.0")
22533)]
22534#[cfg_attr(
22535 target_arch = "arm",
22536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22537)]
22538pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
22539 transmute(vld3_dup_s64(transmute(a)))
22540}
22541#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22543#[doc = "## Safety"]
22544#[doc = " * Neon instrinsic unsafe"]
22545#[inline]
22546#[cfg(target_endian = "little")]
22547#[target_feature(enable = "neon")]
22548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22550#[cfg_attr(
22551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22552 assert_instr(ld3r)
22553)]
22554#[cfg_attr(
22555 not(target_arch = "arm"),
22556 stable(feature = "neon_intrinsics", since = "1.59.0")
22557)]
22558#[cfg_attr(
22559 target_arch = "arm",
22560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22561)]
22562pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22563 transmute(vld3_dup_s8(transmute(a)))
22564}
22565#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
22567#[doc = "## Safety"]
22568#[doc = " * Neon instrinsic unsafe"]
22569#[inline]
22570#[cfg(target_endian = "big")]
22571#[target_feature(enable = "neon")]
22572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22573#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22574#[cfg_attr(
22575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22576 assert_instr(ld3r)
22577)]
22578#[cfg_attr(
22579 not(target_arch = "arm"),
22580 stable(feature = "neon_intrinsics", since = "1.59.0")
22581)]
22582#[cfg_attr(
22583 target_arch = "arm",
22584 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22585)]
22586pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
22587 let mut ret_val: uint8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22588 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22589 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22590 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22591 ret_val
22592}
22593#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22595#[doc = "## Safety"]
22596#[doc = " * Neon instrinsic unsafe"]
22597#[inline]
22598#[cfg(target_endian = "little")]
22599#[target_feature(enable = "neon")]
22600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22602#[cfg_attr(
22603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22604 assert_instr(ld3r)
22605)]
22606#[cfg_attr(
22607 not(target_arch = "arm"),
22608 stable(feature = "neon_intrinsics", since = "1.59.0")
22609)]
22610#[cfg_attr(
22611 target_arch = "arm",
22612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22613)]
22614pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22615 transmute(vld3q_dup_s8(transmute(a)))
22616}
22617#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
22619#[doc = "## Safety"]
22620#[doc = " * Neon instrinsic unsafe"]
22621#[inline]
22622#[cfg(target_endian = "big")]
22623#[target_feature(enable = "neon")]
22624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22626#[cfg_attr(
22627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22628 assert_instr(ld3r)
22629)]
22630#[cfg_attr(
22631 not(target_arch = "arm"),
22632 stable(feature = "neon_intrinsics", since = "1.59.0")
22633)]
22634#[cfg_attr(
22635 target_arch = "arm",
22636 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22637)]
22638pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
22639 let mut ret_val: uint8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
22640 ret_val.0 = unsafe {
22641 simd_shuffle!(
22642 ret_val.0,
22643 ret_val.0,
22644 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22645 )
22646 };
22647 ret_val.1 = unsafe {
22648 simd_shuffle!(
22649 ret_val.1,
22650 ret_val.1,
22651 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22652 )
22653 };
22654 ret_val.2 = unsafe {
22655 simd_shuffle!(
22656 ret_val.2,
22657 ret_val.2,
22658 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22659 )
22660 };
22661 ret_val
22662}
22663#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22665#[doc = "## Safety"]
22666#[doc = " * Neon instrinsic unsafe"]
22667#[inline]
22668#[cfg(target_endian = "little")]
22669#[target_feature(enable = "neon")]
22670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22672#[cfg_attr(
22673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22674 assert_instr(ld3r)
22675)]
22676#[cfg_attr(
22677 not(target_arch = "arm"),
22678 stable(feature = "neon_intrinsics", since = "1.59.0")
22679)]
22680#[cfg_attr(
22681 target_arch = "arm",
22682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22683)]
22684pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22685 transmute(vld3_dup_s16(transmute(a)))
22686}
22687#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
22689#[doc = "## Safety"]
22690#[doc = " * Neon instrinsic unsafe"]
22691#[inline]
22692#[cfg(target_endian = "big")]
22693#[target_feature(enable = "neon")]
22694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22696#[cfg_attr(
22697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22698 assert_instr(ld3r)
22699)]
22700#[cfg_attr(
22701 not(target_arch = "arm"),
22702 stable(feature = "neon_intrinsics", since = "1.59.0")
22703)]
22704#[cfg_attr(
22705 target_arch = "arm",
22706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22707)]
22708pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
22709 let mut ret_val: uint16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
22710 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22711 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22712 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22713 ret_val
22714}
22715#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22717#[doc = "## Safety"]
22718#[doc = " * Neon instrinsic unsafe"]
22719#[inline]
22720#[cfg(target_endian = "little")]
22721#[target_feature(enable = "neon")]
22722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22724#[cfg_attr(
22725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22726 assert_instr(ld3r)
22727)]
22728#[cfg_attr(
22729 not(target_arch = "arm"),
22730 stable(feature = "neon_intrinsics", since = "1.59.0")
22731)]
22732#[cfg_attr(
22733 target_arch = "arm",
22734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22735)]
22736pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22737 transmute(vld3q_dup_s16(transmute(a)))
22738}
22739#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
22741#[doc = "## Safety"]
22742#[doc = " * Neon instrinsic unsafe"]
22743#[inline]
22744#[cfg(target_endian = "big")]
22745#[target_feature(enable = "neon")]
22746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22748#[cfg_attr(
22749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22750 assert_instr(ld3r)
22751)]
22752#[cfg_attr(
22753 not(target_arch = "arm"),
22754 stable(feature = "neon_intrinsics", since = "1.59.0")
22755)]
22756#[cfg_attr(
22757 target_arch = "arm",
22758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22759)]
22760pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
22761 let mut ret_val: uint16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
22762 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22763 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22764 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22765 ret_val
22766}
22767#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22769#[doc = "## Safety"]
22770#[doc = " * Neon instrinsic unsafe"]
22771#[inline]
22772#[cfg(target_endian = "little")]
22773#[target_feature(enable = "neon")]
22774#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22776#[cfg_attr(
22777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22778 assert_instr(ld3r)
22779)]
22780#[cfg_attr(
22781 not(target_arch = "arm"),
22782 stable(feature = "neon_intrinsics", since = "1.59.0")
22783)]
22784#[cfg_attr(
22785 target_arch = "arm",
22786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22787)]
22788pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22789 transmute(vld3_dup_s32(transmute(a)))
22790}
22791#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22792#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
22793#[doc = "## Safety"]
22794#[doc = " * Neon instrinsic unsafe"]
22795#[inline]
22796#[cfg(target_endian = "big")]
22797#[target_feature(enable = "neon")]
22798#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22799#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22800#[cfg_attr(
22801 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22802 assert_instr(ld3r)
22803)]
22804#[cfg_attr(
22805 not(target_arch = "arm"),
22806 stable(feature = "neon_intrinsics", since = "1.59.0")
22807)]
22808#[cfg_attr(
22809 target_arch = "arm",
22810 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22811)]
22812pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
22813 let mut ret_val: uint32x2x3_t = transmute(vld3_dup_s32(transmute(a)));
22814 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
22815 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
22816 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
22817 ret_val
22818}
22819#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22821#[doc = "## Safety"]
22822#[doc = " * Neon instrinsic unsafe"]
22823#[inline]
22824#[cfg(target_endian = "little")]
22825#[target_feature(enable = "neon")]
22826#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22827#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22828#[cfg_attr(
22829 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22830 assert_instr(ld3r)
22831)]
22832#[cfg_attr(
22833 not(target_arch = "arm"),
22834 stable(feature = "neon_intrinsics", since = "1.59.0")
22835)]
22836#[cfg_attr(
22837 target_arch = "arm",
22838 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22839)]
22840pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22841 transmute(vld3q_dup_s32(transmute(a)))
22842}
22843#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
22845#[doc = "## Safety"]
22846#[doc = " * Neon instrinsic unsafe"]
22847#[inline]
22848#[cfg(target_endian = "big")]
22849#[target_feature(enable = "neon")]
22850#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22851#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22852#[cfg_attr(
22853 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22854 assert_instr(ld3r)
22855)]
22856#[cfg_attr(
22857 not(target_arch = "arm"),
22858 stable(feature = "neon_intrinsics", since = "1.59.0")
22859)]
22860#[cfg_attr(
22861 target_arch = "arm",
22862 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22863)]
22864pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
22865 let mut ret_val: uint32x4x3_t = transmute(vld3q_dup_s32(transmute(a)));
22866 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
22867 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
22868 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
22869 ret_val
22870}
22871#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
22873#[doc = "## Safety"]
22874#[doc = " * Neon instrinsic unsafe"]
22875#[inline]
22876#[cfg(target_endian = "little")]
22877#[target_feature(enable = "neon")]
22878#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22879#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22880#[cfg_attr(
22881 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22882 assert_instr(ld3r)
22883)]
22884#[cfg_attr(
22885 not(target_arch = "arm"),
22886 stable(feature = "neon_intrinsics", since = "1.59.0")
22887)]
22888#[cfg_attr(
22889 target_arch = "arm",
22890 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22891)]
22892pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
22893 transmute(vld3_dup_s8(transmute(a)))
22894}
22895#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
22897#[doc = "## Safety"]
22898#[doc = " * Neon instrinsic unsafe"]
22899#[inline]
22900#[cfg(target_endian = "big")]
22901#[target_feature(enable = "neon")]
22902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22903#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22904#[cfg_attr(
22905 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22906 assert_instr(ld3r)
22907)]
22908#[cfg_attr(
22909 not(target_arch = "arm"),
22910 stable(feature = "neon_intrinsics", since = "1.59.0")
22911)]
22912#[cfg_attr(
22913 target_arch = "arm",
22914 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22915)]
22916pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
22917 let mut ret_val: poly8x8x3_t = transmute(vld3_dup_s8(transmute(a)));
22918 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
22919 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
22920 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
22921 ret_val
22922}
22923#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
22925#[doc = "## Safety"]
22926#[doc = " * Neon instrinsic unsafe"]
22927#[inline]
22928#[cfg(target_endian = "little")]
22929#[target_feature(enable = "neon")]
22930#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22931#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22932#[cfg_attr(
22933 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22934 assert_instr(ld3r)
22935)]
22936#[cfg_attr(
22937 not(target_arch = "arm"),
22938 stable(feature = "neon_intrinsics", since = "1.59.0")
22939)]
22940#[cfg_attr(
22941 target_arch = "arm",
22942 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22943)]
22944pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
22945 transmute(vld3q_dup_s8(transmute(a)))
22946}
22947#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22948#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
22949#[doc = "## Safety"]
22950#[doc = " * Neon instrinsic unsafe"]
22951#[inline]
22952#[cfg(target_endian = "big")]
22953#[target_feature(enable = "neon")]
22954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
22955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
22956#[cfg_attr(
22957 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
22958 assert_instr(ld3r)
22959)]
22960#[cfg_attr(
22961 not(target_arch = "arm"),
22962 stable(feature = "neon_intrinsics", since = "1.59.0")
22963)]
22964#[cfg_attr(
22965 target_arch = "arm",
22966 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
22967)]
22968pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
22969 let mut ret_val: poly8x16x3_t = transmute(vld3q_dup_s8(transmute(a)));
22970 ret_val.0 = unsafe {
22971 simd_shuffle!(
22972 ret_val.0,
22973 ret_val.0,
22974 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22975 )
22976 };
22977 ret_val.1 = unsafe {
22978 simd_shuffle!(
22979 ret_val.1,
22980 ret_val.1,
22981 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22982 )
22983 };
22984 ret_val.2 = unsafe {
22985 simd_shuffle!(
22986 ret_val.2,
22987 ret_val.2,
22988 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
22989 )
22990 };
22991 ret_val
22992}
22993#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
22994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
22995#[doc = "## Safety"]
22996#[doc = " * Neon instrinsic unsafe"]
22997#[inline]
22998#[cfg(target_endian = "little")]
22999#[target_feature(enable = "neon")]
23000#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23001#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23002#[cfg_attr(
23003 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23004 assert_instr(ld3r)
23005)]
23006#[cfg_attr(
23007 not(target_arch = "arm"),
23008 stable(feature = "neon_intrinsics", since = "1.59.0")
23009)]
23010#[cfg_attr(
23011 target_arch = "arm",
23012 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23013)]
23014pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23015 transmute(vld3_dup_s16(transmute(a)))
23016}
23017#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
23019#[doc = "## Safety"]
23020#[doc = " * Neon instrinsic unsafe"]
23021#[inline]
23022#[cfg(target_endian = "big")]
23023#[target_feature(enable = "neon")]
23024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23026#[cfg_attr(
23027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23028 assert_instr(ld3r)
23029)]
23030#[cfg_attr(
23031 not(target_arch = "arm"),
23032 stable(feature = "neon_intrinsics", since = "1.59.0")
23033)]
23034#[cfg_attr(
23035 target_arch = "arm",
23036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23037)]
23038pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
23039 let mut ret_val: poly16x4x3_t = transmute(vld3_dup_s16(transmute(a)));
23040 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
23041 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
23042 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
23043 ret_val
23044}
23045#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23047#[doc = "## Safety"]
23048#[doc = " * Neon instrinsic unsafe"]
23049#[inline]
23050#[cfg(target_endian = "little")]
23051#[target_feature(enable = "neon")]
23052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23054#[cfg_attr(
23055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23056 assert_instr(ld3r)
23057)]
23058#[cfg_attr(
23059 not(target_arch = "arm"),
23060 stable(feature = "neon_intrinsics", since = "1.59.0")
23061)]
23062#[cfg_attr(
23063 target_arch = "arm",
23064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23065)]
23066pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23067 transmute(vld3q_dup_s16(transmute(a)))
23068}
23069#[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
23070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
23071#[doc = "## Safety"]
23072#[doc = " * Neon instrinsic unsafe"]
23073#[inline]
23074#[cfg(target_endian = "big")]
23075#[target_feature(enable = "neon")]
23076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23078#[cfg_attr(
23079 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23080 assert_instr(ld3r)
23081)]
23082#[cfg_attr(
23083 not(target_arch = "arm"),
23084 stable(feature = "neon_intrinsics", since = "1.59.0")
23085)]
23086#[cfg_attr(
23087 target_arch = "arm",
23088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23089)]
23090pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
23091 let mut ret_val: poly16x8x3_t = transmute(vld3q_dup_s16(transmute(a)));
23092 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
23093 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
23094 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
23095 ret_val
23096}
23097#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23099#[doc = "## Safety"]
23100#[doc = " * Neon instrinsic unsafe"]
23101#[inline]
23102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23103#[cfg(target_arch = "arm")]
23104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23105#[target_feature(enable = "neon,fp16")]
23106#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23107pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23108 unsafe extern "unadjusted" {
23109 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f16.p0")]
23110 fn _vld3_f16(ptr: *const f16, size: i32) -> float16x4x3_t;
23111 }
23112 _vld3_f16(a as _, 2)
23113}
23114#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23116#[doc = "## Safety"]
23117#[doc = " * Neon instrinsic unsafe"]
23118#[inline]
23119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23120#[cfg(target_arch = "arm")]
23121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
23122#[target_feature(enable = "neon,fp16")]
23123#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23124pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23125 unsafe extern "unadjusted" {
23126 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8f16.p0")]
23127 fn _vld3q_f16(ptr: *const f16, size: i32) -> float16x8x3_t;
23128 }
23129 _vld3q_f16(a as _, 2)
23130}
23131#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
23133#[doc = "## Safety"]
23134#[doc = " * Neon instrinsic unsafe"]
23135#[inline]
23136#[cfg(not(target_arch = "arm"))]
23137#[cfg_attr(
23138 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23139 assert_instr(ld3)
23140)]
23141#[target_feature(enable = "neon,fp16")]
23142#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23143pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
23144 unsafe extern "unadjusted" {
23145 #[cfg_attr(
23146 any(target_arch = "aarch64", target_arch = "arm64ec"),
23147 link_name = "llvm.aarch64.neon.ld3.v4f16.p0"
23148 )]
23149 fn _vld3_f16(ptr: *const f16) -> float16x4x3_t;
23150 }
23151 _vld3_f16(a as _)
23152}
23153#[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
23154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
23155#[doc = "## Safety"]
23156#[doc = " * Neon instrinsic unsafe"]
23157#[inline]
23158#[cfg(not(target_arch = "arm"))]
23159#[cfg_attr(
23160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23161 assert_instr(ld3)
23162)]
23163#[target_feature(enable = "neon,fp16")]
23164#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23165pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
23166 unsafe extern "unadjusted" {
23167 #[cfg_attr(
23168 any(target_arch = "aarch64", target_arch = "arm64ec"),
23169 link_name = "llvm.aarch64.neon.ld3.v8f16.p0"
23170 )]
23171 fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t;
23172 }
23173 _vld3q_f16(a as _)
23174}
23175#[doc = "Load multiple 3-element structures to three registers"]
23176#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23177#[doc = "## Safety"]
23178#[doc = " * Neon instrinsic unsafe"]
23179#[inline]
23180#[target_feature(enable = "neon")]
23181#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23182#[cfg(not(target_arch = "arm"))]
23183#[cfg_attr(test, assert_instr(ld3))]
23184pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23185 unsafe extern "unadjusted" {
23186 #[cfg_attr(
23187 any(target_arch = "aarch64", target_arch = "arm64ec"),
23188 link_name = "llvm.aarch64.neon.ld3.v2f32.p0"
23189 )]
23190 fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t;
23191 }
23192 _vld3_f32(a as _)
23193}
23194#[doc = "Load multiple 3-element structures to three registers"]
23195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23196#[doc = "## Safety"]
23197#[doc = " * Neon instrinsic unsafe"]
23198#[inline]
23199#[target_feature(enable = "neon")]
23200#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23201#[cfg(not(target_arch = "arm"))]
23202#[cfg_attr(test, assert_instr(ld3))]
23203pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23204 unsafe extern "unadjusted" {
23205 #[cfg_attr(
23206 any(target_arch = "aarch64", target_arch = "arm64ec"),
23207 link_name = "llvm.aarch64.neon.ld3.v4f32.p0"
23208 )]
23209 fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t;
23210 }
23211 _vld3q_f32(a as _)
23212}
23213#[doc = "Load multiple 3-element structures to three registers"]
23214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23215#[doc = "## Safety"]
23216#[doc = " * Neon instrinsic unsafe"]
23217#[inline]
23218#[target_feature(enable = "neon")]
23219#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23220#[cfg(not(target_arch = "arm"))]
23221#[cfg_attr(test, assert_instr(ld3))]
23222pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23223 unsafe extern "unadjusted" {
23224 #[cfg_attr(
23225 any(target_arch = "aarch64", target_arch = "arm64ec"),
23226 link_name = "llvm.aarch64.neon.ld3.v8i8.p0"
23227 )]
23228 fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t;
23229 }
23230 _vld3_s8(a as _)
23231}
23232#[doc = "Load multiple 3-element structures to three registers"]
23233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23234#[doc = "## Safety"]
23235#[doc = " * Neon instrinsic unsafe"]
23236#[inline]
23237#[target_feature(enable = "neon")]
23238#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23239#[cfg(not(target_arch = "arm"))]
23240#[cfg_attr(test, assert_instr(ld3))]
23241pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23242 unsafe extern "unadjusted" {
23243 #[cfg_attr(
23244 any(target_arch = "aarch64", target_arch = "arm64ec"),
23245 link_name = "llvm.aarch64.neon.ld3.v16i8.p0"
23246 )]
23247 fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t;
23248 }
23249 _vld3q_s8(a as _)
23250}
23251#[doc = "Load multiple 3-element structures to three registers"]
23252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23253#[doc = "## Safety"]
23254#[doc = " * Neon instrinsic unsafe"]
23255#[inline]
23256#[target_feature(enable = "neon")]
23257#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23258#[cfg(not(target_arch = "arm"))]
23259#[cfg_attr(test, assert_instr(ld3))]
23260pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23261 unsafe extern "unadjusted" {
23262 #[cfg_attr(
23263 any(target_arch = "aarch64", target_arch = "arm64ec"),
23264 link_name = "llvm.aarch64.neon.ld3.v4i16.p0"
23265 )]
23266 fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t;
23267 }
23268 _vld3_s16(a as _)
23269}
23270#[doc = "Load multiple 3-element structures to three registers"]
23271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23272#[doc = "## Safety"]
23273#[doc = " * Neon instrinsic unsafe"]
23274#[inline]
23275#[target_feature(enable = "neon")]
23276#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23277#[cfg(not(target_arch = "arm"))]
23278#[cfg_attr(test, assert_instr(ld3))]
23279pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23280 unsafe extern "unadjusted" {
23281 #[cfg_attr(
23282 any(target_arch = "aarch64", target_arch = "arm64ec"),
23283 link_name = "llvm.aarch64.neon.ld3.v8i16.p0"
23284 )]
23285 fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t;
23286 }
23287 _vld3q_s16(a as _)
23288}
23289#[doc = "Load multiple 3-element structures to three registers"]
23290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23291#[doc = "## Safety"]
23292#[doc = " * Neon instrinsic unsafe"]
23293#[inline]
23294#[target_feature(enable = "neon")]
23295#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23296#[cfg(not(target_arch = "arm"))]
23297#[cfg_attr(test, assert_instr(ld3))]
23298pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23299 unsafe extern "unadjusted" {
23300 #[cfg_attr(
23301 any(target_arch = "aarch64", target_arch = "arm64ec"),
23302 link_name = "llvm.aarch64.neon.ld3.v2i32.p0"
23303 )]
23304 fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t;
23305 }
23306 _vld3_s32(a as _)
23307}
23308#[doc = "Load multiple 3-element structures to three registers"]
23309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23310#[doc = "## Safety"]
23311#[doc = " * Neon instrinsic unsafe"]
23312#[inline]
23313#[target_feature(enable = "neon")]
23314#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23315#[cfg(not(target_arch = "arm"))]
23316#[cfg_attr(test, assert_instr(ld3))]
23317pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23318 unsafe extern "unadjusted" {
23319 #[cfg_attr(
23320 any(target_arch = "aarch64", target_arch = "arm64ec"),
23321 link_name = "llvm.aarch64.neon.ld3.v4i32.p0"
23322 )]
23323 fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t;
23324 }
23325 _vld3q_s32(a as _)
23326}
23327#[doc = "Load multiple 3-element structures to three registers"]
23328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
23329#[doc = "## Safety"]
23330#[doc = " * Neon instrinsic unsafe"]
23331#[inline]
23332#[cfg(target_arch = "arm")]
23333#[target_feature(enable = "neon,v7")]
23334#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23335#[cfg_attr(test, assert_instr(vld3))]
23336pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
23337 unsafe extern "unadjusted" {
23338 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0")]
23339 fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t;
23340 }
23341 _vld3_f32(a as *const i8, 4)
23342}
23343#[doc = "Load multiple 3-element structures to three registers"]
23344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
23345#[doc = "## Safety"]
23346#[doc = " * Neon instrinsic unsafe"]
23347#[inline]
23348#[cfg(target_arch = "arm")]
23349#[target_feature(enable = "neon,v7")]
23350#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23351#[cfg_attr(test, assert_instr(vld3))]
23352pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
23353 unsafe extern "unadjusted" {
23354 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0")]
23355 fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t;
23356 }
23357 _vld3q_f32(a as *const i8, 4)
23358}
23359#[doc = "Load multiple 3-element structures to three registers"]
23360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
23361#[doc = "## Safety"]
23362#[doc = " * Neon instrinsic unsafe"]
23363#[inline]
23364#[cfg(target_arch = "arm")]
23365#[target_feature(enable = "neon,v7")]
23366#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23367#[cfg_attr(test, assert_instr(vld3))]
23368pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
23369 unsafe extern "unadjusted" {
23370 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0")]
23371 fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t;
23372 }
23373 _vld3_s8(a as *const i8, 1)
23374}
23375#[doc = "Load multiple 3-element structures to three registers"]
23376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
23377#[doc = "## Safety"]
23378#[doc = " * Neon instrinsic unsafe"]
23379#[inline]
23380#[cfg(target_arch = "arm")]
23381#[target_feature(enable = "neon,v7")]
23382#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23383#[cfg_attr(test, assert_instr(vld3))]
23384pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
23385 unsafe extern "unadjusted" {
23386 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0")]
23387 fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t;
23388 }
23389 _vld3q_s8(a as *const i8, 1)
23390}
23391#[doc = "Load multiple 3-element structures to three registers"]
23392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
23393#[doc = "## Safety"]
23394#[doc = " * Neon instrinsic unsafe"]
23395#[inline]
23396#[cfg(target_arch = "arm")]
23397#[target_feature(enable = "neon,v7")]
23398#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23399#[cfg_attr(test, assert_instr(vld3))]
23400pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
23401 unsafe extern "unadjusted" {
23402 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0")]
23403 fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t;
23404 }
23405 _vld3_s16(a as *const i8, 2)
23406}
23407#[doc = "Load multiple 3-element structures to three registers"]
23408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
23409#[doc = "## Safety"]
23410#[doc = " * Neon instrinsic unsafe"]
23411#[inline]
23412#[cfg(target_arch = "arm")]
23413#[target_feature(enable = "neon,v7")]
23414#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23415#[cfg_attr(test, assert_instr(vld3))]
23416pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
23417 unsafe extern "unadjusted" {
23418 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0")]
23419 fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t;
23420 }
23421 _vld3q_s16(a as *const i8, 2)
23422}
23423#[doc = "Load multiple 3-element structures to three registers"]
23424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
23425#[doc = "## Safety"]
23426#[doc = " * Neon instrinsic unsafe"]
23427#[inline]
23428#[cfg(target_arch = "arm")]
23429#[target_feature(enable = "neon,v7")]
23430#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23431#[cfg_attr(test, assert_instr(vld3))]
23432pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
23433 unsafe extern "unadjusted" {
23434 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0")]
23435 fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t;
23436 }
23437 _vld3_s32(a as *const i8, 4)
23438}
23439#[doc = "Load multiple 3-element structures to three registers"]
23440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
23441#[doc = "## Safety"]
23442#[doc = " * Neon instrinsic unsafe"]
23443#[inline]
23444#[cfg(target_arch = "arm")]
23445#[target_feature(enable = "neon,v7")]
23446#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23447#[cfg_attr(test, assert_instr(vld3))]
23448pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
23449 unsafe extern "unadjusted" {
23450 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0")]
23451 fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t;
23452 }
23453 _vld3q_s32(a as *const i8, 4)
23454}
23455#[doc = "Load multiple 3-element structures to two registers"]
23456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23457#[doc = "## Safety"]
23458#[doc = " * Neon instrinsic unsafe"]
23459#[inline]
23460#[target_feature(enable = "neon,v7")]
23461#[cfg(target_arch = "arm")]
23462#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23463#[rustc_legacy_const_generics(2)]
23464#[target_feature(enable = "neon,fp16")]
23465#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23466pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23467 static_assert_uimm_bits!(LANE, 2);
23468 unsafe extern "unadjusted" {
23469 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f16.p0")]
23470 fn _vld3_lane_f16(
23471 ptr: *const f16,
23472 a: float16x4_t,
23473 b: float16x4_t,
23474 c: float16x4_t,
23475 n: i32,
23476 size: i32,
23477 ) -> float16x4x3_t;
23478 }
23479 _vld3_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23480}
23481#[doc = "Load multiple 3-element structures to two registers"]
23482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23483#[doc = "## Safety"]
23484#[doc = " * Neon instrinsic unsafe"]
23485#[inline]
23486#[target_feature(enable = "neon,v7")]
23487#[cfg(target_arch = "arm")]
23488#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23489#[rustc_legacy_const_generics(2)]
23490#[target_feature(enable = "neon,fp16")]
23491#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23492pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23493 static_assert_uimm_bits!(LANE, 3);
23494 unsafe extern "unadjusted" {
23495 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8f16.p0")]
23496 fn _vld3q_lane_f16(
23497 ptr: *const f16,
23498 a: float16x8_t,
23499 b: float16x8_t,
23500 c: float16x8_t,
23501 n: i32,
23502 size: i32,
23503 ) -> float16x8x3_t;
23504 }
23505 _vld3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 2)
23506}
23507#[doc = "Load multiple 3-element structures to two registers"]
23508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
23509#[doc = "## Safety"]
23510#[doc = " * Neon instrinsic unsafe"]
23511#[inline]
23512#[cfg(not(target_arch = "arm"))]
23513#[cfg_attr(
23514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23515 assert_instr(ld3, LANE = 0)
23516)]
23517#[rustc_legacy_const_generics(2)]
23518#[target_feature(enable = "neon,fp16")]
23519#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23520pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) -> float16x4x3_t {
23521 static_assert_uimm_bits!(LANE, 2);
23522 unsafe extern "unadjusted" {
23523 #[cfg_attr(
23524 any(target_arch = "aarch64", target_arch = "arm64ec"),
23525 link_name = "llvm.aarch64.neon.ld3lane.v4f16.p0"
23526 )]
23527 fn _vld3_lane_f16(
23528 a: float16x4_t,
23529 b: float16x4_t,
23530 c: float16x4_t,
23531 n: i64,
23532 ptr: *const f16,
23533 ) -> float16x4x3_t;
23534 }
23535 _vld3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23536}
23537#[doc = "Load multiple 3-element structures to two registers"]
23538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
23539#[doc = "## Safety"]
23540#[doc = " * Neon instrinsic unsafe"]
23541#[inline]
23542#[cfg(not(target_arch = "arm"))]
23543#[cfg_attr(
23544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23545 assert_instr(ld3, LANE = 0)
23546)]
23547#[rustc_legacy_const_generics(2)]
23548#[target_feature(enable = "neon,fp16")]
23549#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
23550pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -> float16x8x3_t {
23551 static_assert_uimm_bits!(LANE, 3);
23552 unsafe extern "unadjusted" {
23553 #[cfg_attr(
23554 any(target_arch = "aarch64", target_arch = "arm64ec"),
23555 link_name = "llvm.aarch64.neon.ld3lane.v8f16.p0"
23556 )]
23557 fn _vld3q_lane_f16(
23558 a: float16x8_t,
23559 b: float16x8_t,
23560 c: float16x8_t,
23561 n: i64,
23562 ptr: *const f16,
23563 ) -> float16x8x3_t;
23564 }
23565 _vld3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
23566}
23567#[doc = "Load multiple 3-element structures to three registers"]
23568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23569#[doc = "## Safety"]
23570#[doc = " * Neon instrinsic unsafe"]
23571#[inline]
23572#[target_feature(enable = "neon")]
23573#[cfg(not(target_arch = "arm"))]
23574#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23575#[rustc_legacy_const_generics(2)]
23576#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23577pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23578 static_assert_uimm_bits!(LANE, 1);
23579 unsafe extern "unadjusted" {
23580 #[cfg_attr(
23581 any(target_arch = "aarch64", target_arch = "arm64ec"),
23582 link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0"
23583 )]
23584 fn _vld3_lane_f32(
23585 a: float32x2_t,
23586 b: float32x2_t,
23587 c: float32x2_t,
23588 n: i64,
23589 ptr: *const i8,
23590 ) -> float32x2x3_t;
23591 }
23592 _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23593}
23594#[doc = "Load multiple 3-element structures to three registers"]
23595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
23596#[doc = "## Safety"]
23597#[doc = " * Neon instrinsic unsafe"]
23598#[inline]
23599#[target_feature(enable = "neon")]
23600#[cfg(not(target_arch = "arm"))]
23601#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23602#[rustc_legacy_const_generics(2)]
23603#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23604pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
23605 static_assert_uimm_bits!(LANE, 2);
23606 unsafe extern "unadjusted" {
23607 #[cfg_attr(
23608 any(target_arch = "aarch64", target_arch = "arm64ec"),
23609 link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0"
23610 )]
23611 fn _vld3q_lane_f32(
23612 a: float32x4_t,
23613 b: float32x4_t,
23614 c: float32x4_t,
23615 n: i64,
23616 ptr: *const i8,
23617 ) -> float32x4x3_t;
23618 }
23619 _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
23620}
23621#[doc = "Load multiple 3-element structures to three registers"]
23622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
23623#[doc = "## Safety"]
23624#[doc = " * Neon instrinsic unsafe"]
23625#[inline]
23626#[cfg(target_arch = "arm")]
23627#[target_feature(enable = "neon,v7")]
23628#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23629#[rustc_legacy_const_generics(2)]
23630#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23631pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) -> float32x2x3_t {
23632 static_assert_uimm_bits!(LANE, 1);
23633 unsafe extern "unadjusted" {
23634 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0")]
23635 fn _vld3_lane_f32(
23636 ptr: *const i8,
23637 a: float32x2_t,
23638 b: float32x2_t,
23639 c: float32x2_t,
23640 n: i32,
23641 size: i32,
23642 ) -> float32x2x3_t;
23643 }
23644 _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
23645}
23646#[doc = "Load multiple 3-element structures to two registers"]
23647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23648#[doc = "## Safety"]
23649#[doc = " * Neon instrinsic unsafe"]
23650#[inline]
23651#[target_feature(enable = "neon")]
23652#[cfg(not(target_arch = "arm"))]
23653#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23654#[rustc_legacy_const_generics(2)]
23655#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23656pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23657 static_assert_uimm_bits!(LANE, 3);
23658 unsafe extern "unadjusted" {
23659 #[cfg_attr(
23660 any(target_arch = "aarch64", target_arch = "arm64ec"),
23661 link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0"
23662 )]
23663 fn _vld3_lane_s8(
23664 a: int8x8_t,
23665 b: int8x8_t,
23666 c: int8x8_t,
23667 n: i64,
23668 ptr: *const i8,
23669 ) -> int8x8x3_t;
23670 }
23671 _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
23672}
23673#[doc = "Load multiple 3-element structures to two registers"]
23674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23675#[doc = "## Safety"]
23676#[doc = " * Neon instrinsic unsafe"]
23677#[inline]
23678#[target_feature(enable = "neon")]
23679#[cfg(not(target_arch = "arm"))]
23680#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23681#[rustc_legacy_const_generics(2)]
23682#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23683pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23684 static_assert_uimm_bits!(LANE, 2);
23685 unsafe extern "unadjusted" {
23686 #[cfg_attr(
23687 any(target_arch = "aarch64", target_arch = "arm64ec"),
23688 link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0"
23689 )]
23690 fn _vld3_lane_s16(
23691 a: int16x4_t,
23692 b: int16x4_t,
23693 c: int16x4_t,
23694 n: i64,
23695 ptr: *const i8,
23696 ) -> int16x4x3_t;
23697 }
23698 _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23699}
23700#[doc = "Load multiple 3-element structures to two registers"]
23701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23702#[doc = "## Safety"]
23703#[doc = " * Neon instrinsic unsafe"]
23704#[inline]
23705#[target_feature(enable = "neon")]
23706#[cfg(not(target_arch = "arm"))]
23707#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23708#[rustc_legacy_const_generics(2)]
23709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23710pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23711 static_assert_uimm_bits!(LANE, 4);
23712 unsafe extern "unadjusted" {
23713 #[cfg_attr(
23714 any(target_arch = "aarch64", target_arch = "arm64ec"),
23715 link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0"
23716 )]
23717 fn _vld3q_lane_s16(
23718 a: int16x8_t,
23719 b: int16x8_t,
23720 c: int16x8_t,
23721 n: i64,
23722 ptr: *const i8,
23723 ) -> int16x8x3_t;
23724 }
23725 _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
23726}
23727#[doc = "Load multiple 3-element structures to two registers"]
23728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23729#[doc = "## Safety"]
23730#[doc = " * Neon instrinsic unsafe"]
23731#[inline]
23732#[target_feature(enable = "neon")]
23733#[cfg(not(target_arch = "arm"))]
23734#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23735#[rustc_legacy_const_generics(2)]
23736#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23737pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23738 static_assert_uimm_bits!(LANE, 1);
23739 unsafe extern "unadjusted" {
23740 #[cfg_attr(
23741 any(target_arch = "aarch64", target_arch = "arm64ec"),
23742 link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0"
23743 )]
23744 fn _vld3_lane_s32(
23745 a: int32x2_t,
23746 b: int32x2_t,
23747 c: int32x2_t,
23748 n: i64,
23749 ptr: *const i8,
23750 ) -> int32x2x3_t;
23751 }
23752 _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23753}
23754#[doc = "Load multiple 3-element structures to two registers"]
23755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23756#[doc = "## Safety"]
23757#[doc = " * Neon instrinsic unsafe"]
23758#[inline]
23759#[target_feature(enable = "neon")]
23760#[cfg(not(target_arch = "arm"))]
23761#[cfg_attr(test, assert_instr(ld3, LANE = 0))]
23762#[rustc_legacy_const_generics(2)]
23763#[stable(feature = "neon_intrinsics", since = "1.59.0")]
23764pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23765 static_assert_uimm_bits!(LANE, 2);
23766 unsafe extern "unadjusted" {
23767 #[cfg_attr(
23768 any(target_arch = "aarch64", target_arch = "arm64ec"),
23769 link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0"
23770 )]
23771 fn _vld3q_lane_s32(
23772 a: int32x4_t,
23773 b: int32x4_t,
23774 c: int32x4_t,
23775 n: i64,
23776 ptr: *const i8,
23777 ) -> int32x4x3_t;
23778 }
23779 _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
23780}
23781#[doc = "Load multiple 3-element structures to two registers"]
23782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
23783#[doc = "## Safety"]
23784#[doc = " * Neon instrinsic unsafe"]
23785#[inline]
23786#[cfg(target_arch = "arm")]
23787#[target_feature(enable = "neon,v7")]
23788#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23789#[rustc_legacy_const_generics(2)]
23790#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23791pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8x8x3_t {
23792 static_assert_uimm_bits!(LANE, 3);
23793 unsafe extern "unadjusted" {
23794 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0")]
23795 fn _vld3_lane_s8(
23796 ptr: *const i8,
23797 a: int8x8_t,
23798 b: int8x8_t,
23799 c: int8x8_t,
23800 n: i32,
23801 size: i32,
23802 ) -> int8x8x3_t;
23803 }
23804 _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
23805}
23806#[doc = "Load multiple 3-element structures to two registers"]
23807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
23808#[doc = "## Safety"]
23809#[doc = " * Neon instrinsic unsafe"]
23810#[inline]
23811#[cfg(target_arch = "arm")]
23812#[target_feature(enable = "neon,v7")]
23813#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23814#[rustc_legacy_const_generics(2)]
23815#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23816pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> int16x4x3_t {
23817 static_assert_uimm_bits!(LANE, 2);
23818 unsafe extern "unadjusted" {
23819 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0")]
23820 fn _vld3_lane_s16(
23821 ptr: *const i8,
23822 a: int16x4_t,
23823 b: int16x4_t,
23824 c: int16x4_t,
23825 n: i32,
23826 size: i32,
23827 ) -> int16x4x3_t;
23828 }
23829 _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23830}
23831#[doc = "Load multiple 3-element structures to two registers"]
23832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
23833#[doc = "## Safety"]
23834#[doc = " * Neon instrinsic unsafe"]
23835#[inline]
23836#[cfg(target_arch = "arm")]
23837#[target_feature(enable = "neon,v7")]
23838#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23839#[rustc_legacy_const_generics(2)]
23840#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23841pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) -> int16x8x3_t {
23842 static_assert_uimm_bits!(LANE, 3);
23843 unsafe extern "unadjusted" {
23844 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0")]
23845 fn _vld3q_lane_s16(
23846 ptr: *const i8,
23847 a: int16x8_t,
23848 b: int16x8_t,
23849 c: int16x8_t,
23850 n: i32,
23851 size: i32,
23852 ) -> int16x8x3_t;
23853 }
23854 _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
23855}
23856#[doc = "Load multiple 3-element structures to two registers"]
23857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
23858#[doc = "## Safety"]
23859#[doc = " * Neon instrinsic unsafe"]
23860#[inline]
23861#[cfg(target_arch = "arm")]
23862#[target_feature(enable = "neon,v7")]
23863#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23864#[rustc_legacy_const_generics(2)]
23865#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23866pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> int32x2x3_t {
23867 static_assert_uimm_bits!(LANE, 1);
23868 unsafe extern "unadjusted" {
23869 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0")]
23870 fn _vld3_lane_s32(
23871 ptr: *const i8,
23872 a: int32x2_t,
23873 b: int32x2_t,
23874 c: int32x2_t,
23875 n: i32,
23876 size: i32,
23877 ) -> int32x2x3_t;
23878 }
23879 _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
23880}
23881#[doc = "Load multiple 3-element structures to two registers"]
23882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
23883#[doc = "## Safety"]
23884#[doc = " * Neon instrinsic unsafe"]
23885#[inline]
23886#[cfg(target_arch = "arm")]
23887#[target_feature(enable = "neon,v7")]
23888#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
23889#[rustc_legacy_const_generics(2)]
23890#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
23891pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) -> int32x4x3_t {
23892 static_assert_uimm_bits!(LANE, 2);
23893 unsafe extern "unadjusted" {
23894 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0")]
23895 fn _vld3q_lane_s32(
23896 ptr: *const i8,
23897 a: int32x4_t,
23898 b: int32x4_t,
23899 c: int32x4_t,
23900 n: i32,
23901 size: i32,
23902 ) -> int32x4x3_t;
23903 }
23904 _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
23905}
23906#[doc = "Load multiple 3-element structures to three registers"]
23907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
23908#[doc = "## Safety"]
23909#[doc = " * Neon instrinsic unsafe"]
23910#[inline]
23911#[target_feature(enable = "neon")]
23912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23914#[cfg_attr(
23915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23916 assert_instr(ld3, LANE = 0)
23917)]
23918#[rustc_legacy_const_generics(2)]
23919#[cfg_attr(
23920 not(target_arch = "arm"),
23921 stable(feature = "neon_intrinsics", since = "1.59.0")
23922)]
23923#[cfg_attr(
23924 target_arch = "arm",
23925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23926)]
23927pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t {
23928 static_assert_uimm_bits!(LANE, 3);
23929 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
23930}
23931#[doc = "Load multiple 3-element structures to three registers"]
23932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
23933#[doc = "## Safety"]
23934#[doc = " * Neon instrinsic unsafe"]
23935#[inline]
23936#[target_feature(enable = "neon")]
23937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23939#[cfg_attr(
23940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23941 assert_instr(ld3, LANE = 0)
23942)]
23943#[rustc_legacy_const_generics(2)]
23944#[cfg_attr(
23945 not(target_arch = "arm"),
23946 stable(feature = "neon_intrinsics", since = "1.59.0")
23947)]
23948#[cfg_attr(
23949 target_arch = "arm",
23950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23951)]
23952pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t {
23953 static_assert_uimm_bits!(LANE, 2);
23954 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
23955}
23956#[doc = "Load multiple 3-element structures to three registers"]
23957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
23958#[doc = "## Safety"]
23959#[doc = " * Neon instrinsic unsafe"]
23960#[inline]
23961#[target_feature(enable = "neon")]
23962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23964#[cfg_attr(
23965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23966 assert_instr(ld3, LANE = 0)
23967)]
23968#[rustc_legacy_const_generics(2)]
23969#[cfg_attr(
23970 not(target_arch = "arm"),
23971 stable(feature = "neon_intrinsics", since = "1.59.0")
23972)]
23973#[cfg_attr(
23974 target_arch = "arm",
23975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
23976)]
23977pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t {
23978 static_assert_uimm_bits!(LANE, 3);
23979 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
23980}
23981#[doc = "Load multiple 3-element structures to three registers"]
23982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
23983#[doc = "## Safety"]
23984#[doc = " * Neon instrinsic unsafe"]
23985#[inline]
23986#[target_feature(enable = "neon")]
23987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
23988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
23989#[cfg_attr(
23990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
23991 assert_instr(ld3, LANE = 0)
23992)]
23993#[rustc_legacy_const_generics(2)]
23994#[cfg_attr(
23995 not(target_arch = "arm"),
23996 stable(feature = "neon_intrinsics", since = "1.59.0")
23997)]
23998#[cfg_attr(
23999 target_arch = "arm",
24000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24001)]
24002pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t {
24003 static_assert_uimm_bits!(LANE, 1);
24004 transmute(vld3_lane_s32::<LANE>(transmute(a), transmute(b)))
24005}
24006#[doc = "Load multiple 3-element structures to three registers"]
24007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
24008#[doc = "## Safety"]
24009#[doc = " * Neon instrinsic unsafe"]
24010#[inline]
24011#[target_feature(enable = "neon")]
24012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24014#[cfg_attr(
24015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24016 assert_instr(ld3, LANE = 0)
24017)]
24018#[rustc_legacy_const_generics(2)]
24019#[cfg_attr(
24020 not(target_arch = "arm"),
24021 stable(feature = "neon_intrinsics", since = "1.59.0")
24022)]
24023#[cfg_attr(
24024 target_arch = "arm",
24025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24026)]
24027pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t {
24028 static_assert_uimm_bits!(LANE, 2);
24029 transmute(vld3q_lane_s32::<LANE>(transmute(a), transmute(b)))
24030}
24031#[doc = "Load multiple 3-element structures to three registers"]
24032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
24033#[doc = "## Safety"]
24034#[doc = " * Neon instrinsic unsafe"]
24035#[inline]
24036#[target_feature(enable = "neon")]
24037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24039#[cfg_attr(
24040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24041 assert_instr(ld3, LANE = 0)
24042)]
24043#[rustc_legacy_const_generics(2)]
24044#[cfg_attr(
24045 not(target_arch = "arm"),
24046 stable(feature = "neon_intrinsics", since = "1.59.0")
24047)]
24048#[cfg_attr(
24049 target_arch = "arm",
24050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24051)]
24052pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t {
24053 static_assert_uimm_bits!(LANE, 3);
24054 transmute(vld3_lane_s8::<LANE>(transmute(a), transmute(b)))
24055}
24056#[doc = "Load multiple 3-element structures to three registers"]
24057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
24058#[doc = "## Safety"]
24059#[doc = " * Neon instrinsic unsafe"]
24060#[inline]
24061#[target_feature(enable = "neon")]
24062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24064#[cfg_attr(
24065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24066 assert_instr(ld3, LANE = 0)
24067)]
24068#[rustc_legacy_const_generics(2)]
24069#[cfg_attr(
24070 not(target_arch = "arm"),
24071 stable(feature = "neon_intrinsics", since = "1.59.0")
24072)]
24073#[cfg_attr(
24074 target_arch = "arm",
24075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24076)]
24077pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t {
24078 static_assert_uimm_bits!(LANE, 2);
24079 transmute(vld3_lane_s16::<LANE>(transmute(a), transmute(b)))
24080}
24081#[doc = "Load multiple 3-element structures to three registers"]
24082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
24083#[doc = "## Safety"]
24084#[doc = " * Neon instrinsic unsafe"]
24085#[inline]
24086#[target_feature(enable = "neon")]
24087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
24089#[cfg_attr(
24090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24091 assert_instr(ld3, LANE = 0)
24092)]
24093#[rustc_legacy_const_generics(2)]
24094#[cfg_attr(
24095 not(target_arch = "arm"),
24096 stable(feature = "neon_intrinsics", since = "1.59.0")
24097)]
24098#[cfg_attr(
24099 target_arch = "arm",
24100 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24101)]
24102pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t {
24103 static_assert_uimm_bits!(LANE, 3);
24104 transmute(vld3q_lane_s16::<LANE>(transmute(a), transmute(b)))
24105}
24106#[doc = "Load multiple 3-element structures to three registers"]
24107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
24108#[doc = "## Safety"]
24109#[doc = " * Neon instrinsic unsafe"]
24110#[inline]
24111#[target_feature(enable = "neon,aes")]
24112#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
24113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24114#[cfg_attr(
24115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24116 assert_instr(nop)
24117)]
24118#[cfg_attr(
24119 not(target_arch = "arm"),
24120 stable(feature = "neon_intrinsics", since = "1.59.0")
24121)]
24122#[cfg_attr(
24123 target_arch = "arm",
24124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24125)]
24126pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
24127 transmute(vld3_s64(transmute(a)))
24128}
24129#[doc = "Load multiple 3-element structures to three registers"]
24130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24131#[doc = "## Safety"]
24132#[doc = " * Neon instrinsic unsafe"]
24133#[inline]
24134#[target_feature(enable = "neon")]
24135#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24136#[cfg(not(target_arch = "arm"))]
24137#[cfg_attr(test, assert_instr(nop))]
24138pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24139 unsafe extern "unadjusted" {
24140 #[cfg_attr(
24141 any(target_arch = "aarch64", target_arch = "arm64ec"),
24142 link_name = "llvm.aarch64.neon.ld3.v1i64.p0"
24143 )]
24144 fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t;
24145 }
24146 _vld3_s64(a as _)
24147}
24148#[doc = "Load multiple 3-element structures to three registers"]
24149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
24150#[doc = "## Safety"]
24151#[doc = " * Neon instrinsic unsafe"]
24152#[inline]
24153#[cfg(target_arch = "arm")]
24154#[target_feature(enable = "neon,v7")]
24155#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24156#[cfg_attr(test, assert_instr(nop))]
24157pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
24158 unsafe extern "unadjusted" {
24159 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0")]
24160 fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t;
24161 }
24162 _vld3_s64(a as *const i8, 8)
24163}
24164#[doc = "Load multiple 3-element structures to three registers"]
24165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
24166#[doc = "## Safety"]
24167#[doc = " * Neon instrinsic unsafe"]
24168#[inline]
24169#[target_feature(enable = "neon")]
24170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
24172#[cfg_attr(
24173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24174 assert_instr(nop)
24175)]
24176#[cfg_attr(
24177 not(target_arch = "arm"),
24178 stable(feature = "neon_intrinsics", since = "1.59.0")
24179)]
24180#[cfg_attr(
24181 target_arch = "arm",
24182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24183)]
24184pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
24185 transmute(vld3_s64(transmute(a)))
24186}
24187#[doc = "Load multiple 3-element structures to three registers"]
24188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24189#[doc = "## Safety"]
24190#[doc = " * Neon instrinsic unsafe"]
24191#[inline]
24192#[cfg(target_endian = "little")]
24193#[target_feature(enable = "neon")]
24194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24196#[cfg_attr(
24197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24198 assert_instr(ld3)
24199)]
24200#[cfg_attr(
24201 not(target_arch = "arm"),
24202 stable(feature = "neon_intrinsics", since = "1.59.0")
24203)]
24204#[cfg_attr(
24205 target_arch = "arm",
24206 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24207)]
24208pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24209 transmute(vld3_s8(transmute(a)))
24210}
24211#[doc = "Load multiple 3-element structures to three registers"]
24212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
24213#[doc = "## Safety"]
24214#[doc = " * Neon instrinsic unsafe"]
24215#[inline]
24216#[cfg(target_endian = "big")]
24217#[target_feature(enable = "neon")]
24218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24220#[cfg_attr(
24221 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24222 assert_instr(ld3)
24223)]
24224#[cfg_attr(
24225 not(target_arch = "arm"),
24226 stable(feature = "neon_intrinsics", since = "1.59.0")
24227)]
24228#[cfg_attr(
24229 target_arch = "arm",
24230 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24231)]
24232pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
24233 let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a)));
24234 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24235 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24236 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24237 ret_val
24238}
24239#[doc = "Load multiple 3-element structures to three registers"]
24240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24241#[doc = "## Safety"]
24242#[doc = " * Neon instrinsic unsafe"]
24243#[inline]
24244#[cfg(target_endian = "little")]
24245#[target_feature(enable = "neon")]
24246#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24248#[cfg_attr(
24249 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24250 assert_instr(ld3)
24251)]
24252#[cfg_attr(
24253 not(target_arch = "arm"),
24254 stable(feature = "neon_intrinsics", since = "1.59.0")
24255)]
24256#[cfg_attr(
24257 target_arch = "arm",
24258 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24259)]
24260pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24261 transmute(vld3q_s8(transmute(a)))
24262}
24263#[doc = "Load multiple 3-element structures to three registers"]
24264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
24265#[doc = "## Safety"]
24266#[doc = " * Neon instrinsic unsafe"]
24267#[inline]
24268#[cfg(target_endian = "big")]
24269#[target_feature(enable = "neon")]
24270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24272#[cfg_attr(
24273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24274 assert_instr(ld3)
24275)]
24276#[cfg_attr(
24277 not(target_arch = "arm"),
24278 stable(feature = "neon_intrinsics", since = "1.59.0")
24279)]
24280#[cfg_attr(
24281 target_arch = "arm",
24282 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24283)]
24284pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
24285 let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a)));
24286 ret_val.0 = unsafe {
24287 simd_shuffle!(
24288 ret_val.0,
24289 ret_val.0,
24290 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24291 )
24292 };
24293 ret_val.1 = unsafe {
24294 simd_shuffle!(
24295 ret_val.1,
24296 ret_val.1,
24297 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24298 )
24299 };
24300 ret_val.2 = unsafe {
24301 simd_shuffle!(
24302 ret_val.2,
24303 ret_val.2,
24304 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24305 )
24306 };
24307 ret_val
24308}
24309#[doc = "Load multiple 3-element structures to three registers"]
24310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24311#[doc = "## Safety"]
24312#[doc = " * Neon instrinsic unsafe"]
24313#[inline]
24314#[cfg(target_endian = "little")]
24315#[target_feature(enable = "neon")]
24316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24318#[cfg_attr(
24319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24320 assert_instr(ld3)
24321)]
24322#[cfg_attr(
24323 not(target_arch = "arm"),
24324 stable(feature = "neon_intrinsics", since = "1.59.0")
24325)]
24326#[cfg_attr(
24327 target_arch = "arm",
24328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24329)]
24330pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24331 transmute(vld3_s16(transmute(a)))
24332}
24333#[doc = "Load multiple 3-element structures to three registers"]
24334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
24335#[doc = "## Safety"]
24336#[doc = " * Neon instrinsic unsafe"]
24337#[inline]
24338#[cfg(target_endian = "big")]
24339#[target_feature(enable = "neon")]
24340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24341#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24342#[cfg_attr(
24343 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24344 assert_instr(ld3)
24345)]
24346#[cfg_attr(
24347 not(target_arch = "arm"),
24348 stable(feature = "neon_intrinsics", since = "1.59.0")
24349)]
24350#[cfg_attr(
24351 target_arch = "arm",
24352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24353)]
24354pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
24355 let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a)));
24356 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24357 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24358 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24359 ret_val
24360}
24361#[doc = "Load multiple 3-element structures to three registers"]
24362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24363#[doc = "## Safety"]
24364#[doc = " * Neon instrinsic unsafe"]
24365#[inline]
24366#[cfg(target_endian = "little")]
24367#[target_feature(enable = "neon")]
24368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24370#[cfg_attr(
24371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24372 assert_instr(ld3)
24373)]
24374#[cfg_attr(
24375 not(target_arch = "arm"),
24376 stable(feature = "neon_intrinsics", since = "1.59.0")
24377)]
24378#[cfg_attr(
24379 target_arch = "arm",
24380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24381)]
24382pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24383 transmute(vld3q_s16(transmute(a)))
24384}
24385#[doc = "Load multiple 3-element structures to three registers"]
24386#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
24387#[doc = "## Safety"]
24388#[doc = " * Neon instrinsic unsafe"]
24389#[inline]
24390#[cfg(target_endian = "big")]
24391#[target_feature(enable = "neon")]
24392#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24393#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24394#[cfg_attr(
24395 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24396 assert_instr(ld3)
24397)]
24398#[cfg_attr(
24399 not(target_arch = "arm"),
24400 stable(feature = "neon_intrinsics", since = "1.59.0")
24401)]
24402#[cfg_attr(
24403 target_arch = "arm",
24404 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24405)]
24406pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
24407 let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a)));
24408 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24409 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24410 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24411 ret_val
24412}
24413#[doc = "Load multiple 3-element structures to three registers"]
24414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24415#[doc = "## Safety"]
24416#[doc = " * Neon instrinsic unsafe"]
24417#[inline]
24418#[cfg(target_endian = "little")]
24419#[target_feature(enable = "neon")]
24420#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24421#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24422#[cfg_attr(
24423 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24424 assert_instr(ld3)
24425)]
24426#[cfg_attr(
24427 not(target_arch = "arm"),
24428 stable(feature = "neon_intrinsics", since = "1.59.0")
24429)]
24430#[cfg_attr(
24431 target_arch = "arm",
24432 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24433)]
24434pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24435 transmute(vld3_s32(transmute(a)))
24436}
24437#[doc = "Load multiple 3-element structures to three registers"]
24438#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
24439#[doc = "## Safety"]
24440#[doc = " * Neon instrinsic unsafe"]
24441#[inline]
24442#[cfg(target_endian = "big")]
24443#[target_feature(enable = "neon")]
24444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24446#[cfg_attr(
24447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24448 assert_instr(ld3)
24449)]
24450#[cfg_attr(
24451 not(target_arch = "arm"),
24452 stable(feature = "neon_intrinsics", since = "1.59.0")
24453)]
24454#[cfg_attr(
24455 target_arch = "arm",
24456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24457)]
24458pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
24459 let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a)));
24460 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
24461 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
24462 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
24463 ret_val
24464}
24465#[doc = "Load multiple 3-element structures to three registers"]
24466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24467#[doc = "## Safety"]
24468#[doc = " * Neon instrinsic unsafe"]
24469#[inline]
24470#[cfg(target_endian = "little")]
24471#[target_feature(enable = "neon")]
24472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24474#[cfg_attr(
24475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24476 assert_instr(ld3)
24477)]
24478#[cfg_attr(
24479 not(target_arch = "arm"),
24480 stable(feature = "neon_intrinsics", since = "1.59.0")
24481)]
24482#[cfg_attr(
24483 target_arch = "arm",
24484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24485)]
24486pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24487 transmute(vld3q_s32(transmute(a)))
24488}
24489#[doc = "Load multiple 3-element structures to three registers"]
24490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
24491#[doc = "## Safety"]
24492#[doc = " * Neon instrinsic unsafe"]
24493#[inline]
24494#[cfg(target_endian = "big")]
24495#[target_feature(enable = "neon")]
24496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24498#[cfg_attr(
24499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24500 assert_instr(ld3)
24501)]
24502#[cfg_attr(
24503 not(target_arch = "arm"),
24504 stable(feature = "neon_intrinsics", since = "1.59.0")
24505)]
24506#[cfg_attr(
24507 target_arch = "arm",
24508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24509)]
24510pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
24511 let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a)));
24512 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24513 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24514 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24515 ret_val
24516}
24517#[doc = "Load multiple 3-element structures to three registers"]
24518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24519#[doc = "## Safety"]
24520#[doc = " * Neon instrinsic unsafe"]
24521#[inline]
24522#[cfg(target_endian = "little")]
24523#[target_feature(enable = "neon")]
24524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24526#[cfg_attr(
24527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24528 assert_instr(ld3)
24529)]
24530#[cfg_attr(
24531 not(target_arch = "arm"),
24532 stable(feature = "neon_intrinsics", since = "1.59.0")
24533)]
24534#[cfg_attr(
24535 target_arch = "arm",
24536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24537)]
24538pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24539 transmute(vld3_s8(transmute(a)))
24540}
24541#[doc = "Load multiple 3-element structures to three registers"]
24542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
24543#[doc = "## Safety"]
24544#[doc = " * Neon instrinsic unsafe"]
24545#[inline]
24546#[cfg(target_endian = "big")]
24547#[target_feature(enable = "neon")]
24548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24550#[cfg_attr(
24551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24552 assert_instr(ld3)
24553)]
24554#[cfg_attr(
24555 not(target_arch = "arm"),
24556 stable(feature = "neon_intrinsics", since = "1.59.0")
24557)]
24558#[cfg_attr(
24559 target_arch = "arm",
24560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24561)]
24562pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
24563 let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a)));
24564 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24565 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24566 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24567 ret_val
24568}
24569#[doc = "Load multiple 3-element structures to three registers"]
24570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24571#[doc = "## Safety"]
24572#[doc = " * Neon instrinsic unsafe"]
24573#[inline]
24574#[cfg(target_endian = "little")]
24575#[target_feature(enable = "neon")]
24576#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24577#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24578#[cfg_attr(
24579 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24580 assert_instr(ld3)
24581)]
24582#[cfg_attr(
24583 not(target_arch = "arm"),
24584 stable(feature = "neon_intrinsics", since = "1.59.0")
24585)]
24586#[cfg_attr(
24587 target_arch = "arm",
24588 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24589)]
24590pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24591 transmute(vld3q_s8(transmute(a)))
24592}
24593#[doc = "Load multiple 3-element structures to three registers"]
24594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
24595#[doc = "## Safety"]
24596#[doc = " * Neon instrinsic unsafe"]
24597#[inline]
24598#[cfg(target_endian = "big")]
24599#[target_feature(enable = "neon")]
24600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24602#[cfg_attr(
24603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24604 assert_instr(ld3)
24605)]
24606#[cfg_attr(
24607 not(target_arch = "arm"),
24608 stable(feature = "neon_intrinsics", since = "1.59.0")
24609)]
24610#[cfg_attr(
24611 target_arch = "arm",
24612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24613)]
24614pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
24615 let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a)));
24616 ret_val.0 = unsafe {
24617 simd_shuffle!(
24618 ret_val.0,
24619 ret_val.0,
24620 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24621 )
24622 };
24623 ret_val.1 = unsafe {
24624 simd_shuffle!(
24625 ret_val.1,
24626 ret_val.1,
24627 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24628 )
24629 };
24630 ret_val.2 = unsafe {
24631 simd_shuffle!(
24632 ret_val.2,
24633 ret_val.2,
24634 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
24635 )
24636 };
24637 ret_val
24638}
24639#[doc = "Load multiple 3-element structures to three registers"]
24640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24641#[doc = "## Safety"]
24642#[doc = " * Neon instrinsic unsafe"]
24643#[inline]
24644#[cfg(target_endian = "little")]
24645#[target_feature(enable = "neon")]
24646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24648#[cfg_attr(
24649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24650 assert_instr(ld3)
24651)]
24652#[cfg_attr(
24653 not(target_arch = "arm"),
24654 stable(feature = "neon_intrinsics", since = "1.59.0")
24655)]
24656#[cfg_attr(
24657 target_arch = "arm",
24658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24659)]
24660pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24661 transmute(vld3_s16(transmute(a)))
24662}
24663#[doc = "Load multiple 3-element structures to three registers"]
24664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
24665#[doc = "## Safety"]
24666#[doc = " * Neon instrinsic unsafe"]
24667#[inline]
24668#[cfg(target_endian = "big")]
24669#[target_feature(enable = "neon")]
24670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24672#[cfg_attr(
24673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24674 assert_instr(ld3)
24675)]
24676#[cfg_attr(
24677 not(target_arch = "arm"),
24678 stable(feature = "neon_intrinsics", since = "1.59.0")
24679)]
24680#[cfg_attr(
24681 target_arch = "arm",
24682 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24683)]
24684pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
24685 let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a)));
24686 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
24687 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
24688 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
24689 ret_val
24690}
24691#[doc = "Load multiple 3-element structures to three registers"]
24692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24693#[doc = "## Safety"]
24694#[doc = " * Neon instrinsic unsafe"]
24695#[inline]
24696#[cfg(target_endian = "little")]
24697#[target_feature(enable = "neon")]
24698#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24699#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24700#[cfg_attr(
24701 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24702 assert_instr(ld3)
24703)]
24704#[cfg_attr(
24705 not(target_arch = "arm"),
24706 stable(feature = "neon_intrinsics", since = "1.59.0")
24707)]
24708#[cfg_attr(
24709 target_arch = "arm",
24710 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24711)]
24712pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24713 transmute(vld3q_s16(transmute(a)))
24714}
24715#[doc = "Load multiple 3-element structures to three registers"]
24716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
24717#[doc = "## Safety"]
24718#[doc = " * Neon instrinsic unsafe"]
24719#[inline]
24720#[cfg(target_endian = "big")]
24721#[target_feature(enable = "neon")]
24722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))]
24724#[cfg_attr(
24725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24726 assert_instr(ld3)
24727)]
24728#[cfg_attr(
24729 not(target_arch = "arm"),
24730 stable(feature = "neon_intrinsics", since = "1.59.0")
24731)]
24732#[cfg_attr(
24733 target_arch = "arm",
24734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
24735)]
24736pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
24737 let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a)));
24738 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
24739 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
24740 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
24741 ret_val
24742}
24743#[doc = "Load multiple 3-element structures to three registers"]
24744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
24745#[doc = "## Safety"]
24746#[doc = " * Neon instrinsic unsafe"]
24747#[inline]
24748#[cfg(target_arch = "arm")]
24749#[target_feature(enable = "neon,v7")]
24750#[cfg_attr(test, assert_instr(vld3, LANE = 0))]
24751#[rustc_legacy_const_generics(2)]
24752#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24753pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -> float32x4x3_t {
24754 static_assert_uimm_bits!(LANE, 2);
24755 unsafe extern "unadjusted" {
24756 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0")]
24757 fn _vld3q_lane_f32(
24758 ptr: *const i8,
24759 a: float32x4_t,
24760 b: float32x4_t,
24761 c: float32x4_t,
24762 n: i32,
24763 size: i32,
24764 ) -> float32x4x3_t;
24765 }
24766 _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
24767}
24768#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24770#[doc = "## Safety"]
24771#[doc = " * Neon instrinsic unsafe"]
24772#[inline]
24773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24774#[cfg(target_arch = "arm")]
24775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24776#[target_feature(enable = "neon,fp16")]
24777#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24778pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24779 unsafe extern "unadjusted" {
24780 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f16.p0")]
24781 fn _vld4_dup_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
24782 }
24783 _vld4_dup_f16(a as _, 2)
24784}
24785#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24787#[doc = "## Safety"]
24788#[doc = " * Neon instrinsic unsafe"]
24789#[inline]
24790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
24791#[cfg(target_arch = "arm")]
24792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
24793#[target_feature(enable = "neon,fp16")]
24794#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24795pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24796 unsafe extern "unadjusted" {
24797 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8f16.p0")]
24798 fn _vld4q_dup_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
24799 }
24800 _vld4q_dup_f16(a as _, 2)
24801}
24802#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
24804#[doc = "## Safety"]
24805#[doc = " * Neon instrinsic unsafe"]
24806#[inline]
24807#[cfg(not(target_arch = "arm"))]
24808#[cfg_attr(
24809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24810 assert_instr(ld4r)
24811)]
24812#[target_feature(enable = "neon,fp16")]
24813#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24814pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
24815 unsafe extern "unadjusted" {
24816 #[cfg_attr(
24817 any(target_arch = "aarch64", target_arch = "arm64ec"),
24818 link_name = "llvm.aarch64.neon.ld4r.v4f16.p0"
24819 )]
24820 fn _vld4_dup_f16(ptr: *const f16) -> float16x4x4_t;
24821 }
24822 _vld4_dup_f16(a as _)
24823}
24824#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
24825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
24826#[doc = "## Safety"]
24827#[doc = " * Neon instrinsic unsafe"]
24828#[inline]
24829#[cfg(not(target_arch = "arm"))]
24830#[cfg_attr(
24831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
24832 assert_instr(ld4r)
24833)]
24834#[target_feature(enable = "neon,fp16")]
24835#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
24836pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
24837 unsafe extern "unadjusted" {
24838 #[cfg_attr(
24839 any(target_arch = "aarch64", target_arch = "arm64ec"),
24840 link_name = "llvm.aarch64.neon.ld4r.v8f16.p0"
24841 )]
24842 fn _vld4q_dup_f16(ptr: *const f16) -> float16x8x4_t;
24843 }
24844 _vld4q_dup_f16(a as _)
24845}
24846#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
24848#[doc = "## Safety"]
24849#[doc = " * Neon instrinsic unsafe"]
24850#[inline]
24851#[cfg(target_arch = "arm")]
24852#[target_feature(enable = "neon,v7")]
24853#[cfg_attr(test, assert_instr(vld4))]
24854#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24855pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
24856 unsafe extern "unadjusted" {
24857 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0")]
24858 fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
24859 }
24860 _vld4_dup_f32(a as *const i8, 4)
24861}
24862#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
24864#[doc = "## Safety"]
24865#[doc = " * Neon instrinsic unsafe"]
24866#[inline]
24867#[cfg(target_arch = "arm")]
24868#[target_feature(enable = "neon,v7")]
24869#[cfg_attr(test, assert_instr(vld4))]
24870#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24871pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
24872 unsafe extern "unadjusted" {
24873 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0")]
24874 fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
24875 }
24876 _vld4q_dup_f32(a as *const i8, 4)
24877}
24878#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
24880#[doc = "## Safety"]
24881#[doc = " * Neon instrinsic unsafe"]
24882#[inline]
24883#[cfg(target_arch = "arm")]
24884#[target_feature(enable = "neon,v7")]
24885#[cfg_attr(test, assert_instr(vld4))]
24886#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24887pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
24888 unsafe extern "unadjusted" {
24889 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0")]
24890 fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
24891 }
24892 _vld4_dup_s8(a as *const i8, 1)
24893}
24894#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
24896#[doc = "## Safety"]
24897#[doc = " * Neon instrinsic unsafe"]
24898#[inline]
24899#[cfg(target_arch = "arm")]
24900#[target_feature(enable = "neon,v7")]
24901#[cfg_attr(test, assert_instr(vld4))]
24902#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24903pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
24904 unsafe extern "unadjusted" {
24905 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0")]
24906 fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
24907 }
24908 _vld4q_dup_s8(a as *const i8, 1)
24909}
24910#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
24912#[doc = "## Safety"]
24913#[doc = " * Neon instrinsic unsafe"]
24914#[inline]
24915#[cfg(target_arch = "arm")]
24916#[target_feature(enable = "neon,v7")]
24917#[cfg_attr(test, assert_instr(vld4))]
24918#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24919pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
24920 unsafe extern "unadjusted" {
24921 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0")]
24922 fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
24923 }
24924 _vld4_dup_s16(a as *const i8, 2)
24925}
24926#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
24928#[doc = "## Safety"]
24929#[doc = " * Neon instrinsic unsafe"]
24930#[inline]
24931#[cfg(target_arch = "arm")]
24932#[target_feature(enable = "neon,v7")]
24933#[cfg_attr(test, assert_instr(vld4))]
24934#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24935pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
24936 unsafe extern "unadjusted" {
24937 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0")]
24938 fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
24939 }
24940 _vld4q_dup_s16(a as *const i8, 2)
24941}
24942#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
24944#[doc = "## Safety"]
24945#[doc = " * Neon instrinsic unsafe"]
24946#[inline]
24947#[cfg(target_arch = "arm")]
24948#[target_feature(enable = "neon,v7")]
24949#[cfg_attr(test, assert_instr(vld4))]
24950#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24951pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
24952 unsafe extern "unadjusted" {
24953 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0")]
24954 fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
24955 }
24956 _vld4_dup_s32(a as *const i8, 4)
24957}
24958#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
24960#[doc = "## Safety"]
24961#[doc = " * Neon instrinsic unsafe"]
24962#[inline]
24963#[cfg(target_arch = "arm")]
24964#[target_feature(enable = "neon,v7")]
24965#[cfg_attr(test, assert_instr(vld4))]
24966#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
24967pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
24968 unsafe extern "unadjusted" {
24969 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0")]
24970 fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
24971 }
24972 _vld4q_dup_s32(a as *const i8, 4)
24973}
24974#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
24976#[doc = "## Safety"]
24977#[doc = " * Neon instrinsic unsafe"]
24978#[inline]
24979#[target_feature(enable = "neon")]
24980#[cfg(not(target_arch = "arm"))]
24981#[cfg_attr(test, assert_instr(ld4r))]
24982#[stable(feature = "neon_intrinsics", since = "1.59.0")]
24983pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
24984 unsafe extern "unadjusted" {
24985 #[cfg_attr(
24986 any(target_arch = "aarch64", target_arch = "arm64ec"),
24987 link_name = "llvm.aarch64.neon.ld4r.v2f32.p0.p0"
24988 )]
24989 fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t;
24990 }
24991 _vld4_dup_f32(a as _)
24992}
24993#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
24994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
24995#[doc = "## Safety"]
24996#[doc = " * Neon instrinsic unsafe"]
24997#[inline]
24998#[target_feature(enable = "neon")]
24999#[cfg(not(target_arch = "arm"))]
25000#[cfg_attr(test, assert_instr(ld4r))]
25001#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25002pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
25003 unsafe extern "unadjusted" {
25004 #[cfg_attr(
25005 any(target_arch = "aarch64", target_arch = "arm64ec"),
25006 link_name = "llvm.aarch64.neon.ld4r.v4f32.p0.p0"
25007 )]
25008 fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t;
25009 }
25010 _vld4q_dup_f32(a as _)
25011}
25012#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
25014#[doc = "## Safety"]
25015#[doc = " * Neon instrinsic unsafe"]
25016#[inline]
25017#[target_feature(enable = "neon")]
25018#[cfg(not(target_arch = "arm"))]
25019#[cfg_attr(test, assert_instr(ld4r))]
25020#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25021pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
25022 unsafe extern "unadjusted" {
25023 #[cfg_attr(
25024 any(target_arch = "aarch64", target_arch = "arm64ec"),
25025 link_name = "llvm.aarch64.neon.ld4r.v8i8.p0.p0"
25026 )]
25027 fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t;
25028 }
25029 _vld4_dup_s8(a as _)
25030}
25031#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
25033#[doc = "## Safety"]
25034#[doc = " * Neon instrinsic unsafe"]
25035#[inline]
25036#[target_feature(enable = "neon")]
25037#[cfg(not(target_arch = "arm"))]
25038#[cfg_attr(test, assert_instr(ld4r))]
25039#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25040pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
25041 unsafe extern "unadjusted" {
25042 #[cfg_attr(
25043 any(target_arch = "aarch64", target_arch = "arm64ec"),
25044 link_name = "llvm.aarch64.neon.ld4r.v16i8.p0.p0"
25045 )]
25046 fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t;
25047 }
25048 _vld4q_dup_s8(a as _)
25049}
25050#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
25052#[doc = "## Safety"]
25053#[doc = " * Neon instrinsic unsafe"]
25054#[inline]
25055#[target_feature(enable = "neon")]
25056#[cfg(not(target_arch = "arm"))]
25057#[cfg_attr(test, assert_instr(ld4r))]
25058#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25059pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
25060 unsafe extern "unadjusted" {
25061 #[cfg_attr(
25062 any(target_arch = "aarch64", target_arch = "arm64ec"),
25063 link_name = "llvm.aarch64.neon.ld4r.v4i16.p0.p0"
25064 )]
25065 fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t;
25066 }
25067 _vld4_dup_s16(a as _)
25068}
25069#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
25071#[doc = "## Safety"]
25072#[doc = " * Neon instrinsic unsafe"]
25073#[inline]
25074#[target_feature(enable = "neon")]
25075#[cfg(not(target_arch = "arm"))]
25076#[cfg_attr(test, assert_instr(ld4r))]
25077#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25078pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
25079 unsafe extern "unadjusted" {
25080 #[cfg_attr(
25081 any(target_arch = "aarch64", target_arch = "arm64ec"),
25082 link_name = "llvm.aarch64.neon.ld4r.v8i16.p0.p0"
25083 )]
25084 fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t;
25085 }
25086 _vld4q_dup_s16(a as _)
25087}
25088#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
25090#[doc = "## Safety"]
25091#[doc = " * Neon instrinsic unsafe"]
25092#[inline]
25093#[target_feature(enable = "neon")]
25094#[cfg(not(target_arch = "arm"))]
25095#[cfg_attr(test, assert_instr(ld4r))]
25096#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25097pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
25098 unsafe extern "unadjusted" {
25099 #[cfg_attr(
25100 any(target_arch = "aarch64", target_arch = "arm64ec"),
25101 link_name = "llvm.aarch64.neon.ld4r.v2i32.p0.p0"
25102 )]
25103 fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t;
25104 }
25105 _vld4_dup_s32(a as _)
25106}
25107#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
25109#[doc = "## Safety"]
25110#[doc = " * Neon instrinsic unsafe"]
25111#[inline]
25112#[target_feature(enable = "neon")]
25113#[cfg(not(target_arch = "arm"))]
25114#[cfg_attr(test, assert_instr(ld4r))]
25115#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25116pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
25117 unsafe extern "unadjusted" {
25118 #[cfg_attr(
25119 any(target_arch = "aarch64", target_arch = "arm64ec"),
25120 link_name = "llvm.aarch64.neon.ld4r.v4i32.p0.p0"
25121 )]
25122 fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t;
25123 }
25124 _vld4q_dup_s32(a as _)
25125}
25126#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25128#[doc = "## Safety"]
25129#[doc = " * Neon instrinsic unsafe"]
25130#[inline]
25131#[target_feature(enable = "neon")]
25132#[cfg(not(target_arch = "arm"))]
25133#[cfg_attr(test, assert_instr(ld4r))]
25134#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25135pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25136 unsafe extern "unadjusted" {
25137 #[cfg_attr(
25138 any(target_arch = "aarch64", target_arch = "arm64ec"),
25139 link_name = "llvm.aarch64.neon.ld4r.v1i64.p0.p0"
25140 )]
25141 fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t;
25142 }
25143 _vld4_dup_s64(a as _)
25144}
25145#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25146#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
25147#[doc = "## Safety"]
25148#[doc = " * Neon instrinsic unsafe"]
25149#[inline]
25150#[target_feature(enable = "neon,aes")]
25151#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
25152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25153#[cfg_attr(
25154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25155 assert_instr(ld4r)
25156)]
25157#[cfg_attr(
25158 not(target_arch = "arm"),
25159 stable(feature = "neon_intrinsics", since = "1.59.0")
25160)]
25161#[cfg_attr(
25162 target_arch = "arm",
25163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25164)]
25165pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
25166 transmute(vld4_dup_s64(transmute(a)))
25167}
25168#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
25170#[doc = "## Safety"]
25171#[doc = " * Neon instrinsic unsafe"]
25172#[inline]
25173#[cfg(target_arch = "arm")]
25174#[target_feature(enable = "neon,v7")]
25175#[cfg_attr(test, assert_instr(nop))]
25176#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
25177pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
25178 unsafe extern "unadjusted" {
25179 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0")]
25180 fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
25181 }
25182 _vld4_dup_s64(a as *const i8, 8)
25183}
25184#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
25186#[doc = "## Safety"]
25187#[doc = " * Neon instrinsic unsafe"]
25188#[inline]
25189#[target_feature(enable = "neon")]
25190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
25192#[cfg_attr(
25193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25194 assert_instr(ld4r)
25195)]
25196#[cfg_attr(
25197 not(target_arch = "arm"),
25198 stable(feature = "neon_intrinsics", since = "1.59.0")
25199)]
25200#[cfg_attr(
25201 target_arch = "arm",
25202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25203)]
25204pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
25205 transmute(vld4_dup_s64(transmute(a)))
25206}
25207#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25209#[doc = "## Safety"]
25210#[doc = " * Neon instrinsic unsafe"]
25211#[inline]
25212#[cfg(target_endian = "little")]
25213#[target_feature(enable = "neon")]
25214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25216#[cfg_attr(
25217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25218 assert_instr(ld4r)
25219)]
25220#[cfg_attr(
25221 not(target_arch = "arm"),
25222 stable(feature = "neon_intrinsics", since = "1.59.0")
25223)]
25224#[cfg_attr(
25225 target_arch = "arm",
25226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25227)]
25228pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25229 transmute(vld4_dup_s8(transmute(a)))
25230}
25231#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
25233#[doc = "## Safety"]
25234#[doc = " * Neon instrinsic unsafe"]
25235#[inline]
25236#[cfg(target_endian = "big")]
25237#[target_feature(enable = "neon")]
25238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25240#[cfg_attr(
25241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25242 assert_instr(ld4r)
25243)]
25244#[cfg_attr(
25245 not(target_arch = "arm"),
25246 stable(feature = "neon_intrinsics", since = "1.59.0")
25247)]
25248#[cfg_attr(
25249 target_arch = "arm",
25250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25251)]
25252pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
25253 let mut ret_val: uint8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25254 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25255 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25256 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25257 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25258 ret_val
25259}
25260#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25262#[doc = "## Safety"]
25263#[doc = " * Neon instrinsic unsafe"]
25264#[inline]
25265#[cfg(target_endian = "little")]
25266#[target_feature(enable = "neon")]
25267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25269#[cfg_attr(
25270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25271 assert_instr(ld4r)
25272)]
25273#[cfg_attr(
25274 not(target_arch = "arm"),
25275 stable(feature = "neon_intrinsics", since = "1.59.0")
25276)]
25277#[cfg_attr(
25278 target_arch = "arm",
25279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25280)]
25281pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25282 transmute(vld4q_dup_s8(transmute(a)))
25283}
25284#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
25286#[doc = "## Safety"]
25287#[doc = " * Neon instrinsic unsafe"]
25288#[inline]
25289#[cfg(target_endian = "big")]
25290#[target_feature(enable = "neon")]
25291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25293#[cfg_attr(
25294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25295 assert_instr(ld4r)
25296)]
25297#[cfg_attr(
25298 not(target_arch = "arm"),
25299 stable(feature = "neon_intrinsics", since = "1.59.0")
25300)]
25301#[cfg_attr(
25302 target_arch = "arm",
25303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25304)]
25305pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
25306 let mut ret_val: uint8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25307 ret_val.0 = unsafe {
25308 simd_shuffle!(
25309 ret_val.0,
25310 ret_val.0,
25311 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25312 )
25313 };
25314 ret_val.1 = unsafe {
25315 simd_shuffle!(
25316 ret_val.1,
25317 ret_val.1,
25318 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25319 )
25320 };
25321 ret_val.2 = unsafe {
25322 simd_shuffle!(
25323 ret_val.2,
25324 ret_val.2,
25325 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25326 )
25327 };
25328 ret_val.3 = unsafe {
25329 simd_shuffle!(
25330 ret_val.3,
25331 ret_val.3,
25332 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25333 )
25334 };
25335 ret_val
25336}
25337#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25339#[doc = "## Safety"]
25340#[doc = " * Neon instrinsic unsafe"]
25341#[inline]
25342#[cfg(target_endian = "little")]
25343#[target_feature(enable = "neon")]
25344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25346#[cfg_attr(
25347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25348 assert_instr(ld4r)
25349)]
25350#[cfg_attr(
25351 not(target_arch = "arm"),
25352 stable(feature = "neon_intrinsics", since = "1.59.0")
25353)]
25354#[cfg_attr(
25355 target_arch = "arm",
25356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25357)]
25358pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25359 transmute(vld4_dup_s16(transmute(a)))
25360}
25361#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
25363#[doc = "## Safety"]
25364#[doc = " * Neon instrinsic unsafe"]
25365#[inline]
25366#[cfg(target_endian = "big")]
25367#[target_feature(enable = "neon")]
25368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25370#[cfg_attr(
25371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25372 assert_instr(ld4r)
25373)]
25374#[cfg_attr(
25375 not(target_arch = "arm"),
25376 stable(feature = "neon_intrinsics", since = "1.59.0")
25377)]
25378#[cfg_attr(
25379 target_arch = "arm",
25380 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25381)]
25382pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
25383 let mut ret_val: uint16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25384 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25385 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25386 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25387 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25388 ret_val
25389}
25390#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25392#[doc = "## Safety"]
25393#[doc = " * Neon instrinsic unsafe"]
25394#[inline]
25395#[cfg(target_endian = "little")]
25396#[target_feature(enable = "neon")]
25397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25399#[cfg_attr(
25400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25401 assert_instr(ld4r)
25402)]
25403#[cfg_attr(
25404 not(target_arch = "arm"),
25405 stable(feature = "neon_intrinsics", since = "1.59.0")
25406)]
25407#[cfg_attr(
25408 target_arch = "arm",
25409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25410)]
25411pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25412 transmute(vld4q_dup_s16(transmute(a)))
25413}
25414#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
25416#[doc = "## Safety"]
25417#[doc = " * Neon instrinsic unsafe"]
25418#[inline]
25419#[cfg(target_endian = "big")]
25420#[target_feature(enable = "neon")]
25421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25423#[cfg_attr(
25424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25425 assert_instr(ld4r)
25426)]
25427#[cfg_attr(
25428 not(target_arch = "arm"),
25429 stable(feature = "neon_intrinsics", since = "1.59.0")
25430)]
25431#[cfg_attr(
25432 target_arch = "arm",
25433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25434)]
25435pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
25436 let mut ret_val: uint16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25437 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25438 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25439 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25440 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25441 ret_val
25442}
25443#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25445#[doc = "## Safety"]
25446#[doc = " * Neon instrinsic unsafe"]
25447#[inline]
25448#[cfg(target_endian = "little")]
25449#[target_feature(enable = "neon")]
25450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25452#[cfg_attr(
25453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25454 assert_instr(ld4r)
25455)]
25456#[cfg_attr(
25457 not(target_arch = "arm"),
25458 stable(feature = "neon_intrinsics", since = "1.59.0")
25459)]
25460#[cfg_attr(
25461 target_arch = "arm",
25462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25463)]
25464pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25465 transmute(vld4_dup_s32(transmute(a)))
25466}
25467#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
25469#[doc = "## Safety"]
25470#[doc = " * Neon instrinsic unsafe"]
25471#[inline]
25472#[cfg(target_endian = "big")]
25473#[target_feature(enable = "neon")]
25474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25476#[cfg_attr(
25477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25478 assert_instr(ld4r)
25479)]
25480#[cfg_attr(
25481 not(target_arch = "arm"),
25482 stable(feature = "neon_intrinsics", since = "1.59.0")
25483)]
25484#[cfg_attr(
25485 target_arch = "arm",
25486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25487)]
25488pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
25489 let mut ret_val: uint32x2x4_t = transmute(vld4_dup_s32(transmute(a)));
25490 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
25491 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
25492 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
25493 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
25494 ret_val
25495}
25496#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25498#[doc = "## Safety"]
25499#[doc = " * Neon instrinsic unsafe"]
25500#[inline]
25501#[cfg(target_endian = "little")]
25502#[target_feature(enable = "neon")]
25503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25505#[cfg_attr(
25506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25507 assert_instr(ld4r)
25508)]
25509#[cfg_attr(
25510 not(target_arch = "arm"),
25511 stable(feature = "neon_intrinsics", since = "1.59.0")
25512)]
25513#[cfg_attr(
25514 target_arch = "arm",
25515 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25516)]
25517pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25518 transmute(vld4q_dup_s32(transmute(a)))
25519}
25520#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
25522#[doc = "## Safety"]
25523#[doc = " * Neon instrinsic unsafe"]
25524#[inline]
25525#[cfg(target_endian = "big")]
25526#[target_feature(enable = "neon")]
25527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25529#[cfg_attr(
25530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25531 assert_instr(ld4r)
25532)]
25533#[cfg_attr(
25534 not(target_arch = "arm"),
25535 stable(feature = "neon_intrinsics", since = "1.59.0")
25536)]
25537#[cfg_attr(
25538 target_arch = "arm",
25539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25540)]
25541pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
25542 let mut ret_val: uint32x4x4_t = transmute(vld4q_dup_s32(transmute(a)));
25543 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25544 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25545 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25546 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25547 ret_val
25548}
25549#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25551#[doc = "## Safety"]
25552#[doc = " * Neon instrinsic unsafe"]
25553#[inline]
25554#[cfg(target_endian = "little")]
25555#[target_feature(enable = "neon")]
25556#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25557#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25558#[cfg_attr(
25559 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25560 assert_instr(ld4r)
25561)]
25562#[cfg_attr(
25563 not(target_arch = "arm"),
25564 stable(feature = "neon_intrinsics", since = "1.59.0")
25565)]
25566#[cfg_attr(
25567 target_arch = "arm",
25568 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25569)]
25570pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25571 transmute(vld4_dup_s8(transmute(a)))
25572}
25573#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25574#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
25575#[doc = "## Safety"]
25576#[doc = " * Neon instrinsic unsafe"]
25577#[inline]
25578#[cfg(target_endian = "big")]
25579#[target_feature(enable = "neon")]
25580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25582#[cfg_attr(
25583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25584 assert_instr(ld4r)
25585)]
25586#[cfg_attr(
25587 not(target_arch = "arm"),
25588 stable(feature = "neon_intrinsics", since = "1.59.0")
25589)]
25590#[cfg_attr(
25591 target_arch = "arm",
25592 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25593)]
25594pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
25595 let mut ret_val: poly8x8x4_t = transmute(vld4_dup_s8(transmute(a)));
25596 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25597 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25598 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25599 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25600 ret_val
25601}
25602#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25603#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25604#[doc = "## Safety"]
25605#[doc = " * Neon instrinsic unsafe"]
25606#[inline]
25607#[cfg(target_endian = "little")]
25608#[target_feature(enable = "neon")]
25609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25611#[cfg_attr(
25612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25613 assert_instr(ld4r)
25614)]
25615#[cfg_attr(
25616 not(target_arch = "arm"),
25617 stable(feature = "neon_intrinsics", since = "1.59.0")
25618)]
25619#[cfg_attr(
25620 target_arch = "arm",
25621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25622)]
25623pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25624 transmute(vld4q_dup_s8(transmute(a)))
25625}
25626#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
25628#[doc = "## Safety"]
25629#[doc = " * Neon instrinsic unsafe"]
25630#[inline]
25631#[cfg(target_endian = "big")]
25632#[target_feature(enable = "neon")]
25633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25635#[cfg_attr(
25636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25637 assert_instr(ld4r)
25638)]
25639#[cfg_attr(
25640 not(target_arch = "arm"),
25641 stable(feature = "neon_intrinsics", since = "1.59.0")
25642)]
25643#[cfg_attr(
25644 target_arch = "arm",
25645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25646)]
25647pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
25648 let mut ret_val: poly8x16x4_t = transmute(vld4q_dup_s8(transmute(a)));
25649 ret_val.0 = unsafe {
25650 simd_shuffle!(
25651 ret_val.0,
25652 ret_val.0,
25653 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25654 )
25655 };
25656 ret_val.1 = unsafe {
25657 simd_shuffle!(
25658 ret_val.1,
25659 ret_val.1,
25660 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25661 )
25662 };
25663 ret_val.2 = unsafe {
25664 simd_shuffle!(
25665 ret_val.2,
25666 ret_val.2,
25667 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25668 )
25669 };
25670 ret_val.3 = unsafe {
25671 simd_shuffle!(
25672 ret_val.3,
25673 ret_val.3,
25674 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
25675 )
25676 };
25677 ret_val
25678}
25679#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25681#[doc = "## Safety"]
25682#[doc = " * Neon instrinsic unsafe"]
25683#[inline]
25684#[cfg(target_endian = "little")]
25685#[target_feature(enable = "neon")]
25686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25688#[cfg_attr(
25689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25690 assert_instr(ld4r)
25691)]
25692#[cfg_attr(
25693 not(target_arch = "arm"),
25694 stable(feature = "neon_intrinsics", since = "1.59.0")
25695)]
25696#[cfg_attr(
25697 target_arch = "arm",
25698 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25699)]
25700pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25701 transmute(vld4_dup_s16(transmute(a)))
25702}
25703#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
25705#[doc = "## Safety"]
25706#[doc = " * Neon instrinsic unsafe"]
25707#[inline]
25708#[cfg(target_endian = "big")]
25709#[target_feature(enable = "neon")]
25710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25711#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25712#[cfg_attr(
25713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25714 assert_instr(ld4r)
25715)]
25716#[cfg_attr(
25717 not(target_arch = "arm"),
25718 stable(feature = "neon_intrinsics", since = "1.59.0")
25719)]
25720#[cfg_attr(
25721 target_arch = "arm",
25722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25723)]
25724pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
25725 let mut ret_val: poly16x4x4_t = transmute(vld4_dup_s16(transmute(a)));
25726 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
25727 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
25728 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
25729 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
25730 ret_val
25731}
25732#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25734#[doc = "## Safety"]
25735#[doc = " * Neon instrinsic unsafe"]
25736#[inline]
25737#[cfg(target_endian = "little")]
25738#[target_feature(enable = "neon")]
25739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25741#[cfg_attr(
25742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25743 assert_instr(ld4r)
25744)]
25745#[cfg_attr(
25746 not(target_arch = "arm"),
25747 stable(feature = "neon_intrinsics", since = "1.59.0")
25748)]
25749#[cfg_attr(
25750 target_arch = "arm",
25751 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25752)]
25753pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25754 transmute(vld4q_dup_s16(transmute(a)))
25755}
25756#[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
25757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
25758#[doc = "## Safety"]
25759#[doc = " * Neon instrinsic unsafe"]
25760#[inline]
25761#[cfg(target_endian = "big")]
25762#[target_feature(enable = "neon")]
25763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25765#[cfg_attr(
25766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25767 assert_instr(ld4r)
25768)]
25769#[cfg_attr(
25770 not(target_arch = "arm"),
25771 stable(feature = "neon_intrinsics", since = "1.59.0")
25772)]
25773#[cfg_attr(
25774 target_arch = "arm",
25775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
25776)]
25777pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
25778 let mut ret_val: poly16x8x4_t = transmute(vld4q_dup_s16(transmute(a)));
25779 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
25780 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
25781 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
25782 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
25783 ret_val
25784}
25785#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25787#[doc = "## Safety"]
25788#[doc = " * Neon instrinsic unsafe"]
25789#[inline]
25790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25791#[cfg(target_arch = "arm")]
25792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25793#[target_feature(enable = "neon,fp16")]
25794#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25795pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25796 unsafe extern "unadjusted" {
25797 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f16.p0")]
25798 fn _vld4_f16(ptr: *const f16, size: i32) -> float16x4x4_t;
25799 }
25800 _vld4_f16(a as _, 2)
25801}
25802#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25804#[doc = "## Safety"]
25805#[doc = " * Neon instrinsic unsafe"]
25806#[inline]
25807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
25808#[cfg(target_arch = "arm")]
25809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
25810#[target_feature(enable = "neon,fp16")]
25811#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25812pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25813 unsafe extern "unadjusted" {
25814 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8f16.p0")]
25815 fn _vld4q_f16(ptr: *const f16, size: i32) -> float16x8x4_t;
25816 }
25817 _vld4q_f16(a as _, 2)
25818}
25819#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25820#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
25821#[doc = "## Safety"]
25822#[doc = " * Neon instrinsic unsafe"]
25823#[inline]
25824#[cfg(not(target_arch = "arm"))]
25825#[cfg_attr(
25826 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25827 assert_instr(ld4)
25828)]
25829#[target_feature(enable = "neon,fp16")]
25830#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25831pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
25832 unsafe extern "unadjusted" {
25833 #[cfg_attr(
25834 any(target_arch = "aarch64", target_arch = "arm64ec"),
25835 link_name = "llvm.aarch64.neon.ld4.v4f16.p0"
25836 )]
25837 fn _vld4_f16(ptr: *const f16) -> float16x4x4_t;
25838 }
25839 _vld4_f16(a as _)
25840}
25841#[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
25842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
25843#[doc = "## Safety"]
25844#[doc = " * Neon instrinsic unsafe"]
25845#[inline]
25846#[cfg(not(target_arch = "arm"))]
25847#[cfg_attr(
25848 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
25849 assert_instr(ld4)
25850)]
25851#[target_feature(enable = "neon,fp16")]
25852#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
25853pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
25854 unsafe extern "unadjusted" {
25855 #[cfg_attr(
25856 any(target_arch = "aarch64", target_arch = "arm64ec"),
25857 link_name = "llvm.aarch64.neon.ld4.v8f16.p0"
25858 )]
25859 fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t;
25860 }
25861 _vld4q_f16(a as _)
25862}
25863#[doc = "Load multiple 4-element structures to four registers"]
25864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
25865#[doc = "## Safety"]
25866#[doc = " * Neon instrinsic unsafe"]
25867#[inline]
25868#[target_feature(enable = "neon")]
25869#[cfg(not(target_arch = "arm"))]
25870#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25871#[cfg_attr(test, assert_instr(ld4))]
25872pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
25873 unsafe extern "unadjusted" {
25874 #[cfg_attr(
25875 any(target_arch = "aarch64", target_arch = "arm64ec"),
25876 link_name = "llvm.aarch64.neon.ld4.v2f32.p0"
25877 )]
25878 fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t;
25879 }
25880 _vld4_f32(a as _)
25881}
25882#[doc = "Load multiple 4-element structures to four registers"]
25883#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
25884#[doc = "## Safety"]
25885#[doc = " * Neon instrinsic unsafe"]
25886#[inline]
25887#[target_feature(enable = "neon")]
25888#[cfg(not(target_arch = "arm"))]
25889#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25890#[cfg_attr(test, assert_instr(ld4))]
25891pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
25892 unsafe extern "unadjusted" {
25893 #[cfg_attr(
25894 any(target_arch = "aarch64", target_arch = "arm64ec"),
25895 link_name = "llvm.aarch64.neon.ld4.v4f32.p0"
25896 )]
25897 fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t;
25898 }
25899 _vld4q_f32(a as _)
25900}
25901#[doc = "Load multiple 4-element structures to four registers"]
25902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
25903#[doc = "## Safety"]
25904#[doc = " * Neon instrinsic unsafe"]
25905#[inline]
25906#[target_feature(enable = "neon")]
25907#[cfg(not(target_arch = "arm"))]
25908#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25909#[cfg_attr(test, assert_instr(ld4))]
25910pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
25911 unsafe extern "unadjusted" {
25912 #[cfg_attr(
25913 any(target_arch = "aarch64", target_arch = "arm64ec"),
25914 link_name = "llvm.aarch64.neon.ld4.v8i8.p0"
25915 )]
25916 fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t;
25917 }
25918 _vld4_s8(a as _)
25919}
25920#[doc = "Load multiple 4-element structures to four registers"]
25921#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
25922#[doc = "## Safety"]
25923#[doc = " * Neon instrinsic unsafe"]
25924#[inline]
25925#[target_feature(enable = "neon")]
25926#[cfg(not(target_arch = "arm"))]
25927#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25928#[cfg_attr(test, assert_instr(ld4))]
25929pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
25930 unsafe extern "unadjusted" {
25931 #[cfg_attr(
25932 any(target_arch = "aarch64", target_arch = "arm64ec"),
25933 link_name = "llvm.aarch64.neon.ld4.v16i8.p0"
25934 )]
25935 fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t;
25936 }
25937 _vld4q_s8(a as _)
25938}
25939#[doc = "Load multiple 4-element structures to four registers"]
25940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
25941#[doc = "## Safety"]
25942#[doc = " * Neon instrinsic unsafe"]
25943#[inline]
25944#[target_feature(enable = "neon")]
25945#[cfg(not(target_arch = "arm"))]
25946#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25947#[cfg_attr(test, assert_instr(ld4))]
25948pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
25949 unsafe extern "unadjusted" {
25950 #[cfg_attr(
25951 any(target_arch = "aarch64", target_arch = "arm64ec"),
25952 link_name = "llvm.aarch64.neon.ld4.v4i16.p0"
25953 )]
25954 fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t;
25955 }
25956 _vld4_s16(a as _)
25957}
25958#[doc = "Load multiple 4-element structures to four registers"]
25959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
25960#[doc = "## Safety"]
25961#[doc = " * Neon instrinsic unsafe"]
25962#[inline]
25963#[target_feature(enable = "neon")]
25964#[cfg(not(target_arch = "arm"))]
25965#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25966#[cfg_attr(test, assert_instr(ld4))]
25967pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
25968 unsafe extern "unadjusted" {
25969 #[cfg_attr(
25970 any(target_arch = "aarch64", target_arch = "arm64ec"),
25971 link_name = "llvm.aarch64.neon.ld4.v8i16.p0"
25972 )]
25973 fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t;
25974 }
25975 _vld4q_s16(a as _)
25976}
25977#[doc = "Load multiple 4-element structures to four registers"]
25978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
25979#[doc = "## Safety"]
25980#[doc = " * Neon instrinsic unsafe"]
25981#[inline]
25982#[target_feature(enable = "neon")]
25983#[cfg(not(target_arch = "arm"))]
25984#[stable(feature = "neon_intrinsics", since = "1.59.0")]
25985#[cfg_attr(test, assert_instr(ld4))]
25986pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
25987 unsafe extern "unadjusted" {
25988 #[cfg_attr(
25989 any(target_arch = "aarch64", target_arch = "arm64ec"),
25990 link_name = "llvm.aarch64.neon.ld4.v2i32.p0"
25991 )]
25992 fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t;
25993 }
25994 _vld4_s32(a as _)
25995}
25996#[doc = "Load multiple 4-element structures to four registers"]
25997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
25998#[doc = "## Safety"]
25999#[doc = " * Neon instrinsic unsafe"]
26000#[inline]
26001#[target_feature(enable = "neon")]
26002#[cfg(not(target_arch = "arm"))]
26003#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26004#[cfg_attr(test, assert_instr(ld4))]
26005pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26006 unsafe extern "unadjusted" {
26007 #[cfg_attr(
26008 any(target_arch = "aarch64", target_arch = "arm64ec"),
26009 link_name = "llvm.aarch64.neon.ld4.v4i32.p0"
26010 )]
26011 fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t;
26012 }
26013 _vld4q_s32(a as _)
26014}
26015#[doc = "Load multiple 4-element structures to four registers"]
26016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
26017#[doc = "## Safety"]
26018#[doc = " * Neon instrinsic unsafe"]
26019#[inline]
26020#[target_feature(enable = "neon,v7")]
26021#[cfg(target_arch = "arm")]
26022#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26023#[cfg_attr(test, assert_instr(vld4))]
26024pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
26025 unsafe extern "unadjusted" {
26026 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0")]
26027 fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t;
26028 }
26029 _vld4_f32(a as *const i8, 4)
26030}
26031#[doc = "Load multiple 4-element structures to four registers"]
26032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
26033#[doc = "## Safety"]
26034#[doc = " * Neon instrinsic unsafe"]
26035#[inline]
26036#[target_feature(enable = "neon,v7")]
26037#[cfg(target_arch = "arm")]
26038#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26039#[cfg_attr(test, assert_instr(vld4))]
26040pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
26041 unsafe extern "unadjusted" {
26042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0")]
26043 fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t;
26044 }
26045 _vld4q_f32(a as *const i8, 4)
26046}
26047#[doc = "Load multiple 4-element structures to four registers"]
26048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
26049#[doc = "## Safety"]
26050#[doc = " * Neon instrinsic unsafe"]
26051#[inline]
26052#[target_feature(enable = "neon,v7")]
26053#[cfg(target_arch = "arm")]
26054#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26055#[cfg_attr(test, assert_instr(vld4))]
26056pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
26057 unsafe extern "unadjusted" {
26058 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0")]
26059 fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t;
26060 }
26061 _vld4_s8(a as *const i8, 1)
26062}
26063#[doc = "Load multiple 4-element structures to four registers"]
26064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
26065#[doc = "## Safety"]
26066#[doc = " * Neon instrinsic unsafe"]
26067#[inline]
26068#[target_feature(enable = "neon,v7")]
26069#[cfg(target_arch = "arm")]
26070#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26071#[cfg_attr(test, assert_instr(vld4))]
26072pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
26073 unsafe extern "unadjusted" {
26074 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0")]
26075 fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t;
26076 }
26077 _vld4q_s8(a as *const i8, 1)
26078}
26079#[doc = "Load multiple 4-element structures to four registers"]
26080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
26081#[doc = "## Safety"]
26082#[doc = " * Neon instrinsic unsafe"]
26083#[inline]
26084#[target_feature(enable = "neon,v7")]
26085#[cfg(target_arch = "arm")]
26086#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26087#[cfg_attr(test, assert_instr(vld4))]
26088pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
26089 unsafe extern "unadjusted" {
26090 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0")]
26091 fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t;
26092 }
26093 _vld4_s16(a as *const i8, 2)
26094}
26095#[doc = "Load multiple 4-element structures to four registers"]
26096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
26097#[doc = "## Safety"]
26098#[doc = " * Neon instrinsic unsafe"]
26099#[inline]
26100#[target_feature(enable = "neon,v7")]
26101#[cfg(target_arch = "arm")]
26102#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26103#[cfg_attr(test, assert_instr(vld4))]
26104pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
26105 unsafe extern "unadjusted" {
26106 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0")]
26107 fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t;
26108 }
26109 _vld4q_s16(a as *const i8, 2)
26110}
26111#[doc = "Load multiple 4-element structures to four registers"]
26112#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
26113#[doc = "## Safety"]
26114#[doc = " * Neon instrinsic unsafe"]
26115#[inline]
26116#[target_feature(enable = "neon,v7")]
26117#[cfg(target_arch = "arm")]
26118#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26119#[cfg_attr(test, assert_instr(vld4))]
26120pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
26121 unsafe extern "unadjusted" {
26122 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0")]
26123 fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t;
26124 }
26125 _vld4_s32(a as *const i8, 4)
26126}
26127#[doc = "Load multiple 4-element structures to four registers"]
26128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
26129#[doc = "## Safety"]
26130#[doc = " * Neon instrinsic unsafe"]
26131#[inline]
26132#[target_feature(enable = "neon,v7")]
26133#[cfg(target_arch = "arm")]
26134#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26135#[cfg_attr(test, assert_instr(vld4))]
26136pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
26137 unsafe extern "unadjusted" {
26138 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0")]
26139 fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t;
26140 }
26141 _vld4q_s32(a as *const i8, 4)
26142}
26143#[doc = "Load multiple 4-element structures to two registers"]
26144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26145#[doc = "## Safety"]
26146#[doc = " * Neon instrinsic unsafe"]
26147#[inline]
26148#[target_feature(enable = "neon,v7")]
26149#[cfg(target_arch = "arm")]
26150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26151#[rustc_legacy_const_generics(2)]
26152#[target_feature(enable = "neon,fp16")]
26153#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26154pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26155 static_assert_uimm_bits!(LANE, 2);
26156 unsafe extern "unadjusted" {
26157 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f16.p0")]
26158 fn _vld4_lane_f16(
26159 ptr: *const f16,
26160 a: float16x4_t,
26161 b: float16x4_t,
26162 c: float16x4_t,
26163 d: float16x4_t,
26164 n: i32,
26165 size: i32,
26166 ) -> float16x4x4_t;
26167 }
26168 _vld4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26169}
26170#[doc = "Load multiple 4-element structures to two registers"]
26171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26172#[doc = "## Safety"]
26173#[doc = " * Neon instrinsic unsafe"]
26174#[inline]
26175#[target_feature(enable = "neon,v7")]
26176#[cfg(target_arch = "arm")]
26177#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26178#[rustc_legacy_const_generics(2)]
26179#[target_feature(enable = "neon,fp16")]
26180#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26181pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26182 static_assert_uimm_bits!(LANE, 3);
26183 unsafe extern "unadjusted" {
26184 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8f16.p0")]
26185 fn _vld4q_lane_f16(
26186 ptr: *const f16,
26187 a: float16x8_t,
26188 b: float16x8_t,
26189 c: float16x8_t,
26190 d: float16x8_t,
26191 n: i32,
26192 size: i32,
26193 ) -> float16x8x4_t;
26194 }
26195 _vld4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26196}
26197#[doc = "Load multiple 4-element structures to two registers"]
26198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
26199#[doc = "## Safety"]
26200#[doc = " * Neon instrinsic unsafe"]
26201#[inline]
26202#[cfg(not(target_arch = "arm"))]
26203#[cfg_attr(
26204 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26205 assert_instr(ld4, LANE = 0)
26206)]
26207#[rustc_legacy_const_generics(2)]
26208#[target_feature(enable = "neon,fp16")]
26209#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26210pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) -> float16x4x4_t {
26211 static_assert_uimm_bits!(LANE, 2);
26212 unsafe extern "unadjusted" {
26213 #[cfg_attr(
26214 any(target_arch = "aarch64", target_arch = "arm64ec"),
26215 link_name = "llvm.aarch64.neon.ld4lane.v4f16.p0"
26216 )]
26217 fn _vld4_lane_f16(
26218 a: float16x4_t,
26219 b: float16x4_t,
26220 c: float16x4_t,
26221 d: float16x4_t,
26222 n: i64,
26223 ptr: *const f16,
26224 ) -> float16x4x4_t;
26225 }
26226 _vld4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26227}
26228#[doc = "Load multiple 4-element structures to two registers"]
26229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
26230#[doc = "## Safety"]
26231#[doc = " * Neon instrinsic unsafe"]
26232#[inline]
26233#[cfg(not(target_arch = "arm"))]
26234#[cfg_attr(
26235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26236 assert_instr(ld4, LANE = 0)
26237)]
26238#[rustc_legacy_const_generics(2)]
26239#[target_feature(enable = "neon,fp16")]
26240#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
26241pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -> float16x8x4_t {
26242 static_assert_uimm_bits!(LANE, 3);
26243 unsafe extern "unadjusted" {
26244 #[cfg_attr(
26245 any(target_arch = "aarch64", target_arch = "arm64ec"),
26246 link_name = "llvm.aarch64.neon.ld4lane.v8f16.p0"
26247 )]
26248 fn _vld4q_lane_f16(
26249 a: float16x8_t,
26250 b: float16x8_t,
26251 c: float16x8_t,
26252 d: float16x8_t,
26253 n: i64,
26254 ptr: *const f16,
26255 ) -> float16x8x4_t;
26256 }
26257 _vld4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26258}
26259#[doc = "Load multiple 4-element structures to four registers"]
26260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26261#[doc = "## Safety"]
26262#[doc = " * Neon instrinsic unsafe"]
26263#[inline]
26264#[target_feature(enable = "neon")]
26265#[cfg(not(target_arch = "arm"))]
26266#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26267#[rustc_legacy_const_generics(2)]
26268#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26269pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26270 static_assert_uimm_bits!(LANE, 1);
26271 unsafe extern "unadjusted" {
26272 #[cfg_attr(
26273 any(target_arch = "aarch64", target_arch = "arm64ec"),
26274 link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0"
26275 )]
26276 fn _vld4_lane_f32(
26277 a: float32x2_t,
26278 b: float32x2_t,
26279 c: float32x2_t,
26280 d: float32x2_t,
26281 n: i64,
26282 ptr: *const i8,
26283 ) -> float32x2x4_t;
26284 }
26285 _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26286}
26287#[doc = "Load multiple 4-element structures to four registers"]
26288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26289#[doc = "## Safety"]
26290#[doc = " * Neon instrinsic unsafe"]
26291#[inline]
26292#[target_feature(enable = "neon")]
26293#[cfg(not(target_arch = "arm"))]
26294#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26295#[rustc_legacy_const_generics(2)]
26296#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26297pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26298 static_assert_uimm_bits!(LANE, 2);
26299 unsafe extern "unadjusted" {
26300 #[cfg_attr(
26301 any(target_arch = "aarch64", target_arch = "arm64ec"),
26302 link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0"
26303 )]
26304 fn _vld4q_lane_f32(
26305 a: float32x4_t,
26306 b: float32x4_t,
26307 c: float32x4_t,
26308 d: float32x4_t,
26309 n: i64,
26310 ptr: *const i8,
26311 ) -> float32x4x4_t;
26312 }
26313 _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26314}
26315#[doc = "Load multiple 4-element structures to four registers"]
26316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26317#[doc = "## Safety"]
26318#[doc = " * Neon instrinsic unsafe"]
26319#[inline]
26320#[target_feature(enable = "neon")]
26321#[cfg(not(target_arch = "arm"))]
26322#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26323#[rustc_legacy_const_generics(2)]
26324#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26325pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26326 static_assert_uimm_bits!(LANE, 3);
26327 unsafe extern "unadjusted" {
26328 #[cfg_attr(
26329 any(target_arch = "aarch64", target_arch = "arm64ec"),
26330 link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0"
26331 )]
26332 fn _vld4_lane_s8(
26333 a: int8x8_t,
26334 b: int8x8_t,
26335 c: int8x8_t,
26336 d: int8x8_t,
26337 n: i64,
26338 ptr: *const i8,
26339 ) -> int8x8x4_t;
26340 }
26341 _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26342}
26343#[doc = "Load multiple 4-element structures to four registers"]
26344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26345#[doc = "## Safety"]
26346#[doc = " * Neon instrinsic unsafe"]
26347#[inline]
26348#[target_feature(enable = "neon")]
26349#[cfg(not(target_arch = "arm"))]
26350#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26351#[rustc_legacy_const_generics(2)]
26352#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26353pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26354 static_assert_uimm_bits!(LANE, 2);
26355 unsafe extern "unadjusted" {
26356 #[cfg_attr(
26357 any(target_arch = "aarch64", target_arch = "arm64ec"),
26358 link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0"
26359 )]
26360 fn _vld4_lane_s16(
26361 a: int16x4_t,
26362 b: int16x4_t,
26363 c: int16x4_t,
26364 d: int16x4_t,
26365 n: i64,
26366 ptr: *const i8,
26367 ) -> int16x4x4_t;
26368 }
26369 _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26370}
26371#[doc = "Load multiple 4-element structures to four registers"]
26372#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26373#[doc = "## Safety"]
26374#[doc = " * Neon instrinsic unsafe"]
26375#[inline]
26376#[target_feature(enable = "neon")]
26377#[cfg(not(target_arch = "arm"))]
26378#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26379#[rustc_legacy_const_generics(2)]
26380#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26381pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26382 static_assert_uimm_bits!(LANE, 3);
26383 unsafe extern "unadjusted" {
26384 #[cfg_attr(
26385 any(target_arch = "aarch64", target_arch = "arm64ec"),
26386 link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0"
26387 )]
26388 fn _vld4q_lane_s16(
26389 a: int16x8_t,
26390 b: int16x8_t,
26391 c: int16x8_t,
26392 d: int16x8_t,
26393 n: i64,
26394 ptr: *const i8,
26395 ) -> int16x8x4_t;
26396 }
26397 _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26398}
26399#[doc = "Load multiple 4-element structures to four registers"]
26400#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26401#[doc = "## Safety"]
26402#[doc = " * Neon instrinsic unsafe"]
26403#[inline]
26404#[target_feature(enable = "neon")]
26405#[cfg(not(target_arch = "arm"))]
26406#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26407#[rustc_legacy_const_generics(2)]
26408#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26409pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26410 static_assert_uimm_bits!(LANE, 1);
26411 unsafe extern "unadjusted" {
26412 #[cfg_attr(
26413 any(target_arch = "aarch64", target_arch = "arm64ec"),
26414 link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0"
26415 )]
26416 fn _vld4_lane_s32(
26417 a: int32x2_t,
26418 b: int32x2_t,
26419 c: int32x2_t,
26420 d: int32x2_t,
26421 n: i64,
26422 ptr: *const i8,
26423 ) -> int32x2x4_t;
26424 }
26425 _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26426}
26427#[doc = "Load multiple 4-element structures to four registers"]
26428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26429#[doc = "## Safety"]
26430#[doc = " * Neon instrinsic unsafe"]
26431#[inline]
26432#[target_feature(enable = "neon")]
26433#[cfg(not(target_arch = "arm"))]
26434#[cfg_attr(test, assert_instr(ld4, LANE = 0))]
26435#[rustc_legacy_const_generics(2)]
26436#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26437pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26438 static_assert_uimm_bits!(LANE, 2);
26439 unsafe extern "unadjusted" {
26440 #[cfg_attr(
26441 any(target_arch = "aarch64", target_arch = "arm64ec"),
26442 link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0"
26443 )]
26444 fn _vld4q_lane_s32(
26445 a: int32x4_t,
26446 b: int32x4_t,
26447 c: int32x4_t,
26448 d: int32x4_t,
26449 n: i64,
26450 ptr: *const i8,
26451 ) -> int32x4x4_t;
26452 }
26453 _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
26454}
26455#[doc = "Load multiple 4-element structures to four registers"]
26456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
26457#[doc = "## Safety"]
26458#[doc = " * Neon instrinsic unsafe"]
26459#[inline]
26460#[target_feature(enable = "neon,v7")]
26461#[cfg(target_arch = "arm")]
26462#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26463#[rustc_legacy_const_generics(2)]
26464#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26465pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) -> float32x2x4_t {
26466 static_assert_uimm_bits!(LANE, 1);
26467 unsafe extern "unadjusted" {
26468 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0")]
26469 fn _vld4_lane_f32(
26470 ptr: *const i8,
26471 a: float32x2_t,
26472 b: float32x2_t,
26473 c: float32x2_t,
26474 d: float32x2_t,
26475 n: i32,
26476 size: i32,
26477 ) -> float32x2x4_t;
26478 }
26479 _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26480}
26481#[doc = "Load multiple 4-element structures to four registers"]
26482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
26483#[doc = "## Safety"]
26484#[doc = " * Neon instrinsic unsafe"]
26485#[inline]
26486#[target_feature(enable = "neon,v7")]
26487#[cfg(target_arch = "arm")]
26488#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26489#[rustc_legacy_const_generics(2)]
26490#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26491pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -> float32x4x4_t {
26492 static_assert_uimm_bits!(LANE, 2);
26493 unsafe extern "unadjusted" {
26494 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0")]
26495 fn _vld4q_lane_f32(
26496 ptr: *const i8,
26497 a: float32x4_t,
26498 b: float32x4_t,
26499 c: float32x4_t,
26500 d: float32x4_t,
26501 n: i32,
26502 size: i32,
26503 ) -> float32x4x4_t;
26504 }
26505 _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26506}
26507#[doc = "Load multiple 4-element structures to four registers"]
26508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
26509#[doc = "## Safety"]
26510#[doc = " * Neon instrinsic unsafe"]
26511#[inline]
26512#[target_feature(enable = "neon,v7")]
26513#[cfg(target_arch = "arm")]
26514#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26515#[rustc_legacy_const_generics(2)]
26516#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26517pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8x8x4_t {
26518 static_assert_uimm_bits!(LANE, 3);
26519 unsafe extern "unadjusted" {
26520 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0")]
26521 fn _vld4_lane_s8(
26522 ptr: *const i8,
26523 a: int8x8_t,
26524 b: int8x8_t,
26525 c: int8x8_t,
26526 d: int8x8_t,
26527 n: i32,
26528 size: i32,
26529 ) -> int8x8x4_t;
26530 }
26531 _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
26532}
26533#[doc = "Load multiple 4-element structures to four registers"]
26534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
26535#[doc = "## Safety"]
26536#[doc = " * Neon instrinsic unsafe"]
26537#[inline]
26538#[target_feature(enable = "neon,v7")]
26539#[cfg(target_arch = "arm")]
26540#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26541#[rustc_legacy_const_generics(2)]
26542#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26543pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> int16x4x4_t {
26544 static_assert_uimm_bits!(LANE, 2);
26545 unsafe extern "unadjusted" {
26546 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0")]
26547 fn _vld4_lane_s16(
26548 ptr: *const i8,
26549 a: int16x4_t,
26550 b: int16x4_t,
26551 c: int16x4_t,
26552 d: int16x4_t,
26553 n: i32,
26554 size: i32,
26555 ) -> int16x4x4_t;
26556 }
26557 _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26558}
26559#[doc = "Load multiple 4-element structures to four registers"]
26560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
26561#[doc = "## Safety"]
26562#[doc = " * Neon instrinsic unsafe"]
26563#[inline]
26564#[target_feature(enable = "neon,v7")]
26565#[cfg(target_arch = "arm")]
26566#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26567#[rustc_legacy_const_generics(2)]
26568#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26569pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) -> int16x8x4_t {
26570 static_assert_uimm_bits!(LANE, 3);
26571 unsafe extern "unadjusted" {
26572 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0")]
26573 fn _vld4q_lane_s16(
26574 ptr: *const i8,
26575 a: int16x8_t,
26576 b: int16x8_t,
26577 c: int16x8_t,
26578 d: int16x8_t,
26579 n: i32,
26580 size: i32,
26581 ) -> int16x8x4_t;
26582 }
26583 _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
26584}
26585#[doc = "Load multiple 4-element structures to four registers"]
26586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
26587#[doc = "## Safety"]
26588#[doc = " * Neon instrinsic unsafe"]
26589#[inline]
26590#[target_feature(enable = "neon,v7")]
26591#[cfg(target_arch = "arm")]
26592#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26593#[rustc_legacy_const_generics(2)]
26594#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26595pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> int32x2x4_t {
26596 static_assert_uimm_bits!(LANE, 1);
26597 unsafe extern "unadjusted" {
26598 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0")]
26599 fn _vld4_lane_s32(
26600 ptr: *const i8,
26601 a: int32x2_t,
26602 b: int32x2_t,
26603 c: int32x2_t,
26604 d: int32x2_t,
26605 n: i32,
26606 size: i32,
26607 ) -> int32x2x4_t;
26608 }
26609 _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26610}
26611#[doc = "Load multiple 4-element structures to four registers"]
26612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
26613#[doc = "## Safety"]
26614#[doc = " * Neon instrinsic unsafe"]
26615#[inline]
26616#[target_feature(enable = "neon,v7")]
26617#[cfg(target_arch = "arm")]
26618#[cfg_attr(test, assert_instr(vld4, LANE = 0))]
26619#[rustc_legacy_const_generics(2)]
26620#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26621pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) -> int32x4x4_t {
26622 static_assert_uimm_bits!(LANE, 2);
26623 unsafe extern "unadjusted" {
26624 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0")]
26625 fn _vld4q_lane_s32(
26626 ptr: *const i8,
26627 a: int32x4_t,
26628 b: int32x4_t,
26629 c: int32x4_t,
26630 d: int32x4_t,
26631 n: i32,
26632 size: i32,
26633 ) -> int32x4x4_t;
26634 }
26635 _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
26636}
26637#[doc = "Load multiple 4-element structures to four registers"]
26638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
26639#[doc = "## Safety"]
26640#[doc = " * Neon instrinsic unsafe"]
26641#[inline]
26642#[target_feature(enable = "neon")]
26643#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26644#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26645#[cfg_attr(
26646 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26647 assert_instr(ld4, LANE = 0)
26648)]
26649#[rustc_legacy_const_generics(2)]
26650#[cfg_attr(
26651 not(target_arch = "arm"),
26652 stable(feature = "neon_intrinsics", since = "1.59.0")
26653)]
26654#[cfg_attr(
26655 target_arch = "arm",
26656 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26657)]
26658pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t {
26659 static_assert_uimm_bits!(LANE, 3);
26660 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26661}
26662#[doc = "Load multiple 4-element structures to four registers"]
26663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
26664#[doc = "## Safety"]
26665#[doc = " * Neon instrinsic unsafe"]
26666#[inline]
26667#[target_feature(enable = "neon")]
26668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26670#[cfg_attr(
26671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26672 assert_instr(ld4, LANE = 0)
26673)]
26674#[rustc_legacy_const_generics(2)]
26675#[cfg_attr(
26676 not(target_arch = "arm"),
26677 stable(feature = "neon_intrinsics", since = "1.59.0")
26678)]
26679#[cfg_attr(
26680 target_arch = "arm",
26681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26682)]
26683pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t {
26684 static_assert_uimm_bits!(LANE, 2);
26685 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26686}
26687#[doc = "Load multiple 4-element structures to four registers"]
26688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
26689#[doc = "## Safety"]
26690#[doc = " * Neon instrinsic unsafe"]
26691#[inline]
26692#[target_feature(enable = "neon")]
26693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26695#[cfg_attr(
26696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26697 assert_instr(ld4, LANE = 0)
26698)]
26699#[rustc_legacy_const_generics(2)]
26700#[cfg_attr(
26701 not(target_arch = "arm"),
26702 stable(feature = "neon_intrinsics", since = "1.59.0")
26703)]
26704#[cfg_attr(
26705 target_arch = "arm",
26706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26707)]
26708pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t {
26709 static_assert_uimm_bits!(LANE, 3);
26710 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26711}
26712#[doc = "Load multiple 4-element structures to four registers"]
26713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
26714#[doc = "## Safety"]
26715#[doc = " * Neon instrinsic unsafe"]
26716#[inline]
26717#[target_feature(enable = "neon")]
26718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26720#[cfg_attr(
26721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26722 assert_instr(ld4, LANE = 0)
26723)]
26724#[rustc_legacy_const_generics(2)]
26725#[cfg_attr(
26726 not(target_arch = "arm"),
26727 stable(feature = "neon_intrinsics", since = "1.59.0")
26728)]
26729#[cfg_attr(
26730 target_arch = "arm",
26731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26732)]
26733pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t {
26734 static_assert_uimm_bits!(LANE, 1);
26735 transmute(vld4_lane_s32::<LANE>(transmute(a), transmute(b)))
26736}
26737#[doc = "Load multiple 4-element structures to four registers"]
26738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
26739#[doc = "## Safety"]
26740#[doc = " * Neon instrinsic unsafe"]
26741#[inline]
26742#[target_feature(enable = "neon")]
26743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26745#[cfg_attr(
26746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26747 assert_instr(ld4, LANE = 0)
26748)]
26749#[rustc_legacy_const_generics(2)]
26750#[cfg_attr(
26751 not(target_arch = "arm"),
26752 stable(feature = "neon_intrinsics", since = "1.59.0")
26753)]
26754#[cfg_attr(
26755 target_arch = "arm",
26756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26757)]
26758pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t {
26759 static_assert_uimm_bits!(LANE, 2);
26760 transmute(vld4q_lane_s32::<LANE>(transmute(a), transmute(b)))
26761}
26762#[doc = "Load multiple 4-element structures to four registers"]
26763#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
26764#[doc = "## Safety"]
26765#[doc = " * Neon instrinsic unsafe"]
26766#[inline]
26767#[target_feature(enable = "neon")]
26768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26770#[cfg_attr(
26771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26772 assert_instr(ld4, LANE = 0)
26773)]
26774#[rustc_legacy_const_generics(2)]
26775#[cfg_attr(
26776 not(target_arch = "arm"),
26777 stable(feature = "neon_intrinsics", since = "1.59.0")
26778)]
26779#[cfg_attr(
26780 target_arch = "arm",
26781 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26782)]
26783pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t {
26784 static_assert_uimm_bits!(LANE, 3);
26785 transmute(vld4_lane_s8::<LANE>(transmute(a), transmute(b)))
26786}
26787#[doc = "Load multiple 4-element structures to four registers"]
26788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
26789#[doc = "## Safety"]
26790#[doc = " * Neon instrinsic unsafe"]
26791#[inline]
26792#[target_feature(enable = "neon")]
26793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26795#[cfg_attr(
26796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26797 assert_instr(ld4, LANE = 0)
26798)]
26799#[rustc_legacy_const_generics(2)]
26800#[cfg_attr(
26801 not(target_arch = "arm"),
26802 stable(feature = "neon_intrinsics", since = "1.59.0")
26803)]
26804#[cfg_attr(
26805 target_arch = "arm",
26806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26807)]
26808pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t {
26809 static_assert_uimm_bits!(LANE, 2);
26810 transmute(vld4_lane_s16::<LANE>(transmute(a), transmute(b)))
26811}
26812#[doc = "Load multiple 4-element structures to four registers"]
26813#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
26814#[doc = "## Safety"]
26815#[doc = " * Neon instrinsic unsafe"]
26816#[inline]
26817#[target_feature(enable = "neon")]
26818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
26820#[cfg_attr(
26821 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26822 assert_instr(ld4, LANE = 0)
26823)]
26824#[rustc_legacy_const_generics(2)]
26825#[cfg_attr(
26826 not(target_arch = "arm"),
26827 stable(feature = "neon_intrinsics", since = "1.59.0")
26828)]
26829#[cfg_attr(
26830 target_arch = "arm",
26831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26832)]
26833pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t {
26834 static_assert_uimm_bits!(LANE, 3);
26835 transmute(vld4q_lane_s16::<LANE>(transmute(a), transmute(b)))
26836}
26837#[doc = "Load multiple 4-element structures to four registers"]
26838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
26839#[doc = "## Safety"]
26840#[doc = " * Neon instrinsic unsafe"]
26841#[inline]
26842#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
26843#[target_feature(enable = "neon,aes")]
26844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26845#[cfg_attr(
26846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26847 assert_instr(nop)
26848)]
26849#[cfg_attr(
26850 not(target_arch = "arm"),
26851 stable(feature = "neon_intrinsics", since = "1.59.0")
26852)]
26853#[cfg_attr(
26854 target_arch = "arm",
26855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26856)]
26857pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
26858 transmute(vld4_s64(transmute(a)))
26859}
26860#[doc = "Load multiple 4-element structures to four registers"]
26861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26862#[doc = "## Safety"]
26863#[doc = " * Neon instrinsic unsafe"]
26864#[inline]
26865#[target_feature(enable = "neon")]
26866#[cfg(not(target_arch = "arm"))]
26867#[stable(feature = "neon_intrinsics", since = "1.59.0")]
26868#[cfg_attr(test, assert_instr(nop))]
26869pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
26870 unsafe extern "unadjusted" {
26871 #[cfg_attr(
26872 any(target_arch = "aarch64", target_arch = "arm64ec"),
26873 link_name = "llvm.aarch64.neon.ld4.v1i64.p0"
26874 )]
26875 fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t;
26876 }
26877 _vld4_s64(a as _)
26878}
26879#[doc = "Load multiple 4-element structures to four registers"]
26880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
26881#[doc = "## Safety"]
26882#[doc = " * Neon instrinsic unsafe"]
26883#[inline]
26884#[target_feature(enable = "neon,v7")]
26885#[cfg(target_arch = "arm")]
26886#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
26887#[cfg_attr(test, assert_instr(nop))]
26888pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
26889 unsafe extern "unadjusted" {
26890 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0")]
26891 fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t;
26892 }
26893 _vld4_s64(a as *const i8, 8)
26894}
26895#[doc = "Load multiple 4-element structures to four registers"]
26896#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
26897#[doc = "## Safety"]
26898#[doc = " * Neon instrinsic unsafe"]
26899#[inline]
26900#[target_feature(enable = "neon")]
26901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
26903#[cfg_attr(
26904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26905 assert_instr(nop)
26906)]
26907#[cfg_attr(
26908 not(target_arch = "arm"),
26909 stable(feature = "neon_intrinsics", since = "1.59.0")
26910)]
26911#[cfg_attr(
26912 target_arch = "arm",
26913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26914)]
26915pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
26916 transmute(vld4_s64(transmute(a)))
26917}
26918#[doc = "Load multiple 4-element structures to four registers"]
26919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
26920#[doc = "## Safety"]
26921#[doc = " * Neon instrinsic unsafe"]
26922#[inline]
26923#[cfg(target_endian = "little")]
26924#[target_feature(enable = "neon")]
26925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
26927#[cfg_attr(
26928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26929 assert_instr(ld4)
26930)]
26931#[cfg_attr(
26932 not(target_arch = "arm"),
26933 stable(feature = "neon_intrinsics", since = "1.59.0")
26934)]
26935#[cfg_attr(
26936 target_arch = "arm",
26937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26938)]
26939pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
26940 transmute(vld4_s8(transmute(a)))
26941}
26942#[doc = "Load multiple 4-element structures to four registers"]
26943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
26944#[doc = "## Safety"]
26945#[doc = " * Neon instrinsic unsafe"]
26946#[inline]
26947#[cfg(target_endian = "big")]
26948#[target_feature(enable = "neon")]
26949#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
26951#[cfg_attr(
26952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26953 assert_instr(ld4)
26954)]
26955#[cfg_attr(
26956 not(target_arch = "arm"),
26957 stable(feature = "neon_intrinsics", since = "1.59.0")
26958)]
26959#[cfg_attr(
26960 target_arch = "arm",
26961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26962)]
26963pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
26964 let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a)));
26965 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
26966 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
26967 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
26968 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
26969 ret_val
26970}
26971#[doc = "Load multiple 4-element structures to four registers"]
26972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
26973#[doc = "## Safety"]
26974#[doc = " * Neon instrinsic unsafe"]
26975#[inline]
26976#[cfg(target_endian = "little")]
26977#[target_feature(enable = "neon")]
26978#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
26979#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
26980#[cfg_attr(
26981 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
26982 assert_instr(ld4)
26983)]
26984#[cfg_attr(
26985 not(target_arch = "arm"),
26986 stable(feature = "neon_intrinsics", since = "1.59.0")
26987)]
26988#[cfg_attr(
26989 target_arch = "arm",
26990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
26991)]
26992pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
26993 transmute(vld4q_s8(transmute(a)))
26994}
26995#[doc = "Load multiple 4-element structures to four registers"]
26996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
26997#[doc = "## Safety"]
26998#[doc = " * Neon instrinsic unsafe"]
26999#[inline]
27000#[cfg(target_endian = "big")]
27001#[target_feature(enable = "neon")]
27002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27004#[cfg_attr(
27005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27006 assert_instr(ld4)
27007)]
27008#[cfg_attr(
27009 not(target_arch = "arm"),
27010 stable(feature = "neon_intrinsics", since = "1.59.0")
27011)]
27012#[cfg_attr(
27013 target_arch = "arm",
27014 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27015)]
27016pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
27017 let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a)));
27018 ret_val.0 = unsafe {
27019 simd_shuffle!(
27020 ret_val.0,
27021 ret_val.0,
27022 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27023 )
27024 };
27025 ret_val.1 = unsafe {
27026 simd_shuffle!(
27027 ret_val.1,
27028 ret_val.1,
27029 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27030 )
27031 };
27032 ret_val.2 = unsafe {
27033 simd_shuffle!(
27034 ret_val.2,
27035 ret_val.2,
27036 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27037 )
27038 };
27039 ret_val.3 = unsafe {
27040 simd_shuffle!(
27041 ret_val.3,
27042 ret_val.3,
27043 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27044 )
27045 };
27046 ret_val
27047}
27048#[doc = "Load multiple 4-element structures to four registers"]
27049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27050#[doc = "## Safety"]
27051#[doc = " * Neon instrinsic unsafe"]
27052#[inline]
27053#[cfg(target_endian = "little")]
27054#[target_feature(enable = "neon")]
27055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27057#[cfg_attr(
27058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27059 assert_instr(ld4)
27060)]
27061#[cfg_attr(
27062 not(target_arch = "arm"),
27063 stable(feature = "neon_intrinsics", since = "1.59.0")
27064)]
27065#[cfg_attr(
27066 target_arch = "arm",
27067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27068)]
27069pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27070 transmute(vld4_s16(transmute(a)))
27071}
27072#[doc = "Load multiple 4-element structures to four registers"]
27073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
27074#[doc = "## Safety"]
27075#[doc = " * Neon instrinsic unsafe"]
27076#[inline]
27077#[cfg(target_endian = "big")]
27078#[target_feature(enable = "neon")]
27079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27081#[cfg_attr(
27082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27083 assert_instr(ld4)
27084)]
27085#[cfg_attr(
27086 not(target_arch = "arm"),
27087 stable(feature = "neon_intrinsics", since = "1.59.0")
27088)]
27089#[cfg_attr(
27090 target_arch = "arm",
27091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27092)]
27093pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
27094 let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a)));
27095 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27096 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27097 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27098 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27099 ret_val
27100}
27101#[doc = "Load multiple 4-element structures to four registers"]
27102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27103#[doc = "## Safety"]
27104#[doc = " * Neon instrinsic unsafe"]
27105#[inline]
27106#[cfg(target_endian = "little")]
27107#[target_feature(enable = "neon")]
27108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27110#[cfg_attr(
27111 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27112 assert_instr(ld4)
27113)]
27114#[cfg_attr(
27115 not(target_arch = "arm"),
27116 stable(feature = "neon_intrinsics", since = "1.59.0")
27117)]
27118#[cfg_attr(
27119 target_arch = "arm",
27120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27121)]
27122pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27123 transmute(vld4q_s16(transmute(a)))
27124}
27125#[doc = "Load multiple 4-element structures to four registers"]
27126#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
27127#[doc = "## Safety"]
27128#[doc = " * Neon instrinsic unsafe"]
27129#[inline]
27130#[cfg(target_endian = "big")]
27131#[target_feature(enable = "neon")]
27132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27134#[cfg_attr(
27135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27136 assert_instr(ld4)
27137)]
27138#[cfg_attr(
27139 not(target_arch = "arm"),
27140 stable(feature = "neon_intrinsics", since = "1.59.0")
27141)]
27142#[cfg_attr(
27143 target_arch = "arm",
27144 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27145)]
27146pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
27147 let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a)));
27148 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27149 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27150 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27151 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27152 ret_val
27153}
27154#[doc = "Load multiple 4-element structures to four registers"]
27155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27156#[doc = "## Safety"]
27157#[doc = " * Neon instrinsic unsafe"]
27158#[inline]
27159#[cfg(target_endian = "little")]
27160#[target_feature(enable = "neon")]
27161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27162#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27163#[cfg_attr(
27164 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27165 assert_instr(ld4)
27166)]
27167#[cfg_attr(
27168 not(target_arch = "arm"),
27169 stable(feature = "neon_intrinsics", since = "1.59.0")
27170)]
27171#[cfg_attr(
27172 target_arch = "arm",
27173 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27174)]
27175pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27176 transmute(vld4_s32(transmute(a)))
27177}
27178#[doc = "Load multiple 4-element structures to four registers"]
27179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
27180#[doc = "## Safety"]
27181#[doc = " * Neon instrinsic unsafe"]
27182#[inline]
27183#[cfg(target_endian = "big")]
27184#[target_feature(enable = "neon")]
27185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27187#[cfg_attr(
27188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27189 assert_instr(ld4)
27190)]
27191#[cfg_attr(
27192 not(target_arch = "arm"),
27193 stable(feature = "neon_intrinsics", since = "1.59.0")
27194)]
27195#[cfg_attr(
27196 target_arch = "arm",
27197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27198)]
27199pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
27200 let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a)));
27201 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) };
27202 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) };
27203 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) };
27204 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
27205 ret_val
27206}
27207#[doc = "Load multiple 4-element structures to four registers"]
27208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27209#[doc = "## Safety"]
27210#[doc = " * Neon instrinsic unsafe"]
27211#[inline]
27212#[cfg(target_endian = "little")]
27213#[target_feature(enable = "neon")]
27214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27216#[cfg_attr(
27217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27218 assert_instr(ld4)
27219)]
27220#[cfg_attr(
27221 not(target_arch = "arm"),
27222 stable(feature = "neon_intrinsics", since = "1.59.0")
27223)]
27224#[cfg_attr(
27225 target_arch = "arm",
27226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27227)]
27228pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27229 transmute(vld4q_s32(transmute(a)))
27230}
27231#[doc = "Load multiple 4-element structures to four registers"]
27232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
27233#[doc = "## Safety"]
27234#[doc = " * Neon instrinsic unsafe"]
27235#[inline]
27236#[cfg(target_endian = "big")]
27237#[target_feature(enable = "neon")]
27238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27240#[cfg_attr(
27241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27242 assert_instr(ld4)
27243)]
27244#[cfg_attr(
27245 not(target_arch = "arm"),
27246 stable(feature = "neon_intrinsics", since = "1.59.0")
27247)]
27248#[cfg_attr(
27249 target_arch = "arm",
27250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27251)]
27252pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
27253 let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a)));
27254 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27255 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27256 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27257 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27258 ret_val
27259}
27260#[doc = "Load multiple 4-element structures to four registers"]
27261#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27262#[doc = "## Safety"]
27263#[doc = " * Neon instrinsic unsafe"]
27264#[inline]
27265#[cfg(target_endian = "little")]
27266#[target_feature(enable = "neon")]
27267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27269#[cfg_attr(
27270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27271 assert_instr(ld4)
27272)]
27273#[cfg_attr(
27274 not(target_arch = "arm"),
27275 stable(feature = "neon_intrinsics", since = "1.59.0")
27276)]
27277#[cfg_attr(
27278 target_arch = "arm",
27279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27280)]
27281pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27282 transmute(vld4_s8(transmute(a)))
27283}
27284#[doc = "Load multiple 4-element structures to four registers"]
27285#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
27286#[doc = "## Safety"]
27287#[doc = " * Neon instrinsic unsafe"]
27288#[inline]
27289#[cfg(target_endian = "big")]
27290#[target_feature(enable = "neon")]
27291#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27293#[cfg_attr(
27294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27295 assert_instr(ld4)
27296)]
27297#[cfg_attr(
27298 not(target_arch = "arm"),
27299 stable(feature = "neon_intrinsics", since = "1.59.0")
27300)]
27301#[cfg_attr(
27302 target_arch = "arm",
27303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27304)]
27305pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
27306 let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a)));
27307 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27308 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27309 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27310 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27311 ret_val
27312}
27313#[doc = "Load multiple 4-element structures to four registers"]
27314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27315#[doc = "## Safety"]
27316#[doc = " * Neon instrinsic unsafe"]
27317#[inline]
27318#[cfg(target_endian = "little")]
27319#[target_feature(enable = "neon")]
27320#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27321#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27322#[cfg_attr(
27323 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27324 assert_instr(ld4)
27325)]
27326#[cfg_attr(
27327 not(target_arch = "arm"),
27328 stable(feature = "neon_intrinsics", since = "1.59.0")
27329)]
27330#[cfg_attr(
27331 target_arch = "arm",
27332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27333)]
27334pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27335 transmute(vld4q_s8(transmute(a)))
27336}
27337#[doc = "Load multiple 4-element structures to four registers"]
27338#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
27339#[doc = "## Safety"]
27340#[doc = " * Neon instrinsic unsafe"]
27341#[inline]
27342#[cfg(target_endian = "big")]
27343#[target_feature(enable = "neon")]
27344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27346#[cfg_attr(
27347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27348 assert_instr(ld4)
27349)]
27350#[cfg_attr(
27351 not(target_arch = "arm"),
27352 stable(feature = "neon_intrinsics", since = "1.59.0")
27353)]
27354#[cfg_attr(
27355 target_arch = "arm",
27356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27357)]
27358pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
27359 let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a)));
27360 ret_val.0 = unsafe {
27361 simd_shuffle!(
27362 ret_val.0,
27363 ret_val.0,
27364 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27365 )
27366 };
27367 ret_val.1 = unsafe {
27368 simd_shuffle!(
27369 ret_val.1,
27370 ret_val.1,
27371 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27372 )
27373 };
27374 ret_val.2 = unsafe {
27375 simd_shuffle!(
27376 ret_val.2,
27377 ret_val.2,
27378 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27379 )
27380 };
27381 ret_val.3 = unsafe {
27382 simd_shuffle!(
27383 ret_val.3,
27384 ret_val.3,
27385 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
27386 )
27387 };
27388 ret_val
27389}
27390#[doc = "Load multiple 4-element structures to four registers"]
27391#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27392#[doc = "## Safety"]
27393#[doc = " * Neon instrinsic unsafe"]
27394#[inline]
27395#[cfg(target_endian = "little")]
27396#[target_feature(enable = "neon")]
27397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27399#[cfg_attr(
27400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27401 assert_instr(ld4)
27402)]
27403#[cfg_attr(
27404 not(target_arch = "arm"),
27405 stable(feature = "neon_intrinsics", since = "1.59.0")
27406)]
27407#[cfg_attr(
27408 target_arch = "arm",
27409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27410)]
27411pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27412 transmute(vld4_s16(transmute(a)))
27413}
27414#[doc = "Load multiple 4-element structures to four registers"]
27415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
27416#[doc = "## Safety"]
27417#[doc = " * Neon instrinsic unsafe"]
27418#[inline]
27419#[cfg(target_endian = "big")]
27420#[target_feature(enable = "neon")]
27421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27422#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27423#[cfg_attr(
27424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27425 assert_instr(ld4)
27426)]
27427#[cfg_attr(
27428 not(target_arch = "arm"),
27429 stable(feature = "neon_intrinsics", since = "1.59.0")
27430)]
27431#[cfg_attr(
27432 target_arch = "arm",
27433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27434)]
27435pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
27436 let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a)));
27437 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) };
27438 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) };
27439 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) };
27440 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) };
27441 ret_val
27442}
27443#[doc = "Load multiple 4-element structures to four registers"]
27444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27445#[doc = "## Safety"]
27446#[doc = " * Neon instrinsic unsafe"]
27447#[inline]
27448#[cfg(target_endian = "little")]
27449#[target_feature(enable = "neon")]
27450#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27451#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27452#[cfg_attr(
27453 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27454 assert_instr(ld4)
27455)]
27456#[cfg_attr(
27457 not(target_arch = "arm"),
27458 stable(feature = "neon_intrinsics", since = "1.59.0")
27459)]
27460#[cfg_attr(
27461 target_arch = "arm",
27462 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27463)]
27464pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27465 transmute(vld4q_s16(transmute(a)))
27466}
27467#[doc = "Load multiple 4-element structures to four registers"]
27468#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
27469#[doc = "## Safety"]
27470#[doc = " * Neon instrinsic unsafe"]
27471#[inline]
27472#[cfg(target_endian = "big")]
27473#[target_feature(enable = "neon")]
27474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
27476#[cfg_attr(
27477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27478 assert_instr(ld4)
27479)]
27480#[cfg_attr(
27481 not(target_arch = "arm"),
27482 stable(feature = "neon_intrinsics", since = "1.59.0")
27483)]
27484#[cfg_attr(
27485 target_arch = "arm",
27486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27487)]
27488pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
27489 let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a)));
27490 ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
27491 ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
27492 ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
27493 ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
27494 ret_val
27495}
27496#[doc = "Store SIMD&FP register (immediate offset)"]
27497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
27498#[doc = "## Safety"]
27499#[doc = " * Neon instrinsic unsafe"]
27500#[inline]
27501#[target_feature(enable = "neon")]
27502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27503#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
27504#[cfg_attr(
27505 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27506 assert_instr(nop)
27507)]
27508#[cfg_attr(
27509 not(target_arch = "arm"),
27510 stable(feature = "neon_intrinsics", since = "1.59.0")
27511)]
27512#[cfg_attr(
27513 target_arch = "arm",
27514 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27515)]
27516pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
27517 *a
27518}
27519#[doc = "Maximum (vector)"]
27520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
27521#[inline]
27522#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27524#[cfg_attr(
27525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27526 assert_instr(fmax)
27527)]
27528#[target_feature(enable = "neon,fp16")]
27529#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27530pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27531 unsafe extern "unadjusted" {
27532 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f16")]
27533 #[cfg_attr(
27534 any(target_arch = "aarch64", target_arch = "arm64ec"),
27535 link_name = "llvm.aarch64.neon.fmax.v4f16"
27536 )]
27537 fn _vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
27538 }
27539 unsafe { _vmax_f16(a, b) }
27540}
27541#[doc = "Maximum (vector)"]
27542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
27543#[inline]
27544#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27546#[cfg_attr(
27547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27548 assert_instr(fmax)
27549)]
27550#[target_feature(enable = "neon,fp16")]
27551#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27552pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27553 unsafe extern "unadjusted" {
27554 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8f16")]
27555 #[cfg_attr(
27556 any(target_arch = "aarch64", target_arch = "arm64ec"),
27557 link_name = "llvm.aarch64.neon.fmax.v8f16"
27558 )]
27559 fn _vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
27560 }
27561 unsafe { _vmaxq_f16(a, b) }
27562}
27563#[doc = "Maximum (vector)"]
27564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
27565#[inline]
27566#[target_feature(enable = "neon")]
27567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27569#[cfg_attr(
27570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27571 assert_instr(fmax)
27572)]
27573#[cfg_attr(
27574 not(target_arch = "arm"),
27575 stable(feature = "neon_intrinsics", since = "1.59.0")
27576)]
27577#[cfg_attr(
27578 target_arch = "arm",
27579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27580)]
27581pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27582 unsafe extern "unadjusted" {
27583 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")]
27584 #[cfg_attr(
27585 any(target_arch = "aarch64", target_arch = "arm64ec"),
27586 link_name = "llvm.aarch64.neon.fmax.v2f32"
27587 )]
27588 fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
27589 }
27590 unsafe { _vmax_f32(a, b) }
27591}
27592#[doc = "Maximum (vector)"]
27593#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
27594#[inline]
27595#[target_feature(enable = "neon")]
27596#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27597#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27598#[cfg_attr(
27599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27600 assert_instr(fmax)
27601)]
27602#[cfg_attr(
27603 not(target_arch = "arm"),
27604 stable(feature = "neon_intrinsics", since = "1.59.0")
27605)]
27606#[cfg_attr(
27607 target_arch = "arm",
27608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27609)]
27610pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27611 unsafe extern "unadjusted" {
27612 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")]
27613 #[cfg_attr(
27614 any(target_arch = "aarch64", target_arch = "arm64ec"),
27615 link_name = "llvm.aarch64.neon.fmax.v4f32"
27616 )]
27617 fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
27618 }
27619 unsafe { _vmaxq_f32(a, b) }
27620}
27621#[doc = "Maximum (vector)"]
27622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
27623#[inline]
27624#[target_feature(enable = "neon")]
27625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27627#[cfg_attr(
27628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27629 assert_instr(smax)
27630)]
27631#[cfg_attr(
27632 not(target_arch = "arm"),
27633 stable(feature = "neon_intrinsics", since = "1.59.0")
27634)]
27635#[cfg_attr(
27636 target_arch = "arm",
27637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27638)]
27639pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
27640 unsafe {
27641 let mask: int8x8_t = simd_ge(a, b);
27642 simd_select(mask, a, b)
27643 }
27644}
27645#[doc = "Maximum (vector)"]
27646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
27647#[inline]
27648#[target_feature(enable = "neon")]
27649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27651#[cfg_attr(
27652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27653 assert_instr(smax)
27654)]
27655#[cfg_attr(
27656 not(target_arch = "arm"),
27657 stable(feature = "neon_intrinsics", since = "1.59.0")
27658)]
27659#[cfg_attr(
27660 target_arch = "arm",
27661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27662)]
27663pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
27664 unsafe {
27665 let mask: int8x16_t = simd_ge(a, b);
27666 simd_select(mask, a, b)
27667 }
27668}
27669#[doc = "Maximum (vector)"]
27670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
27671#[inline]
27672#[target_feature(enable = "neon")]
27673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27675#[cfg_attr(
27676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27677 assert_instr(smax)
27678)]
27679#[cfg_attr(
27680 not(target_arch = "arm"),
27681 stable(feature = "neon_intrinsics", since = "1.59.0")
27682)]
27683#[cfg_attr(
27684 target_arch = "arm",
27685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27686)]
27687pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
27688 unsafe {
27689 let mask: int16x4_t = simd_ge(a, b);
27690 simd_select(mask, a, b)
27691 }
27692}
27693#[doc = "Maximum (vector)"]
27694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
27695#[inline]
27696#[target_feature(enable = "neon")]
27697#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27699#[cfg_attr(
27700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27701 assert_instr(smax)
27702)]
27703#[cfg_attr(
27704 not(target_arch = "arm"),
27705 stable(feature = "neon_intrinsics", since = "1.59.0")
27706)]
27707#[cfg_attr(
27708 target_arch = "arm",
27709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27710)]
27711pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
27712 unsafe {
27713 let mask: int16x8_t = simd_ge(a, b);
27714 simd_select(mask, a, b)
27715 }
27716}
27717#[doc = "Maximum (vector)"]
27718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
27719#[inline]
27720#[target_feature(enable = "neon")]
27721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27723#[cfg_attr(
27724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27725 assert_instr(smax)
27726)]
27727#[cfg_attr(
27728 not(target_arch = "arm"),
27729 stable(feature = "neon_intrinsics", since = "1.59.0")
27730)]
27731#[cfg_attr(
27732 target_arch = "arm",
27733 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27734)]
27735pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
27736 unsafe {
27737 let mask: int32x2_t = simd_ge(a, b);
27738 simd_select(mask, a, b)
27739 }
27740}
27741#[doc = "Maximum (vector)"]
27742#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
27743#[inline]
27744#[target_feature(enable = "neon")]
27745#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27746#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27747#[cfg_attr(
27748 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27749 assert_instr(smax)
27750)]
27751#[cfg_attr(
27752 not(target_arch = "arm"),
27753 stable(feature = "neon_intrinsics", since = "1.59.0")
27754)]
27755#[cfg_attr(
27756 target_arch = "arm",
27757 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27758)]
27759pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
27760 unsafe {
27761 let mask: int32x4_t = simd_ge(a, b);
27762 simd_select(mask, a, b)
27763 }
27764}
27765#[doc = "Maximum (vector)"]
27766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
27767#[inline]
27768#[target_feature(enable = "neon")]
27769#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27771#[cfg_attr(
27772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27773 assert_instr(umax)
27774)]
27775#[cfg_attr(
27776 not(target_arch = "arm"),
27777 stable(feature = "neon_intrinsics", since = "1.59.0")
27778)]
27779#[cfg_attr(
27780 target_arch = "arm",
27781 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27782)]
27783pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
27784 unsafe {
27785 let mask: uint8x8_t = simd_ge(a, b);
27786 simd_select(mask, a, b)
27787 }
27788}
27789#[doc = "Maximum (vector)"]
27790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
27791#[inline]
27792#[target_feature(enable = "neon")]
27793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27795#[cfg_attr(
27796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27797 assert_instr(umax)
27798)]
27799#[cfg_attr(
27800 not(target_arch = "arm"),
27801 stable(feature = "neon_intrinsics", since = "1.59.0")
27802)]
27803#[cfg_attr(
27804 target_arch = "arm",
27805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27806)]
27807pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
27808 unsafe {
27809 let mask: uint8x16_t = simd_ge(a, b);
27810 simd_select(mask, a, b)
27811 }
27812}
27813#[doc = "Maximum (vector)"]
27814#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
27815#[inline]
27816#[target_feature(enable = "neon")]
27817#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27818#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27819#[cfg_attr(
27820 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27821 assert_instr(umax)
27822)]
27823#[cfg_attr(
27824 not(target_arch = "arm"),
27825 stable(feature = "neon_intrinsics", since = "1.59.0")
27826)]
27827#[cfg_attr(
27828 target_arch = "arm",
27829 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27830)]
27831pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
27832 unsafe {
27833 let mask: uint16x4_t = simd_ge(a, b);
27834 simd_select(mask, a, b)
27835 }
27836}
27837#[doc = "Maximum (vector)"]
27838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
27839#[inline]
27840#[target_feature(enable = "neon")]
27841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27843#[cfg_attr(
27844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27845 assert_instr(umax)
27846)]
27847#[cfg_attr(
27848 not(target_arch = "arm"),
27849 stable(feature = "neon_intrinsics", since = "1.59.0")
27850)]
27851#[cfg_attr(
27852 target_arch = "arm",
27853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27854)]
27855pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
27856 unsafe {
27857 let mask: uint16x8_t = simd_ge(a, b);
27858 simd_select(mask, a, b)
27859 }
27860}
27861#[doc = "Maximum (vector)"]
27862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
27863#[inline]
27864#[target_feature(enable = "neon")]
27865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27867#[cfg_attr(
27868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27869 assert_instr(umax)
27870)]
27871#[cfg_attr(
27872 not(target_arch = "arm"),
27873 stable(feature = "neon_intrinsics", since = "1.59.0")
27874)]
27875#[cfg_attr(
27876 target_arch = "arm",
27877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27878)]
27879pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
27880 unsafe {
27881 let mask: uint32x2_t = simd_ge(a, b);
27882 simd_select(mask, a, b)
27883 }
27884}
27885#[doc = "Maximum (vector)"]
27886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
27887#[inline]
27888#[target_feature(enable = "neon")]
27889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
27890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
27891#[cfg_attr(
27892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27893 assert_instr(umax)
27894)]
27895#[cfg_attr(
27896 not(target_arch = "arm"),
27897 stable(feature = "neon_intrinsics", since = "1.59.0")
27898)]
27899#[cfg_attr(
27900 target_arch = "arm",
27901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27902)]
27903pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
27904 unsafe {
27905 let mask: uint32x4_t = simd_ge(a, b);
27906 simd_select(mask, a, b)
27907 }
27908}
27909#[doc = "Floating-point Maximum Number (vector)"]
27910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
27911#[inline]
27912#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
27913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
27914#[cfg_attr(
27915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27916 assert_instr(fmaxnm)
27917)]
27918#[target_feature(enable = "neon,fp16")]
27919#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27920pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27921 unsafe { simd_fmax(a, b) }
27922}
27923#[doc = "Floating-point Maximum Number (vector)"]
27924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
27925#[inline]
27926#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
27927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
27928#[cfg_attr(
27929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27930 assert_instr(fmaxnm)
27931)]
27932#[target_feature(enable = "neon,fp16")]
27933#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27934pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
27935 unsafe { simd_fmax(a, b) }
27936}
27937#[doc = "Floating-point Maximum Number (vector)"]
27938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
27939#[inline]
27940#[target_feature(enable = "neon")]
27941#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
27942#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
27943#[cfg_attr(
27944 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27945 assert_instr(fmaxnm)
27946)]
27947#[cfg_attr(
27948 not(target_arch = "arm"),
27949 stable(feature = "neon_intrinsics", since = "1.59.0")
27950)]
27951#[cfg_attr(
27952 target_arch = "arm",
27953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27954)]
27955pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
27956 unsafe { simd_fmax(a, b) }
27957}
27958#[doc = "Floating-point Maximum Number (vector)"]
27959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
27960#[inline]
27961#[target_feature(enable = "neon")]
27962#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
27963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
27964#[cfg_attr(
27965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27966 assert_instr(fmaxnm)
27967)]
27968#[cfg_attr(
27969 not(target_arch = "arm"),
27970 stable(feature = "neon_intrinsics", since = "1.59.0")
27971)]
27972#[cfg_attr(
27973 target_arch = "arm",
27974 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
27975)]
27976pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
27977 unsafe { simd_fmax(a, b) }
27978}
27979#[doc = "Minimum (vector)"]
27980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
27981#[inline]
27982#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
27983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
27984#[cfg_attr(
27985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
27986 assert_instr(fmin)
27987)]
27988#[target_feature(enable = "neon,fp16")]
27989#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
27990pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
27991 unsafe extern "unadjusted" {
27992 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f16")]
27993 #[cfg_attr(
27994 any(target_arch = "aarch64", target_arch = "arm64ec"),
27995 link_name = "llvm.aarch64.neon.fmin.v4f16"
27996 )]
27997 fn _vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
27998 }
27999 unsafe { _vmin_f16(a, b) }
28000}
28001#[doc = "Minimum (vector)"]
28002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
28003#[inline]
28004#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
28005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28006#[cfg_attr(
28007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28008 assert_instr(fmin)
28009)]
28010#[target_feature(enable = "neon,fp16")]
28011#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28012pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28013 unsafe extern "unadjusted" {
28014 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8f16")]
28015 #[cfg_attr(
28016 any(target_arch = "aarch64", target_arch = "arm64ec"),
28017 link_name = "llvm.aarch64.neon.fmin.v8f16"
28018 )]
28019 fn _vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
28020 }
28021 unsafe { _vminq_f16(a, b) }
28022}
28023#[doc = "Minimum (vector)"]
28024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
28025#[inline]
28026#[target_feature(enable = "neon")]
28027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28029#[cfg_attr(
28030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28031 assert_instr(fmin)
28032)]
28033#[cfg_attr(
28034 not(target_arch = "arm"),
28035 stable(feature = "neon_intrinsics", since = "1.59.0")
28036)]
28037#[cfg_attr(
28038 target_arch = "arm",
28039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28040)]
28041pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28042 unsafe extern "unadjusted" {
28043 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")]
28044 #[cfg_attr(
28045 any(target_arch = "aarch64", target_arch = "arm64ec"),
28046 link_name = "llvm.aarch64.neon.fmin.v2f32"
28047 )]
28048 fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
28049 }
28050 unsafe { _vmin_f32(a, b) }
28051}
28052#[doc = "Minimum (vector)"]
28053#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
28054#[inline]
28055#[target_feature(enable = "neon")]
28056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28058#[cfg_attr(
28059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28060 assert_instr(fmin)
28061)]
28062#[cfg_attr(
28063 not(target_arch = "arm"),
28064 stable(feature = "neon_intrinsics", since = "1.59.0")
28065)]
28066#[cfg_attr(
28067 target_arch = "arm",
28068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28069)]
28070pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28071 unsafe extern "unadjusted" {
28072 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")]
28073 #[cfg_attr(
28074 any(target_arch = "aarch64", target_arch = "arm64ec"),
28075 link_name = "llvm.aarch64.neon.fmin.v4f32"
28076 )]
28077 fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
28078 }
28079 unsafe { _vminq_f32(a, b) }
28080}
28081#[doc = "Minimum (vector)"]
28082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
28083#[inline]
28084#[target_feature(enable = "neon")]
28085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28087#[cfg_attr(
28088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28089 assert_instr(smin)
28090)]
28091#[cfg_attr(
28092 not(target_arch = "arm"),
28093 stable(feature = "neon_intrinsics", since = "1.59.0")
28094)]
28095#[cfg_attr(
28096 target_arch = "arm",
28097 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28098)]
28099pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
28100 unsafe {
28101 let mask: int8x8_t = simd_le(a, b);
28102 simd_select(mask, a, b)
28103 }
28104}
28105#[doc = "Minimum (vector)"]
28106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
28107#[inline]
28108#[target_feature(enable = "neon")]
28109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28111#[cfg_attr(
28112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28113 assert_instr(smin)
28114)]
28115#[cfg_attr(
28116 not(target_arch = "arm"),
28117 stable(feature = "neon_intrinsics", since = "1.59.0")
28118)]
28119#[cfg_attr(
28120 target_arch = "arm",
28121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28122)]
28123pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
28124 unsafe {
28125 let mask: int8x16_t = simd_le(a, b);
28126 simd_select(mask, a, b)
28127 }
28128}
28129#[doc = "Minimum (vector)"]
28130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
28131#[inline]
28132#[target_feature(enable = "neon")]
28133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28135#[cfg_attr(
28136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28137 assert_instr(smin)
28138)]
28139#[cfg_attr(
28140 not(target_arch = "arm"),
28141 stable(feature = "neon_intrinsics", since = "1.59.0")
28142)]
28143#[cfg_attr(
28144 target_arch = "arm",
28145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28146)]
28147pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
28148 unsafe {
28149 let mask: int16x4_t = simd_le(a, b);
28150 simd_select(mask, a, b)
28151 }
28152}
28153#[doc = "Minimum (vector)"]
28154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
28155#[inline]
28156#[target_feature(enable = "neon")]
28157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28159#[cfg_attr(
28160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28161 assert_instr(smin)
28162)]
28163#[cfg_attr(
28164 not(target_arch = "arm"),
28165 stable(feature = "neon_intrinsics", since = "1.59.0")
28166)]
28167#[cfg_attr(
28168 target_arch = "arm",
28169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28170)]
28171pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
28172 unsafe {
28173 let mask: int16x8_t = simd_le(a, b);
28174 simd_select(mask, a, b)
28175 }
28176}
28177#[doc = "Minimum (vector)"]
28178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
28179#[inline]
28180#[target_feature(enable = "neon")]
28181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28183#[cfg_attr(
28184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28185 assert_instr(smin)
28186)]
28187#[cfg_attr(
28188 not(target_arch = "arm"),
28189 stable(feature = "neon_intrinsics", since = "1.59.0")
28190)]
28191#[cfg_attr(
28192 target_arch = "arm",
28193 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28194)]
28195pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
28196 unsafe {
28197 let mask: int32x2_t = simd_le(a, b);
28198 simd_select(mask, a, b)
28199 }
28200}
28201#[doc = "Minimum (vector)"]
28202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
28203#[inline]
28204#[target_feature(enable = "neon")]
28205#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28206#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28207#[cfg_attr(
28208 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28209 assert_instr(smin)
28210)]
28211#[cfg_attr(
28212 not(target_arch = "arm"),
28213 stable(feature = "neon_intrinsics", since = "1.59.0")
28214)]
28215#[cfg_attr(
28216 target_arch = "arm",
28217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28218)]
28219pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
28220 unsafe {
28221 let mask: int32x4_t = simd_le(a, b);
28222 simd_select(mask, a, b)
28223 }
28224}
28225#[doc = "Minimum (vector)"]
28226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
28227#[inline]
28228#[target_feature(enable = "neon")]
28229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28231#[cfg_attr(
28232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28233 assert_instr(umin)
28234)]
28235#[cfg_attr(
28236 not(target_arch = "arm"),
28237 stable(feature = "neon_intrinsics", since = "1.59.0")
28238)]
28239#[cfg_attr(
28240 target_arch = "arm",
28241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28242)]
28243pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
28244 unsafe {
28245 let mask: uint8x8_t = simd_le(a, b);
28246 simd_select(mask, a, b)
28247 }
28248}
28249#[doc = "Minimum (vector)"]
28250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
28251#[inline]
28252#[target_feature(enable = "neon")]
28253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28255#[cfg_attr(
28256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28257 assert_instr(umin)
28258)]
28259#[cfg_attr(
28260 not(target_arch = "arm"),
28261 stable(feature = "neon_intrinsics", since = "1.59.0")
28262)]
28263#[cfg_attr(
28264 target_arch = "arm",
28265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28266)]
28267pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
28268 unsafe {
28269 let mask: uint8x16_t = simd_le(a, b);
28270 simd_select(mask, a, b)
28271 }
28272}
28273#[doc = "Minimum (vector)"]
28274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
28275#[inline]
28276#[target_feature(enable = "neon")]
28277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28279#[cfg_attr(
28280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28281 assert_instr(umin)
28282)]
28283#[cfg_attr(
28284 not(target_arch = "arm"),
28285 stable(feature = "neon_intrinsics", since = "1.59.0")
28286)]
28287#[cfg_attr(
28288 target_arch = "arm",
28289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28290)]
28291pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
28292 unsafe {
28293 let mask: uint16x4_t = simd_le(a, b);
28294 simd_select(mask, a, b)
28295 }
28296}
28297#[doc = "Minimum (vector)"]
28298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
28299#[inline]
28300#[target_feature(enable = "neon")]
28301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28303#[cfg_attr(
28304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28305 assert_instr(umin)
28306)]
28307#[cfg_attr(
28308 not(target_arch = "arm"),
28309 stable(feature = "neon_intrinsics", since = "1.59.0")
28310)]
28311#[cfg_attr(
28312 target_arch = "arm",
28313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28314)]
28315pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
28316 unsafe {
28317 let mask: uint16x8_t = simd_le(a, b);
28318 simd_select(mask, a, b)
28319 }
28320}
28321#[doc = "Minimum (vector)"]
28322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
28323#[inline]
28324#[target_feature(enable = "neon")]
28325#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28326#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28327#[cfg_attr(
28328 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28329 assert_instr(umin)
28330)]
28331#[cfg_attr(
28332 not(target_arch = "arm"),
28333 stable(feature = "neon_intrinsics", since = "1.59.0")
28334)]
28335#[cfg_attr(
28336 target_arch = "arm",
28337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28338)]
28339pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
28340 unsafe {
28341 let mask: uint32x2_t = simd_le(a, b);
28342 simd_select(mask, a, b)
28343 }
28344}
28345#[doc = "Minimum (vector)"]
28346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
28347#[inline]
28348#[target_feature(enable = "neon")]
28349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
28351#[cfg_attr(
28352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28353 assert_instr(umin)
28354)]
28355#[cfg_attr(
28356 not(target_arch = "arm"),
28357 stable(feature = "neon_intrinsics", since = "1.59.0")
28358)]
28359#[cfg_attr(
28360 target_arch = "arm",
28361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28362)]
28363pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
28364 unsafe {
28365 let mask: uint32x4_t = simd_le(a, b);
28366 simd_select(mask, a, b)
28367 }
28368}
28369#[doc = "Floating-point Minimum Number (vector)"]
28370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
28371#[inline]
28372#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28373#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28374#[cfg_attr(
28375 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28376 assert_instr(fminnm)
28377)]
28378#[target_feature(enable = "neon,fp16")]
28379#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28380pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
28381 unsafe { simd_fmin(a, b) }
28382}
28383#[doc = "Floating-point Minimum Number (vector)"]
28384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
28385#[inline]
28386#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28387#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28388#[cfg_attr(
28389 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28390 assert_instr(fminnm)
28391)]
28392#[target_feature(enable = "neon,fp16")]
28393#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
28394pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
28395 unsafe { simd_fmin(a, b) }
28396}
28397#[doc = "Floating-point Minimum Number (vector)"]
28398#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
28399#[inline]
28400#[target_feature(enable = "neon")]
28401#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28403#[cfg_attr(
28404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28405 assert_instr(fminnm)
28406)]
28407#[cfg_attr(
28408 not(target_arch = "arm"),
28409 stable(feature = "neon_intrinsics", since = "1.59.0")
28410)]
28411#[cfg_attr(
28412 target_arch = "arm",
28413 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28414)]
28415pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
28416 unsafe { simd_fmin(a, b) }
28417}
28418#[doc = "Floating-point Minimum Number (vector)"]
28419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
28420#[inline]
28421#[target_feature(enable = "neon")]
28422#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
28423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
28424#[cfg_attr(
28425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28426 assert_instr(fminnm)
28427)]
28428#[cfg_attr(
28429 not(target_arch = "arm"),
28430 stable(feature = "neon_intrinsics", since = "1.59.0")
28431)]
28432#[cfg_attr(
28433 target_arch = "arm",
28434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28435)]
28436pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
28437 unsafe { simd_fmin(a, b) }
28438}
28439#[doc = "Floating-point multiply-add to accumulator"]
28440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
28441#[inline]
28442#[target_feature(enable = "neon")]
28443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28444#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28445#[cfg_attr(
28446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28447 assert_instr(fmul)
28448)]
28449#[cfg_attr(
28450 not(target_arch = "arm"),
28451 stable(feature = "neon_intrinsics", since = "1.59.0")
28452)]
28453#[cfg_attr(
28454 target_arch = "arm",
28455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28456)]
28457pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
28458 unsafe { simd_add(a, simd_mul(b, c)) }
28459}
28460#[doc = "Floating-point multiply-add to accumulator"]
28461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
28462#[inline]
28463#[target_feature(enable = "neon")]
28464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28465#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
28466#[cfg_attr(
28467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28468 assert_instr(fmul)
28469)]
28470#[cfg_attr(
28471 not(target_arch = "arm"),
28472 stable(feature = "neon_intrinsics", since = "1.59.0")
28473)]
28474#[cfg_attr(
28475 target_arch = "arm",
28476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28477)]
28478pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
28479 unsafe { simd_add(a, simd_mul(b, c)) }
28480}
28481#[doc = "Vector multiply accumulate with scalar"]
28482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
28483#[inline]
28484#[target_feature(enable = "neon")]
28485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28486#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28487#[cfg_attr(
28488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28489 assert_instr(fmul, LANE = 1)
28490)]
28491#[rustc_legacy_const_generics(3)]
28492#[cfg_attr(
28493 not(target_arch = "arm"),
28494 stable(feature = "neon_intrinsics", since = "1.59.0")
28495)]
28496#[cfg_attr(
28497 target_arch = "arm",
28498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28499)]
28500pub fn vmla_lane_f32<const LANE: i32>(
28501 a: float32x2_t,
28502 b: float32x2_t,
28503 c: float32x2_t,
28504) -> float32x2_t {
28505 static_assert_uimm_bits!(LANE, 1);
28506 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28507}
28508#[doc = "Vector multiply accumulate with scalar"]
28509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
28510#[inline]
28511#[target_feature(enable = "neon")]
28512#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28513#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28514#[cfg_attr(
28515 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28516 assert_instr(fmul, LANE = 1)
28517)]
28518#[rustc_legacy_const_generics(3)]
28519#[cfg_attr(
28520 not(target_arch = "arm"),
28521 stable(feature = "neon_intrinsics", since = "1.59.0")
28522)]
28523#[cfg_attr(
28524 target_arch = "arm",
28525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28526)]
28527pub fn vmla_laneq_f32<const LANE: i32>(
28528 a: float32x2_t,
28529 b: float32x2_t,
28530 c: float32x4_t,
28531) -> float32x2_t {
28532 static_assert_uimm_bits!(LANE, 2);
28533 unsafe { vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28534}
28535#[doc = "Vector multiply accumulate with scalar"]
28536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
28537#[inline]
28538#[target_feature(enable = "neon")]
28539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28541#[cfg_attr(
28542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28543 assert_instr(fmul, LANE = 1)
28544)]
28545#[rustc_legacy_const_generics(3)]
28546#[cfg_attr(
28547 not(target_arch = "arm"),
28548 stable(feature = "neon_intrinsics", since = "1.59.0")
28549)]
28550#[cfg_attr(
28551 target_arch = "arm",
28552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28553)]
28554pub fn vmlaq_lane_f32<const LANE: i32>(
28555 a: float32x4_t,
28556 b: float32x4_t,
28557 c: float32x2_t,
28558) -> float32x4_t {
28559 static_assert_uimm_bits!(LANE, 1);
28560 unsafe {
28561 vmlaq_f32(
28562 a,
28563 b,
28564 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28565 )
28566 }
28567}
28568#[doc = "Vector multiply accumulate with scalar"]
28569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
28570#[inline]
28571#[target_feature(enable = "neon")]
28572#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
28574#[cfg_attr(
28575 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28576 assert_instr(fmul, LANE = 1)
28577)]
28578#[rustc_legacy_const_generics(3)]
28579#[cfg_attr(
28580 not(target_arch = "arm"),
28581 stable(feature = "neon_intrinsics", since = "1.59.0")
28582)]
28583#[cfg_attr(
28584 target_arch = "arm",
28585 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28586)]
28587pub fn vmlaq_laneq_f32<const LANE: i32>(
28588 a: float32x4_t,
28589 b: float32x4_t,
28590 c: float32x4_t,
28591) -> float32x4_t {
28592 static_assert_uimm_bits!(LANE, 2);
28593 unsafe {
28594 vmlaq_f32(
28595 a,
28596 b,
28597 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28598 )
28599 }
28600}
28601#[doc = "Vector multiply accumulate with scalar"]
28602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
28603#[inline]
28604#[target_feature(enable = "neon")]
28605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28606#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28607#[cfg_attr(
28608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28609 assert_instr(mla, LANE = 1)
28610)]
28611#[rustc_legacy_const_generics(3)]
28612#[cfg_attr(
28613 not(target_arch = "arm"),
28614 stable(feature = "neon_intrinsics", since = "1.59.0")
28615)]
28616#[cfg_attr(
28617 target_arch = "arm",
28618 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28619)]
28620pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
28621 static_assert_uimm_bits!(LANE, 2);
28622 unsafe {
28623 vmla_s16(
28624 a,
28625 b,
28626 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28627 )
28628 }
28629}
28630#[doc = "Vector multiply accumulate with scalar"]
28631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
28632#[inline]
28633#[target_feature(enable = "neon")]
28634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28635#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28636#[cfg_attr(
28637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28638 assert_instr(mla, LANE = 1)
28639)]
28640#[rustc_legacy_const_generics(3)]
28641#[cfg_attr(
28642 not(target_arch = "arm"),
28643 stable(feature = "neon_intrinsics", since = "1.59.0")
28644)]
28645#[cfg_attr(
28646 target_arch = "arm",
28647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28648)]
28649pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
28650 static_assert_uimm_bits!(LANE, 2);
28651 unsafe {
28652 vmla_u16(
28653 a,
28654 b,
28655 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28656 )
28657 }
28658}
28659#[doc = "Vector multiply accumulate with scalar"]
28660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
28661#[inline]
28662#[target_feature(enable = "neon")]
28663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28665#[cfg_attr(
28666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28667 assert_instr(mla, LANE = 1)
28668)]
28669#[rustc_legacy_const_generics(3)]
28670#[cfg_attr(
28671 not(target_arch = "arm"),
28672 stable(feature = "neon_intrinsics", since = "1.59.0")
28673)]
28674#[cfg_attr(
28675 target_arch = "arm",
28676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28677)]
28678pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
28679 static_assert_uimm_bits!(LANE, 3);
28680 unsafe {
28681 vmla_s16(
28682 a,
28683 b,
28684 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28685 )
28686 }
28687}
28688#[doc = "Vector multiply accumulate with scalar"]
28689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
28690#[inline]
28691#[target_feature(enable = "neon")]
28692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28693#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28694#[cfg_attr(
28695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28696 assert_instr(mla, LANE = 1)
28697)]
28698#[rustc_legacy_const_generics(3)]
28699#[cfg_attr(
28700 not(target_arch = "arm"),
28701 stable(feature = "neon_intrinsics", since = "1.59.0")
28702)]
28703#[cfg_attr(
28704 target_arch = "arm",
28705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28706)]
28707pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
28708 static_assert_uimm_bits!(LANE, 3);
28709 unsafe {
28710 vmla_u16(
28711 a,
28712 b,
28713 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
28714 )
28715 }
28716}
28717#[doc = "Vector multiply accumulate with scalar"]
28718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
28719#[inline]
28720#[target_feature(enable = "neon")]
28721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28722#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28723#[cfg_attr(
28724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28725 assert_instr(mla, LANE = 1)
28726)]
28727#[rustc_legacy_const_generics(3)]
28728#[cfg_attr(
28729 not(target_arch = "arm"),
28730 stable(feature = "neon_intrinsics", since = "1.59.0")
28731)]
28732#[cfg_attr(
28733 target_arch = "arm",
28734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28735)]
28736pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
28737 static_assert_uimm_bits!(LANE, 2);
28738 unsafe {
28739 vmlaq_s16(
28740 a,
28741 b,
28742 simd_shuffle!(
28743 c,
28744 c,
28745 [
28746 LANE as u32,
28747 LANE as u32,
28748 LANE as u32,
28749 LANE as u32,
28750 LANE as u32,
28751 LANE as u32,
28752 LANE as u32,
28753 LANE as u32
28754 ]
28755 ),
28756 )
28757 }
28758}
28759#[doc = "Vector multiply accumulate with scalar"]
28760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
28761#[inline]
28762#[target_feature(enable = "neon")]
28763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28764#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28765#[cfg_attr(
28766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28767 assert_instr(mla, LANE = 1)
28768)]
28769#[rustc_legacy_const_generics(3)]
28770#[cfg_attr(
28771 not(target_arch = "arm"),
28772 stable(feature = "neon_intrinsics", since = "1.59.0")
28773)]
28774#[cfg_attr(
28775 target_arch = "arm",
28776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28777)]
28778pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
28779 static_assert_uimm_bits!(LANE, 2);
28780 unsafe {
28781 vmlaq_u16(
28782 a,
28783 b,
28784 simd_shuffle!(
28785 c,
28786 c,
28787 [
28788 LANE as u32,
28789 LANE as u32,
28790 LANE as u32,
28791 LANE as u32,
28792 LANE as u32,
28793 LANE as u32,
28794 LANE as u32,
28795 LANE as u32
28796 ]
28797 ),
28798 )
28799 }
28800}
28801#[doc = "Vector multiply accumulate with scalar"]
28802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
28803#[inline]
28804#[target_feature(enable = "neon")]
28805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28806#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28807#[cfg_attr(
28808 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28809 assert_instr(mla, LANE = 1)
28810)]
28811#[rustc_legacy_const_generics(3)]
28812#[cfg_attr(
28813 not(target_arch = "arm"),
28814 stable(feature = "neon_intrinsics", since = "1.59.0")
28815)]
28816#[cfg_attr(
28817 target_arch = "arm",
28818 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28819)]
28820pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
28821 static_assert_uimm_bits!(LANE, 3);
28822 unsafe {
28823 vmlaq_s16(
28824 a,
28825 b,
28826 simd_shuffle!(
28827 c,
28828 c,
28829 [
28830 LANE as u32,
28831 LANE as u32,
28832 LANE as u32,
28833 LANE as u32,
28834 LANE as u32,
28835 LANE as u32,
28836 LANE as u32,
28837 LANE as u32
28838 ]
28839 ),
28840 )
28841 }
28842}
28843#[doc = "Vector multiply accumulate with scalar"]
28844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
28845#[inline]
28846#[target_feature(enable = "neon")]
28847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28848#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
28849#[cfg_attr(
28850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28851 assert_instr(mla, LANE = 1)
28852)]
28853#[rustc_legacy_const_generics(3)]
28854#[cfg_attr(
28855 not(target_arch = "arm"),
28856 stable(feature = "neon_intrinsics", since = "1.59.0")
28857)]
28858#[cfg_attr(
28859 target_arch = "arm",
28860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28861)]
28862pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
28863 static_assert_uimm_bits!(LANE, 3);
28864 unsafe {
28865 vmlaq_u16(
28866 a,
28867 b,
28868 simd_shuffle!(
28869 c,
28870 c,
28871 [
28872 LANE as u32,
28873 LANE as u32,
28874 LANE as u32,
28875 LANE as u32,
28876 LANE as u32,
28877 LANE as u32,
28878 LANE as u32,
28879 LANE as u32
28880 ]
28881 ),
28882 )
28883 }
28884}
28885#[doc = "Vector multiply accumulate with scalar"]
28886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
28887#[inline]
28888#[target_feature(enable = "neon")]
28889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28890#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
28891#[cfg_attr(
28892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28893 assert_instr(mla, LANE = 1)
28894)]
28895#[rustc_legacy_const_generics(3)]
28896#[cfg_attr(
28897 not(target_arch = "arm"),
28898 stable(feature = "neon_intrinsics", since = "1.59.0")
28899)]
28900#[cfg_attr(
28901 target_arch = "arm",
28902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28903)]
28904pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
28905 static_assert_uimm_bits!(LANE, 1);
28906 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28907}
28908#[doc = "Vector multiply accumulate with scalar"]
28909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
28910#[inline]
28911#[target_feature(enable = "neon")]
28912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28913#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
28914#[cfg_attr(
28915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28916 assert_instr(mla, LANE = 1)
28917)]
28918#[rustc_legacy_const_generics(3)]
28919#[cfg_attr(
28920 not(target_arch = "arm"),
28921 stable(feature = "neon_intrinsics", since = "1.59.0")
28922)]
28923#[cfg_attr(
28924 target_arch = "arm",
28925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28926)]
28927pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
28928 static_assert_uimm_bits!(LANE, 1);
28929 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28930}
28931#[doc = "Vector multiply accumulate with scalar"]
28932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
28933#[inline]
28934#[target_feature(enable = "neon")]
28935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
28937#[cfg_attr(
28938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28939 assert_instr(mla, LANE = 1)
28940)]
28941#[rustc_legacy_const_generics(3)]
28942#[cfg_attr(
28943 not(target_arch = "arm"),
28944 stable(feature = "neon_intrinsics", since = "1.59.0")
28945)]
28946#[cfg_attr(
28947 target_arch = "arm",
28948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28949)]
28950pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
28951 static_assert_uimm_bits!(LANE, 2);
28952 unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28953}
28954#[doc = "Vector multiply accumulate with scalar"]
28955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
28956#[inline]
28957#[target_feature(enable = "neon")]
28958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28959#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
28960#[cfg_attr(
28961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28962 assert_instr(mla, LANE = 1)
28963)]
28964#[rustc_legacy_const_generics(3)]
28965#[cfg_attr(
28966 not(target_arch = "arm"),
28967 stable(feature = "neon_intrinsics", since = "1.59.0")
28968)]
28969#[cfg_attr(
28970 target_arch = "arm",
28971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28972)]
28973pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
28974 static_assert_uimm_bits!(LANE, 2);
28975 unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
28976}
28977#[doc = "Vector multiply accumulate with scalar"]
28978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
28979#[inline]
28980#[target_feature(enable = "neon")]
28981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
28982#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
28983#[cfg_attr(
28984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
28985 assert_instr(mla, LANE = 1)
28986)]
28987#[rustc_legacy_const_generics(3)]
28988#[cfg_attr(
28989 not(target_arch = "arm"),
28990 stable(feature = "neon_intrinsics", since = "1.59.0")
28991)]
28992#[cfg_attr(
28993 target_arch = "arm",
28994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
28995)]
28996pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
28997 static_assert_uimm_bits!(LANE, 1);
28998 unsafe {
28999 vmlaq_s32(
29000 a,
29001 b,
29002 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29003 )
29004 }
29005}
29006#[doc = "Vector multiply accumulate with scalar"]
29007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
29008#[inline]
29009#[target_feature(enable = "neon")]
29010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29011#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29012#[cfg_attr(
29013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29014 assert_instr(mla, LANE = 1)
29015)]
29016#[rustc_legacy_const_generics(3)]
29017#[cfg_attr(
29018 not(target_arch = "arm"),
29019 stable(feature = "neon_intrinsics", since = "1.59.0")
29020)]
29021#[cfg_attr(
29022 target_arch = "arm",
29023 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29024)]
29025pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
29026 static_assert_uimm_bits!(LANE, 1);
29027 unsafe {
29028 vmlaq_u32(
29029 a,
29030 b,
29031 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29032 )
29033 }
29034}
29035#[doc = "Vector multiply accumulate with scalar"]
29036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
29037#[inline]
29038#[target_feature(enable = "neon")]
29039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29041#[cfg_attr(
29042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29043 assert_instr(mla, LANE = 1)
29044)]
29045#[rustc_legacy_const_generics(3)]
29046#[cfg_attr(
29047 not(target_arch = "arm"),
29048 stable(feature = "neon_intrinsics", since = "1.59.0")
29049)]
29050#[cfg_attr(
29051 target_arch = "arm",
29052 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29053)]
29054pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29055 static_assert_uimm_bits!(LANE, 2);
29056 unsafe {
29057 vmlaq_s32(
29058 a,
29059 b,
29060 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29061 )
29062 }
29063}
29064#[doc = "Vector multiply accumulate with scalar"]
29065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
29066#[inline]
29067#[target_feature(enable = "neon")]
29068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29069#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
29070#[cfg_attr(
29071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29072 assert_instr(mla, LANE = 1)
29073)]
29074#[rustc_legacy_const_generics(3)]
29075#[cfg_attr(
29076 not(target_arch = "arm"),
29077 stable(feature = "neon_intrinsics", since = "1.59.0")
29078)]
29079#[cfg_attr(
29080 target_arch = "arm",
29081 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29082)]
29083pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29084 static_assert_uimm_bits!(LANE, 2);
29085 unsafe {
29086 vmlaq_u32(
29087 a,
29088 b,
29089 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29090 )
29091 }
29092}
29093#[doc = "Vector multiply accumulate with scalar"]
29094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
29095#[inline]
29096#[target_feature(enable = "neon")]
29097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29099#[cfg_attr(
29100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29101 assert_instr(fmul)
29102)]
29103#[cfg_attr(
29104 not(target_arch = "arm"),
29105 stable(feature = "neon_intrinsics", since = "1.59.0")
29106)]
29107#[cfg_attr(
29108 target_arch = "arm",
29109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29110)]
29111pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
29112 vmla_f32(a, b, vdup_n_f32(c))
29113}
29114#[doc = "Vector multiply accumulate with scalar"]
29115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
29116#[inline]
29117#[target_feature(enable = "neon")]
29118#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29119#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
29120#[cfg_attr(
29121 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29122 assert_instr(fmul)
29123)]
29124#[cfg_attr(
29125 not(target_arch = "arm"),
29126 stable(feature = "neon_intrinsics", since = "1.59.0")
29127)]
29128#[cfg_attr(
29129 target_arch = "arm",
29130 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29131)]
29132pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
29133 vmlaq_f32(a, b, vdupq_n_f32(c))
29134}
29135#[doc = "Vector multiply accumulate with scalar"]
29136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
29137#[inline]
29138#[target_feature(enable = "neon")]
29139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29141#[cfg_attr(
29142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29143 assert_instr(mla)
29144)]
29145#[cfg_attr(
29146 not(target_arch = "arm"),
29147 stable(feature = "neon_intrinsics", since = "1.59.0")
29148)]
29149#[cfg_attr(
29150 target_arch = "arm",
29151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29152)]
29153pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
29154 vmla_s16(a, b, vdup_n_s16(c))
29155}
29156#[doc = "Vector multiply accumulate with scalar"]
29157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
29158#[inline]
29159#[target_feature(enable = "neon")]
29160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29161#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29162#[cfg_attr(
29163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29164 assert_instr(mla)
29165)]
29166#[cfg_attr(
29167 not(target_arch = "arm"),
29168 stable(feature = "neon_intrinsics", since = "1.59.0")
29169)]
29170#[cfg_attr(
29171 target_arch = "arm",
29172 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29173)]
29174pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
29175 vmlaq_s16(a, b, vdupq_n_s16(c))
29176}
29177#[doc = "Vector multiply accumulate with scalar"]
29178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
29179#[inline]
29180#[target_feature(enable = "neon")]
29181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29182#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29183#[cfg_attr(
29184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29185 assert_instr(mla)
29186)]
29187#[cfg_attr(
29188 not(target_arch = "arm"),
29189 stable(feature = "neon_intrinsics", since = "1.59.0")
29190)]
29191#[cfg_attr(
29192 target_arch = "arm",
29193 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29194)]
29195pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
29196 vmla_u16(a, b, vdup_n_u16(c))
29197}
29198#[doc = "Vector multiply accumulate with scalar"]
29199#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
29200#[inline]
29201#[target_feature(enable = "neon")]
29202#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29203#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29204#[cfg_attr(
29205 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29206 assert_instr(mla)
29207)]
29208#[cfg_attr(
29209 not(target_arch = "arm"),
29210 stable(feature = "neon_intrinsics", since = "1.59.0")
29211)]
29212#[cfg_attr(
29213 target_arch = "arm",
29214 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29215)]
29216pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
29217 vmlaq_u16(a, b, vdupq_n_u16(c))
29218}
29219#[doc = "Vector multiply accumulate with scalar"]
29220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
29221#[inline]
29222#[target_feature(enable = "neon")]
29223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29225#[cfg_attr(
29226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29227 assert_instr(mla)
29228)]
29229#[cfg_attr(
29230 not(target_arch = "arm"),
29231 stable(feature = "neon_intrinsics", since = "1.59.0")
29232)]
29233#[cfg_attr(
29234 target_arch = "arm",
29235 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29236)]
29237pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
29238 vmla_s32(a, b, vdup_n_s32(c))
29239}
29240#[doc = "Vector multiply accumulate with scalar"]
29241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
29242#[inline]
29243#[target_feature(enable = "neon")]
29244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29245#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29246#[cfg_attr(
29247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29248 assert_instr(mla)
29249)]
29250#[cfg_attr(
29251 not(target_arch = "arm"),
29252 stable(feature = "neon_intrinsics", since = "1.59.0")
29253)]
29254#[cfg_attr(
29255 target_arch = "arm",
29256 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29257)]
29258pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
29259 vmlaq_s32(a, b, vdupq_n_s32(c))
29260}
29261#[doc = "Vector multiply accumulate with scalar"]
29262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
29263#[inline]
29264#[target_feature(enable = "neon")]
29265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29266#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29267#[cfg_attr(
29268 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29269 assert_instr(mla)
29270)]
29271#[cfg_attr(
29272 not(target_arch = "arm"),
29273 stable(feature = "neon_intrinsics", since = "1.59.0")
29274)]
29275#[cfg_attr(
29276 target_arch = "arm",
29277 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29278)]
29279pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
29280 vmla_u32(a, b, vdup_n_u32(c))
29281}
29282#[doc = "Vector multiply accumulate with scalar"]
29283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
29284#[inline]
29285#[target_feature(enable = "neon")]
29286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29287#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29288#[cfg_attr(
29289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29290 assert_instr(mla)
29291)]
29292#[cfg_attr(
29293 not(target_arch = "arm"),
29294 stable(feature = "neon_intrinsics", since = "1.59.0")
29295)]
29296#[cfg_attr(
29297 target_arch = "arm",
29298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29299)]
29300pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
29301 vmlaq_u32(a, b, vdupq_n_u32(c))
29302}
29303#[doc = "Multiply-add to accumulator"]
29304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
29305#[inline]
29306#[target_feature(enable = "neon")]
29307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29308#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29309#[cfg_attr(
29310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29311 assert_instr(mla)
29312)]
29313#[cfg_attr(
29314 not(target_arch = "arm"),
29315 stable(feature = "neon_intrinsics", since = "1.59.0")
29316)]
29317#[cfg_attr(
29318 target_arch = "arm",
29319 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29320)]
29321pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
29322 unsafe { simd_add(a, simd_mul(b, c)) }
29323}
29324#[doc = "Multiply-add to accumulator"]
29325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
29326#[inline]
29327#[target_feature(enable = "neon")]
29328#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29329#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29330#[cfg_attr(
29331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29332 assert_instr(mla)
29333)]
29334#[cfg_attr(
29335 not(target_arch = "arm"),
29336 stable(feature = "neon_intrinsics", since = "1.59.0")
29337)]
29338#[cfg_attr(
29339 target_arch = "arm",
29340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29341)]
29342pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
29343 unsafe { simd_add(a, simd_mul(b, c)) }
29344}
29345#[doc = "Multiply-add to accumulator"]
29346#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
29347#[inline]
29348#[target_feature(enable = "neon")]
29349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29350#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29351#[cfg_attr(
29352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29353 assert_instr(mla)
29354)]
29355#[cfg_attr(
29356 not(target_arch = "arm"),
29357 stable(feature = "neon_intrinsics", since = "1.59.0")
29358)]
29359#[cfg_attr(
29360 target_arch = "arm",
29361 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29362)]
29363pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
29364 unsafe { simd_add(a, simd_mul(b, c)) }
29365}
29366#[doc = "Multiply-add to accumulator"]
29367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
29368#[inline]
29369#[target_feature(enable = "neon")]
29370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29371#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29372#[cfg_attr(
29373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29374 assert_instr(mla)
29375)]
29376#[cfg_attr(
29377 not(target_arch = "arm"),
29378 stable(feature = "neon_intrinsics", since = "1.59.0")
29379)]
29380#[cfg_attr(
29381 target_arch = "arm",
29382 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29383)]
29384pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
29385 unsafe { simd_add(a, simd_mul(b, c)) }
29386}
29387#[doc = "Multiply-add to accumulator"]
29388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
29389#[inline]
29390#[target_feature(enable = "neon")]
29391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29392#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29393#[cfg_attr(
29394 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29395 assert_instr(mla)
29396)]
29397#[cfg_attr(
29398 not(target_arch = "arm"),
29399 stable(feature = "neon_intrinsics", since = "1.59.0")
29400)]
29401#[cfg_attr(
29402 target_arch = "arm",
29403 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29404)]
29405pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
29406 unsafe { simd_add(a, simd_mul(b, c)) }
29407}
29408#[doc = "Multiply-add to accumulator"]
29409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
29410#[inline]
29411#[target_feature(enable = "neon")]
29412#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29413#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29414#[cfg_attr(
29415 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29416 assert_instr(mla)
29417)]
29418#[cfg_attr(
29419 not(target_arch = "arm"),
29420 stable(feature = "neon_intrinsics", since = "1.59.0")
29421)]
29422#[cfg_attr(
29423 target_arch = "arm",
29424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29425)]
29426pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
29427 unsafe { simd_add(a, simd_mul(b, c)) }
29428}
29429#[doc = "Multiply-add to accumulator"]
29430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
29431#[inline]
29432#[target_feature(enable = "neon")]
29433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29434#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29435#[cfg_attr(
29436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29437 assert_instr(mla)
29438)]
29439#[cfg_attr(
29440 not(target_arch = "arm"),
29441 stable(feature = "neon_intrinsics", since = "1.59.0")
29442)]
29443#[cfg_attr(
29444 target_arch = "arm",
29445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29446)]
29447pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
29448 unsafe { simd_add(a, simd_mul(b, c)) }
29449}
29450#[doc = "Multiply-add to accumulator"]
29451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
29452#[inline]
29453#[target_feature(enable = "neon")]
29454#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29455#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
29456#[cfg_attr(
29457 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29458 assert_instr(mla)
29459)]
29460#[cfg_attr(
29461 not(target_arch = "arm"),
29462 stable(feature = "neon_intrinsics", since = "1.59.0")
29463)]
29464#[cfg_attr(
29465 target_arch = "arm",
29466 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29467)]
29468pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
29469 unsafe { simd_add(a, simd_mul(b, c)) }
29470}
29471#[doc = "Multiply-add to accumulator"]
29472#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
29473#[inline]
29474#[target_feature(enable = "neon")]
29475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29476#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29477#[cfg_attr(
29478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29479 assert_instr(mla)
29480)]
29481#[cfg_attr(
29482 not(target_arch = "arm"),
29483 stable(feature = "neon_intrinsics", since = "1.59.0")
29484)]
29485#[cfg_attr(
29486 target_arch = "arm",
29487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29488)]
29489pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
29490 unsafe { simd_add(a, simd_mul(b, c)) }
29491}
29492#[doc = "Multiply-add to accumulator"]
29493#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
29494#[inline]
29495#[target_feature(enable = "neon")]
29496#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29497#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
29498#[cfg_attr(
29499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29500 assert_instr(mla)
29501)]
29502#[cfg_attr(
29503 not(target_arch = "arm"),
29504 stable(feature = "neon_intrinsics", since = "1.59.0")
29505)]
29506#[cfg_attr(
29507 target_arch = "arm",
29508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29509)]
29510pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
29511 unsafe { simd_add(a, simd_mul(b, c)) }
29512}
29513#[doc = "Multiply-add to accumulator"]
29514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
29515#[inline]
29516#[target_feature(enable = "neon")]
29517#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29518#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29519#[cfg_attr(
29520 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29521 assert_instr(mla)
29522)]
29523#[cfg_attr(
29524 not(target_arch = "arm"),
29525 stable(feature = "neon_intrinsics", since = "1.59.0")
29526)]
29527#[cfg_attr(
29528 target_arch = "arm",
29529 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29530)]
29531pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
29532 unsafe { simd_add(a, simd_mul(b, c)) }
29533}
29534#[doc = "Multiply-add to accumulator"]
29535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
29536#[inline]
29537#[target_feature(enable = "neon")]
29538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
29540#[cfg_attr(
29541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29542 assert_instr(mla)
29543)]
29544#[cfg_attr(
29545 not(target_arch = "arm"),
29546 stable(feature = "neon_intrinsics", since = "1.59.0")
29547)]
29548#[cfg_attr(
29549 target_arch = "arm",
29550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29551)]
29552pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
29553 unsafe { simd_add(a, simd_mul(b, c)) }
29554}
29555#[doc = "Vector widening multiply accumulate with scalar"]
29556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
29557#[inline]
29558#[target_feature(enable = "neon")]
29559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29560#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29561#[cfg_attr(
29562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29563 assert_instr(smlal, LANE = 1)
29564)]
29565#[rustc_legacy_const_generics(3)]
29566#[cfg_attr(
29567 not(target_arch = "arm"),
29568 stable(feature = "neon_intrinsics", since = "1.59.0")
29569)]
29570#[cfg_attr(
29571 target_arch = "arm",
29572 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29573)]
29574pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
29575 static_assert_uimm_bits!(LANE, 2);
29576 unsafe {
29577 vmlal_s16(
29578 a,
29579 b,
29580 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29581 )
29582 }
29583}
29584#[doc = "Vector widening multiply accumulate with scalar"]
29585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
29586#[inline]
29587#[target_feature(enable = "neon")]
29588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29589#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
29590#[cfg_attr(
29591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29592 assert_instr(smlal, LANE = 1)
29593)]
29594#[rustc_legacy_const_generics(3)]
29595#[cfg_attr(
29596 not(target_arch = "arm"),
29597 stable(feature = "neon_intrinsics", since = "1.59.0")
29598)]
29599#[cfg_attr(
29600 target_arch = "arm",
29601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29602)]
29603pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
29604 static_assert_uimm_bits!(LANE, 3);
29605 unsafe {
29606 vmlal_s16(
29607 a,
29608 b,
29609 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29610 )
29611 }
29612}
29613#[doc = "Vector widening multiply accumulate with scalar"]
29614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
29615#[inline]
29616#[target_feature(enable = "neon")]
29617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29618#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29619#[cfg_attr(
29620 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29621 assert_instr(smlal, LANE = 1)
29622)]
29623#[rustc_legacy_const_generics(3)]
29624#[cfg_attr(
29625 not(target_arch = "arm"),
29626 stable(feature = "neon_intrinsics", since = "1.59.0")
29627)]
29628#[cfg_attr(
29629 target_arch = "arm",
29630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29631)]
29632pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
29633 static_assert_uimm_bits!(LANE, 1);
29634 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29635}
29636#[doc = "Vector widening multiply accumulate with scalar"]
29637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
29638#[inline]
29639#[target_feature(enable = "neon")]
29640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29641#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
29642#[cfg_attr(
29643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29644 assert_instr(smlal, LANE = 1)
29645)]
29646#[rustc_legacy_const_generics(3)]
29647#[cfg_attr(
29648 not(target_arch = "arm"),
29649 stable(feature = "neon_intrinsics", since = "1.59.0")
29650)]
29651#[cfg_attr(
29652 target_arch = "arm",
29653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29654)]
29655pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
29656 static_assert_uimm_bits!(LANE, 2);
29657 unsafe { vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29658}
29659#[doc = "Vector widening multiply accumulate with scalar"]
29660#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
29661#[inline]
29662#[target_feature(enable = "neon")]
29663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29664#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29665#[cfg_attr(
29666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29667 assert_instr(umlal, LANE = 1)
29668)]
29669#[rustc_legacy_const_generics(3)]
29670#[cfg_attr(
29671 not(target_arch = "arm"),
29672 stable(feature = "neon_intrinsics", since = "1.59.0")
29673)]
29674#[cfg_attr(
29675 target_arch = "arm",
29676 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29677)]
29678pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
29679 static_assert_uimm_bits!(LANE, 2);
29680 unsafe {
29681 vmlal_u16(
29682 a,
29683 b,
29684 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29685 )
29686 }
29687}
29688#[doc = "Vector widening multiply accumulate with scalar"]
29689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
29690#[inline]
29691#[target_feature(enable = "neon")]
29692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29693#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
29694#[cfg_attr(
29695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29696 assert_instr(umlal, LANE = 1)
29697)]
29698#[rustc_legacy_const_generics(3)]
29699#[cfg_attr(
29700 not(target_arch = "arm"),
29701 stable(feature = "neon_intrinsics", since = "1.59.0")
29702)]
29703#[cfg_attr(
29704 target_arch = "arm",
29705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29706)]
29707pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
29708 static_assert_uimm_bits!(LANE, 3);
29709 unsafe {
29710 vmlal_u16(
29711 a,
29712 b,
29713 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
29714 )
29715 }
29716}
29717#[doc = "Vector widening multiply accumulate with scalar"]
29718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
29719#[inline]
29720#[target_feature(enable = "neon")]
29721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29722#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
29723#[cfg_attr(
29724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29725 assert_instr(umlal, LANE = 1)
29726)]
29727#[rustc_legacy_const_generics(3)]
29728#[cfg_attr(
29729 not(target_arch = "arm"),
29730 stable(feature = "neon_intrinsics", since = "1.59.0")
29731)]
29732#[cfg_attr(
29733 target_arch = "arm",
29734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29735)]
29736pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
29737 static_assert_uimm_bits!(LANE, 1);
29738 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29739}
29740#[doc = "Vector widening multiply accumulate with scalar"]
29741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
29742#[inline]
29743#[target_feature(enable = "neon")]
29744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
29746#[cfg_attr(
29747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29748 assert_instr(umlal, LANE = 1)
29749)]
29750#[rustc_legacy_const_generics(3)]
29751#[cfg_attr(
29752 not(target_arch = "arm"),
29753 stable(feature = "neon_intrinsics", since = "1.59.0")
29754)]
29755#[cfg_attr(
29756 target_arch = "arm",
29757 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29758)]
29759pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
29760 static_assert_uimm_bits!(LANE, 2);
29761 unsafe { vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
29762}
29763#[doc = "Vector widening multiply accumulate with scalar"]
29764#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
29765#[inline]
29766#[target_feature(enable = "neon")]
29767#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29768#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
29769#[cfg_attr(
29770 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29771 assert_instr(smlal)
29772)]
29773#[cfg_attr(
29774 not(target_arch = "arm"),
29775 stable(feature = "neon_intrinsics", since = "1.59.0")
29776)]
29777#[cfg_attr(
29778 target_arch = "arm",
29779 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29780)]
29781pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
29782 vmlal_s16(a, b, vdup_n_s16(c))
29783}
29784#[doc = "Vector widening multiply accumulate with scalar"]
29785#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
29786#[inline]
29787#[target_feature(enable = "neon")]
29788#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29789#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
29790#[cfg_attr(
29791 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29792 assert_instr(smlal)
29793)]
29794#[cfg_attr(
29795 not(target_arch = "arm"),
29796 stable(feature = "neon_intrinsics", since = "1.59.0")
29797)]
29798#[cfg_attr(
29799 target_arch = "arm",
29800 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29801)]
29802pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
29803 vmlal_s32(a, b, vdup_n_s32(c))
29804}
29805#[doc = "Vector widening multiply accumulate with scalar"]
29806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
29807#[inline]
29808#[target_feature(enable = "neon")]
29809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29810#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
29811#[cfg_attr(
29812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29813 assert_instr(umlal)
29814)]
29815#[cfg_attr(
29816 not(target_arch = "arm"),
29817 stable(feature = "neon_intrinsics", since = "1.59.0")
29818)]
29819#[cfg_attr(
29820 target_arch = "arm",
29821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29822)]
29823pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
29824 vmlal_u16(a, b, vdup_n_u16(c))
29825}
29826#[doc = "Vector widening multiply accumulate with scalar"]
29827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
29828#[inline]
29829#[target_feature(enable = "neon")]
29830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29831#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
29832#[cfg_attr(
29833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29834 assert_instr(umlal)
29835)]
29836#[cfg_attr(
29837 not(target_arch = "arm"),
29838 stable(feature = "neon_intrinsics", since = "1.59.0")
29839)]
29840#[cfg_attr(
29841 target_arch = "arm",
29842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29843)]
29844pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
29845 vmlal_u32(a, b, vdup_n_u32(c))
29846}
29847#[doc = "Signed multiply-add long"]
29848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
29849#[inline]
29850#[target_feature(enable = "neon")]
29851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
29853#[cfg_attr(
29854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29855 assert_instr(smlal)
29856)]
29857#[cfg_attr(
29858 not(target_arch = "arm"),
29859 stable(feature = "neon_intrinsics", since = "1.59.0")
29860)]
29861#[cfg_attr(
29862 target_arch = "arm",
29863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29864)]
29865pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
29866 unsafe { simd_add(a, vmull_s8(b, c)) }
29867}
29868#[doc = "Signed multiply-add long"]
29869#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
29870#[inline]
29871#[target_feature(enable = "neon")]
29872#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29873#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
29874#[cfg_attr(
29875 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29876 assert_instr(smlal)
29877)]
29878#[cfg_attr(
29879 not(target_arch = "arm"),
29880 stable(feature = "neon_intrinsics", since = "1.59.0")
29881)]
29882#[cfg_attr(
29883 target_arch = "arm",
29884 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29885)]
29886pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
29887 unsafe { simd_add(a, vmull_s16(b, c)) }
29888}
29889#[doc = "Signed multiply-add long"]
29890#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
29891#[inline]
29892#[target_feature(enable = "neon")]
29893#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29894#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
29895#[cfg_attr(
29896 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29897 assert_instr(smlal)
29898)]
29899#[cfg_attr(
29900 not(target_arch = "arm"),
29901 stable(feature = "neon_intrinsics", since = "1.59.0")
29902)]
29903#[cfg_attr(
29904 target_arch = "arm",
29905 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29906)]
29907pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
29908 unsafe { simd_add(a, vmull_s32(b, c)) }
29909}
29910#[doc = "Unsigned multiply-add long"]
29911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
29912#[inline]
29913#[target_feature(enable = "neon")]
29914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29915#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
29916#[cfg_attr(
29917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29918 assert_instr(umlal)
29919)]
29920#[cfg_attr(
29921 not(target_arch = "arm"),
29922 stable(feature = "neon_intrinsics", since = "1.59.0")
29923)]
29924#[cfg_attr(
29925 target_arch = "arm",
29926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29927)]
29928pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
29929 unsafe { simd_add(a, vmull_u8(b, c)) }
29930}
29931#[doc = "Unsigned multiply-add long"]
29932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
29933#[inline]
29934#[target_feature(enable = "neon")]
29935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
29937#[cfg_attr(
29938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29939 assert_instr(umlal)
29940)]
29941#[cfg_attr(
29942 not(target_arch = "arm"),
29943 stable(feature = "neon_intrinsics", since = "1.59.0")
29944)]
29945#[cfg_attr(
29946 target_arch = "arm",
29947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29948)]
29949pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
29950 unsafe { simd_add(a, vmull_u16(b, c)) }
29951}
29952#[doc = "Unsigned multiply-add long"]
29953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
29954#[inline]
29955#[target_feature(enable = "neon")]
29956#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29957#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
29958#[cfg_attr(
29959 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29960 assert_instr(umlal)
29961)]
29962#[cfg_attr(
29963 not(target_arch = "arm"),
29964 stable(feature = "neon_intrinsics", since = "1.59.0")
29965)]
29966#[cfg_attr(
29967 target_arch = "arm",
29968 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29969)]
29970pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
29971 unsafe { simd_add(a, vmull_u32(b, c)) }
29972}
29973#[doc = "Floating-point multiply-subtract from accumulator"]
29974#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
29975#[inline]
29976#[target_feature(enable = "neon")]
29977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29978#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
29979#[cfg_attr(
29980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
29981 assert_instr(fmul)
29982)]
29983#[cfg_attr(
29984 not(target_arch = "arm"),
29985 stable(feature = "neon_intrinsics", since = "1.59.0")
29986)]
29987#[cfg_attr(
29988 target_arch = "arm",
29989 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
29990)]
29991pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
29992 unsafe { simd_sub(a, simd_mul(b, c)) }
29993}
29994#[doc = "Floating-point multiply-subtract from accumulator"]
29995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
29996#[inline]
29997#[target_feature(enable = "neon")]
29998#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
29999#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30000#[cfg_attr(
30001 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30002 assert_instr(fmul)
30003)]
30004#[cfg_attr(
30005 not(target_arch = "arm"),
30006 stable(feature = "neon_intrinsics", since = "1.59.0")
30007)]
30008#[cfg_attr(
30009 target_arch = "arm",
30010 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30011)]
30012pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
30013 unsafe { simd_sub(a, simd_mul(b, c)) }
30014}
30015#[doc = "Vector multiply subtract with scalar"]
30016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
30017#[inline]
30018#[target_feature(enable = "neon")]
30019#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30020#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30021#[cfg_attr(
30022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30023 assert_instr(fmul, LANE = 1)
30024)]
30025#[rustc_legacy_const_generics(3)]
30026#[cfg_attr(
30027 not(target_arch = "arm"),
30028 stable(feature = "neon_intrinsics", since = "1.59.0")
30029)]
30030#[cfg_attr(
30031 target_arch = "arm",
30032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30033)]
30034pub fn vmls_lane_f32<const LANE: i32>(
30035 a: float32x2_t,
30036 b: float32x2_t,
30037 c: float32x2_t,
30038) -> float32x2_t {
30039 static_assert_uimm_bits!(LANE, 1);
30040 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30041}
30042#[doc = "Vector multiply subtract with scalar"]
30043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
30044#[inline]
30045#[target_feature(enable = "neon")]
30046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30047#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30048#[cfg_attr(
30049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30050 assert_instr(fmul, LANE = 1)
30051)]
30052#[rustc_legacy_const_generics(3)]
30053#[cfg_attr(
30054 not(target_arch = "arm"),
30055 stable(feature = "neon_intrinsics", since = "1.59.0")
30056)]
30057#[cfg_attr(
30058 target_arch = "arm",
30059 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30060)]
30061pub fn vmls_laneq_f32<const LANE: i32>(
30062 a: float32x2_t,
30063 b: float32x2_t,
30064 c: float32x4_t,
30065) -> float32x2_t {
30066 static_assert_uimm_bits!(LANE, 2);
30067 unsafe { vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30068}
30069#[doc = "Vector multiply subtract with scalar"]
30070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
30071#[inline]
30072#[target_feature(enable = "neon")]
30073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30074#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30075#[cfg_attr(
30076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30077 assert_instr(fmul, LANE = 1)
30078)]
30079#[rustc_legacy_const_generics(3)]
30080#[cfg_attr(
30081 not(target_arch = "arm"),
30082 stable(feature = "neon_intrinsics", since = "1.59.0")
30083)]
30084#[cfg_attr(
30085 target_arch = "arm",
30086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30087)]
30088pub fn vmlsq_lane_f32<const LANE: i32>(
30089 a: float32x4_t,
30090 b: float32x4_t,
30091 c: float32x2_t,
30092) -> float32x4_t {
30093 static_assert_uimm_bits!(LANE, 1);
30094 unsafe {
30095 vmlsq_f32(
30096 a,
30097 b,
30098 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30099 )
30100 }
30101}
30102#[doc = "Vector multiply subtract with scalar"]
30103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
30104#[inline]
30105#[target_feature(enable = "neon")]
30106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30107#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
30108#[cfg_attr(
30109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30110 assert_instr(fmul, LANE = 1)
30111)]
30112#[rustc_legacy_const_generics(3)]
30113#[cfg_attr(
30114 not(target_arch = "arm"),
30115 stable(feature = "neon_intrinsics", since = "1.59.0")
30116)]
30117#[cfg_attr(
30118 target_arch = "arm",
30119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30120)]
30121pub fn vmlsq_laneq_f32<const LANE: i32>(
30122 a: float32x4_t,
30123 b: float32x4_t,
30124 c: float32x4_t,
30125) -> float32x4_t {
30126 static_assert_uimm_bits!(LANE, 2);
30127 unsafe {
30128 vmlsq_f32(
30129 a,
30130 b,
30131 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30132 )
30133 }
30134}
30135#[doc = "Vector multiply subtract with scalar"]
30136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
30137#[inline]
30138#[target_feature(enable = "neon")]
30139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30140#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30141#[cfg_attr(
30142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30143 assert_instr(mls, LANE = 1)
30144)]
30145#[rustc_legacy_const_generics(3)]
30146#[cfg_attr(
30147 not(target_arch = "arm"),
30148 stable(feature = "neon_intrinsics", since = "1.59.0")
30149)]
30150#[cfg_attr(
30151 target_arch = "arm",
30152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30153)]
30154pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
30155 static_assert_uimm_bits!(LANE, 2);
30156 unsafe {
30157 vmls_s16(
30158 a,
30159 b,
30160 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30161 )
30162 }
30163}
30164#[doc = "Vector multiply subtract with scalar"]
30165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
30166#[inline]
30167#[target_feature(enable = "neon")]
30168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30169#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30170#[cfg_attr(
30171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30172 assert_instr(mls, LANE = 1)
30173)]
30174#[rustc_legacy_const_generics(3)]
30175#[cfg_attr(
30176 not(target_arch = "arm"),
30177 stable(feature = "neon_intrinsics", since = "1.59.0")
30178)]
30179#[cfg_attr(
30180 target_arch = "arm",
30181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30182)]
30183pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
30184 static_assert_uimm_bits!(LANE, 2);
30185 unsafe {
30186 vmls_u16(
30187 a,
30188 b,
30189 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30190 )
30191 }
30192}
30193#[doc = "Vector multiply subtract with scalar"]
30194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
30195#[inline]
30196#[target_feature(enable = "neon")]
30197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30199#[cfg_attr(
30200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30201 assert_instr(mls, LANE = 1)
30202)]
30203#[rustc_legacy_const_generics(3)]
30204#[cfg_attr(
30205 not(target_arch = "arm"),
30206 stable(feature = "neon_intrinsics", since = "1.59.0")
30207)]
30208#[cfg_attr(
30209 target_arch = "arm",
30210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30211)]
30212pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t {
30213 static_assert_uimm_bits!(LANE, 3);
30214 unsafe {
30215 vmls_s16(
30216 a,
30217 b,
30218 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30219 )
30220 }
30221}
30222#[doc = "Vector multiply subtract with scalar"]
30223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
30224#[inline]
30225#[target_feature(enable = "neon")]
30226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30228#[cfg_attr(
30229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30230 assert_instr(mls, LANE = 1)
30231)]
30232#[rustc_legacy_const_generics(3)]
30233#[cfg_attr(
30234 not(target_arch = "arm"),
30235 stable(feature = "neon_intrinsics", since = "1.59.0")
30236)]
30237#[cfg_attr(
30238 target_arch = "arm",
30239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30240)]
30241pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t {
30242 static_assert_uimm_bits!(LANE, 3);
30243 unsafe {
30244 vmls_u16(
30245 a,
30246 b,
30247 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30248 )
30249 }
30250}
30251#[doc = "Vector multiply subtract with scalar"]
30252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
30253#[inline]
30254#[target_feature(enable = "neon")]
30255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30257#[cfg_attr(
30258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30259 assert_instr(mls, LANE = 1)
30260)]
30261#[rustc_legacy_const_generics(3)]
30262#[cfg_attr(
30263 not(target_arch = "arm"),
30264 stable(feature = "neon_intrinsics", since = "1.59.0")
30265)]
30266#[cfg_attr(
30267 target_arch = "arm",
30268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30269)]
30270pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t {
30271 static_assert_uimm_bits!(LANE, 2);
30272 unsafe {
30273 vmlsq_s16(
30274 a,
30275 b,
30276 simd_shuffle!(
30277 c,
30278 c,
30279 [
30280 LANE as u32,
30281 LANE as u32,
30282 LANE as u32,
30283 LANE as u32,
30284 LANE as u32,
30285 LANE as u32,
30286 LANE as u32,
30287 LANE as u32
30288 ]
30289 ),
30290 )
30291 }
30292}
30293#[doc = "Vector multiply subtract with scalar"]
30294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
30295#[inline]
30296#[target_feature(enable = "neon")]
30297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30298#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30299#[cfg_attr(
30300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30301 assert_instr(mls, LANE = 1)
30302)]
30303#[rustc_legacy_const_generics(3)]
30304#[cfg_attr(
30305 not(target_arch = "arm"),
30306 stable(feature = "neon_intrinsics", since = "1.59.0")
30307)]
30308#[cfg_attr(
30309 target_arch = "arm",
30310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30311)]
30312pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
30313 static_assert_uimm_bits!(LANE, 2);
30314 unsafe {
30315 vmlsq_u16(
30316 a,
30317 b,
30318 simd_shuffle!(
30319 c,
30320 c,
30321 [
30322 LANE as u32,
30323 LANE as u32,
30324 LANE as u32,
30325 LANE as u32,
30326 LANE as u32,
30327 LANE as u32,
30328 LANE as u32,
30329 LANE as u32
30330 ]
30331 ),
30332 )
30333 }
30334}
30335#[doc = "Vector multiply subtract with scalar"]
30336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
30337#[inline]
30338#[target_feature(enable = "neon")]
30339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30341#[cfg_attr(
30342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30343 assert_instr(mls, LANE = 1)
30344)]
30345#[rustc_legacy_const_generics(3)]
30346#[cfg_attr(
30347 not(target_arch = "arm"),
30348 stable(feature = "neon_intrinsics", since = "1.59.0")
30349)]
30350#[cfg_attr(
30351 target_arch = "arm",
30352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30353)]
30354pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
30355 static_assert_uimm_bits!(LANE, 3);
30356 unsafe {
30357 vmlsq_s16(
30358 a,
30359 b,
30360 simd_shuffle!(
30361 c,
30362 c,
30363 [
30364 LANE as u32,
30365 LANE as u32,
30366 LANE as u32,
30367 LANE as u32,
30368 LANE as u32,
30369 LANE as u32,
30370 LANE as u32,
30371 LANE as u32
30372 ]
30373 ),
30374 )
30375 }
30376}
30377#[doc = "Vector multiply subtract with scalar"]
30378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
30379#[inline]
30380#[target_feature(enable = "neon")]
30381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30382#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
30383#[cfg_attr(
30384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30385 assert_instr(mls, LANE = 1)
30386)]
30387#[rustc_legacy_const_generics(3)]
30388#[cfg_attr(
30389 not(target_arch = "arm"),
30390 stable(feature = "neon_intrinsics", since = "1.59.0")
30391)]
30392#[cfg_attr(
30393 target_arch = "arm",
30394 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30395)]
30396pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
30397 static_assert_uimm_bits!(LANE, 3);
30398 unsafe {
30399 vmlsq_u16(
30400 a,
30401 b,
30402 simd_shuffle!(
30403 c,
30404 c,
30405 [
30406 LANE as u32,
30407 LANE as u32,
30408 LANE as u32,
30409 LANE as u32,
30410 LANE as u32,
30411 LANE as u32,
30412 LANE as u32,
30413 LANE as u32
30414 ]
30415 ),
30416 )
30417 }
30418}
30419#[doc = "Vector multiply subtract with scalar"]
30420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
30421#[inline]
30422#[target_feature(enable = "neon")]
30423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30424#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30425#[cfg_attr(
30426 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30427 assert_instr(mls, LANE = 1)
30428)]
30429#[rustc_legacy_const_generics(3)]
30430#[cfg_attr(
30431 not(target_arch = "arm"),
30432 stable(feature = "neon_intrinsics", since = "1.59.0")
30433)]
30434#[cfg_attr(
30435 target_arch = "arm",
30436 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30437)]
30438pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
30439 static_assert_uimm_bits!(LANE, 1);
30440 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30441}
30442#[doc = "Vector multiply subtract with scalar"]
30443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
30444#[inline]
30445#[target_feature(enable = "neon")]
30446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30447#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30448#[cfg_attr(
30449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30450 assert_instr(mls, LANE = 1)
30451)]
30452#[rustc_legacy_const_generics(3)]
30453#[cfg_attr(
30454 not(target_arch = "arm"),
30455 stable(feature = "neon_intrinsics", since = "1.59.0")
30456)]
30457#[cfg_attr(
30458 target_arch = "arm",
30459 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30460)]
30461pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
30462 static_assert_uimm_bits!(LANE, 1);
30463 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30464}
30465#[doc = "Vector multiply subtract with scalar"]
30466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
30467#[inline]
30468#[target_feature(enable = "neon")]
30469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30470#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30471#[cfg_attr(
30472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30473 assert_instr(mls, LANE = 1)
30474)]
30475#[rustc_legacy_const_generics(3)]
30476#[cfg_attr(
30477 not(target_arch = "arm"),
30478 stable(feature = "neon_intrinsics", since = "1.59.0")
30479)]
30480#[cfg_attr(
30481 target_arch = "arm",
30482 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30483)]
30484pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
30485 static_assert_uimm_bits!(LANE, 2);
30486 unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30487}
30488#[doc = "Vector multiply subtract with scalar"]
30489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
30490#[inline]
30491#[target_feature(enable = "neon")]
30492#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30493#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30494#[cfg_attr(
30495 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30496 assert_instr(mls, LANE = 1)
30497)]
30498#[rustc_legacy_const_generics(3)]
30499#[cfg_attr(
30500 not(target_arch = "arm"),
30501 stable(feature = "neon_intrinsics", since = "1.59.0")
30502)]
30503#[cfg_attr(
30504 target_arch = "arm",
30505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30506)]
30507pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
30508 static_assert_uimm_bits!(LANE, 2);
30509 unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
30510}
30511#[doc = "Vector multiply subtract with scalar"]
30512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
30513#[inline]
30514#[target_feature(enable = "neon")]
30515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30516#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30517#[cfg_attr(
30518 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30519 assert_instr(mls, LANE = 1)
30520)]
30521#[rustc_legacy_const_generics(3)]
30522#[cfg_attr(
30523 not(target_arch = "arm"),
30524 stable(feature = "neon_intrinsics", since = "1.59.0")
30525)]
30526#[cfg_attr(
30527 target_arch = "arm",
30528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30529)]
30530pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
30531 static_assert_uimm_bits!(LANE, 1);
30532 unsafe {
30533 vmlsq_s32(
30534 a,
30535 b,
30536 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30537 )
30538 }
30539}
30540#[doc = "Vector multiply subtract with scalar"]
30541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
30542#[inline]
30543#[target_feature(enable = "neon")]
30544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30545#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30546#[cfg_attr(
30547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30548 assert_instr(mls, LANE = 1)
30549)]
30550#[rustc_legacy_const_generics(3)]
30551#[cfg_attr(
30552 not(target_arch = "arm"),
30553 stable(feature = "neon_intrinsics", since = "1.59.0")
30554)]
30555#[cfg_attr(
30556 target_arch = "arm",
30557 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30558)]
30559pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
30560 static_assert_uimm_bits!(LANE, 1);
30561 unsafe {
30562 vmlsq_u32(
30563 a,
30564 b,
30565 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30566 )
30567 }
30568}
30569#[doc = "Vector multiply subtract with scalar"]
30570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
30571#[inline]
30572#[target_feature(enable = "neon")]
30573#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30574#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30575#[cfg_attr(
30576 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30577 assert_instr(mls, LANE = 1)
30578)]
30579#[rustc_legacy_const_generics(3)]
30580#[cfg_attr(
30581 not(target_arch = "arm"),
30582 stable(feature = "neon_intrinsics", since = "1.59.0")
30583)]
30584#[cfg_attr(
30585 target_arch = "arm",
30586 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30587)]
30588pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
30589 static_assert_uimm_bits!(LANE, 2);
30590 unsafe {
30591 vmlsq_s32(
30592 a,
30593 b,
30594 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30595 )
30596 }
30597}
30598#[doc = "Vector multiply subtract with scalar"]
30599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
30600#[inline]
30601#[target_feature(enable = "neon")]
30602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30603#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
30604#[cfg_attr(
30605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30606 assert_instr(mls, LANE = 1)
30607)]
30608#[rustc_legacy_const_generics(3)]
30609#[cfg_attr(
30610 not(target_arch = "arm"),
30611 stable(feature = "neon_intrinsics", since = "1.59.0")
30612)]
30613#[cfg_attr(
30614 target_arch = "arm",
30615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30616)]
30617pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
30618 static_assert_uimm_bits!(LANE, 2);
30619 unsafe {
30620 vmlsq_u32(
30621 a,
30622 b,
30623 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
30624 )
30625 }
30626}
30627#[doc = "Vector multiply subtract with scalar"]
30628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
30629#[inline]
30630#[target_feature(enable = "neon")]
30631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30632#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30633#[cfg_attr(
30634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30635 assert_instr(fmul)
30636)]
30637#[cfg_attr(
30638 not(target_arch = "arm"),
30639 stable(feature = "neon_intrinsics", since = "1.59.0")
30640)]
30641#[cfg_attr(
30642 target_arch = "arm",
30643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30644)]
30645pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
30646 vmls_f32(a, b, vdup_n_f32(c))
30647}
30648#[doc = "Vector multiply subtract with scalar"]
30649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
30650#[inline]
30651#[target_feature(enable = "neon")]
30652#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30653#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
30654#[cfg_attr(
30655 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30656 assert_instr(fmul)
30657)]
30658#[cfg_attr(
30659 not(target_arch = "arm"),
30660 stable(feature = "neon_intrinsics", since = "1.59.0")
30661)]
30662#[cfg_attr(
30663 target_arch = "arm",
30664 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30665)]
30666pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
30667 vmlsq_f32(a, b, vdupq_n_f32(c))
30668}
30669#[doc = "Vector multiply subtract with scalar"]
30670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
30671#[inline]
30672#[target_feature(enable = "neon")]
30673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30674#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30675#[cfg_attr(
30676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30677 assert_instr(mls)
30678)]
30679#[cfg_attr(
30680 not(target_arch = "arm"),
30681 stable(feature = "neon_intrinsics", since = "1.59.0")
30682)]
30683#[cfg_attr(
30684 target_arch = "arm",
30685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30686)]
30687pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
30688 vmls_s16(a, b, vdup_n_s16(c))
30689}
30690#[doc = "Vector multiply subtract with scalar"]
30691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
30692#[inline]
30693#[target_feature(enable = "neon")]
30694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30695#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30696#[cfg_attr(
30697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30698 assert_instr(mls)
30699)]
30700#[cfg_attr(
30701 not(target_arch = "arm"),
30702 stable(feature = "neon_intrinsics", since = "1.59.0")
30703)]
30704#[cfg_attr(
30705 target_arch = "arm",
30706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30707)]
30708pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
30709 vmlsq_s16(a, b, vdupq_n_s16(c))
30710}
30711#[doc = "Vector multiply subtract with scalar"]
30712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
30713#[inline]
30714#[target_feature(enable = "neon")]
30715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30716#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30717#[cfg_attr(
30718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30719 assert_instr(mls)
30720)]
30721#[cfg_attr(
30722 not(target_arch = "arm"),
30723 stable(feature = "neon_intrinsics", since = "1.59.0")
30724)]
30725#[cfg_attr(
30726 target_arch = "arm",
30727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30728)]
30729pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
30730 vmls_u16(a, b, vdup_n_u16(c))
30731}
30732#[doc = "Vector multiply subtract with scalar"]
30733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
30734#[inline]
30735#[target_feature(enable = "neon")]
30736#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30737#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30738#[cfg_attr(
30739 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30740 assert_instr(mls)
30741)]
30742#[cfg_attr(
30743 not(target_arch = "arm"),
30744 stable(feature = "neon_intrinsics", since = "1.59.0")
30745)]
30746#[cfg_attr(
30747 target_arch = "arm",
30748 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30749)]
30750pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
30751 vmlsq_u16(a, b, vdupq_n_u16(c))
30752}
30753#[doc = "Vector multiply subtract with scalar"]
30754#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
30755#[inline]
30756#[target_feature(enable = "neon")]
30757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30758#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30759#[cfg_attr(
30760 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30761 assert_instr(mls)
30762)]
30763#[cfg_attr(
30764 not(target_arch = "arm"),
30765 stable(feature = "neon_intrinsics", since = "1.59.0")
30766)]
30767#[cfg_attr(
30768 target_arch = "arm",
30769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30770)]
30771pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
30772 vmls_s32(a, b, vdup_n_s32(c))
30773}
30774#[doc = "Vector multiply subtract with scalar"]
30775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
30776#[inline]
30777#[target_feature(enable = "neon")]
30778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30780#[cfg_attr(
30781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30782 assert_instr(mls)
30783)]
30784#[cfg_attr(
30785 not(target_arch = "arm"),
30786 stable(feature = "neon_intrinsics", since = "1.59.0")
30787)]
30788#[cfg_attr(
30789 target_arch = "arm",
30790 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30791)]
30792pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
30793 vmlsq_s32(a, b, vdupq_n_s32(c))
30794}
30795#[doc = "Vector multiply subtract with scalar"]
30796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
30797#[inline]
30798#[target_feature(enable = "neon")]
30799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30800#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30801#[cfg_attr(
30802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30803 assert_instr(mls)
30804)]
30805#[cfg_attr(
30806 not(target_arch = "arm"),
30807 stable(feature = "neon_intrinsics", since = "1.59.0")
30808)]
30809#[cfg_attr(
30810 target_arch = "arm",
30811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30812)]
30813pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
30814 vmls_u32(a, b, vdup_n_u32(c))
30815}
30816#[doc = "Vector multiply subtract with scalar"]
30817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
30818#[inline]
30819#[target_feature(enable = "neon")]
30820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30821#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30822#[cfg_attr(
30823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30824 assert_instr(mls)
30825)]
30826#[cfg_attr(
30827 not(target_arch = "arm"),
30828 stable(feature = "neon_intrinsics", since = "1.59.0")
30829)]
30830#[cfg_attr(
30831 target_arch = "arm",
30832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30833)]
30834pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
30835 vmlsq_u32(a, b, vdupq_n_u32(c))
30836}
30837#[doc = "Multiply-subtract from accumulator"]
30838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
30839#[inline]
30840#[target_feature(enable = "neon")]
30841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30842#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
30843#[cfg_attr(
30844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30845 assert_instr(mls)
30846)]
30847#[cfg_attr(
30848 not(target_arch = "arm"),
30849 stable(feature = "neon_intrinsics", since = "1.59.0")
30850)]
30851#[cfg_attr(
30852 target_arch = "arm",
30853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30854)]
30855pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
30856 unsafe { simd_sub(a, simd_mul(b, c)) }
30857}
30858#[doc = "Multiply-subtract from accumulator"]
30859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
30860#[inline]
30861#[target_feature(enable = "neon")]
30862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30863#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
30864#[cfg_attr(
30865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30866 assert_instr(mls)
30867)]
30868#[cfg_attr(
30869 not(target_arch = "arm"),
30870 stable(feature = "neon_intrinsics", since = "1.59.0")
30871)]
30872#[cfg_attr(
30873 target_arch = "arm",
30874 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30875)]
30876pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
30877 unsafe { simd_sub(a, simd_mul(b, c)) }
30878}
30879#[doc = "Multiply-subtract from accumulator"]
30880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
30881#[inline]
30882#[target_feature(enable = "neon")]
30883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30885#[cfg_attr(
30886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30887 assert_instr(mls)
30888)]
30889#[cfg_attr(
30890 not(target_arch = "arm"),
30891 stable(feature = "neon_intrinsics", since = "1.59.0")
30892)]
30893#[cfg_attr(
30894 target_arch = "arm",
30895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30896)]
30897pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
30898 unsafe { simd_sub(a, simd_mul(b, c)) }
30899}
30900#[doc = "Multiply-subtract from accumulator"]
30901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
30902#[inline]
30903#[target_feature(enable = "neon")]
30904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30905#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
30906#[cfg_attr(
30907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30908 assert_instr(mls)
30909)]
30910#[cfg_attr(
30911 not(target_arch = "arm"),
30912 stable(feature = "neon_intrinsics", since = "1.59.0")
30913)]
30914#[cfg_attr(
30915 target_arch = "arm",
30916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30917)]
30918pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
30919 unsafe { simd_sub(a, simd_mul(b, c)) }
30920}
30921#[doc = "Multiply-subtract from accumulator"]
30922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
30923#[inline]
30924#[target_feature(enable = "neon")]
30925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30926#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30927#[cfg_attr(
30928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30929 assert_instr(mls)
30930)]
30931#[cfg_attr(
30932 not(target_arch = "arm"),
30933 stable(feature = "neon_intrinsics", since = "1.59.0")
30934)]
30935#[cfg_attr(
30936 target_arch = "arm",
30937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30938)]
30939pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
30940 unsafe { simd_sub(a, simd_mul(b, c)) }
30941}
30942#[doc = "Multiply-subtract from accumulator"]
30943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
30944#[inline]
30945#[target_feature(enable = "neon")]
30946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
30948#[cfg_attr(
30949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30950 assert_instr(mls)
30951)]
30952#[cfg_attr(
30953 not(target_arch = "arm"),
30954 stable(feature = "neon_intrinsics", since = "1.59.0")
30955)]
30956#[cfg_attr(
30957 target_arch = "arm",
30958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30959)]
30960pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
30961 unsafe { simd_sub(a, simd_mul(b, c)) }
30962}
30963#[doc = "Multiply-subtract from accumulator"]
30964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
30965#[inline]
30966#[target_feature(enable = "neon")]
30967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30968#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
30969#[cfg_attr(
30970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30971 assert_instr(mls)
30972)]
30973#[cfg_attr(
30974 not(target_arch = "arm"),
30975 stable(feature = "neon_intrinsics", since = "1.59.0")
30976)]
30977#[cfg_attr(
30978 target_arch = "arm",
30979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
30980)]
30981pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
30982 unsafe { simd_sub(a, simd_mul(b, c)) }
30983}
30984#[doc = "Multiply-subtract from accumulator"]
30985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
30986#[inline]
30987#[target_feature(enable = "neon")]
30988#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
30989#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
30990#[cfg_attr(
30991 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
30992 assert_instr(mls)
30993)]
30994#[cfg_attr(
30995 not(target_arch = "arm"),
30996 stable(feature = "neon_intrinsics", since = "1.59.0")
30997)]
30998#[cfg_attr(
30999 target_arch = "arm",
31000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31001)]
31002pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
31003 unsafe { simd_sub(a, simd_mul(b, c)) }
31004}
31005#[doc = "Multiply-subtract from accumulator"]
31006#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
31007#[inline]
31008#[target_feature(enable = "neon")]
31009#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31010#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31011#[cfg_attr(
31012 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31013 assert_instr(mls)
31014)]
31015#[cfg_attr(
31016 not(target_arch = "arm"),
31017 stable(feature = "neon_intrinsics", since = "1.59.0")
31018)]
31019#[cfg_attr(
31020 target_arch = "arm",
31021 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31022)]
31023pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
31024 unsafe { simd_sub(a, simd_mul(b, c)) }
31025}
31026#[doc = "Multiply-subtract from accumulator"]
31027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
31028#[inline]
31029#[target_feature(enable = "neon")]
31030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31031#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
31032#[cfg_attr(
31033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31034 assert_instr(mls)
31035)]
31036#[cfg_attr(
31037 not(target_arch = "arm"),
31038 stable(feature = "neon_intrinsics", since = "1.59.0")
31039)]
31040#[cfg_attr(
31041 target_arch = "arm",
31042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31043)]
31044pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
31045 unsafe { simd_sub(a, simd_mul(b, c)) }
31046}
31047#[doc = "Multiply-subtract from accumulator"]
31048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
31049#[inline]
31050#[target_feature(enable = "neon")]
31051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31052#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31053#[cfg_attr(
31054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31055 assert_instr(mls)
31056)]
31057#[cfg_attr(
31058 not(target_arch = "arm"),
31059 stable(feature = "neon_intrinsics", since = "1.59.0")
31060)]
31061#[cfg_attr(
31062 target_arch = "arm",
31063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31064)]
31065pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
31066 unsafe { simd_sub(a, simd_mul(b, c)) }
31067}
31068#[doc = "Multiply-subtract from accumulator"]
31069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
31070#[inline]
31071#[target_feature(enable = "neon")]
31072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31073#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
31074#[cfg_attr(
31075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31076 assert_instr(mls)
31077)]
31078#[cfg_attr(
31079 not(target_arch = "arm"),
31080 stable(feature = "neon_intrinsics", since = "1.59.0")
31081)]
31082#[cfg_attr(
31083 target_arch = "arm",
31084 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31085)]
31086pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
31087 unsafe { simd_sub(a, simd_mul(b, c)) }
31088}
31089#[doc = "Vector widening multiply subtract with scalar"]
31090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
31091#[inline]
31092#[target_feature(enable = "neon")]
31093#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31094#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31095#[cfg_attr(
31096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31097 assert_instr(smlsl, LANE = 1)
31098)]
31099#[rustc_legacy_const_generics(3)]
31100#[cfg_attr(
31101 not(target_arch = "arm"),
31102 stable(feature = "neon_intrinsics", since = "1.59.0")
31103)]
31104#[cfg_attr(
31105 target_arch = "arm",
31106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31107)]
31108pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31109 static_assert_uimm_bits!(LANE, 2);
31110 unsafe {
31111 vmlsl_s16(
31112 a,
31113 b,
31114 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31115 )
31116 }
31117}
31118#[doc = "Vector widening multiply subtract with scalar"]
31119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
31120#[inline]
31121#[target_feature(enable = "neon")]
31122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
31124#[cfg_attr(
31125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31126 assert_instr(smlsl, LANE = 1)
31127)]
31128#[rustc_legacy_const_generics(3)]
31129#[cfg_attr(
31130 not(target_arch = "arm"),
31131 stable(feature = "neon_intrinsics", since = "1.59.0")
31132)]
31133#[cfg_attr(
31134 target_arch = "arm",
31135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31136)]
31137pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t {
31138 static_assert_uimm_bits!(LANE, 3);
31139 unsafe {
31140 vmlsl_s16(
31141 a,
31142 b,
31143 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31144 )
31145 }
31146}
31147#[doc = "Vector widening multiply subtract with scalar"]
31148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
31149#[inline]
31150#[target_feature(enable = "neon")]
31151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31153#[cfg_attr(
31154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31155 assert_instr(smlsl, LANE = 1)
31156)]
31157#[rustc_legacy_const_generics(3)]
31158#[cfg_attr(
31159 not(target_arch = "arm"),
31160 stable(feature = "neon_intrinsics", since = "1.59.0")
31161)]
31162#[cfg_attr(
31163 target_arch = "arm",
31164 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31165)]
31166pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31167 static_assert_uimm_bits!(LANE, 1);
31168 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31169}
31170#[doc = "Vector widening multiply subtract with scalar"]
31171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
31172#[inline]
31173#[target_feature(enable = "neon")]
31174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31175#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
31176#[cfg_attr(
31177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31178 assert_instr(smlsl, LANE = 1)
31179)]
31180#[rustc_legacy_const_generics(3)]
31181#[cfg_attr(
31182 not(target_arch = "arm"),
31183 stable(feature = "neon_intrinsics", since = "1.59.0")
31184)]
31185#[cfg_attr(
31186 target_arch = "arm",
31187 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31188)]
31189pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t {
31190 static_assert_uimm_bits!(LANE, 2);
31191 unsafe { vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31192}
31193#[doc = "Vector widening multiply subtract with scalar"]
31194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
31195#[inline]
31196#[target_feature(enable = "neon")]
31197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31198#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31199#[cfg_attr(
31200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31201 assert_instr(umlsl, LANE = 1)
31202)]
31203#[rustc_legacy_const_generics(3)]
31204#[cfg_attr(
31205 not(target_arch = "arm"),
31206 stable(feature = "neon_intrinsics", since = "1.59.0")
31207)]
31208#[cfg_attr(
31209 target_arch = "arm",
31210 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31211)]
31212pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31213 static_assert_uimm_bits!(LANE, 2);
31214 unsafe {
31215 vmlsl_u16(
31216 a,
31217 b,
31218 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31219 )
31220 }
31221}
31222#[doc = "Vector widening multiply subtract with scalar"]
31223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
31224#[inline]
31225#[target_feature(enable = "neon")]
31226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31227#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
31228#[cfg_attr(
31229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31230 assert_instr(umlsl, LANE = 1)
31231)]
31232#[rustc_legacy_const_generics(3)]
31233#[cfg_attr(
31234 not(target_arch = "arm"),
31235 stable(feature = "neon_intrinsics", since = "1.59.0")
31236)]
31237#[cfg_attr(
31238 target_arch = "arm",
31239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31240)]
31241pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t {
31242 static_assert_uimm_bits!(LANE, 3);
31243 unsafe {
31244 vmlsl_u16(
31245 a,
31246 b,
31247 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
31248 )
31249 }
31250}
31251#[doc = "Vector widening multiply subtract with scalar"]
31252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
31253#[inline]
31254#[target_feature(enable = "neon")]
31255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31257#[cfg_attr(
31258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31259 assert_instr(umlsl, LANE = 1)
31260)]
31261#[rustc_legacy_const_generics(3)]
31262#[cfg_attr(
31263 not(target_arch = "arm"),
31264 stable(feature = "neon_intrinsics", since = "1.59.0")
31265)]
31266#[cfg_attr(
31267 target_arch = "arm",
31268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31269)]
31270pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31271 static_assert_uimm_bits!(LANE, 1);
31272 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31273}
31274#[doc = "Vector widening multiply subtract with scalar"]
31275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
31276#[inline]
31277#[target_feature(enable = "neon")]
31278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31279#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
31280#[cfg_attr(
31281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31282 assert_instr(umlsl, LANE = 1)
31283)]
31284#[rustc_legacy_const_generics(3)]
31285#[cfg_attr(
31286 not(target_arch = "arm"),
31287 stable(feature = "neon_intrinsics", since = "1.59.0")
31288)]
31289#[cfg_attr(
31290 target_arch = "arm",
31291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31292)]
31293pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t {
31294 static_assert_uimm_bits!(LANE, 2);
31295 unsafe { vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
31296}
31297#[doc = "Vector widening multiply subtract with scalar"]
31298#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
31299#[inline]
31300#[target_feature(enable = "neon")]
31301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31302#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31303#[cfg_attr(
31304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31305 assert_instr(smlsl)
31306)]
31307#[cfg_attr(
31308 not(target_arch = "arm"),
31309 stable(feature = "neon_intrinsics", since = "1.59.0")
31310)]
31311#[cfg_attr(
31312 target_arch = "arm",
31313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31314)]
31315pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
31316 vmlsl_s16(a, b, vdup_n_s16(c))
31317}
31318#[doc = "Vector widening multiply subtract with scalar"]
31319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
31320#[inline]
31321#[target_feature(enable = "neon")]
31322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31323#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31324#[cfg_attr(
31325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31326 assert_instr(smlsl)
31327)]
31328#[cfg_attr(
31329 not(target_arch = "arm"),
31330 stable(feature = "neon_intrinsics", since = "1.59.0")
31331)]
31332#[cfg_attr(
31333 target_arch = "arm",
31334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31335)]
31336pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
31337 vmlsl_s32(a, b, vdup_n_s32(c))
31338}
31339#[doc = "Vector widening multiply subtract with scalar"]
31340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
31341#[inline]
31342#[target_feature(enable = "neon")]
31343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31345#[cfg_attr(
31346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31347 assert_instr(umlsl)
31348)]
31349#[cfg_attr(
31350 not(target_arch = "arm"),
31351 stable(feature = "neon_intrinsics", since = "1.59.0")
31352)]
31353#[cfg_attr(
31354 target_arch = "arm",
31355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31356)]
31357pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
31358 vmlsl_u16(a, b, vdup_n_u16(c))
31359}
31360#[doc = "Vector widening multiply subtract with scalar"]
31361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
31362#[inline]
31363#[target_feature(enable = "neon")]
31364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31365#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31366#[cfg_attr(
31367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31368 assert_instr(umlsl)
31369)]
31370#[cfg_attr(
31371 not(target_arch = "arm"),
31372 stable(feature = "neon_intrinsics", since = "1.59.0")
31373)]
31374#[cfg_attr(
31375 target_arch = "arm",
31376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31377)]
31378pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
31379 vmlsl_u32(a, b, vdup_n_u32(c))
31380}
31381#[doc = "Signed multiply-subtract long"]
31382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
31383#[inline]
31384#[target_feature(enable = "neon")]
31385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31386#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
31387#[cfg_attr(
31388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31389 assert_instr(smlsl)
31390)]
31391#[cfg_attr(
31392 not(target_arch = "arm"),
31393 stable(feature = "neon_intrinsics", since = "1.59.0")
31394)]
31395#[cfg_attr(
31396 target_arch = "arm",
31397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31398)]
31399pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
31400 unsafe { simd_sub(a, vmull_s8(b, c)) }
31401}
31402#[doc = "Signed multiply-subtract long"]
31403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
31404#[inline]
31405#[target_feature(enable = "neon")]
31406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31407#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
31408#[cfg_attr(
31409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31410 assert_instr(smlsl)
31411)]
31412#[cfg_attr(
31413 not(target_arch = "arm"),
31414 stable(feature = "neon_intrinsics", since = "1.59.0")
31415)]
31416#[cfg_attr(
31417 target_arch = "arm",
31418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31419)]
31420pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
31421 unsafe { simd_sub(a, vmull_s16(b, c)) }
31422}
31423#[doc = "Signed multiply-subtract long"]
31424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
31425#[inline]
31426#[target_feature(enable = "neon")]
31427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
31429#[cfg_attr(
31430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31431 assert_instr(smlsl)
31432)]
31433#[cfg_attr(
31434 not(target_arch = "arm"),
31435 stable(feature = "neon_intrinsics", since = "1.59.0")
31436)]
31437#[cfg_attr(
31438 target_arch = "arm",
31439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31440)]
31441pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
31442 unsafe { simd_sub(a, vmull_s32(b, c)) }
31443}
31444#[doc = "Unsigned multiply-subtract long"]
31445#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
31446#[inline]
31447#[target_feature(enable = "neon")]
31448#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31449#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
31450#[cfg_attr(
31451 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31452 assert_instr(umlsl)
31453)]
31454#[cfg_attr(
31455 not(target_arch = "arm"),
31456 stable(feature = "neon_intrinsics", since = "1.59.0")
31457)]
31458#[cfg_attr(
31459 target_arch = "arm",
31460 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31461)]
31462pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
31463 unsafe { simd_sub(a, vmull_u8(b, c)) }
31464}
31465#[doc = "Unsigned multiply-subtract long"]
31466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
31467#[inline]
31468#[target_feature(enable = "neon")]
31469#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31470#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
31471#[cfg_attr(
31472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31473 assert_instr(umlsl)
31474)]
31475#[cfg_attr(
31476 not(target_arch = "arm"),
31477 stable(feature = "neon_intrinsics", since = "1.59.0")
31478)]
31479#[cfg_attr(
31480 target_arch = "arm",
31481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31482)]
31483pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
31484 unsafe { simd_sub(a, vmull_u16(b, c)) }
31485}
31486#[doc = "Unsigned multiply-subtract long"]
31487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
31488#[inline]
31489#[target_feature(enable = "neon")]
31490#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31491#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
31492#[cfg_attr(
31493 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31494 assert_instr(umlsl)
31495)]
31496#[cfg_attr(
31497 not(target_arch = "arm"),
31498 stable(feature = "neon_intrinsics", since = "1.59.0")
31499)]
31500#[cfg_attr(
31501 target_arch = "arm",
31502 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31503)]
31504pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
31505 unsafe { simd_sub(a, vmull_u32(b, c)) }
31506}
31507#[doc = "8-bit integer matrix multiply-accumulate"]
31508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
31509#[inline]
31510#[target_feature(enable = "neon,i8mm")]
31511#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31513#[cfg_attr(
31514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31515 assert_instr(smmla)
31516)]
31517#[cfg_attr(
31518 not(target_arch = "arm"),
31519 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31520)]
31521#[cfg_attr(
31522 target_arch = "arm",
31523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31524)]
31525pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
31526 unsafe extern "unadjusted" {
31527 #[cfg_attr(
31528 any(target_arch = "aarch64", target_arch = "arm64ec"),
31529 link_name = "llvm.aarch64.neon.smmla.v4i32.v16i8"
31530 )]
31531 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.smmla.v4i32.v16i8")]
31532 fn _vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t;
31533 }
31534 unsafe { _vmmlaq_s32(a, b, c) }
31535}
31536#[doc = "8-bit integer matrix multiply-accumulate"]
31537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
31538#[inline]
31539#[target_feature(enable = "neon,i8mm")]
31540#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
31541#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
31542#[cfg_attr(
31543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31544 assert_instr(ummla)
31545)]
31546#[cfg_attr(
31547 not(target_arch = "arm"),
31548 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
31549)]
31550#[cfg_attr(
31551 target_arch = "arm",
31552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31553)]
31554pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
31555 unsafe extern "unadjusted" {
31556 #[cfg_attr(
31557 any(target_arch = "aarch64", target_arch = "arm64ec"),
31558 link_name = "llvm.aarch64.neon.ummla.v4i32.v16i8"
31559 )]
31560 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.ummla.v4i32.v16i8")]
31561 fn _vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t;
31562 }
31563 unsafe { _vmmlaq_u32(a, b, c) }
31564}
31565#[doc = "Duplicate element to vector"]
31566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
31567#[inline]
31568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31569#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31570#[cfg_attr(
31571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31572 assert_instr(dup)
31573)]
31574#[target_feature(enable = "neon,fp16")]
31575#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31576pub fn vmov_n_f16(a: f16) -> float16x4_t {
31577 vdup_n_f16(a)
31578}
31579#[doc = "Duplicate element to vector"]
31580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
31581#[inline]
31582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31583#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31584#[cfg_attr(
31585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31586 assert_instr(dup)
31587)]
31588#[target_feature(enable = "neon,fp16")]
31589#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
31590pub fn vmovq_n_f16(a: f16) -> float16x8_t {
31591 vdupq_n_f16(a)
31592}
31593#[doc = "Duplicate vector element to vector or scalar"]
31594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
31595#[inline]
31596#[target_feature(enable = "neon")]
31597#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31598#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31599#[cfg_attr(
31600 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31601 assert_instr(dup)
31602)]
31603#[cfg_attr(
31604 not(target_arch = "arm"),
31605 stable(feature = "neon_intrinsics", since = "1.59.0")
31606)]
31607#[cfg_attr(
31608 target_arch = "arm",
31609 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31610)]
31611pub fn vmov_n_f32(value: f32) -> float32x2_t {
31612 vdup_n_f32(value)
31613}
31614#[doc = "Duplicate vector element to vector or scalar"]
31615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
31616#[inline]
31617#[target_feature(enable = "neon")]
31618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31619#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31620#[cfg_attr(
31621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31622 assert_instr(dup)
31623)]
31624#[cfg_attr(
31625 not(target_arch = "arm"),
31626 stable(feature = "neon_intrinsics", since = "1.59.0")
31627)]
31628#[cfg_attr(
31629 target_arch = "arm",
31630 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31631)]
31632pub fn vmov_n_p16(value: p16) -> poly16x4_t {
31633 vdup_n_p16(value)
31634}
31635#[doc = "Duplicate vector element to vector or scalar"]
31636#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
31637#[inline]
31638#[target_feature(enable = "neon")]
31639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31640#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31641#[cfg_attr(
31642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31643 assert_instr(dup)
31644)]
31645#[cfg_attr(
31646 not(target_arch = "arm"),
31647 stable(feature = "neon_intrinsics", since = "1.59.0")
31648)]
31649#[cfg_attr(
31650 target_arch = "arm",
31651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31652)]
31653pub fn vmov_n_p8(value: p8) -> poly8x8_t {
31654 vdup_n_p8(value)
31655}
31656#[doc = "Duplicate vector element to vector or scalar"]
31657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
31658#[inline]
31659#[target_feature(enable = "neon")]
31660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31661#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31662#[cfg_attr(
31663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31664 assert_instr(dup)
31665)]
31666#[cfg_attr(
31667 not(target_arch = "arm"),
31668 stable(feature = "neon_intrinsics", since = "1.59.0")
31669)]
31670#[cfg_attr(
31671 target_arch = "arm",
31672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31673)]
31674pub fn vmov_n_s16(value: i16) -> int16x4_t {
31675 vdup_n_s16(value)
31676}
31677#[doc = "Duplicate vector element to vector or scalar"]
31678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
31679#[inline]
31680#[target_feature(enable = "neon")]
31681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31683#[cfg_attr(
31684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31685 assert_instr(dup)
31686)]
31687#[cfg_attr(
31688 not(target_arch = "arm"),
31689 stable(feature = "neon_intrinsics", since = "1.59.0")
31690)]
31691#[cfg_attr(
31692 target_arch = "arm",
31693 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31694)]
31695pub fn vmov_n_s32(value: i32) -> int32x2_t {
31696 vdup_n_s32(value)
31697}
31698#[doc = "Duplicate vector element to vector or scalar"]
31699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
31700#[inline]
31701#[target_feature(enable = "neon")]
31702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31703#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
31704#[cfg_attr(
31705 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31706 assert_instr(fmov)
31707)]
31708#[cfg_attr(
31709 not(target_arch = "arm"),
31710 stable(feature = "neon_intrinsics", since = "1.59.0")
31711)]
31712#[cfg_attr(
31713 target_arch = "arm",
31714 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31715)]
31716pub fn vmov_n_s64(value: i64) -> int64x1_t {
31717 vdup_n_s64(value)
31718}
31719#[doc = "Duplicate vector element to vector or scalar"]
31720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
31721#[inline]
31722#[target_feature(enable = "neon")]
31723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31724#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31725#[cfg_attr(
31726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31727 assert_instr(dup)
31728)]
31729#[cfg_attr(
31730 not(target_arch = "arm"),
31731 stable(feature = "neon_intrinsics", since = "1.59.0")
31732)]
31733#[cfg_attr(
31734 target_arch = "arm",
31735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31736)]
31737pub fn vmov_n_s8(value: i8) -> int8x8_t {
31738 vdup_n_s8(value)
31739}
31740#[doc = "Duplicate vector element to vector or scalar"]
31741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
31742#[inline]
31743#[target_feature(enable = "neon")]
31744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31745#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31746#[cfg_attr(
31747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31748 assert_instr(dup)
31749)]
31750#[cfg_attr(
31751 not(target_arch = "arm"),
31752 stable(feature = "neon_intrinsics", since = "1.59.0")
31753)]
31754#[cfg_attr(
31755 target_arch = "arm",
31756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31757)]
31758pub fn vmov_n_u16(value: u16) -> uint16x4_t {
31759 vdup_n_u16(value)
31760}
31761#[doc = "Duplicate vector element to vector or scalar"]
31762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
31763#[inline]
31764#[target_feature(enable = "neon")]
31765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31766#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31767#[cfg_attr(
31768 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31769 assert_instr(dup)
31770)]
31771#[cfg_attr(
31772 not(target_arch = "arm"),
31773 stable(feature = "neon_intrinsics", since = "1.59.0")
31774)]
31775#[cfg_attr(
31776 target_arch = "arm",
31777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31778)]
31779pub fn vmov_n_u32(value: u32) -> uint32x2_t {
31780 vdup_n_u32(value)
31781}
31782#[doc = "Duplicate vector element to vector or scalar"]
31783#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
31784#[inline]
31785#[target_feature(enable = "neon")]
31786#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31787#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
31788#[cfg_attr(
31789 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31790 assert_instr(fmov)
31791)]
31792#[cfg_attr(
31793 not(target_arch = "arm"),
31794 stable(feature = "neon_intrinsics", since = "1.59.0")
31795)]
31796#[cfg_attr(
31797 target_arch = "arm",
31798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31799)]
31800pub fn vmov_n_u64(value: u64) -> uint64x1_t {
31801 vdup_n_u64(value)
31802}
31803#[doc = "Duplicate vector element to vector or scalar"]
31804#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
31805#[inline]
31806#[target_feature(enable = "neon")]
31807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31808#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31809#[cfg_attr(
31810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31811 assert_instr(dup)
31812)]
31813#[cfg_attr(
31814 not(target_arch = "arm"),
31815 stable(feature = "neon_intrinsics", since = "1.59.0")
31816)]
31817#[cfg_attr(
31818 target_arch = "arm",
31819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31820)]
31821pub fn vmov_n_u8(value: u8) -> uint8x8_t {
31822 vdup_n_u8(value)
31823}
31824#[doc = "Duplicate vector element to vector or scalar"]
31825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
31826#[inline]
31827#[target_feature(enable = "neon")]
31828#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31829#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31830#[cfg_attr(
31831 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31832 assert_instr(dup)
31833)]
31834#[cfg_attr(
31835 not(target_arch = "arm"),
31836 stable(feature = "neon_intrinsics", since = "1.59.0")
31837)]
31838#[cfg_attr(
31839 target_arch = "arm",
31840 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31841)]
31842pub fn vmovq_n_f32(value: f32) -> float32x4_t {
31843 vdupq_n_f32(value)
31844}
31845#[doc = "Duplicate vector element to vector or scalar"]
31846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
31847#[inline]
31848#[target_feature(enable = "neon")]
31849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31850#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31851#[cfg_attr(
31852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31853 assert_instr(dup)
31854)]
31855#[cfg_attr(
31856 not(target_arch = "arm"),
31857 stable(feature = "neon_intrinsics", since = "1.59.0")
31858)]
31859#[cfg_attr(
31860 target_arch = "arm",
31861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31862)]
31863pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
31864 vdupq_n_p16(value)
31865}
31866#[doc = "Duplicate vector element to vector or scalar"]
31867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
31868#[inline]
31869#[target_feature(enable = "neon")]
31870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31871#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31872#[cfg_attr(
31873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31874 assert_instr(dup)
31875)]
31876#[cfg_attr(
31877 not(target_arch = "arm"),
31878 stable(feature = "neon_intrinsics", since = "1.59.0")
31879)]
31880#[cfg_attr(
31881 target_arch = "arm",
31882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31883)]
31884pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
31885 vdupq_n_p8(value)
31886}
31887#[doc = "Duplicate vector element to vector or scalar"]
31888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
31889#[inline]
31890#[target_feature(enable = "neon")]
31891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31893#[cfg_attr(
31894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31895 assert_instr(dup)
31896)]
31897#[cfg_attr(
31898 not(target_arch = "arm"),
31899 stable(feature = "neon_intrinsics", since = "1.59.0")
31900)]
31901#[cfg_attr(
31902 target_arch = "arm",
31903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31904)]
31905pub fn vmovq_n_s16(value: i16) -> int16x8_t {
31906 vdupq_n_s16(value)
31907}
31908#[doc = "Duplicate vector element to vector or scalar"]
31909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
31910#[inline]
31911#[target_feature(enable = "neon")]
31912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31913#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31914#[cfg_attr(
31915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31916 assert_instr(dup)
31917)]
31918#[cfg_attr(
31919 not(target_arch = "arm"),
31920 stable(feature = "neon_intrinsics", since = "1.59.0")
31921)]
31922#[cfg_attr(
31923 target_arch = "arm",
31924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31925)]
31926pub fn vmovq_n_s32(value: i32) -> int32x4_t {
31927 vdupq_n_s32(value)
31928}
31929#[doc = "Duplicate vector element to vector or scalar"]
31930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
31931#[inline]
31932#[target_feature(enable = "neon")]
31933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31934#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
31935#[cfg_attr(
31936 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31937 assert_instr(dup)
31938)]
31939#[cfg_attr(
31940 not(target_arch = "arm"),
31941 stable(feature = "neon_intrinsics", since = "1.59.0")
31942)]
31943#[cfg_attr(
31944 target_arch = "arm",
31945 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31946)]
31947pub fn vmovq_n_s64(value: i64) -> int64x2_t {
31948 vdupq_n_s64(value)
31949}
31950#[doc = "Duplicate vector element to vector or scalar"]
31951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
31952#[inline]
31953#[target_feature(enable = "neon")]
31954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31955#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
31956#[cfg_attr(
31957 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31958 assert_instr(dup)
31959)]
31960#[cfg_attr(
31961 not(target_arch = "arm"),
31962 stable(feature = "neon_intrinsics", since = "1.59.0")
31963)]
31964#[cfg_attr(
31965 target_arch = "arm",
31966 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31967)]
31968pub fn vmovq_n_s8(value: i8) -> int8x16_t {
31969 vdupq_n_s8(value)
31970}
31971#[doc = "Duplicate vector element to vector or scalar"]
31972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
31973#[inline]
31974#[target_feature(enable = "neon")]
31975#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
31977#[cfg_attr(
31978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
31979 assert_instr(dup)
31980)]
31981#[cfg_attr(
31982 not(target_arch = "arm"),
31983 stable(feature = "neon_intrinsics", since = "1.59.0")
31984)]
31985#[cfg_attr(
31986 target_arch = "arm",
31987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
31988)]
31989pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
31990 vdupq_n_u16(value)
31991}
31992#[doc = "Duplicate vector element to vector or scalar"]
31993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
31994#[inline]
31995#[target_feature(enable = "neon")]
31996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
31997#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
31998#[cfg_attr(
31999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32000 assert_instr(dup)
32001)]
32002#[cfg_attr(
32003 not(target_arch = "arm"),
32004 stable(feature = "neon_intrinsics", since = "1.59.0")
32005)]
32006#[cfg_attr(
32007 target_arch = "arm",
32008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32009)]
32010pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
32011 vdupq_n_u32(value)
32012}
32013#[doc = "Duplicate vector element to vector or scalar"]
32014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
32015#[inline]
32016#[target_feature(enable = "neon")]
32017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32018#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
32019#[cfg_attr(
32020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32021 assert_instr(dup)
32022)]
32023#[cfg_attr(
32024 not(target_arch = "arm"),
32025 stable(feature = "neon_intrinsics", since = "1.59.0")
32026)]
32027#[cfg_attr(
32028 target_arch = "arm",
32029 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32030)]
32031pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
32032 vdupq_n_u64(value)
32033}
32034#[doc = "Duplicate vector element to vector or scalar"]
32035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
32036#[inline]
32037#[target_feature(enable = "neon")]
32038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32039#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
32040#[cfg_attr(
32041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32042 assert_instr(dup)
32043)]
32044#[cfg_attr(
32045 not(target_arch = "arm"),
32046 stable(feature = "neon_intrinsics", since = "1.59.0")
32047)]
32048#[cfg_attr(
32049 target_arch = "arm",
32050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32051)]
32052pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
32053 vdupq_n_u8(value)
32054}
32055#[doc = "Vector long move."]
32056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
32057#[inline]
32058#[target_feature(enable = "neon")]
32059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32061#[cfg_attr(
32062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32063 assert_instr(sxtl)
32064)]
32065#[cfg_attr(
32066 not(target_arch = "arm"),
32067 stable(feature = "neon_intrinsics", since = "1.59.0")
32068)]
32069#[cfg_attr(
32070 target_arch = "arm",
32071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32072)]
32073pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
32074 unsafe { simd_cast(a) }
32075}
32076#[doc = "Vector long move."]
32077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
32078#[inline]
32079#[target_feature(enable = "neon")]
32080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32082#[cfg_attr(
32083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32084 assert_instr(sxtl)
32085)]
32086#[cfg_attr(
32087 not(target_arch = "arm"),
32088 stable(feature = "neon_intrinsics", since = "1.59.0")
32089)]
32090#[cfg_attr(
32091 target_arch = "arm",
32092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32093)]
32094pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
32095 unsafe { simd_cast(a) }
32096}
32097#[doc = "Vector long move."]
32098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
32099#[inline]
32100#[target_feature(enable = "neon")]
32101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32103#[cfg_attr(
32104 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32105 assert_instr(sxtl)
32106)]
32107#[cfg_attr(
32108 not(target_arch = "arm"),
32109 stable(feature = "neon_intrinsics", since = "1.59.0")
32110)]
32111#[cfg_attr(
32112 target_arch = "arm",
32113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32114)]
32115pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
32116 unsafe { simd_cast(a) }
32117}
32118#[doc = "Vector long move."]
32119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
32120#[inline]
32121#[target_feature(enable = "neon")]
32122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32123#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32124#[cfg_attr(
32125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32126 assert_instr(uxtl)
32127)]
32128#[cfg_attr(
32129 not(target_arch = "arm"),
32130 stable(feature = "neon_intrinsics", since = "1.59.0")
32131)]
32132#[cfg_attr(
32133 target_arch = "arm",
32134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32135)]
32136pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
32137 unsafe { simd_cast(a) }
32138}
32139#[doc = "Vector long move."]
32140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
32141#[inline]
32142#[target_feature(enable = "neon")]
32143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32145#[cfg_attr(
32146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32147 assert_instr(uxtl)
32148)]
32149#[cfg_attr(
32150 not(target_arch = "arm"),
32151 stable(feature = "neon_intrinsics", since = "1.59.0")
32152)]
32153#[cfg_attr(
32154 target_arch = "arm",
32155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32156)]
32157pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
32158 unsafe { simd_cast(a) }
32159}
32160#[doc = "Vector long move."]
32161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
32162#[inline]
32163#[target_feature(enable = "neon")]
32164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32165#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
32166#[cfg_attr(
32167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32168 assert_instr(uxtl)
32169)]
32170#[cfg_attr(
32171 not(target_arch = "arm"),
32172 stable(feature = "neon_intrinsics", since = "1.59.0")
32173)]
32174#[cfg_attr(
32175 target_arch = "arm",
32176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32177)]
32178pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
32179 unsafe { simd_cast(a) }
32180}
32181#[doc = "Vector narrow integer."]
32182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
32183#[inline]
32184#[target_feature(enable = "neon")]
32185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32187#[cfg_attr(
32188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32189 assert_instr(xtn)
32190)]
32191#[cfg_attr(
32192 not(target_arch = "arm"),
32193 stable(feature = "neon_intrinsics", since = "1.59.0")
32194)]
32195#[cfg_attr(
32196 target_arch = "arm",
32197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32198)]
32199pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
32200 unsafe { simd_cast(a) }
32201}
32202#[doc = "Vector narrow integer."]
32203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
32204#[inline]
32205#[target_feature(enable = "neon")]
32206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32208#[cfg_attr(
32209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32210 assert_instr(xtn)
32211)]
32212#[cfg_attr(
32213 not(target_arch = "arm"),
32214 stable(feature = "neon_intrinsics", since = "1.59.0")
32215)]
32216#[cfg_attr(
32217 target_arch = "arm",
32218 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32219)]
32220pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
32221 unsafe { simd_cast(a) }
32222}
32223#[doc = "Vector narrow integer."]
32224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
32225#[inline]
32226#[target_feature(enable = "neon")]
32227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32229#[cfg_attr(
32230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32231 assert_instr(xtn)
32232)]
32233#[cfg_attr(
32234 not(target_arch = "arm"),
32235 stable(feature = "neon_intrinsics", since = "1.59.0")
32236)]
32237#[cfg_attr(
32238 target_arch = "arm",
32239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32240)]
32241pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
32242 unsafe { simd_cast(a) }
32243}
32244#[doc = "Vector narrow integer."]
32245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
32246#[inline]
32247#[target_feature(enable = "neon")]
32248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32249#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32250#[cfg_attr(
32251 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32252 assert_instr(xtn)
32253)]
32254#[cfg_attr(
32255 not(target_arch = "arm"),
32256 stable(feature = "neon_intrinsics", since = "1.59.0")
32257)]
32258#[cfg_attr(
32259 target_arch = "arm",
32260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32261)]
32262pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
32263 unsafe { simd_cast(a) }
32264}
32265#[doc = "Vector narrow integer."]
32266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
32267#[inline]
32268#[target_feature(enable = "neon")]
32269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32271#[cfg_attr(
32272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32273 assert_instr(xtn)
32274)]
32275#[cfg_attr(
32276 not(target_arch = "arm"),
32277 stable(feature = "neon_intrinsics", since = "1.59.0")
32278)]
32279#[cfg_attr(
32280 target_arch = "arm",
32281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32282)]
32283pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
32284 unsafe { simd_cast(a) }
32285}
32286#[doc = "Vector narrow integer."]
32287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
32288#[inline]
32289#[target_feature(enable = "neon")]
32290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
32292#[cfg_attr(
32293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32294 assert_instr(xtn)
32295)]
32296#[cfg_attr(
32297 not(target_arch = "arm"),
32298 stable(feature = "neon_intrinsics", since = "1.59.0")
32299)]
32300#[cfg_attr(
32301 target_arch = "arm",
32302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32303)]
32304pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
32305 unsafe { simd_cast(a) }
32306}
32307#[doc = "Multiply"]
32308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
32309#[inline]
32310#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32311#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32312#[cfg_attr(
32313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32314 assert_instr(fmul)
32315)]
32316#[target_feature(enable = "neon,fp16")]
32317#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32318pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
32319 unsafe { simd_mul(a, b) }
32320}
32321#[doc = "Multiply"]
32322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
32323#[inline]
32324#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32325#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
32326#[cfg_attr(
32327 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32328 assert_instr(fmul)
32329)]
32330#[target_feature(enable = "neon,fp16")]
32331#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32332pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
32333 unsafe { simd_mul(a, b) }
32334}
32335#[doc = "Multiply"]
32336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
32337#[inline]
32338#[target_feature(enable = "neon")]
32339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32341#[cfg_attr(
32342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32343 assert_instr(fmul)
32344)]
32345#[cfg_attr(
32346 not(target_arch = "arm"),
32347 stable(feature = "neon_intrinsics", since = "1.59.0")
32348)]
32349#[cfg_attr(
32350 target_arch = "arm",
32351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32352)]
32353pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32354 unsafe { simd_mul(a, b) }
32355}
32356#[doc = "Multiply"]
32357#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
32358#[inline]
32359#[target_feature(enable = "neon")]
32360#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32361#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
32362#[cfg_attr(
32363 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32364 assert_instr(fmul)
32365)]
32366#[cfg_attr(
32367 not(target_arch = "arm"),
32368 stable(feature = "neon_intrinsics", since = "1.59.0")
32369)]
32370#[cfg_attr(
32371 target_arch = "arm",
32372 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32373)]
32374pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32375 unsafe { simd_mul(a, b) }
32376}
32377#[doc = "Multiply"]
32378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
32379#[inline]
32380#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32381#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32382#[cfg_attr(
32383 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32384 assert_instr(fmul, LANE = 1)
32385)]
32386#[rustc_legacy_const_generics(2)]
32387#[target_feature(enable = "neon,fp16")]
32388#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32389pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16x4_t {
32390 static_assert_uimm_bits!(LANE, 2);
32391 unsafe {
32392 simd_mul(
32393 a,
32394 simd_shuffle!(v, v, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32395 )
32396 }
32397}
32398#[doc = "Multiply"]
32399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
32400#[inline]
32401#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
32402#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32403#[cfg_attr(
32404 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32405 assert_instr(fmul, LANE = 1)
32406)]
32407#[rustc_legacy_const_generics(2)]
32408#[target_feature(enable = "neon,fp16")]
32409#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
32410pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float16x8_t {
32411 static_assert_uimm_bits!(LANE, 2);
32412 unsafe {
32413 simd_mul(
32414 a,
32415 simd_shuffle!(
32416 v,
32417 v,
32418 [
32419 LANE as u32,
32420 LANE as u32,
32421 LANE as u32,
32422 LANE as u32,
32423 LANE as u32,
32424 LANE as u32,
32425 LANE as u32,
32426 LANE as u32
32427 ]
32428 ),
32429 )
32430 }
32431}
32432#[doc = "Floating-point multiply"]
32433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
32434#[inline]
32435#[target_feature(enable = "neon")]
32436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32438#[cfg_attr(
32439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32440 assert_instr(fmul, LANE = 0)
32441)]
32442#[rustc_legacy_const_generics(2)]
32443#[cfg_attr(
32444 not(target_arch = "arm"),
32445 stable(feature = "neon_intrinsics", since = "1.59.0")
32446)]
32447#[cfg_attr(
32448 target_arch = "arm",
32449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32450)]
32451pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
32452 static_assert_uimm_bits!(LANE, 1);
32453 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32454}
32455#[doc = "Floating-point multiply"]
32456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
32457#[inline]
32458#[target_feature(enable = "neon")]
32459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32460#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32461#[cfg_attr(
32462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32463 assert_instr(fmul, LANE = 0)
32464)]
32465#[rustc_legacy_const_generics(2)]
32466#[cfg_attr(
32467 not(target_arch = "arm"),
32468 stable(feature = "neon_intrinsics", since = "1.59.0")
32469)]
32470#[cfg_attr(
32471 target_arch = "arm",
32472 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32473)]
32474pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
32475 static_assert_uimm_bits!(LANE, 2);
32476 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32477}
32478#[doc = "Floating-point multiply"]
32479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
32480#[inline]
32481#[target_feature(enable = "neon")]
32482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32484#[cfg_attr(
32485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32486 assert_instr(fmul, LANE = 0)
32487)]
32488#[rustc_legacy_const_generics(2)]
32489#[cfg_attr(
32490 not(target_arch = "arm"),
32491 stable(feature = "neon_intrinsics", since = "1.59.0")
32492)]
32493#[cfg_attr(
32494 target_arch = "arm",
32495 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32496)]
32497pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
32498 static_assert_uimm_bits!(LANE, 1);
32499 unsafe {
32500 simd_mul(
32501 a,
32502 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32503 )
32504 }
32505}
32506#[doc = "Floating-point multiply"]
32507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
32508#[inline]
32509#[target_feature(enable = "neon")]
32510#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32511#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
32512#[cfg_attr(
32513 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32514 assert_instr(fmul, LANE = 0)
32515)]
32516#[rustc_legacy_const_generics(2)]
32517#[cfg_attr(
32518 not(target_arch = "arm"),
32519 stable(feature = "neon_intrinsics", since = "1.59.0")
32520)]
32521#[cfg_attr(
32522 target_arch = "arm",
32523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32524)]
32525pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
32526 static_assert_uimm_bits!(LANE, 2);
32527 unsafe {
32528 simd_mul(
32529 a,
32530 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32531 )
32532 }
32533}
32534#[doc = "Multiply"]
32535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
32536#[inline]
32537#[target_feature(enable = "neon")]
32538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32539#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32540#[cfg_attr(
32541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32542 assert_instr(mul, LANE = 1)
32543)]
32544#[rustc_legacy_const_generics(2)]
32545#[cfg_attr(
32546 not(target_arch = "arm"),
32547 stable(feature = "neon_intrinsics", since = "1.59.0")
32548)]
32549#[cfg_attr(
32550 target_arch = "arm",
32551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32552)]
32553pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
32554 static_assert_uimm_bits!(LANE, 2);
32555 unsafe {
32556 simd_mul(
32557 a,
32558 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32559 )
32560 }
32561}
32562#[doc = "Multiply"]
32563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
32564#[inline]
32565#[target_feature(enable = "neon")]
32566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32568#[cfg_attr(
32569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32570 assert_instr(mul, LANE = 1)
32571)]
32572#[rustc_legacy_const_generics(2)]
32573#[cfg_attr(
32574 not(target_arch = "arm"),
32575 stable(feature = "neon_intrinsics", since = "1.59.0")
32576)]
32577#[cfg_attr(
32578 target_arch = "arm",
32579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32580)]
32581pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
32582 static_assert_uimm_bits!(LANE, 2);
32583 unsafe {
32584 simd_mul(
32585 a,
32586 simd_shuffle!(
32587 b,
32588 b,
32589 [
32590 LANE as u32,
32591 LANE as u32,
32592 LANE as u32,
32593 LANE as u32,
32594 LANE as u32,
32595 LANE as u32,
32596 LANE as u32,
32597 LANE as u32
32598 ]
32599 ),
32600 )
32601 }
32602}
32603#[doc = "Multiply"]
32604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
32605#[inline]
32606#[target_feature(enable = "neon")]
32607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32609#[cfg_attr(
32610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32611 assert_instr(mul, LANE = 1)
32612)]
32613#[rustc_legacy_const_generics(2)]
32614#[cfg_attr(
32615 not(target_arch = "arm"),
32616 stable(feature = "neon_intrinsics", since = "1.59.0")
32617)]
32618#[cfg_attr(
32619 target_arch = "arm",
32620 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32621)]
32622pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
32623 static_assert_uimm_bits!(LANE, 1);
32624 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32625}
32626#[doc = "Multiply"]
32627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
32628#[inline]
32629#[target_feature(enable = "neon")]
32630#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32631#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32632#[cfg_attr(
32633 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32634 assert_instr(mul, LANE = 1)
32635)]
32636#[rustc_legacy_const_generics(2)]
32637#[cfg_attr(
32638 not(target_arch = "arm"),
32639 stable(feature = "neon_intrinsics", since = "1.59.0")
32640)]
32641#[cfg_attr(
32642 target_arch = "arm",
32643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32644)]
32645pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
32646 static_assert_uimm_bits!(LANE, 1);
32647 unsafe {
32648 simd_mul(
32649 a,
32650 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32651 )
32652 }
32653}
32654#[doc = "Multiply"]
32655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
32656#[inline]
32657#[target_feature(enable = "neon")]
32658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32660#[cfg_attr(
32661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32662 assert_instr(mul, LANE = 1)
32663)]
32664#[rustc_legacy_const_generics(2)]
32665#[cfg_attr(
32666 not(target_arch = "arm"),
32667 stable(feature = "neon_intrinsics", since = "1.59.0")
32668)]
32669#[cfg_attr(
32670 target_arch = "arm",
32671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32672)]
32673pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
32674 static_assert_uimm_bits!(LANE, 2);
32675 unsafe {
32676 simd_mul(
32677 a,
32678 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32679 )
32680 }
32681}
32682#[doc = "Multiply"]
32683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
32684#[inline]
32685#[target_feature(enable = "neon")]
32686#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32687#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32688#[cfg_attr(
32689 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32690 assert_instr(mul, LANE = 1)
32691)]
32692#[rustc_legacy_const_generics(2)]
32693#[cfg_attr(
32694 not(target_arch = "arm"),
32695 stable(feature = "neon_intrinsics", since = "1.59.0")
32696)]
32697#[cfg_attr(
32698 target_arch = "arm",
32699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32700)]
32701pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
32702 static_assert_uimm_bits!(LANE, 2);
32703 unsafe {
32704 simd_mul(
32705 a,
32706 simd_shuffle!(
32707 b,
32708 b,
32709 [
32710 LANE as u32,
32711 LANE as u32,
32712 LANE as u32,
32713 LANE as u32,
32714 LANE as u32,
32715 LANE as u32,
32716 LANE as u32,
32717 LANE as u32
32718 ]
32719 ),
32720 )
32721 }
32722}
32723#[doc = "Multiply"]
32724#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
32725#[inline]
32726#[target_feature(enable = "neon")]
32727#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32729#[cfg_attr(
32730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32731 assert_instr(mul, LANE = 1)
32732)]
32733#[rustc_legacy_const_generics(2)]
32734#[cfg_attr(
32735 not(target_arch = "arm"),
32736 stable(feature = "neon_intrinsics", since = "1.59.0")
32737)]
32738#[cfg_attr(
32739 target_arch = "arm",
32740 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32741)]
32742pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
32743 static_assert_uimm_bits!(LANE, 1);
32744 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32745}
32746#[doc = "Multiply"]
32747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
32748#[inline]
32749#[target_feature(enable = "neon")]
32750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32752#[cfg_attr(
32753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32754 assert_instr(mul, LANE = 1)
32755)]
32756#[rustc_legacy_const_generics(2)]
32757#[cfg_attr(
32758 not(target_arch = "arm"),
32759 stable(feature = "neon_intrinsics", since = "1.59.0")
32760)]
32761#[cfg_attr(
32762 target_arch = "arm",
32763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32764)]
32765pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
32766 static_assert_uimm_bits!(LANE, 1);
32767 unsafe {
32768 simd_mul(
32769 a,
32770 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32771 )
32772 }
32773}
32774#[doc = "Multiply"]
32775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
32776#[inline]
32777#[target_feature(enable = "neon")]
32778#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32779#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32780#[cfg_attr(
32781 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32782 assert_instr(mul, LANE = 1)
32783)]
32784#[rustc_legacy_const_generics(2)]
32785#[cfg_attr(
32786 not(target_arch = "arm"),
32787 stable(feature = "neon_intrinsics", since = "1.59.0")
32788)]
32789#[cfg_attr(
32790 target_arch = "arm",
32791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32792)]
32793pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
32794 static_assert_uimm_bits!(LANE, 3);
32795 unsafe {
32796 simd_mul(
32797 a,
32798 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32799 )
32800 }
32801}
32802#[doc = "Multiply"]
32803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
32804#[inline]
32805#[target_feature(enable = "neon")]
32806#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32807#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32808#[cfg_attr(
32809 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32810 assert_instr(mul, LANE = 1)
32811)]
32812#[rustc_legacy_const_generics(2)]
32813#[cfg_attr(
32814 not(target_arch = "arm"),
32815 stable(feature = "neon_intrinsics", since = "1.59.0")
32816)]
32817#[cfg_attr(
32818 target_arch = "arm",
32819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32820)]
32821pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
32822 static_assert_uimm_bits!(LANE, 3);
32823 unsafe {
32824 simd_mul(
32825 a,
32826 simd_shuffle!(
32827 b,
32828 b,
32829 [
32830 LANE as u32,
32831 LANE as u32,
32832 LANE as u32,
32833 LANE as u32,
32834 LANE as u32,
32835 LANE as u32,
32836 LANE as u32,
32837 LANE as u32
32838 ]
32839 ),
32840 )
32841 }
32842}
32843#[doc = "Multiply"]
32844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
32845#[inline]
32846#[target_feature(enable = "neon")]
32847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32849#[cfg_attr(
32850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32851 assert_instr(mul, LANE = 1)
32852)]
32853#[rustc_legacy_const_generics(2)]
32854#[cfg_attr(
32855 not(target_arch = "arm"),
32856 stable(feature = "neon_intrinsics", since = "1.59.0")
32857)]
32858#[cfg_attr(
32859 target_arch = "arm",
32860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32861)]
32862pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
32863 static_assert_uimm_bits!(LANE, 2);
32864 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32865}
32866#[doc = "Multiply"]
32867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
32868#[inline]
32869#[target_feature(enable = "neon")]
32870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32872#[cfg_attr(
32873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32874 assert_instr(mul, LANE = 1)
32875)]
32876#[rustc_legacy_const_generics(2)]
32877#[cfg_attr(
32878 not(target_arch = "arm"),
32879 stable(feature = "neon_intrinsics", since = "1.59.0")
32880)]
32881#[cfg_attr(
32882 target_arch = "arm",
32883 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32884)]
32885pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
32886 static_assert_uimm_bits!(LANE, 2);
32887 unsafe {
32888 simd_mul(
32889 a,
32890 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32891 )
32892 }
32893}
32894#[doc = "Multiply"]
32895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
32896#[inline]
32897#[target_feature(enable = "neon")]
32898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32900#[cfg_attr(
32901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32902 assert_instr(mul, LANE = 1)
32903)]
32904#[rustc_legacy_const_generics(2)]
32905#[cfg_attr(
32906 not(target_arch = "arm"),
32907 stable(feature = "neon_intrinsics", since = "1.59.0")
32908)]
32909#[cfg_attr(
32910 target_arch = "arm",
32911 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32912)]
32913pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
32914 static_assert_uimm_bits!(LANE, 3);
32915 unsafe {
32916 simd_mul(
32917 a,
32918 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
32919 )
32920 }
32921}
32922#[doc = "Multiply"]
32923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
32924#[inline]
32925#[target_feature(enable = "neon")]
32926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32928#[cfg_attr(
32929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32930 assert_instr(mul, LANE = 1)
32931)]
32932#[rustc_legacy_const_generics(2)]
32933#[cfg_attr(
32934 not(target_arch = "arm"),
32935 stable(feature = "neon_intrinsics", since = "1.59.0")
32936)]
32937#[cfg_attr(
32938 target_arch = "arm",
32939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32940)]
32941pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
32942 static_assert_uimm_bits!(LANE, 3);
32943 unsafe {
32944 simd_mul(
32945 a,
32946 simd_shuffle!(
32947 b,
32948 b,
32949 [
32950 LANE as u32,
32951 LANE as u32,
32952 LANE as u32,
32953 LANE as u32,
32954 LANE as u32,
32955 LANE as u32,
32956 LANE as u32,
32957 LANE as u32
32958 ]
32959 ),
32960 )
32961 }
32962}
32963#[doc = "Multiply"]
32964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
32965#[inline]
32966#[target_feature(enable = "neon")]
32967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32969#[cfg_attr(
32970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32971 assert_instr(mul, LANE = 1)
32972)]
32973#[rustc_legacy_const_generics(2)]
32974#[cfg_attr(
32975 not(target_arch = "arm"),
32976 stable(feature = "neon_intrinsics", since = "1.59.0")
32977)]
32978#[cfg_attr(
32979 target_arch = "arm",
32980 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
32981)]
32982pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
32983 static_assert_uimm_bits!(LANE, 2);
32984 unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
32985}
32986#[doc = "Multiply"]
32987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
32988#[inline]
32989#[target_feature(enable = "neon")]
32990#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
32991#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
32992#[cfg_attr(
32993 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
32994 assert_instr(mul, LANE = 1)
32995)]
32996#[rustc_legacy_const_generics(2)]
32997#[cfg_attr(
32998 not(target_arch = "arm"),
32999 stable(feature = "neon_intrinsics", since = "1.59.0")
33000)]
33001#[cfg_attr(
33002 target_arch = "arm",
33003 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33004)]
33005pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33006 static_assert_uimm_bits!(LANE, 2);
33007 unsafe {
33008 simd_mul(
33009 a,
33010 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33011 )
33012 }
33013}
33014#[doc = "Vector multiply by scalar"]
33015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
33016#[inline]
33017#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33019#[cfg_attr(
33020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33021 assert_instr(fmul)
33022)]
33023#[target_feature(enable = "neon,fp16")]
33024#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33025pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
33026 unsafe { simd_mul(a, vdup_n_f16(b)) }
33027}
33028#[doc = "Vector multiply by scalar"]
33029#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
33030#[inline]
33031#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
33032#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33033#[cfg_attr(
33034 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33035 assert_instr(fmul)
33036)]
33037#[target_feature(enable = "neon,fp16")]
33038#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
33039pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
33040 unsafe { simd_mul(a, vdupq_n_f16(b)) }
33041}
33042#[doc = "Vector multiply by scalar"]
33043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
33044#[inline]
33045#[target_feature(enable = "neon")]
33046#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33047#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33048#[cfg_attr(
33049 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33050 assert_instr(fmul)
33051)]
33052#[cfg_attr(
33053 not(target_arch = "arm"),
33054 stable(feature = "neon_intrinsics", since = "1.59.0")
33055)]
33056#[cfg_attr(
33057 target_arch = "arm",
33058 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33059)]
33060pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
33061 unsafe { simd_mul(a, vdup_n_f32(b)) }
33062}
33063#[doc = "Vector multiply by scalar"]
33064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
33065#[inline]
33066#[target_feature(enable = "neon")]
33067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33069#[cfg_attr(
33070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33071 assert_instr(fmul)
33072)]
33073#[cfg_attr(
33074 not(target_arch = "arm"),
33075 stable(feature = "neon_intrinsics", since = "1.59.0")
33076)]
33077#[cfg_attr(
33078 target_arch = "arm",
33079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33080)]
33081pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
33082 unsafe { simd_mul(a, vdupq_n_f32(b)) }
33083}
33084#[doc = "Vector multiply by scalar"]
33085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
33086#[inline]
33087#[target_feature(enable = "neon")]
33088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33089#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33090#[cfg_attr(
33091 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33092 assert_instr(mul)
33093)]
33094#[cfg_attr(
33095 not(target_arch = "arm"),
33096 stable(feature = "neon_intrinsics", since = "1.59.0")
33097)]
33098#[cfg_attr(
33099 target_arch = "arm",
33100 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33101)]
33102pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
33103 unsafe { simd_mul(a, vdup_n_s16(b)) }
33104}
33105#[doc = "Vector multiply by scalar"]
33106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
33107#[inline]
33108#[target_feature(enable = "neon")]
33109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33111#[cfg_attr(
33112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33113 assert_instr(mul)
33114)]
33115#[cfg_attr(
33116 not(target_arch = "arm"),
33117 stable(feature = "neon_intrinsics", since = "1.59.0")
33118)]
33119#[cfg_attr(
33120 target_arch = "arm",
33121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33122)]
33123pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
33124 unsafe { simd_mul(a, vdupq_n_s16(b)) }
33125}
33126#[doc = "Vector multiply by scalar"]
33127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
33128#[inline]
33129#[target_feature(enable = "neon")]
33130#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33131#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33132#[cfg_attr(
33133 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33134 assert_instr(mul)
33135)]
33136#[cfg_attr(
33137 not(target_arch = "arm"),
33138 stable(feature = "neon_intrinsics", since = "1.59.0")
33139)]
33140#[cfg_attr(
33141 target_arch = "arm",
33142 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33143)]
33144pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
33145 unsafe { simd_mul(a, vdup_n_s32(b)) }
33146}
33147#[doc = "Vector multiply by scalar"]
33148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
33149#[inline]
33150#[target_feature(enable = "neon")]
33151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33153#[cfg_attr(
33154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33155 assert_instr(mul)
33156)]
33157#[cfg_attr(
33158 not(target_arch = "arm"),
33159 stable(feature = "neon_intrinsics", since = "1.59.0")
33160)]
33161#[cfg_attr(
33162 target_arch = "arm",
33163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33164)]
33165pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
33166 unsafe { simd_mul(a, vdupq_n_s32(b)) }
33167}
33168#[doc = "Vector multiply by scalar"]
33169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
33170#[inline]
33171#[target_feature(enable = "neon")]
33172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33174#[cfg_attr(
33175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33176 assert_instr(mul)
33177)]
33178#[cfg_attr(
33179 not(target_arch = "arm"),
33180 stable(feature = "neon_intrinsics", since = "1.59.0")
33181)]
33182#[cfg_attr(
33183 target_arch = "arm",
33184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33185)]
33186pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
33187 unsafe { simd_mul(a, vdup_n_u16(b)) }
33188}
33189#[doc = "Vector multiply by scalar"]
33190#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
33191#[inline]
33192#[target_feature(enable = "neon")]
33193#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33194#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33195#[cfg_attr(
33196 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33197 assert_instr(mul)
33198)]
33199#[cfg_attr(
33200 not(target_arch = "arm"),
33201 stable(feature = "neon_intrinsics", since = "1.59.0")
33202)]
33203#[cfg_attr(
33204 target_arch = "arm",
33205 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33206)]
33207pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
33208 unsafe { simd_mul(a, vdupq_n_u16(b)) }
33209}
33210#[doc = "Vector multiply by scalar"]
33211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
33212#[inline]
33213#[target_feature(enable = "neon")]
33214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33215#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33216#[cfg_attr(
33217 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33218 assert_instr(mul)
33219)]
33220#[cfg_attr(
33221 not(target_arch = "arm"),
33222 stable(feature = "neon_intrinsics", since = "1.59.0")
33223)]
33224#[cfg_attr(
33225 target_arch = "arm",
33226 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33227)]
33228pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
33229 unsafe { simd_mul(a, vdup_n_u32(b)) }
33230}
33231#[doc = "Vector multiply by scalar"]
33232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
33233#[inline]
33234#[target_feature(enable = "neon")]
33235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33237#[cfg_attr(
33238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33239 assert_instr(mul)
33240)]
33241#[cfg_attr(
33242 not(target_arch = "arm"),
33243 stable(feature = "neon_intrinsics", since = "1.59.0")
33244)]
33245#[cfg_attr(
33246 target_arch = "arm",
33247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33248)]
33249pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
33250 unsafe { simd_mul(a, vdupq_n_u32(b)) }
33251}
33252#[doc = "Polynomial multiply"]
33253#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
33254#[inline]
33255#[target_feature(enable = "neon")]
33256#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33257#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33258#[cfg_attr(
33259 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33260 assert_instr(pmul)
33261)]
33262#[cfg_attr(
33263 not(target_arch = "arm"),
33264 stable(feature = "neon_intrinsics", since = "1.59.0")
33265)]
33266#[cfg_attr(
33267 target_arch = "arm",
33268 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33269)]
33270pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
33271 unsafe extern "unadjusted" {
33272 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
33273 #[cfg_attr(
33274 any(target_arch = "aarch64", target_arch = "arm64ec"),
33275 link_name = "llvm.aarch64.neon.pmul.v8i8"
33276 )]
33277 fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
33278 }
33279 unsafe { _vmul_p8(a, b) }
33280}
33281#[doc = "Polynomial multiply"]
33282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
33283#[inline]
33284#[target_feature(enable = "neon")]
33285#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33286#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
33287#[cfg_attr(
33288 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33289 assert_instr(pmul)
33290)]
33291#[cfg_attr(
33292 not(target_arch = "arm"),
33293 stable(feature = "neon_intrinsics", since = "1.59.0")
33294)]
33295#[cfg_attr(
33296 target_arch = "arm",
33297 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33298)]
33299pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
33300 unsafe extern "unadjusted" {
33301 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
33302 #[cfg_attr(
33303 any(target_arch = "aarch64", target_arch = "arm64ec"),
33304 link_name = "llvm.aarch64.neon.pmul.v16i8"
33305 )]
33306 fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
33307 }
33308 unsafe { _vmulq_p8(a, b) }
33309}
33310#[doc = "Multiply"]
33311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
33312#[inline]
33313#[target_feature(enable = "neon")]
33314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33315#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33316#[cfg_attr(
33317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33318 assert_instr(mul)
33319)]
33320#[cfg_attr(
33321 not(target_arch = "arm"),
33322 stable(feature = "neon_intrinsics", since = "1.59.0")
33323)]
33324#[cfg_attr(
33325 target_arch = "arm",
33326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33327)]
33328pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
33329 unsafe { simd_mul(a, b) }
33330}
33331#[doc = "Multiply"]
33332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
33333#[inline]
33334#[target_feature(enable = "neon")]
33335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33336#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33337#[cfg_attr(
33338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33339 assert_instr(mul)
33340)]
33341#[cfg_attr(
33342 not(target_arch = "arm"),
33343 stable(feature = "neon_intrinsics", since = "1.59.0")
33344)]
33345#[cfg_attr(
33346 target_arch = "arm",
33347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33348)]
33349pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
33350 unsafe { simd_mul(a, b) }
33351}
33352#[doc = "Multiply"]
33353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
33354#[inline]
33355#[target_feature(enable = "neon")]
33356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33357#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33358#[cfg_attr(
33359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33360 assert_instr(mul)
33361)]
33362#[cfg_attr(
33363 not(target_arch = "arm"),
33364 stable(feature = "neon_intrinsics", since = "1.59.0")
33365)]
33366#[cfg_attr(
33367 target_arch = "arm",
33368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33369)]
33370pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
33371 unsafe { simd_mul(a, b) }
33372}
33373#[doc = "Multiply"]
33374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
33375#[inline]
33376#[target_feature(enable = "neon")]
33377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33378#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
33379#[cfg_attr(
33380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33381 assert_instr(mul)
33382)]
33383#[cfg_attr(
33384 not(target_arch = "arm"),
33385 stable(feature = "neon_intrinsics", since = "1.59.0")
33386)]
33387#[cfg_attr(
33388 target_arch = "arm",
33389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33390)]
33391pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
33392 unsafe { simd_mul(a, b) }
33393}
33394#[doc = "Multiply"]
33395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
33396#[inline]
33397#[target_feature(enable = "neon")]
33398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33399#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33400#[cfg_attr(
33401 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33402 assert_instr(mul)
33403)]
33404#[cfg_attr(
33405 not(target_arch = "arm"),
33406 stable(feature = "neon_intrinsics", since = "1.59.0")
33407)]
33408#[cfg_attr(
33409 target_arch = "arm",
33410 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33411)]
33412pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
33413 unsafe { simd_mul(a, b) }
33414}
33415#[doc = "Multiply"]
33416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
33417#[inline]
33418#[target_feature(enable = "neon")]
33419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33420#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33421#[cfg_attr(
33422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33423 assert_instr(mul)
33424)]
33425#[cfg_attr(
33426 not(target_arch = "arm"),
33427 stable(feature = "neon_intrinsics", since = "1.59.0")
33428)]
33429#[cfg_attr(
33430 target_arch = "arm",
33431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33432)]
33433pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
33434 unsafe { simd_mul(a, b) }
33435}
33436#[doc = "Multiply"]
33437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
33438#[inline]
33439#[target_feature(enable = "neon")]
33440#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33441#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33442#[cfg_attr(
33443 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33444 assert_instr(mul)
33445)]
33446#[cfg_attr(
33447 not(target_arch = "arm"),
33448 stable(feature = "neon_intrinsics", since = "1.59.0")
33449)]
33450#[cfg_attr(
33451 target_arch = "arm",
33452 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33453)]
33454pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
33455 unsafe { simd_mul(a, b) }
33456}
33457#[doc = "Multiply"]
33458#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
33459#[inline]
33460#[target_feature(enable = "neon")]
33461#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33462#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
33463#[cfg_attr(
33464 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33465 assert_instr(mul)
33466)]
33467#[cfg_attr(
33468 not(target_arch = "arm"),
33469 stable(feature = "neon_intrinsics", since = "1.59.0")
33470)]
33471#[cfg_attr(
33472 target_arch = "arm",
33473 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33474)]
33475pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
33476 unsafe { simd_mul(a, b) }
33477}
33478#[doc = "Multiply"]
33479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
33480#[inline]
33481#[target_feature(enable = "neon")]
33482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33483#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33484#[cfg_attr(
33485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33486 assert_instr(mul)
33487)]
33488#[cfg_attr(
33489 not(target_arch = "arm"),
33490 stable(feature = "neon_intrinsics", since = "1.59.0")
33491)]
33492#[cfg_attr(
33493 target_arch = "arm",
33494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33495)]
33496pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
33497 unsafe { simd_mul(a, b) }
33498}
33499#[doc = "Multiply"]
33500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
33501#[inline]
33502#[target_feature(enable = "neon")]
33503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33504#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33505#[cfg_attr(
33506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33507 assert_instr(mul)
33508)]
33509#[cfg_attr(
33510 not(target_arch = "arm"),
33511 stable(feature = "neon_intrinsics", since = "1.59.0")
33512)]
33513#[cfg_attr(
33514 target_arch = "arm",
33515 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33516)]
33517pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
33518 unsafe { simd_mul(a, b) }
33519}
33520#[doc = "Multiply"]
33521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
33522#[inline]
33523#[target_feature(enable = "neon")]
33524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33525#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33526#[cfg_attr(
33527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33528 assert_instr(mul)
33529)]
33530#[cfg_attr(
33531 not(target_arch = "arm"),
33532 stable(feature = "neon_intrinsics", since = "1.59.0")
33533)]
33534#[cfg_attr(
33535 target_arch = "arm",
33536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33537)]
33538pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
33539 unsafe { simd_mul(a, b) }
33540}
33541#[doc = "Multiply"]
33542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
33543#[inline]
33544#[target_feature(enable = "neon")]
33545#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33546#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
33547#[cfg_attr(
33548 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33549 assert_instr(mul)
33550)]
33551#[cfg_attr(
33552 not(target_arch = "arm"),
33553 stable(feature = "neon_intrinsics", since = "1.59.0")
33554)]
33555#[cfg_attr(
33556 target_arch = "arm",
33557 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33558)]
33559pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
33560 unsafe { simd_mul(a, b) }
33561}
33562#[doc = "Vector long multiply by scalar"]
33563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
33564#[inline]
33565#[target_feature(enable = "neon")]
33566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33568#[cfg_attr(
33569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33570 assert_instr(smull, LANE = 1)
33571)]
33572#[rustc_legacy_const_generics(2)]
33573#[cfg_attr(
33574 not(target_arch = "arm"),
33575 stable(feature = "neon_intrinsics", since = "1.59.0")
33576)]
33577#[cfg_attr(
33578 target_arch = "arm",
33579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33580)]
33581pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
33582 static_assert_uimm_bits!(LANE, 2);
33583 unsafe {
33584 vmull_s16(
33585 a,
33586 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33587 )
33588 }
33589}
33590#[doc = "Vector long multiply by scalar"]
33591#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
33592#[inline]
33593#[target_feature(enable = "neon")]
33594#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33595#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33596#[cfg_attr(
33597 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33598 assert_instr(smull, LANE = 1)
33599)]
33600#[rustc_legacy_const_generics(2)]
33601#[cfg_attr(
33602 not(target_arch = "arm"),
33603 stable(feature = "neon_intrinsics", since = "1.59.0")
33604)]
33605#[cfg_attr(
33606 target_arch = "arm",
33607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33608)]
33609pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t {
33610 static_assert_uimm_bits!(LANE, 3);
33611 unsafe {
33612 vmull_s16(
33613 a,
33614 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33615 )
33616 }
33617}
33618#[doc = "Vector long multiply by scalar"]
33619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
33620#[inline]
33621#[target_feature(enable = "neon")]
33622#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33623#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33624#[cfg_attr(
33625 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33626 assert_instr(smull, LANE = 1)
33627)]
33628#[rustc_legacy_const_generics(2)]
33629#[cfg_attr(
33630 not(target_arch = "arm"),
33631 stable(feature = "neon_intrinsics", since = "1.59.0")
33632)]
33633#[cfg_attr(
33634 target_arch = "arm",
33635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33636)]
33637pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
33638 static_assert_uimm_bits!(LANE, 1);
33639 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33640}
33641#[doc = "Vector long multiply by scalar"]
33642#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
33643#[inline]
33644#[target_feature(enable = "neon")]
33645#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33646#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33647#[cfg_attr(
33648 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33649 assert_instr(smull, LANE = 1)
33650)]
33651#[rustc_legacy_const_generics(2)]
33652#[cfg_attr(
33653 not(target_arch = "arm"),
33654 stable(feature = "neon_intrinsics", since = "1.59.0")
33655)]
33656#[cfg_attr(
33657 target_arch = "arm",
33658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33659)]
33660pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t {
33661 static_assert_uimm_bits!(LANE, 2);
33662 unsafe { vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33663}
33664#[doc = "Vector long multiply by scalar"]
33665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
33666#[inline]
33667#[target_feature(enable = "neon")]
33668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33669#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33670#[cfg_attr(
33671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33672 assert_instr(umull, LANE = 1)
33673)]
33674#[rustc_legacy_const_generics(2)]
33675#[cfg_attr(
33676 not(target_arch = "arm"),
33677 stable(feature = "neon_intrinsics", since = "1.59.0")
33678)]
33679#[cfg_attr(
33680 target_arch = "arm",
33681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33682)]
33683pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
33684 static_assert_uimm_bits!(LANE, 2);
33685 unsafe {
33686 vmull_u16(
33687 a,
33688 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33689 )
33690 }
33691}
33692#[doc = "Vector long multiply by scalar"]
33693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
33694#[inline]
33695#[target_feature(enable = "neon")]
33696#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33697#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33698#[cfg_attr(
33699 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33700 assert_instr(umull, LANE = 1)
33701)]
33702#[rustc_legacy_const_generics(2)]
33703#[cfg_attr(
33704 not(target_arch = "arm"),
33705 stable(feature = "neon_intrinsics", since = "1.59.0")
33706)]
33707#[cfg_attr(
33708 target_arch = "arm",
33709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33710)]
33711pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t {
33712 static_assert_uimm_bits!(LANE, 3);
33713 unsafe {
33714 vmull_u16(
33715 a,
33716 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
33717 )
33718 }
33719}
33720#[doc = "Vector long multiply by scalar"]
33721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
33722#[inline]
33723#[target_feature(enable = "neon")]
33724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33726#[cfg_attr(
33727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33728 assert_instr(umull, LANE = 1)
33729)]
33730#[rustc_legacy_const_generics(2)]
33731#[cfg_attr(
33732 not(target_arch = "arm"),
33733 stable(feature = "neon_intrinsics", since = "1.59.0")
33734)]
33735#[cfg_attr(
33736 target_arch = "arm",
33737 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33738)]
33739pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
33740 static_assert_uimm_bits!(LANE, 1);
33741 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33742}
33743#[doc = "Vector long multiply by scalar"]
33744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
33745#[inline]
33746#[target_feature(enable = "neon")]
33747#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33748#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
33749#[cfg_attr(
33750 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33751 assert_instr(umull, LANE = 1)
33752)]
33753#[rustc_legacy_const_generics(2)]
33754#[cfg_attr(
33755 not(target_arch = "arm"),
33756 stable(feature = "neon_intrinsics", since = "1.59.0")
33757)]
33758#[cfg_attr(
33759 target_arch = "arm",
33760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33761)]
33762pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t {
33763 static_assert_uimm_bits!(LANE, 2);
33764 unsafe { vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
33765}
33766#[doc = "Vector long multiply with scalar"]
33767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
33768#[inline]
33769#[target_feature(enable = "neon")]
33770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
33772#[cfg_attr(
33773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33774 assert_instr(smull)
33775)]
33776#[cfg_attr(
33777 not(target_arch = "arm"),
33778 stable(feature = "neon_intrinsics", since = "1.59.0")
33779)]
33780#[cfg_attr(
33781 target_arch = "arm",
33782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33783)]
33784pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
33785 vmull_s16(a, vdup_n_s16(b))
33786}
33787#[doc = "Vector long multiply with scalar"]
33788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
33789#[inline]
33790#[target_feature(enable = "neon")]
33791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
33793#[cfg_attr(
33794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33795 assert_instr(smull)
33796)]
33797#[cfg_attr(
33798 not(target_arch = "arm"),
33799 stable(feature = "neon_intrinsics", since = "1.59.0")
33800)]
33801#[cfg_attr(
33802 target_arch = "arm",
33803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33804)]
33805pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
33806 vmull_s32(a, vdup_n_s32(b))
33807}
33808#[doc = "Vector long multiply with scalar"]
33809#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
33810#[inline]
33811#[target_feature(enable = "neon")]
33812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
33814#[cfg_attr(
33815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33816 assert_instr(umull)
33817)]
33818#[cfg_attr(
33819 not(target_arch = "arm"),
33820 stable(feature = "neon_intrinsics", since = "1.59.0")
33821)]
33822#[cfg_attr(
33823 target_arch = "arm",
33824 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33825)]
33826pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
33827 vmull_u16(a, vdup_n_u16(b))
33828}
33829#[doc = "Vector long multiply with scalar"]
33830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
33831#[inline]
33832#[target_feature(enable = "neon")]
33833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
33835#[cfg_attr(
33836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33837 assert_instr(umull)
33838)]
33839#[cfg_attr(
33840 not(target_arch = "arm"),
33841 stable(feature = "neon_intrinsics", since = "1.59.0")
33842)]
33843#[cfg_attr(
33844 target_arch = "arm",
33845 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33846)]
33847pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
33848 vmull_u32(a, vdup_n_u32(b))
33849}
33850#[doc = "Polynomial multiply long"]
33851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
33852#[inline]
33853#[target_feature(enable = "neon")]
33854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33855#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
33856#[cfg_attr(
33857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33858 assert_instr(pmull)
33859)]
33860#[cfg_attr(
33861 not(target_arch = "arm"),
33862 stable(feature = "neon_intrinsics", since = "1.59.0")
33863)]
33864#[cfg_attr(
33865 target_arch = "arm",
33866 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33867)]
33868pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
33869 unsafe extern "unadjusted" {
33870 #[cfg_attr(
33871 any(target_arch = "aarch64", target_arch = "arm64ec"),
33872 link_name = "llvm.aarch64.neon.pmull.v8i16"
33873 )]
33874 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i16")]
33875 fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t;
33876 }
33877 unsafe { _vmull_p8(a, b) }
33878}
33879#[doc = "Signed multiply long"]
33880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
33881#[inline]
33882#[target_feature(enable = "neon")]
33883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33884#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
33885#[cfg_attr(
33886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33887 assert_instr(smull)
33888)]
33889#[cfg_attr(
33890 not(target_arch = "arm"),
33891 stable(feature = "neon_intrinsics", since = "1.59.0")
33892)]
33893#[cfg_attr(
33894 target_arch = "arm",
33895 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33896)]
33897pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
33898 unsafe extern "unadjusted" {
33899 #[cfg_attr(
33900 any(target_arch = "aarch64", target_arch = "arm64ec"),
33901 link_name = "llvm.aarch64.neon.smull.v4i32"
33902 )]
33903 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")]
33904 fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
33905 }
33906 unsafe { _vmull_s16(a, b) }
33907}
33908#[doc = "Signed multiply long"]
33909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
33910#[inline]
33911#[target_feature(enable = "neon")]
33912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33913#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
33914#[cfg_attr(
33915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33916 assert_instr(smull)
33917)]
33918#[cfg_attr(
33919 not(target_arch = "arm"),
33920 stable(feature = "neon_intrinsics", since = "1.59.0")
33921)]
33922#[cfg_attr(
33923 target_arch = "arm",
33924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33925)]
33926pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
33927 unsafe extern "unadjusted" {
33928 #[cfg_attr(
33929 any(target_arch = "aarch64", target_arch = "arm64ec"),
33930 link_name = "llvm.aarch64.neon.smull.v2i64"
33931 )]
33932 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")]
33933 fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
33934 }
33935 unsafe { _vmull_s32(a, b) }
33936}
33937#[doc = "Signed multiply long"]
33938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
33939#[inline]
33940#[target_feature(enable = "neon")]
33941#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33942#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
33943#[cfg_attr(
33944 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33945 assert_instr(smull)
33946)]
33947#[cfg_attr(
33948 not(target_arch = "arm"),
33949 stable(feature = "neon_intrinsics", since = "1.59.0")
33950)]
33951#[cfg_attr(
33952 target_arch = "arm",
33953 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33954)]
33955pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
33956 unsafe extern "unadjusted" {
33957 #[cfg_attr(
33958 any(target_arch = "aarch64", target_arch = "arm64ec"),
33959 link_name = "llvm.aarch64.neon.smull.v8i16"
33960 )]
33961 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")]
33962 fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t;
33963 }
33964 unsafe { _vmull_s8(a, b) }
33965}
33966#[doc = "Unsigned multiply long"]
33967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
33968#[inline]
33969#[target_feature(enable = "neon")]
33970#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
33971#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
33972#[cfg_attr(
33973 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
33974 assert_instr(umull)
33975)]
33976#[cfg_attr(
33977 not(target_arch = "arm"),
33978 stable(feature = "neon_intrinsics", since = "1.59.0")
33979)]
33980#[cfg_attr(
33981 target_arch = "arm",
33982 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
33983)]
33984pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
33985 unsafe extern "unadjusted" {
33986 #[cfg_attr(
33987 any(target_arch = "aarch64", target_arch = "arm64ec"),
33988 link_name = "llvm.aarch64.neon.umull.v8i16"
33989 )]
33990 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")]
33991 fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t;
33992 }
33993 unsafe { _vmull_u8(a, b) }
33994}
33995#[doc = "Unsigned multiply long"]
33996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
33997#[inline]
33998#[target_feature(enable = "neon")]
33999#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34000#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
34001#[cfg_attr(
34002 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34003 assert_instr(umull)
34004)]
34005#[cfg_attr(
34006 not(target_arch = "arm"),
34007 stable(feature = "neon_intrinsics", since = "1.59.0")
34008)]
34009#[cfg_attr(
34010 target_arch = "arm",
34011 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34012)]
34013pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
34014 unsafe extern "unadjusted" {
34015 #[cfg_attr(
34016 any(target_arch = "aarch64", target_arch = "arm64ec"),
34017 link_name = "llvm.aarch64.neon.umull.v4i32"
34018 )]
34019 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")]
34020 fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t;
34021 }
34022 unsafe { _vmull_u16(a, b) }
34023}
34024#[doc = "Unsigned multiply long"]
34025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
34026#[inline]
34027#[target_feature(enable = "neon")]
34028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34029#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
34030#[cfg_attr(
34031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34032 assert_instr(umull)
34033)]
34034#[cfg_attr(
34035 not(target_arch = "arm"),
34036 stable(feature = "neon_intrinsics", since = "1.59.0")
34037)]
34038#[cfg_attr(
34039 target_arch = "arm",
34040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34041)]
34042pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
34043 unsafe extern "unadjusted" {
34044 #[cfg_attr(
34045 any(target_arch = "aarch64", target_arch = "arm64ec"),
34046 link_name = "llvm.aarch64.neon.umull.v2i64"
34047 )]
34048 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")]
34049 fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t;
34050 }
34051 unsafe { _vmull_u32(a, b) }
34052}
34053#[doc = "Vector bitwise not."]
34054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
34055#[inline]
34056#[target_feature(enable = "neon")]
34057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34059#[cfg_attr(
34060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34061 assert_instr(mvn)
34062)]
34063#[cfg_attr(
34064 not(target_arch = "arm"),
34065 stable(feature = "neon_intrinsics", since = "1.59.0")
34066)]
34067#[cfg_attr(
34068 target_arch = "arm",
34069 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34070)]
34071pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
34072 let b = poly8x8_t::splat(255);
34073 unsafe { simd_xor(a, b) }
34074}
34075#[doc = "Vector bitwise not."]
34076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
34077#[inline]
34078#[target_feature(enable = "neon")]
34079#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34080#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34081#[cfg_attr(
34082 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34083 assert_instr(mvn)
34084)]
34085#[cfg_attr(
34086 not(target_arch = "arm"),
34087 stable(feature = "neon_intrinsics", since = "1.59.0")
34088)]
34089#[cfg_attr(
34090 target_arch = "arm",
34091 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34092)]
34093pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
34094 let b = int16x4_t::splat(-1);
34095 unsafe { simd_xor(a, b) }
34096}
34097#[doc = "Vector bitwise not."]
34098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
34099#[inline]
34100#[target_feature(enable = "neon")]
34101#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34102#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34103#[cfg_attr(
34104 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34105 assert_instr(mvn)
34106)]
34107#[cfg_attr(
34108 not(target_arch = "arm"),
34109 stable(feature = "neon_intrinsics", since = "1.59.0")
34110)]
34111#[cfg_attr(
34112 target_arch = "arm",
34113 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34114)]
34115pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
34116 let b = int32x2_t::splat(-1);
34117 unsafe { simd_xor(a, b) }
34118}
34119#[doc = "Vector bitwise not."]
34120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
34121#[inline]
34122#[target_feature(enable = "neon")]
34123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34125#[cfg_attr(
34126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34127 assert_instr(mvn)
34128)]
34129#[cfg_attr(
34130 not(target_arch = "arm"),
34131 stable(feature = "neon_intrinsics", since = "1.59.0")
34132)]
34133#[cfg_attr(
34134 target_arch = "arm",
34135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34136)]
34137pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
34138 let b = int8x8_t::splat(-1);
34139 unsafe { simd_xor(a, b) }
34140}
34141#[doc = "Vector bitwise not."]
34142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
34143#[inline]
34144#[target_feature(enable = "neon")]
34145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34147#[cfg_attr(
34148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34149 assert_instr(mvn)
34150)]
34151#[cfg_attr(
34152 not(target_arch = "arm"),
34153 stable(feature = "neon_intrinsics", since = "1.59.0")
34154)]
34155#[cfg_attr(
34156 target_arch = "arm",
34157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34158)]
34159pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
34160 let b = uint16x4_t::splat(65_535);
34161 unsafe { simd_xor(a, b) }
34162}
34163#[doc = "Vector bitwise not."]
34164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
34165#[inline]
34166#[target_feature(enable = "neon")]
34167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34169#[cfg_attr(
34170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34171 assert_instr(mvn)
34172)]
34173#[cfg_attr(
34174 not(target_arch = "arm"),
34175 stable(feature = "neon_intrinsics", since = "1.59.0")
34176)]
34177#[cfg_attr(
34178 target_arch = "arm",
34179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34180)]
34181pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
34182 let b = uint32x2_t::splat(4_294_967_295);
34183 unsafe { simd_xor(a, b) }
34184}
34185#[doc = "Vector bitwise not."]
34186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
34187#[inline]
34188#[target_feature(enable = "neon")]
34189#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34190#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34191#[cfg_attr(
34192 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34193 assert_instr(mvn)
34194)]
34195#[cfg_attr(
34196 not(target_arch = "arm"),
34197 stable(feature = "neon_intrinsics", since = "1.59.0")
34198)]
34199#[cfg_attr(
34200 target_arch = "arm",
34201 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34202)]
34203pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
34204 let b = uint8x8_t::splat(255);
34205 unsafe { simd_xor(a, b) }
34206}
34207#[doc = "Vector bitwise not."]
34208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
34209#[inline]
34210#[target_feature(enable = "neon")]
34211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34213#[cfg_attr(
34214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34215 assert_instr(mvn)
34216)]
34217#[cfg_attr(
34218 not(target_arch = "arm"),
34219 stable(feature = "neon_intrinsics", since = "1.59.0")
34220)]
34221#[cfg_attr(
34222 target_arch = "arm",
34223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34224)]
34225pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
34226 let b = poly8x16_t::splat(255);
34227 unsafe { simd_xor(a, b) }
34228}
34229#[doc = "Vector bitwise not."]
34230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
34231#[inline]
34232#[target_feature(enable = "neon")]
34233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34235#[cfg_attr(
34236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34237 assert_instr(mvn)
34238)]
34239#[cfg_attr(
34240 not(target_arch = "arm"),
34241 stable(feature = "neon_intrinsics", since = "1.59.0")
34242)]
34243#[cfg_attr(
34244 target_arch = "arm",
34245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34246)]
34247pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
34248 let b = int16x8_t::splat(-1);
34249 unsafe { simd_xor(a, b) }
34250}
34251#[doc = "Vector bitwise not."]
34252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
34253#[inline]
34254#[target_feature(enable = "neon")]
34255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34257#[cfg_attr(
34258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34259 assert_instr(mvn)
34260)]
34261#[cfg_attr(
34262 not(target_arch = "arm"),
34263 stable(feature = "neon_intrinsics", since = "1.59.0")
34264)]
34265#[cfg_attr(
34266 target_arch = "arm",
34267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34268)]
34269pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
34270 let b = int32x4_t::splat(-1);
34271 unsafe { simd_xor(a, b) }
34272}
34273#[doc = "Vector bitwise not."]
34274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
34275#[inline]
34276#[target_feature(enable = "neon")]
34277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34279#[cfg_attr(
34280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34281 assert_instr(mvn)
34282)]
34283#[cfg_attr(
34284 not(target_arch = "arm"),
34285 stable(feature = "neon_intrinsics", since = "1.59.0")
34286)]
34287#[cfg_attr(
34288 target_arch = "arm",
34289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34290)]
34291pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
34292 let b = int8x16_t::splat(-1);
34293 unsafe { simd_xor(a, b) }
34294}
34295#[doc = "Vector bitwise not."]
34296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
34297#[inline]
34298#[target_feature(enable = "neon")]
34299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34301#[cfg_attr(
34302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34303 assert_instr(mvn)
34304)]
34305#[cfg_attr(
34306 not(target_arch = "arm"),
34307 stable(feature = "neon_intrinsics", since = "1.59.0")
34308)]
34309#[cfg_attr(
34310 target_arch = "arm",
34311 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34312)]
34313pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
34314 let b = uint16x8_t::splat(65_535);
34315 unsafe { simd_xor(a, b) }
34316}
34317#[doc = "Vector bitwise not."]
34318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
34319#[inline]
34320#[target_feature(enable = "neon")]
34321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34323#[cfg_attr(
34324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34325 assert_instr(mvn)
34326)]
34327#[cfg_attr(
34328 not(target_arch = "arm"),
34329 stable(feature = "neon_intrinsics", since = "1.59.0")
34330)]
34331#[cfg_attr(
34332 target_arch = "arm",
34333 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34334)]
34335pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
34336 let b = uint32x4_t::splat(4_294_967_295);
34337 unsafe { simd_xor(a, b) }
34338}
34339#[doc = "Vector bitwise not."]
34340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
34341#[inline]
34342#[target_feature(enable = "neon")]
34343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
34345#[cfg_attr(
34346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34347 assert_instr(mvn)
34348)]
34349#[cfg_attr(
34350 not(target_arch = "arm"),
34351 stable(feature = "neon_intrinsics", since = "1.59.0")
34352)]
34353#[cfg_attr(
34354 target_arch = "arm",
34355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34356)]
34357pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
34358 let b = uint8x16_t::splat(255);
34359 unsafe { simd_xor(a, b) }
34360}
34361#[doc = "Negate"]
34362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
34363#[inline]
34364#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34365#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34366#[cfg_attr(
34367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34368 assert_instr(fneg)
34369)]
34370#[target_feature(enable = "neon,fp16")]
34371#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34372pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
34373 unsafe { simd_neg(a) }
34374}
34375#[doc = "Negate"]
34376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
34377#[inline]
34378#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
34379#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
34380#[cfg_attr(
34381 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34382 assert_instr(fneg)
34383)]
34384#[target_feature(enable = "neon,fp16")]
34385#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
34386pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
34387 unsafe { simd_neg(a) }
34388}
34389#[doc = "Negate"]
34390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
34391#[inline]
34392#[target_feature(enable = "neon")]
34393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34394#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34395#[cfg_attr(
34396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34397 assert_instr(fneg)
34398)]
34399#[cfg_attr(
34400 not(target_arch = "arm"),
34401 stable(feature = "neon_intrinsics", since = "1.59.0")
34402)]
34403#[cfg_attr(
34404 target_arch = "arm",
34405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34406)]
34407pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
34408 unsafe { simd_neg(a) }
34409}
34410#[doc = "Negate"]
34411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
34412#[inline]
34413#[target_feature(enable = "neon")]
34414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34415#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
34416#[cfg_attr(
34417 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34418 assert_instr(fneg)
34419)]
34420#[cfg_attr(
34421 not(target_arch = "arm"),
34422 stable(feature = "neon_intrinsics", since = "1.59.0")
34423)]
34424#[cfg_attr(
34425 target_arch = "arm",
34426 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34427)]
34428pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
34429 unsafe { simd_neg(a) }
34430}
34431#[doc = "Negate"]
34432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
34433#[inline]
34434#[target_feature(enable = "neon")]
34435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34436#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34437#[cfg_attr(
34438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34439 assert_instr(neg)
34440)]
34441#[cfg_attr(
34442 not(target_arch = "arm"),
34443 stable(feature = "neon_intrinsics", since = "1.59.0")
34444)]
34445#[cfg_attr(
34446 target_arch = "arm",
34447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34448)]
34449pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
34450 unsafe { simd_neg(a) }
34451}
34452#[doc = "Negate"]
34453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
34454#[inline]
34455#[target_feature(enable = "neon")]
34456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34457#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
34458#[cfg_attr(
34459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34460 assert_instr(neg)
34461)]
34462#[cfg_attr(
34463 not(target_arch = "arm"),
34464 stable(feature = "neon_intrinsics", since = "1.59.0")
34465)]
34466#[cfg_attr(
34467 target_arch = "arm",
34468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34469)]
34470pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
34471 unsafe { simd_neg(a) }
34472}
34473#[doc = "Negate"]
34474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
34475#[inline]
34476#[target_feature(enable = "neon")]
34477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34478#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34479#[cfg_attr(
34480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34481 assert_instr(neg)
34482)]
34483#[cfg_attr(
34484 not(target_arch = "arm"),
34485 stable(feature = "neon_intrinsics", since = "1.59.0")
34486)]
34487#[cfg_attr(
34488 target_arch = "arm",
34489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34490)]
34491pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
34492 unsafe { simd_neg(a) }
34493}
34494#[doc = "Negate"]
34495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
34496#[inline]
34497#[target_feature(enable = "neon")]
34498#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34499#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
34500#[cfg_attr(
34501 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34502 assert_instr(neg)
34503)]
34504#[cfg_attr(
34505 not(target_arch = "arm"),
34506 stable(feature = "neon_intrinsics", since = "1.59.0")
34507)]
34508#[cfg_attr(
34509 target_arch = "arm",
34510 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34511)]
34512pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
34513 unsafe { simd_neg(a) }
34514}
34515#[doc = "Negate"]
34516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
34517#[inline]
34518#[target_feature(enable = "neon")]
34519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34520#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34521#[cfg_attr(
34522 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34523 assert_instr(neg)
34524)]
34525#[cfg_attr(
34526 not(target_arch = "arm"),
34527 stable(feature = "neon_intrinsics", since = "1.59.0")
34528)]
34529#[cfg_attr(
34530 target_arch = "arm",
34531 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34532)]
34533pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
34534 unsafe { simd_neg(a) }
34535}
34536#[doc = "Negate"]
34537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
34538#[inline]
34539#[target_feature(enable = "neon")]
34540#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34541#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
34542#[cfg_attr(
34543 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34544 assert_instr(neg)
34545)]
34546#[cfg_attr(
34547 not(target_arch = "arm"),
34548 stable(feature = "neon_intrinsics", since = "1.59.0")
34549)]
34550#[cfg_attr(
34551 target_arch = "arm",
34552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34553)]
34554pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
34555 unsafe { simd_neg(a) }
34556}
34557#[doc = "Vector bitwise inclusive OR NOT"]
34558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
34559#[inline]
34560#[target_feature(enable = "neon")]
34561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34563#[cfg_attr(
34564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34565 assert_instr(orn)
34566)]
34567#[cfg_attr(
34568 not(target_arch = "arm"),
34569 stable(feature = "neon_intrinsics", since = "1.59.0")
34570)]
34571#[cfg_attr(
34572 target_arch = "arm",
34573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34574)]
34575pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
34576 let c = int16x4_t::splat(-1);
34577 unsafe { simd_or(simd_xor(b, c), a) }
34578}
34579#[doc = "Vector bitwise inclusive OR NOT"]
34580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
34581#[inline]
34582#[target_feature(enable = "neon")]
34583#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34584#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34585#[cfg_attr(
34586 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34587 assert_instr(orn)
34588)]
34589#[cfg_attr(
34590 not(target_arch = "arm"),
34591 stable(feature = "neon_intrinsics", since = "1.59.0")
34592)]
34593#[cfg_attr(
34594 target_arch = "arm",
34595 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34596)]
34597pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
34598 let c = int32x2_t::splat(-1);
34599 unsafe { simd_or(simd_xor(b, c), a) }
34600}
34601#[doc = "Vector bitwise inclusive OR NOT"]
34602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
34603#[inline]
34604#[target_feature(enable = "neon")]
34605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34606#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34607#[cfg_attr(
34608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34609 assert_instr(orn)
34610)]
34611#[cfg_attr(
34612 not(target_arch = "arm"),
34613 stable(feature = "neon_intrinsics", since = "1.59.0")
34614)]
34615#[cfg_attr(
34616 target_arch = "arm",
34617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34618)]
34619pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
34620 let c = int64x1_t::splat(-1);
34621 unsafe { simd_or(simd_xor(b, c), a) }
34622}
34623#[doc = "Vector bitwise inclusive OR NOT"]
34624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
34625#[inline]
34626#[target_feature(enable = "neon")]
34627#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34628#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34629#[cfg_attr(
34630 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34631 assert_instr(orn)
34632)]
34633#[cfg_attr(
34634 not(target_arch = "arm"),
34635 stable(feature = "neon_intrinsics", since = "1.59.0")
34636)]
34637#[cfg_attr(
34638 target_arch = "arm",
34639 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34640)]
34641pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
34642 let c = int8x8_t::splat(-1);
34643 unsafe { simd_or(simd_xor(b, c), a) }
34644}
34645#[doc = "Vector bitwise inclusive OR NOT"]
34646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
34647#[inline]
34648#[target_feature(enable = "neon")]
34649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34651#[cfg_attr(
34652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34653 assert_instr(orn)
34654)]
34655#[cfg_attr(
34656 not(target_arch = "arm"),
34657 stable(feature = "neon_intrinsics", since = "1.59.0")
34658)]
34659#[cfg_attr(
34660 target_arch = "arm",
34661 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34662)]
34663pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
34664 let c = int16x8_t::splat(-1);
34665 unsafe { simd_or(simd_xor(b, c), a) }
34666}
34667#[doc = "Vector bitwise inclusive OR NOT"]
34668#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
34669#[inline]
34670#[target_feature(enable = "neon")]
34671#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34672#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34673#[cfg_attr(
34674 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34675 assert_instr(orn)
34676)]
34677#[cfg_attr(
34678 not(target_arch = "arm"),
34679 stable(feature = "neon_intrinsics", since = "1.59.0")
34680)]
34681#[cfg_attr(
34682 target_arch = "arm",
34683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34684)]
34685pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
34686 let c = int32x4_t::splat(-1);
34687 unsafe { simd_or(simd_xor(b, c), a) }
34688}
34689#[doc = "Vector bitwise inclusive OR NOT"]
34690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
34691#[inline]
34692#[target_feature(enable = "neon")]
34693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34695#[cfg_attr(
34696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34697 assert_instr(orn)
34698)]
34699#[cfg_attr(
34700 not(target_arch = "arm"),
34701 stable(feature = "neon_intrinsics", since = "1.59.0")
34702)]
34703#[cfg_attr(
34704 target_arch = "arm",
34705 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34706)]
34707pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
34708 let c = int64x2_t::splat(-1);
34709 unsafe { simd_or(simd_xor(b, c), a) }
34710}
34711#[doc = "Vector bitwise inclusive OR NOT"]
34712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
34713#[inline]
34714#[target_feature(enable = "neon")]
34715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34717#[cfg_attr(
34718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34719 assert_instr(orn)
34720)]
34721#[cfg_attr(
34722 not(target_arch = "arm"),
34723 stable(feature = "neon_intrinsics", since = "1.59.0")
34724)]
34725#[cfg_attr(
34726 target_arch = "arm",
34727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34728)]
34729pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
34730 let c = int8x16_t::splat(-1);
34731 unsafe { simd_or(simd_xor(b, c), a) }
34732}
34733#[doc = "Vector bitwise inclusive OR NOT"]
34734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
34735#[inline]
34736#[target_feature(enable = "neon")]
34737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34739#[cfg_attr(
34740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34741 assert_instr(orn)
34742)]
34743#[cfg_attr(
34744 not(target_arch = "arm"),
34745 stable(feature = "neon_intrinsics", since = "1.59.0")
34746)]
34747#[cfg_attr(
34748 target_arch = "arm",
34749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34750)]
34751pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
34752 let c = int16x4_t::splat(-1);
34753 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34754}
34755#[doc = "Vector bitwise inclusive OR NOT"]
34756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
34757#[inline]
34758#[target_feature(enable = "neon")]
34759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34761#[cfg_attr(
34762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34763 assert_instr(orn)
34764)]
34765#[cfg_attr(
34766 not(target_arch = "arm"),
34767 stable(feature = "neon_intrinsics", since = "1.59.0")
34768)]
34769#[cfg_attr(
34770 target_arch = "arm",
34771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34772)]
34773pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
34774 let c = int32x2_t::splat(-1);
34775 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34776}
34777#[doc = "Vector bitwise inclusive OR NOT"]
34778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
34779#[inline]
34780#[target_feature(enable = "neon")]
34781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34783#[cfg_attr(
34784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34785 assert_instr(orn)
34786)]
34787#[cfg_attr(
34788 not(target_arch = "arm"),
34789 stable(feature = "neon_intrinsics", since = "1.59.0")
34790)]
34791#[cfg_attr(
34792 target_arch = "arm",
34793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34794)]
34795pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
34796 let c = int64x1_t::splat(-1);
34797 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34798}
34799#[doc = "Vector bitwise inclusive OR NOT"]
34800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
34801#[inline]
34802#[target_feature(enable = "neon")]
34803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34805#[cfg_attr(
34806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34807 assert_instr(orn)
34808)]
34809#[cfg_attr(
34810 not(target_arch = "arm"),
34811 stable(feature = "neon_intrinsics", since = "1.59.0")
34812)]
34813#[cfg_attr(
34814 target_arch = "arm",
34815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34816)]
34817pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
34818 let c = int8x8_t::splat(-1);
34819 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34820}
34821#[doc = "Vector bitwise inclusive OR NOT"]
34822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
34823#[inline]
34824#[target_feature(enable = "neon")]
34825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34827#[cfg_attr(
34828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34829 assert_instr(orn)
34830)]
34831#[cfg_attr(
34832 not(target_arch = "arm"),
34833 stable(feature = "neon_intrinsics", since = "1.59.0")
34834)]
34835#[cfg_attr(
34836 target_arch = "arm",
34837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34838)]
34839pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
34840 let c = int16x8_t::splat(-1);
34841 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34842}
34843#[doc = "Vector bitwise inclusive OR NOT"]
34844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
34845#[inline]
34846#[target_feature(enable = "neon")]
34847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34849#[cfg_attr(
34850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34851 assert_instr(orn)
34852)]
34853#[cfg_attr(
34854 not(target_arch = "arm"),
34855 stable(feature = "neon_intrinsics", since = "1.59.0")
34856)]
34857#[cfg_attr(
34858 target_arch = "arm",
34859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34860)]
34861pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
34862 let c = int32x4_t::splat(-1);
34863 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34864}
34865#[doc = "Vector bitwise inclusive OR NOT"]
34866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
34867#[inline]
34868#[target_feature(enable = "neon")]
34869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34871#[cfg_attr(
34872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34873 assert_instr(orn)
34874)]
34875#[cfg_attr(
34876 not(target_arch = "arm"),
34877 stable(feature = "neon_intrinsics", since = "1.59.0")
34878)]
34879#[cfg_attr(
34880 target_arch = "arm",
34881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34882)]
34883pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
34884 let c = int64x2_t::splat(-1);
34885 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34886}
34887#[doc = "Vector bitwise inclusive OR NOT"]
34888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
34889#[inline]
34890#[target_feature(enable = "neon")]
34891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
34893#[cfg_attr(
34894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34895 assert_instr(orn)
34896)]
34897#[cfg_attr(
34898 not(target_arch = "arm"),
34899 stable(feature = "neon_intrinsics", since = "1.59.0")
34900)]
34901#[cfg_attr(
34902 target_arch = "arm",
34903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34904)]
34905pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
34906 let c = int8x16_t::splat(-1);
34907 unsafe { simd_or(simd_xor(b, transmute(c)), a) }
34908}
34909#[doc = "Vector bitwise or (immediate, inclusive)"]
34910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
34911#[inline]
34912#[target_feature(enable = "neon")]
34913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34914#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
34915#[cfg_attr(
34916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34917 assert_instr(orr)
34918)]
34919#[cfg_attr(
34920 not(target_arch = "arm"),
34921 stable(feature = "neon_intrinsics", since = "1.59.0")
34922)]
34923#[cfg_attr(
34924 target_arch = "arm",
34925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34926)]
34927pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
34928 unsafe { simd_or(a, b) }
34929}
34930#[doc = "Vector bitwise or (immediate, inclusive)"]
34931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
34932#[inline]
34933#[target_feature(enable = "neon")]
34934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
34936#[cfg_attr(
34937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34938 assert_instr(orr)
34939)]
34940#[cfg_attr(
34941 not(target_arch = "arm"),
34942 stable(feature = "neon_intrinsics", since = "1.59.0")
34943)]
34944#[cfg_attr(
34945 target_arch = "arm",
34946 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34947)]
34948pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
34949 unsafe { simd_or(a, b) }
34950}
34951#[doc = "Vector bitwise or (immediate, inclusive)"]
34952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
34953#[inline]
34954#[target_feature(enable = "neon")]
34955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
34957#[cfg_attr(
34958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34959 assert_instr(orr)
34960)]
34961#[cfg_attr(
34962 not(target_arch = "arm"),
34963 stable(feature = "neon_intrinsics", since = "1.59.0")
34964)]
34965#[cfg_attr(
34966 target_arch = "arm",
34967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34968)]
34969pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
34970 unsafe { simd_or(a, b) }
34971}
34972#[doc = "Vector bitwise or (immediate, inclusive)"]
34973#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
34974#[inline]
34975#[target_feature(enable = "neon")]
34976#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34977#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
34978#[cfg_attr(
34979 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
34980 assert_instr(orr)
34981)]
34982#[cfg_attr(
34983 not(target_arch = "arm"),
34984 stable(feature = "neon_intrinsics", since = "1.59.0")
34985)]
34986#[cfg_attr(
34987 target_arch = "arm",
34988 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
34989)]
34990pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
34991 unsafe { simd_or(a, b) }
34992}
34993#[doc = "Vector bitwise or (immediate, inclusive)"]
34994#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
34995#[inline]
34996#[target_feature(enable = "neon")]
34997#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
34998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
34999#[cfg_attr(
35000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35001 assert_instr(orr)
35002)]
35003#[cfg_attr(
35004 not(target_arch = "arm"),
35005 stable(feature = "neon_intrinsics", since = "1.59.0")
35006)]
35007#[cfg_attr(
35008 target_arch = "arm",
35009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35010)]
35011pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35012 unsafe { simd_or(a, b) }
35013}
35014#[doc = "Vector bitwise or (immediate, inclusive)"]
35015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
35016#[inline]
35017#[target_feature(enable = "neon")]
35018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35020#[cfg_attr(
35021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35022 assert_instr(orr)
35023)]
35024#[cfg_attr(
35025 not(target_arch = "arm"),
35026 stable(feature = "neon_intrinsics", since = "1.59.0")
35027)]
35028#[cfg_attr(
35029 target_arch = "arm",
35030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35031)]
35032pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
35033 unsafe { simd_or(a, b) }
35034}
35035#[doc = "Vector bitwise or (immediate, inclusive)"]
35036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
35037#[inline]
35038#[target_feature(enable = "neon")]
35039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35041#[cfg_attr(
35042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35043 assert_instr(orr)
35044)]
35045#[cfg_attr(
35046 not(target_arch = "arm"),
35047 stable(feature = "neon_intrinsics", since = "1.59.0")
35048)]
35049#[cfg_attr(
35050 target_arch = "arm",
35051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35052)]
35053pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
35054 unsafe { simd_or(a, b) }
35055}
35056#[doc = "Vector bitwise or (immediate, inclusive)"]
35057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
35058#[inline]
35059#[target_feature(enable = "neon")]
35060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35061#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35062#[cfg_attr(
35063 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35064 assert_instr(orr)
35065)]
35066#[cfg_attr(
35067 not(target_arch = "arm"),
35068 stable(feature = "neon_intrinsics", since = "1.59.0")
35069)]
35070#[cfg_attr(
35071 target_arch = "arm",
35072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35073)]
35074pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
35075 unsafe { simd_or(a, b) }
35076}
35077#[doc = "Vector bitwise or (immediate, inclusive)"]
35078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
35079#[inline]
35080#[target_feature(enable = "neon")]
35081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35083#[cfg_attr(
35084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35085 assert_instr(orr)
35086)]
35087#[cfg_attr(
35088 not(target_arch = "arm"),
35089 stable(feature = "neon_intrinsics", since = "1.59.0")
35090)]
35091#[cfg_attr(
35092 target_arch = "arm",
35093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35094)]
35095pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35096 unsafe { simd_or(a, b) }
35097}
35098#[doc = "Vector bitwise or (immediate, inclusive)"]
35099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
35100#[inline]
35101#[target_feature(enable = "neon")]
35102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35104#[cfg_attr(
35105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35106 assert_instr(orr)
35107)]
35108#[cfg_attr(
35109 not(target_arch = "arm"),
35110 stable(feature = "neon_intrinsics", since = "1.59.0")
35111)]
35112#[cfg_attr(
35113 target_arch = "arm",
35114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35115)]
35116pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
35117 unsafe { simd_or(a, b) }
35118}
35119#[doc = "Vector bitwise or (immediate, inclusive)"]
35120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
35121#[inline]
35122#[target_feature(enable = "neon")]
35123#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35124#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35125#[cfg_attr(
35126 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35127 assert_instr(orr)
35128)]
35129#[cfg_attr(
35130 not(target_arch = "arm"),
35131 stable(feature = "neon_intrinsics", since = "1.59.0")
35132)]
35133#[cfg_attr(
35134 target_arch = "arm",
35135 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35136)]
35137pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35138 unsafe { simd_or(a, b) }
35139}
35140#[doc = "Vector bitwise or (immediate, inclusive)"]
35141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
35142#[inline]
35143#[target_feature(enable = "neon")]
35144#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35145#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35146#[cfg_attr(
35147 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35148 assert_instr(orr)
35149)]
35150#[cfg_attr(
35151 not(target_arch = "arm"),
35152 stable(feature = "neon_intrinsics", since = "1.59.0")
35153)]
35154#[cfg_attr(
35155 target_arch = "arm",
35156 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35157)]
35158pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
35159 unsafe { simd_or(a, b) }
35160}
35161#[doc = "Vector bitwise or (immediate, inclusive)"]
35162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
35163#[inline]
35164#[target_feature(enable = "neon")]
35165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35167#[cfg_attr(
35168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35169 assert_instr(orr)
35170)]
35171#[cfg_attr(
35172 not(target_arch = "arm"),
35173 stable(feature = "neon_intrinsics", since = "1.59.0")
35174)]
35175#[cfg_attr(
35176 target_arch = "arm",
35177 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35178)]
35179pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35180 unsafe { simd_or(a, b) }
35181}
35182#[doc = "Vector bitwise or (immediate, inclusive)"]
35183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
35184#[inline]
35185#[target_feature(enable = "neon")]
35186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35188#[cfg_attr(
35189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35190 assert_instr(orr)
35191)]
35192#[cfg_attr(
35193 not(target_arch = "arm"),
35194 stable(feature = "neon_intrinsics", since = "1.59.0")
35195)]
35196#[cfg_attr(
35197 target_arch = "arm",
35198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35199)]
35200pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
35201 unsafe { simd_or(a, b) }
35202}
35203#[doc = "Vector bitwise or (immediate, inclusive)"]
35204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
35205#[inline]
35206#[target_feature(enable = "neon")]
35207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35209#[cfg_attr(
35210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35211 assert_instr(orr)
35212)]
35213#[cfg_attr(
35214 not(target_arch = "arm"),
35215 stable(feature = "neon_intrinsics", since = "1.59.0")
35216)]
35217#[cfg_attr(
35218 target_arch = "arm",
35219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35220)]
35221pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
35222 unsafe { simd_or(a, b) }
35223}
35224#[doc = "Vector bitwise or (immediate, inclusive)"]
35225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
35226#[inline]
35227#[target_feature(enable = "neon")]
35228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
35230#[cfg_attr(
35231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35232 assert_instr(orr)
35233)]
35234#[cfg_attr(
35235 not(target_arch = "arm"),
35236 stable(feature = "neon_intrinsics", since = "1.59.0")
35237)]
35238#[cfg_attr(
35239 target_arch = "arm",
35240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35241)]
35242pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
35243 unsafe { simd_or(a, b) }
35244}
35245#[doc = "Signed Add and Accumulate Long Pairwise."]
35246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
35247#[inline]
35248#[target_feature(enable = "neon")]
35249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35250#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35251#[cfg_attr(
35252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35253 assert_instr(sadalp)
35254)]
35255#[cfg_attr(
35256 not(target_arch = "arm"),
35257 stable(feature = "neon_intrinsics", since = "1.59.0")
35258)]
35259#[cfg_attr(
35260 target_arch = "arm",
35261 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35262)]
35263pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
35264 let x: int16x4_t;
35265 #[cfg(target_arch = "arm")]
35266 {
35267 x = priv_vpadal_s8(a, b);
35268 }
35269 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35270 unsafe {
35271 x = simd_add(vpaddl_s8(b), a);
35272 };
35273 x
35274}
35275#[doc = "Signed Add and Accumulate Long Pairwise."]
35276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
35277#[inline]
35278#[target_feature(enable = "neon")]
35279#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35280#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
35281#[cfg_attr(
35282 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35283 assert_instr(sadalp)
35284)]
35285#[cfg_attr(
35286 not(target_arch = "arm"),
35287 stable(feature = "neon_intrinsics", since = "1.59.0")
35288)]
35289#[cfg_attr(
35290 target_arch = "arm",
35291 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35292)]
35293pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
35294 let x: int16x8_t;
35295 #[cfg(target_arch = "arm")]
35296 {
35297 x = priv_vpadalq_s8(a, b);
35298 }
35299 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35300 unsafe {
35301 x = simd_add(vpaddlq_s8(b), a);
35302 };
35303 x
35304}
35305#[doc = "Signed Add and Accumulate Long Pairwise."]
35306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
35307#[inline]
35308#[target_feature(enable = "neon")]
35309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35310#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35311#[cfg_attr(
35312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35313 assert_instr(sadalp)
35314)]
35315#[cfg_attr(
35316 not(target_arch = "arm"),
35317 stable(feature = "neon_intrinsics", since = "1.59.0")
35318)]
35319#[cfg_attr(
35320 target_arch = "arm",
35321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35322)]
35323pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
35324 let x: int32x2_t;
35325 #[cfg(target_arch = "arm")]
35326 {
35327 x = priv_vpadal_s16(a, b);
35328 }
35329 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35330 unsafe {
35331 x = simd_add(vpaddl_s16(b), a);
35332 };
35333 x
35334}
35335#[doc = "Signed Add and Accumulate Long Pairwise."]
35336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
35337#[inline]
35338#[target_feature(enable = "neon")]
35339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35340#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
35341#[cfg_attr(
35342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35343 assert_instr(sadalp)
35344)]
35345#[cfg_attr(
35346 not(target_arch = "arm"),
35347 stable(feature = "neon_intrinsics", since = "1.59.0")
35348)]
35349#[cfg_attr(
35350 target_arch = "arm",
35351 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35352)]
35353pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
35354 let x: int32x4_t;
35355 #[cfg(target_arch = "arm")]
35356 {
35357 x = priv_vpadalq_s16(a, b);
35358 }
35359 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35360 unsafe {
35361 x = simd_add(vpaddlq_s16(b), a);
35362 };
35363 x
35364}
35365#[doc = "Signed Add and Accumulate Long Pairwise."]
35366#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
35367#[inline]
35368#[target_feature(enable = "neon")]
35369#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35370#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35371#[cfg_attr(
35372 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35373 assert_instr(sadalp)
35374)]
35375#[cfg_attr(
35376 not(target_arch = "arm"),
35377 stable(feature = "neon_intrinsics", since = "1.59.0")
35378)]
35379#[cfg_attr(
35380 target_arch = "arm",
35381 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35382)]
35383pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
35384 let x: int64x1_t;
35385 #[cfg(target_arch = "arm")]
35386 {
35387 x = priv_vpadal_s32(a, b);
35388 }
35389 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35390 unsafe {
35391 x = simd_add(vpaddl_s32(b), a);
35392 };
35393 x
35394}
35395#[doc = "Signed Add and Accumulate Long Pairwise."]
35396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
35397#[inline]
35398#[target_feature(enable = "neon")]
35399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35400#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
35401#[cfg_attr(
35402 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35403 assert_instr(sadalp)
35404)]
35405#[cfg_attr(
35406 not(target_arch = "arm"),
35407 stable(feature = "neon_intrinsics", since = "1.59.0")
35408)]
35409#[cfg_attr(
35410 target_arch = "arm",
35411 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35412)]
35413pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
35414 let x: int64x2_t;
35415 #[cfg(target_arch = "arm")]
35416 {
35417 x = priv_vpadalq_s32(a, b);
35418 }
35419 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35420 unsafe {
35421 x = simd_add(vpaddlq_s32(b), a);
35422 };
35423 x
35424}
35425#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
35427#[inline]
35428#[target_feature(enable = "neon")]
35429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35430#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35431#[cfg_attr(
35432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35433 assert_instr(uadalp)
35434)]
35435#[cfg_attr(
35436 not(target_arch = "arm"),
35437 stable(feature = "neon_intrinsics", since = "1.59.0")
35438)]
35439#[cfg_attr(
35440 target_arch = "arm",
35441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35442)]
35443pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
35444 let x: uint16x4_t;
35445 #[cfg(target_arch = "arm")]
35446 {
35447 x = priv_vpadal_u8(a, b);
35448 }
35449 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35450 unsafe {
35451 x = simd_add(vpaddl_u8(b), a);
35452 };
35453 x
35454}
35455#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35456#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
35457#[inline]
35458#[target_feature(enable = "neon")]
35459#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35460#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
35461#[cfg_attr(
35462 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35463 assert_instr(uadalp)
35464)]
35465#[cfg_attr(
35466 not(target_arch = "arm"),
35467 stable(feature = "neon_intrinsics", since = "1.59.0")
35468)]
35469#[cfg_attr(
35470 target_arch = "arm",
35471 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35472)]
35473pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
35474 let x: uint16x8_t;
35475 #[cfg(target_arch = "arm")]
35476 {
35477 x = priv_vpadalq_u8(a, b);
35478 }
35479 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35480 unsafe {
35481 x = simd_add(vpaddlq_u8(b), a);
35482 };
35483 x
35484}
35485#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
35487#[inline]
35488#[target_feature(enable = "neon")]
35489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35490#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35491#[cfg_attr(
35492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35493 assert_instr(uadalp)
35494)]
35495#[cfg_attr(
35496 not(target_arch = "arm"),
35497 stable(feature = "neon_intrinsics", since = "1.59.0")
35498)]
35499#[cfg_attr(
35500 target_arch = "arm",
35501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35502)]
35503pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
35504 let x: uint32x2_t;
35505 #[cfg(target_arch = "arm")]
35506 {
35507 x = priv_vpadal_u16(a, b);
35508 }
35509 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35510 unsafe {
35511 x = simd_add(vpaddl_u16(b), a);
35512 };
35513 x
35514}
35515#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35516#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
35517#[inline]
35518#[target_feature(enable = "neon")]
35519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35520#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
35521#[cfg_attr(
35522 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35523 assert_instr(uadalp)
35524)]
35525#[cfg_attr(
35526 not(target_arch = "arm"),
35527 stable(feature = "neon_intrinsics", since = "1.59.0")
35528)]
35529#[cfg_attr(
35530 target_arch = "arm",
35531 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35532)]
35533pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
35534 let x: uint32x4_t;
35535 #[cfg(target_arch = "arm")]
35536 {
35537 x = priv_vpadalq_u16(a, b);
35538 }
35539 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35540 unsafe {
35541 x = simd_add(vpaddlq_u16(b), a);
35542 };
35543 x
35544}
35545#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
35547#[inline]
35548#[target_feature(enable = "neon")]
35549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35550#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35551#[cfg_attr(
35552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35553 assert_instr(uadalp)
35554)]
35555#[cfg_attr(
35556 not(target_arch = "arm"),
35557 stable(feature = "neon_intrinsics", since = "1.59.0")
35558)]
35559#[cfg_attr(
35560 target_arch = "arm",
35561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35562)]
35563pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
35564 let x: uint64x1_t;
35565 #[cfg(target_arch = "arm")]
35566 {
35567 x = priv_vpadal_u32(a, b);
35568 }
35569 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35570 unsafe {
35571 x = simd_add(vpaddl_u32(b), a);
35572 };
35573 x
35574}
35575#[doc = "Unsigned Add and Accumulate Long Pairwise."]
35576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
35577#[inline]
35578#[target_feature(enable = "neon")]
35579#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35580#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
35581#[cfg_attr(
35582 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35583 assert_instr(uadalp)
35584)]
35585#[cfg_attr(
35586 not(target_arch = "arm"),
35587 stable(feature = "neon_intrinsics", since = "1.59.0")
35588)]
35589#[cfg_attr(
35590 target_arch = "arm",
35591 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35592)]
35593pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
35594 let x: uint64x2_t;
35595 #[cfg(target_arch = "arm")]
35596 {
35597 x = priv_vpadalq_u32(a, b);
35598 }
35599 #[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
35600 unsafe {
35601 x = simd_add(vpaddlq_u32(b), a);
35602 };
35603 x
35604}
35605#[doc = "Floating-point add pairwise"]
35606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
35607#[inline]
35608#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
35609#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35610#[cfg_attr(
35611 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35612 assert_instr(faddp)
35613)]
35614#[target_feature(enable = "neon,fp16")]
35615#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
35616pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
35617 unsafe extern "unadjusted" {
35618 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4f16")]
35619 #[cfg_attr(
35620 any(target_arch = "aarch64", target_arch = "arm64ec"),
35621 link_name = "llvm.aarch64.neon.faddp.v4f16"
35622 )]
35623 fn _vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
35624 }
35625 unsafe { _vpadd_f16(a, b) }
35626}
35627#[doc = "Floating-point add pairwise"]
35628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
35629#[inline]
35630#[target_feature(enable = "neon")]
35631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35633#[cfg_attr(
35634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35635 assert_instr(faddp)
35636)]
35637#[cfg_attr(
35638 not(target_arch = "arm"),
35639 stable(feature = "neon_intrinsics", since = "1.59.0")
35640)]
35641#[cfg_attr(
35642 target_arch = "arm",
35643 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35644)]
35645pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
35646 unsafe extern "unadjusted" {
35647 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")]
35648 #[cfg_attr(
35649 any(target_arch = "aarch64", target_arch = "arm64ec"),
35650 link_name = "llvm.aarch64.neon.faddp.v2f32"
35651 )]
35652 fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
35653 }
35654 unsafe { _vpadd_f32(a, b) }
35655}
35656#[doc = "Add pairwise."]
35657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
35658#[inline]
35659#[target_feature(enable = "neon")]
35660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35662#[cfg_attr(
35663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35664 assert_instr(addp)
35665)]
35666#[cfg_attr(
35667 not(target_arch = "arm"),
35668 stable(feature = "neon_intrinsics", since = "1.59.0")
35669)]
35670#[cfg_attr(
35671 target_arch = "arm",
35672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35673)]
35674pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
35675 unsafe extern "unadjusted" {
35676 #[cfg_attr(
35677 any(target_arch = "aarch64", target_arch = "arm64ec"),
35678 link_name = "llvm.aarch64.neon.addp.v8i8"
35679 )]
35680 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v8i8")]
35681 fn _vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
35682 }
35683 unsafe { _vpadd_s8(a, b) }
35684}
35685#[doc = "Add pairwise."]
35686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
35687#[inline]
35688#[target_feature(enable = "neon")]
35689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35691#[cfg_attr(
35692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35693 assert_instr(addp)
35694)]
35695#[cfg_attr(
35696 not(target_arch = "arm"),
35697 stable(feature = "neon_intrinsics", since = "1.59.0")
35698)]
35699#[cfg_attr(
35700 target_arch = "arm",
35701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35702)]
35703pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
35704 unsafe extern "unadjusted" {
35705 #[cfg_attr(
35706 any(target_arch = "aarch64", target_arch = "arm64ec"),
35707 link_name = "llvm.aarch64.neon.addp.v4i16"
35708 )]
35709 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v4i16")]
35710 fn _vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
35711 }
35712 unsafe { _vpadd_s16(a, b) }
35713}
35714#[doc = "Add pairwise."]
35715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
35716#[inline]
35717#[target_feature(enable = "neon")]
35718#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35720#[cfg_attr(
35721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35722 assert_instr(addp)
35723)]
35724#[cfg_attr(
35725 not(target_arch = "arm"),
35726 stable(feature = "neon_intrinsics", since = "1.59.0")
35727)]
35728#[cfg_attr(
35729 target_arch = "arm",
35730 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35731)]
35732pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
35733 unsafe extern "unadjusted" {
35734 #[cfg_attr(
35735 any(target_arch = "aarch64", target_arch = "arm64ec"),
35736 link_name = "llvm.aarch64.neon.addp.v2i32"
35737 )]
35738 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2i32")]
35739 fn _vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
35740 }
35741 unsafe { _vpadd_s32(a, b) }
35742}
35743#[doc = "Add pairwise."]
35744#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
35745#[inline]
35746#[cfg(target_endian = "little")]
35747#[target_feature(enable = "neon")]
35748#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35749#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35750#[cfg_attr(
35751 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35752 assert_instr(addp)
35753)]
35754#[cfg_attr(
35755 not(target_arch = "arm"),
35756 stable(feature = "neon_intrinsics", since = "1.59.0")
35757)]
35758#[cfg_attr(
35759 target_arch = "arm",
35760 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35761)]
35762pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35763 unsafe { transmute(vpadd_s8(transmute(a), transmute(b))) }
35764}
35765#[doc = "Add pairwise."]
35766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
35767#[inline]
35768#[cfg(target_endian = "big")]
35769#[target_feature(enable = "neon")]
35770#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35771#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35772#[cfg_attr(
35773 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35774 assert_instr(addp)
35775)]
35776#[cfg_attr(
35777 not(target_arch = "arm"),
35778 stable(feature = "neon_intrinsics", since = "1.59.0")
35779)]
35780#[cfg_attr(
35781 target_arch = "arm",
35782 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35783)]
35784pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
35785 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
35786 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
35787 unsafe {
35788 let ret_val: uint8x8_t = transmute(vpadd_s8(transmute(a), transmute(b)));
35789 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
35790 }
35791}
35792#[doc = "Add pairwise."]
35793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
35794#[inline]
35795#[cfg(target_endian = "little")]
35796#[target_feature(enable = "neon")]
35797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35799#[cfg_attr(
35800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35801 assert_instr(addp)
35802)]
35803#[cfg_attr(
35804 not(target_arch = "arm"),
35805 stable(feature = "neon_intrinsics", since = "1.59.0")
35806)]
35807#[cfg_attr(
35808 target_arch = "arm",
35809 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35810)]
35811pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35812 unsafe { transmute(vpadd_s16(transmute(a), transmute(b))) }
35813}
35814#[doc = "Add pairwise."]
35815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
35816#[inline]
35817#[cfg(target_endian = "big")]
35818#[target_feature(enable = "neon")]
35819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35821#[cfg_attr(
35822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35823 assert_instr(addp)
35824)]
35825#[cfg_attr(
35826 not(target_arch = "arm"),
35827 stable(feature = "neon_intrinsics", since = "1.59.0")
35828)]
35829#[cfg_attr(
35830 target_arch = "arm",
35831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35832)]
35833pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
35834 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
35835 let b: uint16x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
35836 unsafe {
35837 let ret_val: uint16x4_t = transmute(vpadd_s16(transmute(a), transmute(b)));
35838 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
35839 }
35840}
35841#[doc = "Add pairwise."]
35842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
35843#[inline]
35844#[cfg(target_endian = "little")]
35845#[target_feature(enable = "neon")]
35846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35848#[cfg_attr(
35849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35850 assert_instr(addp)
35851)]
35852#[cfg_attr(
35853 not(target_arch = "arm"),
35854 stable(feature = "neon_intrinsics", since = "1.59.0")
35855)]
35856#[cfg_attr(
35857 target_arch = "arm",
35858 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35859)]
35860pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35861 unsafe { transmute(vpadd_s32(transmute(a), transmute(b))) }
35862}
35863#[doc = "Add pairwise."]
35864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
35865#[inline]
35866#[cfg(target_endian = "big")]
35867#[target_feature(enable = "neon")]
35868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
35870#[cfg_attr(
35871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35872 assert_instr(addp)
35873)]
35874#[cfg_attr(
35875 not(target_arch = "arm"),
35876 stable(feature = "neon_intrinsics", since = "1.59.0")
35877)]
35878#[cfg_attr(
35879 target_arch = "arm",
35880 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35881)]
35882pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
35883 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
35884 let b: uint32x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
35885 unsafe {
35886 let ret_val: uint32x2_t = transmute(vpadd_s32(transmute(a), transmute(b)));
35887 simd_shuffle!(ret_val, ret_val, [1, 0])
35888 }
35889}
35890#[doc = "Signed Add and Accumulate Long Pairwise."]
35891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
35892#[inline]
35893#[target_feature(enable = "neon")]
35894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35895#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
35896#[cfg_attr(
35897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35898 assert_instr(saddlp)
35899)]
35900#[cfg_attr(
35901 not(target_arch = "arm"),
35902 stable(feature = "neon_intrinsics", since = "1.59.0")
35903)]
35904#[cfg_attr(
35905 target_arch = "arm",
35906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35907)]
35908pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
35909 unsafe extern "unadjusted" {
35910 #[cfg_attr(
35911 any(target_arch = "aarch64", target_arch = "arm64ec"),
35912 link_name = "llvm.aarch64.neon.saddlp.v4i16.v8i8"
35913 )]
35914 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i16.v8i8")]
35915 fn _vpaddl_s8(a: int8x8_t) -> int16x4_t;
35916 }
35917 unsafe { _vpaddl_s8(a) }
35918}
35919#[doc = "Signed Add and Accumulate Long Pairwise."]
35920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
35921#[inline]
35922#[target_feature(enable = "neon")]
35923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35924#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
35925#[cfg_attr(
35926 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35927 assert_instr(saddlp)
35928)]
35929#[cfg_attr(
35930 not(target_arch = "arm"),
35931 stable(feature = "neon_intrinsics", since = "1.59.0")
35932)]
35933#[cfg_attr(
35934 target_arch = "arm",
35935 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35936)]
35937pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
35938 unsafe extern "unadjusted" {
35939 #[cfg_attr(
35940 any(target_arch = "aarch64", target_arch = "arm64ec"),
35941 link_name = "llvm.aarch64.neon.saddlp.v8i16.v16i8"
35942 )]
35943 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v8i16.v16i8")]
35944 fn _vpaddlq_s8(a: int8x16_t) -> int16x8_t;
35945 }
35946 unsafe { _vpaddlq_s8(a) }
35947}
35948#[doc = "Signed Add and Accumulate Long Pairwise."]
35949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
35950#[inline]
35951#[target_feature(enable = "neon")]
35952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35953#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
35954#[cfg_attr(
35955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35956 assert_instr(saddlp)
35957)]
35958#[cfg_attr(
35959 not(target_arch = "arm"),
35960 stable(feature = "neon_intrinsics", since = "1.59.0")
35961)]
35962#[cfg_attr(
35963 target_arch = "arm",
35964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35965)]
35966pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
35967 unsafe extern "unadjusted" {
35968 #[cfg_attr(
35969 any(target_arch = "aarch64", target_arch = "arm64ec"),
35970 link_name = "llvm.aarch64.neon.saddlp.v2i32.v4i16"
35971 )]
35972 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i32.v4i16")]
35973 fn _vpaddl_s16(a: int16x4_t) -> int32x2_t;
35974 }
35975 unsafe { _vpaddl_s16(a) }
35976}
35977#[doc = "Signed Add and Accumulate Long Pairwise."]
35978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
35979#[inline]
35980#[target_feature(enable = "neon")]
35981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
35982#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
35983#[cfg_attr(
35984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
35985 assert_instr(saddlp)
35986)]
35987#[cfg_attr(
35988 not(target_arch = "arm"),
35989 stable(feature = "neon_intrinsics", since = "1.59.0")
35990)]
35991#[cfg_attr(
35992 target_arch = "arm",
35993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
35994)]
35995pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
35996 unsafe extern "unadjusted" {
35997 #[cfg_attr(
35998 any(target_arch = "aarch64", target_arch = "arm64ec"),
35999 link_name = "llvm.aarch64.neon.saddlp.v4i32.v8i16"
36000 )]
36001 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v4i32.v8i16")]
36002 fn _vpaddlq_s16(a: int16x8_t) -> int32x4_t;
36003 }
36004 unsafe { _vpaddlq_s16(a) }
36005}
36006#[doc = "Signed Add and Accumulate Long Pairwise."]
36007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
36008#[inline]
36009#[target_feature(enable = "neon")]
36010#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36011#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36012#[cfg_attr(
36013 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36014 assert_instr(saddlp)
36015)]
36016#[cfg_attr(
36017 not(target_arch = "arm"),
36018 stable(feature = "neon_intrinsics", since = "1.59.0")
36019)]
36020#[cfg_attr(
36021 target_arch = "arm",
36022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36023)]
36024pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
36025 unsafe extern "unadjusted" {
36026 #[cfg_attr(
36027 any(target_arch = "aarch64", target_arch = "arm64ec"),
36028 link_name = "llvm.aarch64.neon.saddlp.v1i64.v2i32"
36029 )]
36030 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v1i64.v2i32")]
36031 fn _vpaddl_s32(a: int32x2_t) -> int64x1_t;
36032 }
36033 unsafe { _vpaddl_s32(a) }
36034}
36035#[doc = "Signed Add and Accumulate Long Pairwise."]
36036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
36037#[inline]
36038#[target_feature(enable = "neon")]
36039#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36040#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
36041#[cfg_attr(
36042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36043 assert_instr(saddlp)
36044)]
36045#[cfg_attr(
36046 not(target_arch = "arm"),
36047 stable(feature = "neon_intrinsics", since = "1.59.0")
36048)]
36049#[cfg_attr(
36050 target_arch = "arm",
36051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36052)]
36053pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
36054 unsafe extern "unadjusted" {
36055 #[cfg_attr(
36056 any(target_arch = "aarch64", target_arch = "arm64ec"),
36057 link_name = "llvm.aarch64.neon.saddlp.v2i64.v4i32"
36058 )]
36059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddls.v2i64.v4i32")]
36060 fn _vpaddlq_s32(a: int32x4_t) -> int64x2_t;
36061 }
36062 unsafe { _vpaddlq_s32(a) }
36063}
36064#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
36066#[inline]
36067#[target_feature(enable = "neon")]
36068#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36069#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36070#[cfg_attr(
36071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36072 assert_instr(uaddlp)
36073)]
36074#[cfg_attr(
36075 not(target_arch = "arm"),
36076 stable(feature = "neon_intrinsics", since = "1.59.0")
36077)]
36078#[cfg_attr(
36079 target_arch = "arm",
36080 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36081)]
36082pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
36083 unsafe extern "unadjusted" {
36084 #[cfg_attr(
36085 any(target_arch = "aarch64", target_arch = "arm64ec"),
36086 link_name = "llvm.aarch64.neon.uaddlp.v4i16.v8i8"
36087 )]
36088 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i16.v8i8")]
36089 fn _vpaddl_u8(a: uint8x8_t) -> uint16x4_t;
36090 }
36091 unsafe { _vpaddl_u8(a) }
36092}
36093#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
36095#[inline]
36096#[target_feature(enable = "neon")]
36097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36098#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
36099#[cfg_attr(
36100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36101 assert_instr(uaddlp)
36102)]
36103#[cfg_attr(
36104 not(target_arch = "arm"),
36105 stable(feature = "neon_intrinsics", since = "1.59.0")
36106)]
36107#[cfg_attr(
36108 target_arch = "arm",
36109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36110)]
36111pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
36112 unsafe extern "unadjusted" {
36113 #[cfg_attr(
36114 any(target_arch = "aarch64", target_arch = "arm64ec"),
36115 link_name = "llvm.aarch64.neon.uaddlp.v8i16.v16i8"
36116 )]
36117 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v8i16.v16i8")]
36118 fn _vpaddlq_u8(a: uint8x16_t) -> uint16x8_t;
36119 }
36120 unsafe { _vpaddlq_u8(a) }
36121}
36122#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
36124#[inline]
36125#[target_feature(enable = "neon")]
36126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36127#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36128#[cfg_attr(
36129 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36130 assert_instr(uaddlp)
36131)]
36132#[cfg_attr(
36133 not(target_arch = "arm"),
36134 stable(feature = "neon_intrinsics", since = "1.59.0")
36135)]
36136#[cfg_attr(
36137 target_arch = "arm",
36138 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36139)]
36140pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
36141 unsafe extern "unadjusted" {
36142 #[cfg_attr(
36143 any(target_arch = "aarch64", target_arch = "arm64ec"),
36144 link_name = "llvm.aarch64.neon.uaddlp.v2i32.v4i16"
36145 )]
36146 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i32.v4i16")]
36147 fn _vpaddl_u16(a: uint16x4_t) -> uint32x2_t;
36148 }
36149 unsafe { _vpaddl_u16(a) }
36150}
36151#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
36153#[inline]
36154#[target_feature(enable = "neon")]
36155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36156#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
36157#[cfg_attr(
36158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36159 assert_instr(uaddlp)
36160)]
36161#[cfg_attr(
36162 not(target_arch = "arm"),
36163 stable(feature = "neon_intrinsics", since = "1.59.0")
36164)]
36165#[cfg_attr(
36166 target_arch = "arm",
36167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36168)]
36169pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
36170 unsafe extern "unadjusted" {
36171 #[cfg_attr(
36172 any(target_arch = "aarch64", target_arch = "arm64ec"),
36173 link_name = "llvm.aarch64.neon.uaddlp.v4i32.v8i16"
36174 )]
36175 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v4i32.v8i16")]
36176 fn _vpaddlq_u16(a: uint16x8_t) -> uint32x4_t;
36177 }
36178 unsafe { _vpaddlq_u16(a) }
36179}
36180#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
36182#[inline]
36183#[target_feature(enable = "neon")]
36184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36185#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36186#[cfg_attr(
36187 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36188 assert_instr(uaddlp)
36189)]
36190#[cfg_attr(
36191 not(target_arch = "arm"),
36192 stable(feature = "neon_intrinsics", since = "1.59.0")
36193)]
36194#[cfg_attr(
36195 target_arch = "arm",
36196 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36197)]
36198pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
36199 unsafe extern "unadjusted" {
36200 #[cfg_attr(
36201 any(target_arch = "aarch64", target_arch = "arm64ec"),
36202 link_name = "llvm.aarch64.neon.uaddlp.v1i64.v2i32"
36203 )]
36204 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v1i64.v2i32")]
36205 fn _vpaddl_u32(a: uint32x2_t) -> uint64x1_t;
36206 }
36207 unsafe { _vpaddl_u32(a) }
36208}
36209#[doc = "Unsigned Add and Accumulate Long Pairwise."]
36210#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
36211#[inline]
36212#[target_feature(enable = "neon")]
36213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36214#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
36215#[cfg_attr(
36216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36217 assert_instr(uaddlp)
36218)]
36219#[cfg_attr(
36220 not(target_arch = "arm"),
36221 stable(feature = "neon_intrinsics", since = "1.59.0")
36222)]
36223#[cfg_attr(
36224 target_arch = "arm",
36225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36226)]
36227pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
36228 unsafe extern "unadjusted" {
36229 #[cfg_attr(
36230 any(target_arch = "aarch64", target_arch = "arm64ec"),
36231 link_name = "llvm.aarch64.neon.uaddlp.v2i64.v4i32"
36232 )]
36233 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpaddlu.v2i64.v4i32")]
36234 fn _vpaddlq_u32(a: uint32x4_t) -> uint64x2_t;
36235 }
36236 unsafe { _vpaddlq_u32(a) }
36237}
36238#[doc = "Folding maximum of adjacent pairs"]
36239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
36240#[inline]
36241#[target_feature(enable = "neon")]
36242#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36243#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36244#[cfg_attr(
36245 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36246 assert_instr(fmaxp)
36247)]
36248#[cfg_attr(
36249 not(target_arch = "arm"),
36250 stable(feature = "neon_intrinsics", since = "1.59.0")
36251)]
36252#[cfg_attr(
36253 target_arch = "arm",
36254 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36255)]
36256pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36257 unsafe extern "unadjusted" {
36258 #[cfg_attr(
36259 any(target_arch = "aarch64", target_arch = "arm64ec"),
36260 link_name = "llvm.aarch64.neon.fmaxp.v2f32"
36261 )]
36262 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
36263 fn _vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36264 }
36265 unsafe { _vpmax_f32(a, b) }
36266}
36267#[doc = "Folding maximum of adjacent pairs"]
36268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
36269#[inline]
36270#[target_feature(enable = "neon")]
36271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36272#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36273#[cfg_attr(
36274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36275 assert_instr(smaxp)
36276)]
36277#[cfg_attr(
36278 not(target_arch = "arm"),
36279 stable(feature = "neon_intrinsics", since = "1.59.0")
36280)]
36281#[cfg_attr(
36282 target_arch = "arm",
36283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36284)]
36285pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36286 unsafe extern "unadjusted" {
36287 #[cfg_attr(
36288 any(target_arch = "aarch64", target_arch = "arm64ec"),
36289 link_name = "llvm.aarch64.neon.smaxp.v8i8"
36290 )]
36291 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v8i8")]
36292 fn _vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36293 }
36294 unsafe { _vpmax_s8(a, b) }
36295}
36296#[doc = "Folding maximum of adjacent pairs"]
36297#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
36298#[inline]
36299#[target_feature(enable = "neon")]
36300#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36301#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36302#[cfg_attr(
36303 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36304 assert_instr(smaxp)
36305)]
36306#[cfg_attr(
36307 not(target_arch = "arm"),
36308 stable(feature = "neon_intrinsics", since = "1.59.0")
36309)]
36310#[cfg_attr(
36311 target_arch = "arm",
36312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36313)]
36314pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36315 unsafe extern "unadjusted" {
36316 #[cfg_attr(
36317 any(target_arch = "aarch64", target_arch = "arm64ec"),
36318 link_name = "llvm.aarch64.neon.smaxp.v4i16"
36319 )]
36320 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
36321 fn _vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36322 }
36323 unsafe { _vpmax_s16(a, b) }
36324}
36325#[doc = "Folding maximum of adjacent pairs"]
36326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
36327#[inline]
36328#[target_feature(enable = "neon")]
36329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36331#[cfg_attr(
36332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36333 assert_instr(smaxp)
36334)]
36335#[cfg_attr(
36336 not(target_arch = "arm"),
36337 stable(feature = "neon_intrinsics", since = "1.59.0")
36338)]
36339#[cfg_attr(
36340 target_arch = "arm",
36341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36342)]
36343pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36344 unsafe extern "unadjusted" {
36345 #[cfg_attr(
36346 any(target_arch = "aarch64", target_arch = "arm64ec"),
36347 link_name = "llvm.aarch64.neon.smaxp.v2i32"
36348 )]
36349 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
36350 fn _vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36351 }
36352 unsafe { _vpmax_s32(a, b) }
36353}
36354#[doc = "Folding maximum of adjacent pairs"]
36355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
36356#[inline]
36357#[target_feature(enable = "neon")]
36358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36360#[cfg_attr(
36361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36362 assert_instr(umaxp)
36363)]
36364#[cfg_attr(
36365 not(target_arch = "arm"),
36366 stable(feature = "neon_intrinsics", since = "1.59.0")
36367)]
36368#[cfg_attr(
36369 target_arch = "arm",
36370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36371)]
36372pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36373 unsafe extern "unadjusted" {
36374 #[cfg_attr(
36375 any(target_arch = "aarch64", target_arch = "arm64ec"),
36376 link_name = "llvm.aarch64.neon.umaxp.v8i8"
36377 )]
36378 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v8i8")]
36379 fn _vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36380 }
36381 unsafe { _vpmax_u8(a, b) }
36382}
36383#[doc = "Folding maximum of adjacent pairs"]
36384#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
36385#[inline]
36386#[target_feature(enable = "neon")]
36387#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36388#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36389#[cfg_attr(
36390 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36391 assert_instr(umaxp)
36392)]
36393#[cfg_attr(
36394 not(target_arch = "arm"),
36395 stable(feature = "neon_intrinsics", since = "1.59.0")
36396)]
36397#[cfg_attr(
36398 target_arch = "arm",
36399 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36400)]
36401pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36402 unsafe extern "unadjusted" {
36403 #[cfg_attr(
36404 any(target_arch = "aarch64", target_arch = "arm64ec"),
36405 link_name = "llvm.aarch64.neon.umaxp.v4i16"
36406 )]
36407 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
36408 fn _vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36409 }
36410 unsafe { _vpmax_u16(a, b) }
36411}
36412#[doc = "Folding maximum of adjacent pairs"]
36413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
36414#[inline]
36415#[target_feature(enable = "neon")]
36416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
36418#[cfg_attr(
36419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36420 assert_instr(umaxp)
36421)]
36422#[cfg_attr(
36423 not(target_arch = "arm"),
36424 stable(feature = "neon_intrinsics", since = "1.59.0")
36425)]
36426#[cfg_attr(
36427 target_arch = "arm",
36428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36429)]
36430pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36431 unsafe extern "unadjusted" {
36432 #[cfg_attr(
36433 any(target_arch = "aarch64", target_arch = "arm64ec"),
36434 link_name = "llvm.aarch64.neon.umaxp.v2i32"
36435 )]
36436 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
36437 fn _vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36438 }
36439 unsafe { _vpmax_u32(a, b) }
36440}
36441#[doc = "Folding minimum of adjacent pairs"]
36442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
36443#[inline]
36444#[target_feature(enable = "neon")]
36445#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36446#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36447#[cfg_attr(
36448 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36449 assert_instr(fminp)
36450)]
36451#[cfg_attr(
36452 not(target_arch = "arm"),
36453 stable(feature = "neon_intrinsics", since = "1.59.0")
36454)]
36455#[cfg_attr(
36456 target_arch = "arm",
36457 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36458)]
36459pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
36460 unsafe extern "unadjusted" {
36461 #[cfg_attr(
36462 any(target_arch = "aarch64", target_arch = "arm64ec"),
36463 link_name = "llvm.aarch64.neon.fminp.v2f32"
36464 )]
36465 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
36466 fn _vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
36467 }
36468 unsafe { _vpmin_f32(a, b) }
36469}
36470#[doc = "Folding minimum of adjacent pairs"]
36471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
36472#[inline]
36473#[target_feature(enable = "neon")]
36474#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36476#[cfg_attr(
36477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36478 assert_instr(sminp)
36479)]
36480#[cfg_attr(
36481 not(target_arch = "arm"),
36482 stable(feature = "neon_intrinsics", since = "1.59.0")
36483)]
36484#[cfg_attr(
36485 target_arch = "arm",
36486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36487)]
36488pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36489 unsafe extern "unadjusted" {
36490 #[cfg_attr(
36491 any(target_arch = "aarch64", target_arch = "arm64ec"),
36492 link_name = "llvm.aarch64.neon.sminp.v8i8"
36493 )]
36494 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
36495 fn _vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36496 }
36497 unsafe { _vpmin_s8(a, b) }
36498}
36499#[doc = "Folding minimum of adjacent pairs"]
36500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
36501#[inline]
36502#[target_feature(enable = "neon")]
36503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36505#[cfg_attr(
36506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36507 assert_instr(sminp)
36508)]
36509#[cfg_attr(
36510 not(target_arch = "arm"),
36511 stable(feature = "neon_intrinsics", since = "1.59.0")
36512)]
36513#[cfg_attr(
36514 target_arch = "arm",
36515 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36516)]
36517pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36518 unsafe extern "unadjusted" {
36519 #[cfg_attr(
36520 any(target_arch = "aarch64", target_arch = "arm64ec"),
36521 link_name = "llvm.aarch64.neon.sminp.v4i16"
36522 )]
36523 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
36524 fn _vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36525 }
36526 unsafe { _vpmin_s16(a, b) }
36527}
36528#[doc = "Folding minimum of adjacent pairs"]
36529#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
36530#[inline]
36531#[target_feature(enable = "neon")]
36532#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36533#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36534#[cfg_attr(
36535 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36536 assert_instr(sminp)
36537)]
36538#[cfg_attr(
36539 not(target_arch = "arm"),
36540 stable(feature = "neon_intrinsics", since = "1.59.0")
36541)]
36542#[cfg_attr(
36543 target_arch = "arm",
36544 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36545)]
36546pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36547 unsafe extern "unadjusted" {
36548 #[cfg_attr(
36549 any(target_arch = "aarch64", target_arch = "arm64ec"),
36550 link_name = "llvm.aarch64.neon.sminp.v2i32"
36551 )]
36552 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
36553 fn _vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36554 }
36555 unsafe { _vpmin_s32(a, b) }
36556}
36557#[doc = "Folding minimum of adjacent pairs"]
36558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
36559#[inline]
36560#[target_feature(enable = "neon")]
36561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36563#[cfg_attr(
36564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36565 assert_instr(uminp)
36566)]
36567#[cfg_attr(
36568 not(target_arch = "arm"),
36569 stable(feature = "neon_intrinsics", since = "1.59.0")
36570)]
36571#[cfg_attr(
36572 target_arch = "arm",
36573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36574)]
36575pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
36576 unsafe extern "unadjusted" {
36577 #[cfg_attr(
36578 any(target_arch = "aarch64", target_arch = "arm64ec"),
36579 link_name = "llvm.aarch64.neon.uminp.v8i8"
36580 )]
36581 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v8i8")]
36582 fn _vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
36583 }
36584 unsafe { _vpmin_u8(a, b) }
36585}
36586#[doc = "Folding minimum of adjacent pairs"]
36587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
36588#[inline]
36589#[target_feature(enable = "neon")]
36590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36591#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36592#[cfg_attr(
36593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36594 assert_instr(uminp)
36595)]
36596#[cfg_attr(
36597 not(target_arch = "arm"),
36598 stable(feature = "neon_intrinsics", since = "1.59.0")
36599)]
36600#[cfg_attr(
36601 target_arch = "arm",
36602 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36603)]
36604pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
36605 unsafe extern "unadjusted" {
36606 #[cfg_attr(
36607 any(target_arch = "aarch64", target_arch = "arm64ec"),
36608 link_name = "llvm.aarch64.neon.uminp.v4i16"
36609 )]
36610 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
36611 fn _vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
36612 }
36613 unsafe { _vpmin_u16(a, b) }
36614}
36615#[doc = "Folding minimum of adjacent pairs"]
36616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
36617#[inline]
36618#[target_feature(enable = "neon")]
36619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
36621#[cfg_attr(
36622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36623 assert_instr(uminp)
36624)]
36625#[cfg_attr(
36626 not(target_arch = "arm"),
36627 stable(feature = "neon_intrinsics", since = "1.59.0")
36628)]
36629#[cfg_attr(
36630 target_arch = "arm",
36631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36632)]
36633pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
36634 unsafe extern "unadjusted" {
36635 #[cfg_attr(
36636 any(target_arch = "aarch64", target_arch = "arm64ec"),
36637 link_name = "llvm.aarch64.neon.uminp.v2i32"
36638 )]
36639 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
36640 fn _vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
36641 }
36642 unsafe { _vpmin_u32(a, b) }
36643}
36644#[doc = "Signed saturating Absolute value"]
36645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
36646#[inline]
36647#[target_feature(enable = "neon")]
36648#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36649#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36650#[cfg_attr(
36651 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36652 assert_instr(sqabs)
36653)]
36654#[cfg_attr(
36655 not(target_arch = "arm"),
36656 stable(feature = "neon_intrinsics", since = "1.59.0")
36657)]
36658#[cfg_attr(
36659 target_arch = "arm",
36660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36661)]
36662pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
36663 unsafe extern "unadjusted" {
36664 #[cfg_attr(
36665 any(target_arch = "aarch64", target_arch = "arm64ec"),
36666 link_name = "llvm.aarch64.neon.sqabs.v8i8"
36667 )]
36668 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")]
36669 fn _vqabs_s8(a: int8x8_t) -> int8x8_t;
36670 }
36671 unsafe { _vqabs_s8(a) }
36672}
36673#[doc = "Signed saturating Absolute value"]
36674#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
36675#[inline]
36676#[target_feature(enable = "neon")]
36677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36678#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
36679#[cfg_attr(
36680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36681 assert_instr(sqabs)
36682)]
36683#[cfg_attr(
36684 not(target_arch = "arm"),
36685 stable(feature = "neon_intrinsics", since = "1.59.0")
36686)]
36687#[cfg_attr(
36688 target_arch = "arm",
36689 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36690)]
36691pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
36692 unsafe extern "unadjusted" {
36693 #[cfg_attr(
36694 any(target_arch = "aarch64", target_arch = "arm64ec"),
36695 link_name = "llvm.aarch64.neon.sqabs.v16i8"
36696 )]
36697 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")]
36698 fn _vqabsq_s8(a: int8x16_t) -> int8x16_t;
36699 }
36700 unsafe { _vqabsq_s8(a) }
36701}
36702#[doc = "Signed saturating Absolute value"]
36703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
36704#[inline]
36705#[target_feature(enable = "neon")]
36706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
36708#[cfg_attr(
36709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36710 assert_instr(sqabs)
36711)]
36712#[cfg_attr(
36713 not(target_arch = "arm"),
36714 stable(feature = "neon_intrinsics", since = "1.59.0")
36715)]
36716#[cfg_attr(
36717 target_arch = "arm",
36718 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36719)]
36720pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
36721 unsafe extern "unadjusted" {
36722 #[cfg_attr(
36723 any(target_arch = "aarch64", target_arch = "arm64ec"),
36724 link_name = "llvm.aarch64.neon.sqabs.v4i16"
36725 )]
36726 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")]
36727 fn _vqabs_s16(a: int16x4_t) -> int16x4_t;
36728 }
36729 unsafe { _vqabs_s16(a) }
36730}
36731#[doc = "Signed saturating Absolute value"]
36732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
36733#[inline]
36734#[target_feature(enable = "neon")]
36735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36736#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
36737#[cfg_attr(
36738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36739 assert_instr(sqabs)
36740)]
36741#[cfg_attr(
36742 not(target_arch = "arm"),
36743 stable(feature = "neon_intrinsics", since = "1.59.0")
36744)]
36745#[cfg_attr(
36746 target_arch = "arm",
36747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36748)]
36749pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
36750 unsafe extern "unadjusted" {
36751 #[cfg_attr(
36752 any(target_arch = "aarch64", target_arch = "arm64ec"),
36753 link_name = "llvm.aarch64.neon.sqabs.v8i16"
36754 )]
36755 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")]
36756 fn _vqabsq_s16(a: int16x8_t) -> int16x8_t;
36757 }
36758 unsafe { _vqabsq_s16(a) }
36759}
36760#[doc = "Signed saturating Absolute value"]
36761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
36762#[inline]
36763#[target_feature(enable = "neon")]
36764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36765#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
36766#[cfg_attr(
36767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36768 assert_instr(sqabs)
36769)]
36770#[cfg_attr(
36771 not(target_arch = "arm"),
36772 stable(feature = "neon_intrinsics", since = "1.59.0")
36773)]
36774#[cfg_attr(
36775 target_arch = "arm",
36776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36777)]
36778pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
36779 unsafe extern "unadjusted" {
36780 #[cfg_attr(
36781 any(target_arch = "aarch64", target_arch = "arm64ec"),
36782 link_name = "llvm.aarch64.neon.sqabs.v2i32"
36783 )]
36784 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")]
36785 fn _vqabs_s32(a: int32x2_t) -> int32x2_t;
36786 }
36787 unsafe { _vqabs_s32(a) }
36788}
36789#[doc = "Signed saturating Absolute value"]
36790#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
36791#[inline]
36792#[target_feature(enable = "neon")]
36793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
36795#[cfg_attr(
36796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36797 assert_instr(sqabs)
36798)]
36799#[cfg_attr(
36800 not(target_arch = "arm"),
36801 stable(feature = "neon_intrinsics", since = "1.59.0")
36802)]
36803#[cfg_attr(
36804 target_arch = "arm",
36805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36806)]
36807pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
36808 unsafe extern "unadjusted" {
36809 #[cfg_attr(
36810 any(target_arch = "aarch64", target_arch = "arm64ec"),
36811 link_name = "llvm.aarch64.neon.sqabs.v4i32"
36812 )]
36813 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")]
36814 fn _vqabsq_s32(a: int32x4_t) -> int32x4_t;
36815 }
36816 unsafe { _vqabsq_s32(a) }
36817}
36818#[doc = "Saturating add"]
36819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
36820#[inline]
36821#[target_feature(enable = "neon")]
36822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36823#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
36824#[cfg_attr(
36825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36826 assert_instr(sqadd)
36827)]
36828#[cfg_attr(
36829 not(target_arch = "arm"),
36830 stable(feature = "neon_intrinsics", since = "1.59.0")
36831)]
36832#[cfg_attr(
36833 target_arch = "arm",
36834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36835)]
36836pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
36837 unsafe extern "unadjusted" {
36838 #[cfg_attr(
36839 any(target_arch = "aarch64", target_arch = "arm64ec"),
36840 link_name = "llvm.aarch64.neon.sqadd.v8i8"
36841 )]
36842 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")]
36843 fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
36844 }
36845 unsafe { _vqadd_s8(a, b) }
36846}
36847#[doc = "Saturating add"]
36848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
36849#[inline]
36850#[target_feature(enable = "neon")]
36851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36852#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
36853#[cfg_attr(
36854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36855 assert_instr(sqadd)
36856)]
36857#[cfg_attr(
36858 not(target_arch = "arm"),
36859 stable(feature = "neon_intrinsics", since = "1.59.0")
36860)]
36861#[cfg_attr(
36862 target_arch = "arm",
36863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36864)]
36865pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
36866 unsafe extern "unadjusted" {
36867 #[cfg_attr(
36868 any(target_arch = "aarch64", target_arch = "arm64ec"),
36869 link_name = "llvm.aarch64.neon.sqadd.v16i8"
36870 )]
36871 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")]
36872 fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
36873 }
36874 unsafe { _vqaddq_s8(a, b) }
36875}
36876#[doc = "Saturating add"]
36877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
36878#[inline]
36879#[target_feature(enable = "neon")]
36880#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36881#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
36882#[cfg_attr(
36883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36884 assert_instr(sqadd)
36885)]
36886#[cfg_attr(
36887 not(target_arch = "arm"),
36888 stable(feature = "neon_intrinsics", since = "1.59.0")
36889)]
36890#[cfg_attr(
36891 target_arch = "arm",
36892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36893)]
36894pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
36895 unsafe extern "unadjusted" {
36896 #[cfg_attr(
36897 any(target_arch = "aarch64", target_arch = "arm64ec"),
36898 link_name = "llvm.aarch64.neon.sqadd.v4i16"
36899 )]
36900 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")]
36901 fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
36902 }
36903 unsafe { _vqadd_s16(a, b) }
36904}
36905#[doc = "Saturating add"]
36906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
36907#[inline]
36908#[target_feature(enable = "neon")]
36909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36910#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
36911#[cfg_attr(
36912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36913 assert_instr(sqadd)
36914)]
36915#[cfg_attr(
36916 not(target_arch = "arm"),
36917 stable(feature = "neon_intrinsics", since = "1.59.0")
36918)]
36919#[cfg_attr(
36920 target_arch = "arm",
36921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36922)]
36923pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
36924 unsafe extern "unadjusted" {
36925 #[cfg_attr(
36926 any(target_arch = "aarch64", target_arch = "arm64ec"),
36927 link_name = "llvm.aarch64.neon.sqadd.v8i16"
36928 )]
36929 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")]
36930 fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
36931 }
36932 unsafe { _vqaddq_s16(a, b) }
36933}
36934#[doc = "Saturating add"]
36935#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
36936#[inline]
36937#[target_feature(enable = "neon")]
36938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36939#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
36940#[cfg_attr(
36941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36942 assert_instr(sqadd)
36943)]
36944#[cfg_attr(
36945 not(target_arch = "arm"),
36946 stable(feature = "neon_intrinsics", since = "1.59.0")
36947)]
36948#[cfg_attr(
36949 target_arch = "arm",
36950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36951)]
36952pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
36953 unsafe extern "unadjusted" {
36954 #[cfg_attr(
36955 any(target_arch = "aarch64", target_arch = "arm64ec"),
36956 link_name = "llvm.aarch64.neon.sqadd.v2i32"
36957 )]
36958 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")]
36959 fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
36960 }
36961 unsafe { _vqadd_s32(a, b) }
36962}
36963#[doc = "Saturating add"]
36964#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
36965#[inline]
36966#[target_feature(enable = "neon")]
36967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36968#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
36969#[cfg_attr(
36970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
36971 assert_instr(sqadd)
36972)]
36973#[cfg_attr(
36974 not(target_arch = "arm"),
36975 stable(feature = "neon_intrinsics", since = "1.59.0")
36976)]
36977#[cfg_attr(
36978 target_arch = "arm",
36979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
36980)]
36981pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
36982 unsafe extern "unadjusted" {
36983 #[cfg_attr(
36984 any(target_arch = "aarch64", target_arch = "arm64ec"),
36985 link_name = "llvm.aarch64.neon.sqadd.v4i32"
36986 )]
36987 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")]
36988 fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
36989 }
36990 unsafe { _vqaddq_s32(a, b) }
36991}
36992#[doc = "Saturating add"]
36993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
36994#[inline]
36995#[target_feature(enable = "neon")]
36996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
36997#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
36998#[cfg_attr(
36999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37000 assert_instr(sqadd)
37001)]
37002#[cfg_attr(
37003 not(target_arch = "arm"),
37004 stable(feature = "neon_intrinsics", since = "1.59.0")
37005)]
37006#[cfg_attr(
37007 target_arch = "arm",
37008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37009)]
37010pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
37011 unsafe extern "unadjusted" {
37012 #[cfg_attr(
37013 any(target_arch = "aarch64", target_arch = "arm64ec"),
37014 link_name = "llvm.aarch64.neon.sqadd.v1i64"
37015 )]
37016 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")]
37017 fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
37018 }
37019 unsafe { _vqadd_s64(a, b) }
37020}
37021#[doc = "Saturating add"]
37022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
37023#[inline]
37024#[target_feature(enable = "neon")]
37025#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37026#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
37027#[cfg_attr(
37028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37029 assert_instr(sqadd)
37030)]
37031#[cfg_attr(
37032 not(target_arch = "arm"),
37033 stable(feature = "neon_intrinsics", since = "1.59.0")
37034)]
37035#[cfg_attr(
37036 target_arch = "arm",
37037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37038)]
37039pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
37040 unsafe extern "unadjusted" {
37041 #[cfg_attr(
37042 any(target_arch = "aarch64", target_arch = "arm64ec"),
37043 link_name = "llvm.aarch64.neon.sqadd.v2i64"
37044 )]
37045 #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")]
37046 fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
37047 }
37048 unsafe { _vqaddq_s64(a, b) }
37049}
37050#[doc = "Saturating add"]
37051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
37052#[inline]
37053#[target_feature(enable = "neon")]
37054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37055#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37056#[cfg_attr(
37057 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37058 assert_instr(uqadd)
37059)]
37060#[cfg_attr(
37061 not(target_arch = "arm"),
37062 stable(feature = "neon_intrinsics", since = "1.59.0")
37063)]
37064#[cfg_attr(
37065 target_arch = "arm",
37066 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37067)]
37068pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
37069 unsafe extern "unadjusted" {
37070 #[cfg_attr(
37071 any(target_arch = "aarch64", target_arch = "arm64ec"),
37072 link_name = "llvm.aarch64.neon.uqadd.v8i8"
37073 )]
37074 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")]
37075 fn _vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
37076 }
37077 unsafe { _vqadd_u8(a, b) }
37078}
37079#[doc = "Saturating add"]
37080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
37081#[inline]
37082#[target_feature(enable = "neon")]
37083#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37084#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
37085#[cfg_attr(
37086 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37087 assert_instr(uqadd)
37088)]
37089#[cfg_attr(
37090 not(target_arch = "arm"),
37091 stable(feature = "neon_intrinsics", since = "1.59.0")
37092)]
37093#[cfg_attr(
37094 target_arch = "arm",
37095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37096)]
37097pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
37098 unsafe extern "unadjusted" {
37099 #[cfg_attr(
37100 any(target_arch = "aarch64", target_arch = "arm64ec"),
37101 link_name = "llvm.aarch64.neon.uqadd.v16i8"
37102 )]
37103 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")]
37104 fn _vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
37105 }
37106 unsafe { _vqaddq_u8(a, b) }
37107}
37108#[doc = "Saturating add"]
37109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
37110#[inline]
37111#[target_feature(enable = "neon")]
37112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37113#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37114#[cfg_attr(
37115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37116 assert_instr(uqadd)
37117)]
37118#[cfg_attr(
37119 not(target_arch = "arm"),
37120 stable(feature = "neon_intrinsics", since = "1.59.0")
37121)]
37122#[cfg_attr(
37123 target_arch = "arm",
37124 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37125)]
37126pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
37127 unsafe extern "unadjusted" {
37128 #[cfg_attr(
37129 any(target_arch = "aarch64", target_arch = "arm64ec"),
37130 link_name = "llvm.aarch64.neon.uqadd.v4i16"
37131 )]
37132 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")]
37133 fn _vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
37134 }
37135 unsafe { _vqadd_u16(a, b) }
37136}
37137#[doc = "Saturating add"]
37138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
37139#[inline]
37140#[target_feature(enable = "neon")]
37141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37142#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
37143#[cfg_attr(
37144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37145 assert_instr(uqadd)
37146)]
37147#[cfg_attr(
37148 not(target_arch = "arm"),
37149 stable(feature = "neon_intrinsics", since = "1.59.0")
37150)]
37151#[cfg_attr(
37152 target_arch = "arm",
37153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37154)]
37155pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
37156 unsafe extern "unadjusted" {
37157 #[cfg_attr(
37158 any(target_arch = "aarch64", target_arch = "arm64ec"),
37159 link_name = "llvm.aarch64.neon.uqadd.v8i16"
37160 )]
37161 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")]
37162 fn _vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
37163 }
37164 unsafe { _vqaddq_u16(a, b) }
37165}
37166#[doc = "Saturating add"]
37167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
37168#[inline]
37169#[target_feature(enable = "neon")]
37170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37171#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37172#[cfg_attr(
37173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37174 assert_instr(uqadd)
37175)]
37176#[cfg_attr(
37177 not(target_arch = "arm"),
37178 stable(feature = "neon_intrinsics", since = "1.59.0")
37179)]
37180#[cfg_attr(
37181 target_arch = "arm",
37182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37183)]
37184pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
37185 unsafe extern "unadjusted" {
37186 #[cfg_attr(
37187 any(target_arch = "aarch64", target_arch = "arm64ec"),
37188 link_name = "llvm.aarch64.neon.uqadd.v2i32"
37189 )]
37190 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")]
37191 fn _vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
37192 }
37193 unsafe { _vqadd_u32(a, b) }
37194}
37195#[doc = "Saturating add"]
37196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
37197#[inline]
37198#[target_feature(enable = "neon")]
37199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37200#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
37201#[cfg_attr(
37202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37203 assert_instr(uqadd)
37204)]
37205#[cfg_attr(
37206 not(target_arch = "arm"),
37207 stable(feature = "neon_intrinsics", since = "1.59.0")
37208)]
37209#[cfg_attr(
37210 target_arch = "arm",
37211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37212)]
37213pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
37214 unsafe extern "unadjusted" {
37215 #[cfg_attr(
37216 any(target_arch = "aarch64", target_arch = "arm64ec"),
37217 link_name = "llvm.aarch64.neon.uqadd.v4i32"
37218 )]
37219 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")]
37220 fn _vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
37221 }
37222 unsafe { _vqaddq_u32(a, b) }
37223}
37224#[doc = "Saturating add"]
37225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
37226#[inline]
37227#[target_feature(enable = "neon")]
37228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37229#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37230#[cfg_attr(
37231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37232 assert_instr(uqadd)
37233)]
37234#[cfg_attr(
37235 not(target_arch = "arm"),
37236 stable(feature = "neon_intrinsics", since = "1.59.0")
37237)]
37238#[cfg_attr(
37239 target_arch = "arm",
37240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37241)]
37242pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
37243 unsafe extern "unadjusted" {
37244 #[cfg_attr(
37245 any(target_arch = "aarch64", target_arch = "arm64ec"),
37246 link_name = "llvm.aarch64.neon.uqadd.v1i64"
37247 )]
37248 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")]
37249 fn _vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
37250 }
37251 unsafe { _vqadd_u64(a, b) }
37252}
37253#[doc = "Saturating add"]
37254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
37255#[inline]
37256#[target_feature(enable = "neon")]
37257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37258#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
37259#[cfg_attr(
37260 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37261 assert_instr(uqadd)
37262)]
37263#[cfg_attr(
37264 not(target_arch = "arm"),
37265 stable(feature = "neon_intrinsics", since = "1.59.0")
37266)]
37267#[cfg_attr(
37268 target_arch = "arm",
37269 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37270)]
37271pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
37272 unsafe extern "unadjusted" {
37273 #[cfg_attr(
37274 any(target_arch = "aarch64", target_arch = "arm64ec"),
37275 link_name = "llvm.aarch64.neon.uqadd.v2i64"
37276 )]
37277 #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")]
37278 fn _vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
37279 }
37280 unsafe { _vqaddq_u64(a, b) }
37281}
37282#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
37284#[inline]
37285#[target_feature(enable = "neon")]
37286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
37288#[cfg_attr(
37289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37290 assert_instr(sqdmlal, N = 2)
37291)]
37292#[rustc_legacy_const_generics(3)]
37293#[cfg_attr(
37294 not(target_arch = "arm"),
37295 stable(feature = "neon_intrinsics", since = "1.59.0")
37296)]
37297#[cfg_attr(
37298 target_arch = "arm",
37299 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37300)]
37301pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37302 static_assert_uimm_bits!(N, 2);
37303 vqaddq_s32(a, vqdmull_lane_s16::<N>(b, c))
37304}
37305#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37306#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
37307#[inline]
37308#[target_feature(enable = "neon")]
37309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
37311#[cfg_attr(
37312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37313 assert_instr(sqdmlal, N = 1)
37314)]
37315#[rustc_legacy_const_generics(3)]
37316#[cfg_attr(
37317 not(target_arch = "arm"),
37318 stable(feature = "neon_intrinsics", since = "1.59.0")
37319)]
37320#[cfg_attr(
37321 target_arch = "arm",
37322 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37323)]
37324pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37325 static_assert_uimm_bits!(N, 1);
37326 vqaddq_s64(a, vqdmull_lane_s32::<N>(b, c))
37327}
37328#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
37330#[inline]
37331#[target_feature(enable = "neon")]
37332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37333#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37334#[cfg_attr(
37335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37336 assert_instr(sqdmlal)
37337)]
37338#[cfg_attr(
37339 not(target_arch = "arm"),
37340 stable(feature = "neon_intrinsics", since = "1.59.0")
37341)]
37342#[cfg_attr(
37343 target_arch = "arm",
37344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37345)]
37346pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37347 vqaddq_s32(a, vqdmull_n_s16(b, c))
37348}
37349#[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
37350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
37351#[inline]
37352#[target_feature(enable = "neon")]
37353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37355#[cfg_attr(
37356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37357 assert_instr(sqdmlal)
37358)]
37359#[cfg_attr(
37360 not(target_arch = "arm"),
37361 stable(feature = "neon_intrinsics", since = "1.59.0")
37362)]
37363#[cfg_attr(
37364 target_arch = "arm",
37365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37366)]
37367pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37368 vqaddq_s64(a, vqdmull_n_s32(b, c))
37369}
37370#[doc = "Signed saturating doubling multiply-add long"]
37371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
37372#[inline]
37373#[target_feature(enable = "neon")]
37374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37376#[cfg_attr(
37377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37378 assert_instr(sqdmlal)
37379)]
37380#[cfg_attr(
37381 not(target_arch = "arm"),
37382 stable(feature = "neon_intrinsics", since = "1.59.0")
37383)]
37384#[cfg_attr(
37385 target_arch = "arm",
37386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37387)]
37388pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37389 vqaddq_s32(a, vqdmull_s16(b, c))
37390}
37391#[doc = "Signed saturating doubling multiply-add long"]
37392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
37393#[inline]
37394#[target_feature(enable = "neon")]
37395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37396#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
37397#[cfg_attr(
37398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37399 assert_instr(sqdmlal)
37400)]
37401#[cfg_attr(
37402 not(target_arch = "arm"),
37403 stable(feature = "neon_intrinsics", since = "1.59.0")
37404)]
37405#[cfg_attr(
37406 target_arch = "arm",
37407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37408)]
37409pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37410 vqaddq_s64(a, vqdmull_s32(b, c))
37411}
37412#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
37414#[inline]
37415#[target_feature(enable = "neon")]
37416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
37418#[cfg_attr(
37419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37420 assert_instr(sqdmlsl, N = 2)
37421)]
37422#[rustc_legacy_const_generics(3)]
37423#[cfg_attr(
37424 not(target_arch = "arm"),
37425 stable(feature = "neon_intrinsics", since = "1.59.0")
37426)]
37427#[cfg_attr(
37428 target_arch = "arm",
37429 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37430)]
37431pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37432 static_assert_uimm_bits!(N, 2);
37433 vqsubq_s32(a, vqdmull_lane_s16::<N>(b, c))
37434}
37435#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
37437#[inline]
37438#[target_feature(enable = "neon")]
37439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
37441#[cfg_attr(
37442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37443 assert_instr(sqdmlsl, N = 1)
37444)]
37445#[rustc_legacy_const_generics(3)]
37446#[cfg_attr(
37447 not(target_arch = "arm"),
37448 stable(feature = "neon_intrinsics", since = "1.59.0")
37449)]
37450#[cfg_attr(
37451 target_arch = "arm",
37452 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37453)]
37454pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37455 static_assert_uimm_bits!(N, 1);
37456 vqsubq_s64(a, vqdmull_lane_s32::<N>(b, c))
37457}
37458#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
37460#[inline]
37461#[target_feature(enable = "neon")]
37462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37464#[cfg_attr(
37465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37466 assert_instr(sqdmlsl)
37467)]
37468#[cfg_attr(
37469 not(target_arch = "arm"),
37470 stable(feature = "neon_intrinsics", since = "1.59.0")
37471)]
37472#[cfg_attr(
37473 target_arch = "arm",
37474 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37475)]
37476pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
37477 vqsubq_s32(a, vqdmull_n_s16(b, c))
37478}
37479#[doc = "Vector widening saturating doubling multiply subtract with scalar"]
37480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
37481#[inline]
37482#[target_feature(enable = "neon")]
37483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37484#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37485#[cfg_attr(
37486 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37487 assert_instr(sqdmlsl)
37488)]
37489#[cfg_attr(
37490 not(target_arch = "arm"),
37491 stable(feature = "neon_intrinsics", since = "1.59.0")
37492)]
37493#[cfg_attr(
37494 target_arch = "arm",
37495 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37496)]
37497pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
37498 vqsubq_s64(a, vqdmull_n_s32(b, c))
37499}
37500#[doc = "Signed saturating doubling multiply-subtract long"]
37501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
37502#[inline]
37503#[target_feature(enable = "neon")]
37504#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37506#[cfg_attr(
37507 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37508 assert_instr(sqdmlsl)
37509)]
37510#[cfg_attr(
37511 not(target_arch = "arm"),
37512 stable(feature = "neon_intrinsics", since = "1.59.0")
37513)]
37514#[cfg_attr(
37515 target_arch = "arm",
37516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37517)]
37518pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
37519 vqsubq_s32(a, vqdmull_s16(b, c))
37520}
37521#[doc = "Signed saturating doubling multiply-subtract long"]
37522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
37523#[inline]
37524#[target_feature(enable = "neon")]
37525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
37527#[cfg_attr(
37528 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37529 assert_instr(sqdmlsl)
37530)]
37531#[cfg_attr(
37532 not(target_arch = "arm"),
37533 stable(feature = "neon_intrinsics", since = "1.59.0")
37534)]
37535#[cfg_attr(
37536 target_arch = "arm",
37537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37538)]
37539pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
37540 vqsubq_s64(a, vqdmull_s32(b, c))
37541}
37542#[doc = "Vector saturating doubling multiply high by scalar"]
37543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
37544#[inline]
37545#[target_feature(enable = "neon")]
37546#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37547#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37548#[cfg_attr(
37549 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37550 assert_instr(sqdmulh, LANE = 0)
37551)]
37552#[rustc_legacy_const_generics(2)]
37553#[cfg_attr(
37554 not(target_arch = "arm"),
37555 stable(feature = "neon_intrinsics", since = "1.59.0")
37556)]
37557#[cfg_attr(
37558 target_arch = "arm",
37559 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37560)]
37561pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
37562 static_assert_uimm_bits!(LANE, 3);
37563 unsafe { vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) }
37564}
37565#[doc = "Vector saturating doubling multiply high by scalar"]
37566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
37567#[inline]
37568#[target_feature(enable = "neon")]
37569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37571#[cfg_attr(
37572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37573 assert_instr(sqdmulh, LANE = 0)
37574)]
37575#[rustc_legacy_const_generics(2)]
37576#[cfg_attr(
37577 not(target_arch = "arm"),
37578 stable(feature = "neon_intrinsics", since = "1.59.0")
37579)]
37580#[cfg_attr(
37581 target_arch = "arm",
37582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37583)]
37584pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37585 static_assert_uimm_bits!(LANE, 3);
37586 unsafe { vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) }
37587}
37588#[doc = "Vector saturating doubling multiply high by scalar"]
37589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
37590#[inline]
37591#[target_feature(enable = "neon")]
37592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37594#[cfg_attr(
37595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37596 assert_instr(sqdmulh, LANE = 0)
37597)]
37598#[rustc_legacy_const_generics(2)]
37599#[cfg_attr(
37600 not(target_arch = "arm"),
37601 stable(feature = "neon_intrinsics", since = "1.59.0")
37602)]
37603#[cfg_attr(
37604 target_arch = "arm",
37605 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37606)]
37607pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
37608 static_assert_uimm_bits!(LANE, 2);
37609 unsafe { vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) }
37610}
37611#[doc = "Vector saturating doubling multiply high by scalar"]
37612#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
37613#[inline]
37614#[target_feature(enable = "neon")]
37615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
37617#[cfg_attr(
37618 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37619 assert_instr(sqdmulh, LANE = 0)
37620)]
37621#[rustc_legacy_const_generics(2)]
37622#[cfg_attr(
37623 not(target_arch = "arm"),
37624 stable(feature = "neon_intrinsics", since = "1.59.0")
37625)]
37626#[cfg_attr(
37627 target_arch = "arm",
37628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37629)]
37630pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37631 static_assert_uimm_bits!(LANE, 2);
37632 unsafe { vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) }
37633}
37634#[doc = "Vector saturating doubling multiply high with scalar"]
37635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
37636#[inline]
37637#[target_feature(enable = "neon")]
37638#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37639#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37640#[cfg_attr(
37641 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37642 assert_instr(sqdmulh)
37643)]
37644#[cfg_attr(
37645 not(target_arch = "arm"),
37646 stable(feature = "neon_intrinsics", since = "1.59.0")
37647)]
37648#[cfg_attr(
37649 target_arch = "arm",
37650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37651)]
37652pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
37653 let b: int16x4_t = vdup_n_s16(b);
37654 vqdmulh_s16(a, b)
37655}
37656#[doc = "Vector saturating doubling multiply high with scalar"]
37657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
37658#[inline]
37659#[target_feature(enable = "neon")]
37660#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37661#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37662#[cfg_attr(
37663 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37664 assert_instr(sqdmulh)
37665)]
37666#[cfg_attr(
37667 not(target_arch = "arm"),
37668 stable(feature = "neon_intrinsics", since = "1.59.0")
37669)]
37670#[cfg_attr(
37671 target_arch = "arm",
37672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37673)]
37674pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
37675 let b: int16x8_t = vdupq_n_s16(b);
37676 vqdmulhq_s16(a, b)
37677}
37678#[doc = "Vector saturating doubling multiply high with scalar"]
37679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
37680#[inline]
37681#[target_feature(enable = "neon")]
37682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37684#[cfg_attr(
37685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37686 assert_instr(sqdmulh)
37687)]
37688#[cfg_attr(
37689 not(target_arch = "arm"),
37690 stable(feature = "neon_intrinsics", since = "1.59.0")
37691)]
37692#[cfg_attr(
37693 target_arch = "arm",
37694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37695)]
37696pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
37697 let b: int32x2_t = vdup_n_s32(b);
37698 vqdmulh_s32(a, b)
37699}
37700#[doc = "Vector saturating doubling multiply high with scalar"]
37701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
37702#[inline]
37703#[target_feature(enable = "neon")]
37704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37706#[cfg_attr(
37707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37708 assert_instr(sqdmulh)
37709)]
37710#[cfg_attr(
37711 not(target_arch = "arm"),
37712 stable(feature = "neon_intrinsics", since = "1.59.0")
37713)]
37714#[cfg_attr(
37715 target_arch = "arm",
37716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37717)]
37718pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
37719 let b: int32x4_t = vdupq_n_s32(b);
37720 vqdmulhq_s32(a, b)
37721}
37722#[doc = "Signed saturating doubling multiply returning high half"]
37723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
37724#[inline]
37725#[target_feature(enable = "neon")]
37726#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37727#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37728#[cfg_attr(
37729 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37730 assert_instr(sqdmulh)
37731)]
37732#[cfg_attr(
37733 not(target_arch = "arm"),
37734 stable(feature = "neon_intrinsics", since = "1.59.0")
37735)]
37736#[cfg_attr(
37737 target_arch = "arm",
37738 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37739)]
37740pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
37741 unsafe extern "unadjusted" {
37742 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")]
37743 #[cfg_attr(
37744 any(target_arch = "aarch64", target_arch = "arm64ec"),
37745 link_name = "llvm.aarch64.neon.sqdmulh.v4i16"
37746 )]
37747 fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
37748 }
37749 unsafe { _vqdmulh_s16(a, b) }
37750}
37751#[doc = "Signed saturating doubling multiply returning high half"]
37752#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
37753#[inline]
37754#[target_feature(enable = "neon")]
37755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37756#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37757#[cfg_attr(
37758 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37759 assert_instr(sqdmulh)
37760)]
37761#[cfg_attr(
37762 not(target_arch = "arm"),
37763 stable(feature = "neon_intrinsics", since = "1.59.0")
37764)]
37765#[cfg_attr(
37766 target_arch = "arm",
37767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37768)]
37769pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
37770 unsafe extern "unadjusted" {
37771 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")]
37772 #[cfg_attr(
37773 any(target_arch = "aarch64", target_arch = "arm64ec"),
37774 link_name = "llvm.aarch64.neon.sqdmulh.v8i16"
37775 )]
37776 fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
37777 }
37778 unsafe { _vqdmulhq_s16(a, b) }
37779}
37780#[doc = "Signed saturating doubling multiply returning high half"]
37781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
37782#[inline]
37783#[target_feature(enable = "neon")]
37784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37786#[cfg_attr(
37787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37788 assert_instr(sqdmulh)
37789)]
37790#[cfg_attr(
37791 not(target_arch = "arm"),
37792 stable(feature = "neon_intrinsics", since = "1.59.0")
37793)]
37794#[cfg_attr(
37795 target_arch = "arm",
37796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37797)]
37798pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
37799 unsafe extern "unadjusted" {
37800 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")]
37801 #[cfg_attr(
37802 any(target_arch = "aarch64", target_arch = "arm64ec"),
37803 link_name = "llvm.aarch64.neon.sqdmulh.v2i32"
37804 )]
37805 fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
37806 }
37807 unsafe { _vqdmulh_s32(a, b) }
37808}
37809#[doc = "Signed saturating doubling multiply returning high half"]
37810#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
37811#[inline]
37812#[target_feature(enable = "neon")]
37813#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37814#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
37815#[cfg_attr(
37816 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37817 assert_instr(sqdmulh)
37818)]
37819#[cfg_attr(
37820 not(target_arch = "arm"),
37821 stable(feature = "neon_intrinsics", since = "1.59.0")
37822)]
37823#[cfg_attr(
37824 target_arch = "arm",
37825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37826)]
37827pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
37828 unsafe extern "unadjusted" {
37829 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")]
37830 #[cfg_attr(
37831 any(target_arch = "aarch64", target_arch = "arm64ec"),
37832 link_name = "llvm.aarch64.neon.sqdmulh.v4i32"
37833 )]
37834 fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
37835 }
37836 unsafe { _vqdmulhq_s32(a, b) }
37837}
37838#[doc = "Vector saturating doubling long multiply by scalar"]
37839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
37840#[inline]
37841#[target_feature(enable = "neon")]
37842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
37844#[cfg_attr(
37845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37846 assert_instr(sqdmull, N = 2)
37847)]
37848#[rustc_legacy_const_generics(2)]
37849#[cfg_attr(
37850 not(target_arch = "arm"),
37851 stable(feature = "neon_intrinsics", since = "1.59.0")
37852)]
37853#[cfg_attr(
37854 target_arch = "arm",
37855 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37856)]
37857pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
37858 static_assert_uimm_bits!(N, 2);
37859 unsafe {
37860 let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]);
37861 vqdmull_s16(a, b)
37862 }
37863}
37864#[doc = "Vector saturating doubling long multiply by scalar"]
37865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
37866#[inline]
37867#[target_feature(enable = "neon")]
37868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
37870#[cfg_attr(
37871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37872 assert_instr(sqdmull, N = 1)
37873)]
37874#[rustc_legacy_const_generics(2)]
37875#[cfg_attr(
37876 not(target_arch = "arm"),
37877 stable(feature = "neon_intrinsics", since = "1.59.0")
37878)]
37879#[cfg_attr(
37880 target_arch = "arm",
37881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37882)]
37883pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
37884 static_assert_uimm_bits!(N, 1);
37885 unsafe {
37886 let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]);
37887 vqdmull_s32(a, b)
37888 }
37889}
37890#[doc = "Vector saturating doubling long multiply with scalar"]
37891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
37892#[inline]
37893#[target_feature(enable = "neon")]
37894#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37895#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
37896#[cfg_attr(
37897 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37898 assert_instr(sqdmull)
37899)]
37900#[cfg_attr(
37901 not(target_arch = "arm"),
37902 stable(feature = "neon_intrinsics", since = "1.59.0")
37903)]
37904#[cfg_attr(
37905 target_arch = "arm",
37906 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37907)]
37908pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
37909 vqdmull_s16(a, vdup_n_s16(b))
37910}
37911#[doc = "Vector saturating doubling long multiply with scalar"]
37912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
37913#[inline]
37914#[target_feature(enable = "neon")]
37915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
37917#[cfg_attr(
37918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37919 assert_instr(sqdmull)
37920)]
37921#[cfg_attr(
37922 not(target_arch = "arm"),
37923 stable(feature = "neon_intrinsics", since = "1.59.0")
37924)]
37925#[cfg_attr(
37926 target_arch = "arm",
37927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37928)]
37929pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
37930 vqdmull_s32(a, vdup_n_s32(b))
37931}
37932#[doc = "Signed saturating doubling multiply long"]
37933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
37934#[inline]
37935#[target_feature(enable = "neon")]
37936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
37938#[cfg_attr(
37939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37940 assert_instr(sqdmull)
37941)]
37942#[cfg_attr(
37943 not(target_arch = "arm"),
37944 stable(feature = "neon_intrinsics", since = "1.59.0")
37945)]
37946#[cfg_attr(
37947 target_arch = "arm",
37948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37949)]
37950pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
37951 unsafe extern "unadjusted" {
37952 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")]
37953 #[cfg_attr(
37954 any(target_arch = "aarch64", target_arch = "arm64ec"),
37955 link_name = "llvm.aarch64.neon.sqdmull.v4i32"
37956 )]
37957 fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t;
37958 }
37959 unsafe { _vqdmull_s16(a, b) }
37960}
37961#[doc = "Signed saturating doubling multiply long"]
37962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
37963#[inline]
37964#[target_feature(enable = "neon")]
37965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
37967#[cfg_attr(
37968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37969 assert_instr(sqdmull)
37970)]
37971#[cfg_attr(
37972 not(target_arch = "arm"),
37973 stable(feature = "neon_intrinsics", since = "1.59.0")
37974)]
37975#[cfg_attr(
37976 target_arch = "arm",
37977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
37978)]
37979pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
37980 unsafe extern "unadjusted" {
37981 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")]
37982 #[cfg_attr(
37983 any(target_arch = "aarch64", target_arch = "arm64ec"),
37984 link_name = "llvm.aarch64.neon.sqdmull.v2i64"
37985 )]
37986 fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t;
37987 }
37988 unsafe { _vqdmull_s32(a, b) }
37989}
37990#[doc = "Signed saturating extract narrow"]
37991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
37992#[inline]
37993#[target_feature(enable = "neon")]
37994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
37995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
37996#[cfg_attr(
37997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
37998 assert_instr(sqxtn)
37999)]
38000#[cfg_attr(
38001 not(target_arch = "arm"),
38002 stable(feature = "neon_intrinsics", since = "1.59.0")
38003)]
38004#[cfg_attr(
38005 target_arch = "arm",
38006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38007)]
38008pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
38009 unsafe extern "unadjusted" {
38010 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")]
38011 #[cfg_attr(
38012 any(target_arch = "aarch64", target_arch = "arm64ec"),
38013 link_name = "llvm.aarch64.neon.sqxtn.v8i8"
38014 )]
38015 fn _vqmovn_s16(a: int16x8_t) -> int8x8_t;
38016 }
38017 unsafe { _vqmovn_s16(a) }
38018}
38019#[doc = "Signed saturating extract narrow"]
38020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
38021#[inline]
38022#[target_feature(enable = "neon")]
38023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38025#[cfg_attr(
38026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38027 assert_instr(sqxtn)
38028)]
38029#[cfg_attr(
38030 not(target_arch = "arm"),
38031 stable(feature = "neon_intrinsics", since = "1.59.0")
38032)]
38033#[cfg_attr(
38034 target_arch = "arm",
38035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38036)]
38037pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
38038 unsafe extern "unadjusted" {
38039 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")]
38040 #[cfg_attr(
38041 any(target_arch = "aarch64", target_arch = "arm64ec"),
38042 link_name = "llvm.aarch64.neon.sqxtn.v4i16"
38043 )]
38044 fn _vqmovn_s32(a: int32x4_t) -> int16x4_t;
38045 }
38046 unsafe { _vqmovn_s32(a) }
38047}
38048#[doc = "Signed saturating extract narrow"]
38049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
38050#[inline]
38051#[target_feature(enable = "neon")]
38052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38054#[cfg_attr(
38055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38056 assert_instr(sqxtn)
38057)]
38058#[cfg_attr(
38059 not(target_arch = "arm"),
38060 stable(feature = "neon_intrinsics", since = "1.59.0")
38061)]
38062#[cfg_attr(
38063 target_arch = "arm",
38064 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38065)]
38066pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
38067 unsafe extern "unadjusted" {
38068 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")]
38069 #[cfg_attr(
38070 any(target_arch = "aarch64", target_arch = "arm64ec"),
38071 link_name = "llvm.aarch64.neon.sqxtn.v2i32"
38072 )]
38073 fn _vqmovn_s64(a: int64x2_t) -> int32x2_t;
38074 }
38075 unsafe { _vqmovn_s64(a) }
38076}
38077#[doc = "Unsigned saturating extract narrow"]
38078#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
38079#[inline]
38080#[target_feature(enable = "neon")]
38081#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38083#[cfg_attr(
38084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38085 assert_instr(uqxtn)
38086)]
38087#[cfg_attr(
38088 not(target_arch = "arm"),
38089 stable(feature = "neon_intrinsics", since = "1.59.0")
38090)]
38091#[cfg_attr(
38092 target_arch = "arm",
38093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38094)]
38095pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
38096 unsafe extern "unadjusted" {
38097 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")]
38098 #[cfg_attr(
38099 any(target_arch = "aarch64", target_arch = "arm64ec"),
38100 link_name = "llvm.aarch64.neon.uqxtn.v8i8"
38101 )]
38102 fn _vqmovn_u16(a: uint16x8_t) -> uint8x8_t;
38103 }
38104 unsafe { _vqmovn_u16(a) }
38105}
38106#[doc = "Unsigned saturating extract narrow"]
38107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
38108#[inline]
38109#[target_feature(enable = "neon")]
38110#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38111#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38112#[cfg_attr(
38113 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38114 assert_instr(uqxtn)
38115)]
38116#[cfg_attr(
38117 not(target_arch = "arm"),
38118 stable(feature = "neon_intrinsics", since = "1.59.0")
38119)]
38120#[cfg_attr(
38121 target_arch = "arm",
38122 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38123)]
38124pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
38125 unsafe extern "unadjusted" {
38126 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")]
38127 #[cfg_attr(
38128 any(target_arch = "aarch64", target_arch = "arm64ec"),
38129 link_name = "llvm.aarch64.neon.uqxtn.v4i16"
38130 )]
38131 fn _vqmovn_u32(a: uint32x4_t) -> uint16x4_t;
38132 }
38133 unsafe { _vqmovn_u32(a) }
38134}
38135#[doc = "Unsigned saturating extract narrow"]
38136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
38137#[inline]
38138#[target_feature(enable = "neon")]
38139#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38140#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
38141#[cfg_attr(
38142 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38143 assert_instr(uqxtn)
38144)]
38145#[cfg_attr(
38146 not(target_arch = "arm"),
38147 stable(feature = "neon_intrinsics", since = "1.59.0")
38148)]
38149#[cfg_attr(
38150 target_arch = "arm",
38151 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38152)]
38153pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
38154 unsafe extern "unadjusted" {
38155 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")]
38156 #[cfg_attr(
38157 any(target_arch = "aarch64", target_arch = "arm64ec"),
38158 link_name = "llvm.aarch64.neon.uqxtn.v2i32"
38159 )]
38160 fn _vqmovn_u64(a: uint64x2_t) -> uint32x2_t;
38161 }
38162 unsafe { _vqmovn_u64(a) }
38163}
38164#[doc = "Signed saturating extract unsigned narrow"]
38165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
38166#[inline]
38167#[target_feature(enable = "neon")]
38168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38170#[cfg_attr(
38171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38172 assert_instr(sqxtun)
38173)]
38174#[cfg_attr(
38175 not(target_arch = "arm"),
38176 stable(feature = "neon_intrinsics", since = "1.59.0")
38177)]
38178#[cfg_attr(
38179 target_arch = "arm",
38180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38181)]
38182pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
38183 unsafe extern "unadjusted" {
38184 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")]
38185 #[cfg_attr(
38186 any(target_arch = "aarch64", target_arch = "arm64ec"),
38187 link_name = "llvm.aarch64.neon.sqxtun.v8i8"
38188 )]
38189 fn _vqmovun_s16(a: int16x8_t) -> uint8x8_t;
38190 }
38191 unsafe { _vqmovun_s16(a) }
38192}
38193#[doc = "Signed saturating extract unsigned narrow"]
38194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
38195#[inline]
38196#[target_feature(enable = "neon")]
38197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38199#[cfg_attr(
38200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38201 assert_instr(sqxtun)
38202)]
38203#[cfg_attr(
38204 not(target_arch = "arm"),
38205 stable(feature = "neon_intrinsics", since = "1.59.0")
38206)]
38207#[cfg_attr(
38208 target_arch = "arm",
38209 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38210)]
38211pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
38212 unsafe extern "unadjusted" {
38213 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")]
38214 #[cfg_attr(
38215 any(target_arch = "aarch64", target_arch = "arm64ec"),
38216 link_name = "llvm.aarch64.neon.sqxtun.v4i16"
38217 )]
38218 fn _vqmovun_s32(a: int32x4_t) -> uint16x4_t;
38219 }
38220 unsafe { _vqmovun_s32(a) }
38221}
38222#[doc = "Signed saturating extract unsigned narrow"]
38223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
38224#[inline]
38225#[target_feature(enable = "neon")]
38226#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38227#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
38228#[cfg_attr(
38229 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38230 assert_instr(sqxtun)
38231)]
38232#[cfg_attr(
38233 not(target_arch = "arm"),
38234 stable(feature = "neon_intrinsics", since = "1.59.0")
38235)]
38236#[cfg_attr(
38237 target_arch = "arm",
38238 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38239)]
38240pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
38241 unsafe extern "unadjusted" {
38242 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")]
38243 #[cfg_attr(
38244 any(target_arch = "aarch64", target_arch = "arm64ec"),
38245 link_name = "llvm.aarch64.neon.sqxtun.v2i32"
38246 )]
38247 fn _vqmovun_s64(a: int64x2_t) -> uint32x2_t;
38248 }
38249 unsafe { _vqmovun_s64(a) }
38250}
38251#[doc = "Signed saturating negate"]
38252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
38253#[inline]
38254#[target_feature(enable = "neon")]
38255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38256#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38257#[cfg_attr(
38258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38259 assert_instr(sqneg)
38260)]
38261#[cfg_attr(
38262 not(target_arch = "arm"),
38263 stable(feature = "neon_intrinsics", since = "1.59.0")
38264)]
38265#[cfg_attr(
38266 target_arch = "arm",
38267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38268)]
38269pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
38270 unsafe extern "unadjusted" {
38271 #[cfg_attr(
38272 any(target_arch = "aarch64", target_arch = "arm64ec"),
38273 link_name = "llvm.aarch64.neon.sqneg.v8i8"
38274 )]
38275 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")]
38276 fn _vqneg_s8(a: int8x8_t) -> int8x8_t;
38277 }
38278 unsafe { _vqneg_s8(a) }
38279}
38280#[doc = "Signed saturating negate"]
38281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
38282#[inline]
38283#[target_feature(enable = "neon")]
38284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38285#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
38286#[cfg_attr(
38287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38288 assert_instr(sqneg)
38289)]
38290#[cfg_attr(
38291 not(target_arch = "arm"),
38292 stable(feature = "neon_intrinsics", since = "1.59.0")
38293)]
38294#[cfg_attr(
38295 target_arch = "arm",
38296 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38297)]
38298pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
38299 unsafe extern "unadjusted" {
38300 #[cfg_attr(
38301 any(target_arch = "aarch64", target_arch = "arm64ec"),
38302 link_name = "llvm.aarch64.neon.sqneg.v16i8"
38303 )]
38304 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")]
38305 fn _vqnegq_s8(a: int8x16_t) -> int8x16_t;
38306 }
38307 unsafe { _vqnegq_s8(a) }
38308}
38309#[doc = "Signed saturating negate"]
38310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
38311#[inline]
38312#[target_feature(enable = "neon")]
38313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38314#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38315#[cfg_attr(
38316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38317 assert_instr(sqneg)
38318)]
38319#[cfg_attr(
38320 not(target_arch = "arm"),
38321 stable(feature = "neon_intrinsics", since = "1.59.0")
38322)]
38323#[cfg_attr(
38324 target_arch = "arm",
38325 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38326)]
38327pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
38328 unsafe extern "unadjusted" {
38329 #[cfg_attr(
38330 any(target_arch = "aarch64", target_arch = "arm64ec"),
38331 link_name = "llvm.aarch64.neon.sqneg.v4i16"
38332 )]
38333 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")]
38334 fn _vqneg_s16(a: int16x4_t) -> int16x4_t;
38335 }
38336 unsafe { _vqneg_s16(a) }
38337}
38338#[doc = "Signed saturating negate"]
38339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
38340#[inline]
38341#[target_feature(enable = "neon")]
38342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38343#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
38344#[cfg_attr(
38345 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38346 assert_instr(sqneg)
38347)]
38348#[cfg_attr(
38349 not(target_arch = "arm"),
38350 stable(feature = "neon_intrinsics", since = "1.59.0")
38351)]
38352#[cfg_attr(
38353 target_arch = "arm",
38354 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38355)]
38356pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
38357 unsafe extern "unadjusted" {
38358 #[cfg_attr(
38359 any(target_arch = "aarch64", target_arch = "arm64ec"),
38360 link_name = "llvm.aarch64.neon.sqneg.v8i16"
38361 )]
38362 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")]
38363 fn _vqnegq_s16(a: int16x8_t) -> int16x8_t;
38364 }
38365 unsafe { _vqnegq_s16(a) }
38366}
38367#[doc = "Signed saturating negate"]
38368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
38369#[inline]
38370#[target_feature(enable = "neon")]
38371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38373#[cfg_attr(
38374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38375 assert_instr(sqneg)
38376)]
38377#[cfg_attr(
38378 not(target_arch = "arm"),
38379 stable(feature = "neon_intrinsics", since = "1.59.0")
38380)]
38381#[cfg_attr(
38382 target_arch = "arm",
38383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38384)]
38385pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
38386 unsafe extern "unadjusted" {
38387 #[cfg_attr(
38388 any(target_arch = "aarch64", target_arch = "arm64ec"),
38389 link_name = "llvm.aarch64.neon.sqneg.v2i32"
38390 )]
38391 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")]
38392 fn _vqneg_s32(a: int32x2_t) -> int32x2_t;
38393 }
38394 unsafe { _vqneg_s32(a) }
38395}
38396#[doc = "Signed saturating negate"]
38397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
38398#[inline]
38399#[target_feature(enable = "neon")]
38400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38401#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
38402#[cfg_attr(
38403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38404 assert_instr(sqneg)
38405)]
38406#[cfg_attr(
38407 not(target_arch = "arm"),
38408 stable(feature = "neon_intrinsics", since = "1.59.0")
38409)]
38410#[cfg_attr(
38411 target_arch = "arm",
38412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38413)]
38414pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
38415 unsafe extern "unadjusted" {
38416 #[cfg_attr(
38417 any(target_arch = "aarch64", target_arch = "arm64ec"),
38418 link_name = "llvm.aarch64.neon.sqneg.v4i32"
38419 )]
38420 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")]
38421 fn _vqnegq_s32(a: int32x4_t) -> int32x4_t;
38422 }
38423 unsafe { _vqnegq_s32(a) }
38424}
38425#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38426#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
38427#[inline]
38428#[target_feature(enable = "neon")]
38429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38431#[cfg_attr(
38432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38433 assert_instr(sqrdmulh, LANE = 1)
38434)]
38435#[rustc_legacy_const_generics(2)]
38436#[cfg_attr(
38437 not(target_arch = "arm"),
38438 stable(feature = "neon_intrinsics", since = "1.59.0")
38439)]
38440#[cfg_attr(
38441 target_arch = "arm",
38442 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38443)]
38444pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38445 static_assert_uimm_bits!(LANE, 2);
38446 unsafe {
38447 let b: int16x4_t =
38448 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38449 vqrdmulh_s16(a, b)
38450 }
38451}
38452#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38453#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
38454#[inline]
38455#[target_feature(enable = "neon")]
38456#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38457#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38458#[cfg_attr(
38459 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38460 assert_instr(sqrdmulh, LANE = 1)
38461)]
38462#[rustc_legacy_const_generics(2)]
38463#[cfg_attr(
38464 not(target_arch = "arm"),
38465 stable(feature = "neon_intrinsics", since = "1.59.0")
38466)]
38467#[cfg_attr(
38468 target_arch = "arm",
38469 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38470)]
38471pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38472 static_assert_uimm_bits!(LANE, 1);
38473 unsafe {
38474 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38475 vqrdmulh_s32(a, b)
38476 }
38477}
38478#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
38480#[inline]
38481#[target_feature(enable = "neon")]
38482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38484#[cfg_attr(
38485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38486 assert_instr(sqrdmulh, LANE = 1)
38487)]
38488#[rustc_legacy_const_generics(2)]
38489#[cfg_attr(
38490 not(target_arch = "arm"),
38491 stable(feature = "neon_intrinsics", since = "1.59.0")
38492)]
38493#[cfg_attr(
38494 target_arch = "arm",
38495 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38496)]
38497pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
38498 static_assert_uimm_bits!(LANE, 3);
38499 unsafe {
38500 let b: int16x4_t =
38501 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38502 vqrdmulh_s16(a, b)
38503 }
38504}
38505#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
38507#[inline]
38508#[target_feature(enable = "neon")]
38509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38510#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38511#[cfg_attr(
38512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38513 assert_instr(sqrdmulh, LANE = 1)
38514)]
38515#[rustc_legacy_const_generics(2)]
38516#[cfg_attr(
38517 not(target_arch = "arm"),
38518 stable(feature = "neon_intrinsics", since = "1.59.0")
38519)]
38520#[cfg_attr(
38521 target_arch = "arm",
38522 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38523)]
38524pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
38525 static_assert_uimm_bits!(LANE, 2);
38526 unsafe {
38527 let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]);
38528 vqrdmulh_s32(a, b)
38529 }
38530}
38531#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
38533#[inline]
38534#[target_feature(enable = "neon")]
38535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38537#[cfg_attr(
38538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38539 assert_instr(sqrdmulh, LANE = 1)
38540)]
38541#[rustc_legacy_const_generics(2)]
38542#[cfg_attr(
38543 not(target_arch = "arm"),
38544 stable(feature = "neon_intrinsics", since = "1.59.0")
38545)]
38546#[cfg_attr(
38547 target_arch = "arm",
38548 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38549)]
38550pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
38551 static_assert_uimm_bits!(LANE, 2);
38552 unsafe {
38553 let b: int16x8_t = simd_shuffle!(
38554 b,
38555 b,
38556 [
38557 LANE as u32,
38558 LANE as u32,
38559 LANE as u32,
38560 LANE as u32,
38561 LANE as u32,
38562 LANE as u32,
38563 LANE as u32,
38564 LANE as u32
38565 ]
38566 );
38567 vqrdmulhq_s16(a, b)
38568 }
38569}
38570#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
38572#[inline]
38573#[target_feature(enable = "neon")]
38574#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38575#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38576#[cfg_attr(
38577 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38578 assert_instr(sqrdmulh, LANE = 1)
38579)]
38580#[rustc_legacy_const_generics(2)]
38581#[cfg_attr(
38582 not(target_arch = "arm"),
38583 stable(feature = "neon_intrinsics", since = "1.59.0")
38584)]
38585#[cfg_attr(
38586 target_arch = "arm",
38587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38588)]
38589pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
38590 static_assert_uimm_bits!(LANE, 1);
38591 unsafe {
38592 let b: int32x4_t =
38593 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38594 vqrdmulhq_s32(a, b)
38595 }
38596}
38597#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
38599#[inline]
38600#[target_feature(enable = "neon")]
38601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38603#[cfg_attr(
38604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38605 assert_instr(sqrdmulh, LANE = 1)
38606)]
38607#[rustc_legacy_const_generics(2)]
38608#[cfg_attr(
38609 not(target_arch = "arm"),
38610 stable(feature = "neon_intrinsics", since = "1.59.0")
38611)]
38612#[cfg_attr(
38613 target_arch = "arm",
38614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38615)]
38616pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38617 static_assert_uimm_bits!(LANE, 3);
38618 unsafe {
38619 let b: int16x8_t = simd_shuffle!(
38620 b,
38621 b,
38622 [
38623 LANE as u32,
38624 LANE as u32,
38625 LANE as u32,
38626 LANE as u32,
38627 LANE as u32,
38628 LANE as u32,
38629 LANE as u32,
38630 LANE as u32
38631 ]
38632 );
38633 vqrdmulhq_s16(a, b)
38634 }
38635}
38636#[doc = "Vector rounding saturating doubling multiply high by scalar"]
38637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
38638#[inline]
38639#[target_feature(enable = "neon")]
38640#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38641#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
38642#[cfg_attr(
38643 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38644 assert_instr(sqrdmulh, LANE = 1)
38645)]
38646#[rustc_legacy_const_generics(2)]
38647#[cfg_attr(
38648 not(target_arch = "arm"),
38649 stable(feature = "neon_intrinsics", since = "1.59.0")
38650)]
38651#[cfg_attr(
38652 target_arch = "arm",
38653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38654)]
38655pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38656 static_assert_uimm_bits!(LANE, 2);
38657 unsafe {
38658 let b: int32x4_t =
38659 simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
38660 vqrdmulhq_s32(a, b)
38661 }
38662}
38663#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
38665#[inline]
38666#[target_feature(enable = "neon")]
38667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38669#[cfg_attr(
38670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38671 assert_instr(sqrdmulh)
38672)]
38673#[cfg_attr(
38674 not(target_arch = "arm"),
38675 stable(feature = "neon_intrinsics", since = "1.59.0")
38676)]
38677#[cfg_attr(
38678 target_arch = "arm",
38679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38680)]
38681pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
38682 vqrdmulh_s16(a, vdup_n_s16(b))
38683}
38684#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
38686#[inline]
38687#[target_feature(enable = "neon")]
38688#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38689#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38690#[cfg_attr(
38691 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38692 assert_instr(sqrdmulh)
38693)]
38694#[cfg_attr(
38695 not(target_arch = "arm"),
38696 stable(feature = "neon_intrinsics", since = "1.59.0")
38697)]
38698#[cfg_attr(
38699 target_arch = "arm",
38700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38701)]
38702pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
38703 vqrdmulhq_s16(a, vdupq_n_s16(b))
38704}
38705#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
38707#[inline]
38708#[target_feature(enable = "neon")]
38709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38711#[cfg_attr(
38712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38713 assert_instr(sqrdmulh)
38714)]
38715#[cfg_attr(
38716 not(target_arch = "arm"),
38717 stable(feature = "neon_intrinsics", since = "1.59.0")
38718)]
38719#[cfg_attr(
38720 target_arch = "arm",
38721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38722)]
38723pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
38724 vqrdmulh_s32(a, vdup_n_s32(b))
38725}
38726#[doc = "Vector saturating rounding doubling multiply high with scalar"]
38727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
38728#[inline]
38729#[target_feature(enable = "neon")]
38730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38732#[cfg_attr(
38733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38734 assert_instr(sqrdmulh)
38735)]
38736#[cfg_attr(
38737 not(target_arch = "arm"),
38738 stable(feature = "neon_intrinsics", since = "1.59.0")
38739)]
38740#[cfg_attr(
38741 target_arch = "arm",
38742 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38743)]
38744pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
38745 vqrdmulhq_s32(a, vdupq_n_s32(b))
38746}
38747#[doc = "Signed saturating rounding doubling multiply returning high half"]
38748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
38749#[inline]
38750#[target_feature(enable = "neon")]
38751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38753#[cfg_attr(
38754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38755 assert_instr(sqrdmulh)
38756)]
38757#[cfg_attr(
38758 not(target_arch = "arm"),
38759 stable(feature = "neon_intrinsics", since = "1.59.0")
38760)]
38761#[cfg_attr(
38762 target_arch = "arm",
38763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38764)]
38765pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38766 unsafe extern "unadjusted" {
38767 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")]
38768 #[cfg_attr(
38769 any(target_arch = "aarch64", target_arch = "arm64ec"),
38770 link_name = "llvm.aarch64.neon.sqrdmulh.v4i16"
38771 )]
38772 fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
38773 }
38774 unsafe { _vqrdmulh_s16(a, b) }
38775}
38776#[doc = "Signed saturating rounding doubling multiply returning high half"]
38777#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
38778#[inline]
38779#[target_feature(enable = "neon")]
38780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38782#[cfg_attr(
38783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38784 assert_instr(sqrdmulh)
38785)]
38786#[cfg_attr(
38787 not(target_arch = "arm"),
38788 stable(feature = "neon_intrinsics", since = "1.59.0")
38789)]
38790#[cfg_attr(
38791 target_arch = "arm",
38792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38793)]
38794pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38795 unsafe extern "unadjusted" {
38796 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")]
38797 #[cfg_attr(
38798 any(target_arch = "aarch64", target_arch = "arm64ec"),
38799 link_name = "llvm.aarch64.neon.sqrdmulh.v8i16"
38800 )]
38801 fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
38802 }
38803 unsafe { _vqrdmulhq_s16(a, b) }
38804}
38805#[doc = "Signed saturating rounding doubling multiply returning high half"]
38806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
38807#[inline]
38808#[target_feature(enable = "neon")]
38809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38811#[cfg_attr(
38812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38813 assert_instr(sqrdmulh)
38814)]
38815#[cfg_attr(
38816 not(target_arch = "arm"),
38817 stable(feature = "neon_intrinsics", since = "1.59.0")
38818)]
38819#[cfg_attr(
38820 target_arch = "arm",
38821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38822)]
38823pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38824 unsafe extern "unadjusted" {
38825 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")]
38826 #[cfg_attr(
38827 any(target_arch = "aarch64", target_arch = "arm64ec"),
38828 link_name = "llvm.aarch64.neon.sqrdmulh.v2i32"
38829 )]
38830 fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
38831 }
38832 unsafe { _vqrdmulh_s32(a, b) }
38833}
38834#[doc = "Signed saturating rounding doubling multiply returning high half"]
38835#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
38836#[inline]
38837#[target_feature(enable = "neon")]
38838#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38839#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
38840#[cfg_attr(
38841 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38842 assert_instr(sqrdmulh)
38843)]
38844#[cfg_attr(
38845 not(target_arch = "arm"),
38846 stable(feature = "neon_intrinsics", since = "1.59.0")
38847)]
38848#[cfg_attr(
38849 target_arch = "arm",
38850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38851)]
38852pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
38853 unsafe extern "unadjusted" {
38854 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")]
38855 #[cfg_attr(
38856 any(target_arch = "aarch64", target_arch = "arm64ec"),
38857 link_name = "llvm.aarch64.neon.sqrdmulh.v4i32"
38858 )]
38859 fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
38860 }
38861 unsafe { _vqrdmulhq_s32(a, b) }
38862}
38863#[doc = "Signed saturating rounding shift left"]
38864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
38865#[inline]
38866#[target_feature(enable = "neon")]
38867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
38869#[cfg_attr(
38870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38871 assert_instr(sqrshl)
38872)]
38873#[cfg_attr(
38874 not(target_arch = "arm"),
38875 stable(feature = "neon_intrinsics", since = "1.59.0")
38876)]
38877#[cfg_attr(
38878 target_arch = "arm",
38879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38880)]
38881pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
38882 unsafe extern "unadjusted" {
38883 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")]
38884 #[cfg_attr(
38885 any(target_arch = "aarch64", target_arch = "arm64ec"),
38886 link_name = "llvm.aarch64.neon.sqrshl.v8i8"
38887 )]
38888 fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
38889 }
38890 unsafe { _vqrshl_s8(a, b) }
38891}
38892#[doc = "Signed saturating rounding shift left"]
38893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
38894#[inline]
38895#[target_feature(enable = "neon")]
38896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
38898#[cfg_attr(
38899 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38900 assert_instr(sqrshl)
38901)]
38902#[cfg_attr(
38903 not(target_arch = "arm"),
38904 stable(feature = "neon_intrinsics", since = "1.59.0")
38905)]
38906#[cfg_attr(
38907 target_arch = "arm",
38908 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38909)]
38910pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
38911 unsafe extern "unadjusted" {
38912 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")]
38913 #[cfg_attr(
38914 any(target_arch = "aarch64", target_arch = "arm64ec"),
38915 link_name = "llvm.aarch64.neon.sqrshl.v16i8"
38916 )]
38917 fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
38918 }
38919 unsafe { _vqrshlq_s8(a, b) }
38920}
38921#[doc = "Signed saturating rounding shift left"]
38922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
38923#[inline]
38924#[target_feature(enable = "neon")]
38925#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38926#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
38927#[cfg_attr(
38928 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38929 assert_instr(sqrshl)
38930)]
38931#[cfg_attr(
38932 not(target_arch = "arm"),
38933 stable(feature = "neon_intrinsics", since = "1.59.0")
38934)]
38935#[cfg_attr(
38936 target_arch = "arm",
38937 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38938)]
38939pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
38940 unsafe extern "unadjusted" {
38941 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")]
38942 #[cfg_attr(
38943 any(target_arch = "aarch64", target_arch = "arm64ec"),
38944 link_name = "llvm.aarch64.neon.sqrshl.v4i16"
38945 )]
38946 fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
38947 }
38948 unsafe { _vqrshl_s16(a, b) }
38949}
38950#[doc = "Signed saturating rounding shift left"]
38951#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
38952#[inline]
38953#[target_feature(enable = "neon")]
38954#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38955#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
38956#[cfg_attr(
38957 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38958 assert_instr(sqrshl)
38959)]
38960#[cfg_attr(
38961 not(target_arch = "arm"),
38962 stable(feature = "neon_intrinsics", since = "1.59.0")
38963)]
38964#[cfg_attr(
38965 target_arch = "arm",
38966 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38967)]
38968pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
38969 unsafe extern "unadjusted" {
38970 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")]
38971 #[cfg_attr(
38972 any(target_arch = "aarch64", target_arch = "arm64ec"),
38973 link_name = "llvm.aarch64.neon.sqrshl.v8i16"
38974 )]
38975 fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
38976 }
38977 unsafe { _vqrshlq_s16(a, b) }
38978}
38979#[doc = "Signed saturating rounding shift left"]
38980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
38981#[inline]
38982#[target_feature(enable = "neon")]
38983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
38984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
38985#[cfg_attr(
38986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
38987 assert_instr(sqrshl)
38988)]
38989#[cfg_attr(
38990 not(target_arch = "arm"),
38991 stable(feature = "neon_intrinsics", since = "1.59.0")
38992)]
38993#[cfg_attr(
38994 target_arch = "arm",
38995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
38996)]
38997pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
38998 unsafe extern "unadjusted" {
38999 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")]
39000 #[cfg_attr(
39001 any(target_arch = "aarch64", target_arch = "arm64ec"),
39002 link_name = "llvm.aarch64.neon.sqrshl.v2i32"
39003 )]
39004 fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
39005 }
39006 unsafe { _vqrshl_s32(a, b) }
39007}
39008#[doc = "Signed saturating rounding shift left"]
39009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
39010#[inline]
39011#[target_feature(enable = "neon")]
39012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39014#[cfg_attr(
39015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39016 assert_instr(sqrshl)
39017)]
39018#[cfg_attr(
39019 not(target_arch = "arm"),
39020 stable(feature = "neon_intrinsics", since = "1.59.0")
39021)]
39022#[cfg_attr(
39023 target_arch = "arm",
39024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39025)]
39026pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
39027 unsafe extern "unadjusted" {
39028 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")]
39029 #[cfg_attr(
39030 any(target_arch = "aarch64", target_arch = "arm64ec"),
39031 link_name = "llvm.aarch64.neon.sqrshl.v4i32"
39032 )]
39033 fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
39034 }
39035 unsafe { _vqrshlq_s32(a, b) }
39036}
39037#[doc = "Signed saturating rounding shift left"]
39038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
39039#[inline]
39040#[target_feature(enable = "neon")]
39041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39043#[cfg_attr(
39044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39045 assert_instr(sqrshl)
39046)]
39047#[cfg_attr(
39048 not(target_arch = "arm"),
39049 stable(feature = "neon_intrinsics", since = "1.59.0")
39050)]
39051#[cfg_attr(
39052 target_arch = "arm",
39053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39054)]
39055pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
39056 unsafe extern "unadjusted" {
39057 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")]
39058 #[cfg_attr(
39059 any(target_arch = "aarch64", target_arch = "arm64ec"),
39060 link_name = "llvm.aarch64.neon.sqrshl.v1i64"
39061 )]
39062 fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
39063 }
39064 unsafe { _vqrshl_s64(a, b) }
39065}
39066#[doc = "Signed saturating rounding shift left"]
39067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
39068#[inline]
39069#[target_feature(enable = "neon")]
39070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39072#[cfg_attr(
39073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39074 assert_instr(sqrshl)
39075)]
39076#[cfg_attr(
39077 not(target_arch = "arm"),
39078 stable(feature = "neon_intrinsics", since = "1.59.0")
39079)]
39080#[cfg_attr(
39081 target_arch = "arm",
39082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39083)]
39084pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
39085 unsafe extern "unadjusted" {
39086 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")]
39087 #[cfg_attr(
39088 any(target_arch = "aarch64", target_arch = "arm64ec"),
39089 link_name = "llvm.aarch64.neon.sqrshl.v2i64"
39090 )]
39091 fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
39092 }
39093 unsafe { _vqrshlq_s64(a, b) }
39094}
39095#[doc = "Unsigned signed saturating rounding shift left"]
39096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
39097#[inline]
39098#[target_feature(enable = "neon")]
39099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39101#[cfg_attr(
39102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39103 assert_instr(uqrshl)
39104)]
39105#[cfg_attr(
39106 not(target_arch = "arm"),
39107 stable(feature = "neon_intrinsics", since = "1.59.0")
39108)]
39109#[cfg_attr(
39110 target_arch = "arm",
39111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39112)]
39113pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
39114 unsafe extern "unadjusted" {
39115 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")]
39116 #[cfg_attr(
39117 any(target_arch = "aarch64", target_arch = "arm64ec"),
39118 link_name = "llvm.aarch64.neon.uqrshl.v8i8"
39119 )]
39120 fn _vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
39121 }
39122 unsafe { _vqrshl_u8(a, b) }
39123}
39124#[doc = "Unsigned signed saturating rounding shift left"]
39125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
39126#[inline]
39127#[target_feature(enable = "neon")]
39128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39130#[cfg_attr(
39131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39132 assert_instr(uqrshl)
39133)]
39134#[cfg_attr(
39135 not(target_arch = "arm"),
39136 stable(feature = "neon_intrinsics", since = "1.59.0")
39137)]
39138#[cfg_attr(
39139 target_arch = "arm",
39140 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39141)]
39142pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
39143 unsafe extern "unadjusted" {
39144 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")]
39145 #[cfg_attr(
39146 any(target_arch = "aarch64", target_arch = "arm64ec"),
39147 link_name = "llvm.aarch64.neon.uqrshl.v16i8"
39148 )]
39149 fn _vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
39150 }
39151 unsafe { _vqrshlq_u8(a, b) }
39152}
39153#[doc = "Unsigned signed saturating rounding shift left"]
39154#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
39155#[inline]
39156#[target_feature(enable = "neon")]
39157#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39158#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39159#[cfg_attr(
39160 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39161 assert_instr(uqrshl)
39162)]
39163#[cfg_attr(
39164 not(target_arch = "arm"),
39165 stable(feature = "neon_intrinsics", since = "1.59.0")
39166)]
39167#[cfg_attr(
39168 target_arch = "arm",
39169 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39170)]
39171pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
39172 unsafe extern "unadjusted" {
39173 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")]
39174 #[cfg_attr(
39175 any(target_arch = "aarch64", target_arch = "arm64ec"),
39176 link_name = "llvm.aarch64.neon.uqrshl.v4i16"
39177 )]
39178 fn _vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
39179 }
39180 unsafe { _vqrshl_u16(a, b) }
39181}
39182#[doc = "Unsigned signed saturating rounding shift left"]
39183#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
39184#[inline]
39185#[target_feature(enable = "neon")]
39186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39188#[cfg_attr(
39189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39190 assert_instr(uqrshl)
39191)]
39192#[cfg_attr(
39193 not(target_arch = "arm"),
39194 stable(feature = "neon_intrinsics", since = "1.59.0")
39195)]
39196#[cfg_attr(
39197 target_arch = "arm",
39198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39199)]
39200pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
39201 unsafe extern "unadjusted" {
39202 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")]
39203 #[cfg_attr(
39204 any(target_arch = "aarch64", target_arch = "arm64ec"),
39205 link_name = "llvm.aarch64.neon.uqrshl.v8i16"
39206 )]
39207 fn _vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
39208 }
39209 unsafe { _vqrshlq_u16(a, b) }
39210}
39211#[doc = "Unsigned signed saturating rounding shift left"]
39212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
39213#[inline]
39214#[target_feature(enable = "neon")]
39215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39217#[cfg_attr(
39218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39219 assert_instr(uqrshl)
39220)]
39221#[cfg_attr(
39222 not(target_arch = "arm"),
39223 stable(feature = "neon_intrinsics", since = "1.59.0")
39224)]
39225#[cfg_attr(
39226 target_arch = "arm",
39227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39228)]
39229pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
39230 unsafe extern "unadjusted" {
39231 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")]
39232 #[cfg_attr(
39233 any(target_arch = "aarch64", target_arch = "arm64ec"),
39234 link_name = "llvm.aarch64.neon.uqrshl.v2i32"
39235 )]
39236 fn _vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
39237 }
39238 unsafe { _vqrshl_u32(a, b) }
39239}
39240#[doc = "Unsigned signed saturating rounding shift left"]
39241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
39242#[inline]
39243#[target_feature(enable = "neon")]
39244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39246#[cfg_attr(
39247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39248 assert_instr(uqrshl)
39249)]
39250#[cfg_attr(
39251 not(target_arch = "arm"),
39252 stable(feature = "neon_intrinsics", since = "1.59.0")
39253)]
39254#[cfg_attr(
39255 target_arch = "arm",
39256 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39257)]
39258pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
39259 unsafe extern "unadjusted" {
39260 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")]
39261 #[cfg_attr(
39262 any(target_arch = "aarch64", target_arch = "arm64ec"),
39263 link_name = "llvm.aarch64.neon.uqrshl.v4i32"
39264 )]
39265 fn _vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
39266 }
39267 unsafe { _vqrshlq_u32(a, b) }
39268}
39269#[doc = "Unsigned signed saturating rounding shift left"]
39270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
39271#[inline]
39272#[target_feature(enable = "neon")]
39273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39275#[cfg_attr(
39276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39277 assert_instr(uqrshl)
39278)]
39279#[cfg_attr(
39280 not(target_arch = "arm"),
39281 stable(feature = "neon_intrinsics", since = "1.59.0")
39282)]
39283#[cfg_attr(
39284 target_arch = "arm",
39285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39286)]
39287pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
39288 unsafe extern "unadjusted" {
39289 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")]
39290 #[cfg_attr(
39291 any(target_arch = "aarch64", target_arch = "arm64ec"),
39292 link_name = "llvm.aarch64.neon.uqrshl.v1i64"
39293 )]
39294 fn _vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
39295 }
39296 unsafe { _vqrshl_u64(a, b) }
39297}
39298#[doc = "Unsigned signed saturating rounding shift left"]
39299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
39300#[inline]
39301#[target_feature(enable = "neon")]
39302#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39303#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
39304#[cfg_attr(
39305 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39306 assert_instr(uqrshl)
39307)]
39308#[cfg_attr(
39309 not(target_arch = "arm"),
39310 stable(feature = "neon_intrinsics", since = "1.59.0")
39311)]
39312#[cfg_attr(
39313 target_arch = "arm",
39314 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39315)]
39316pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
39317 unsafe extern "unadjusted" {
39318 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")]
39319 #[cfg_attr(
39320 any(target_arch = "aarch64", target_arch = "arm64ec"),
39321 link_name = "llvm.aarch64.neon.uqrshl.v2i64"
39322 )]
39323 fn _vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
39324 }
39325 unsafe { _vqrshlq_u64(a, b) }
39326}
39327#[doc = "Signed saturating rounded shift right narrow"]
39328#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39329#[inline]
39330#[cfg(target_arch = "arm")]
39331#[target_feature(enable = "neon,v7")]
39332#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39333#[rustc_legacy_const_generics(1)]
39334#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39335pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39336 static_assert!(N >= 1 && N <= 8);
39337 unsafe extern "unadjusted" {
39338 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
39339 fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
39340 }
39341 unsafe { _vqrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
39342}
39343#[doc = "Signed saturating rounded shift right narrow"]
39344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39345#[inline]
39346#[cfg(target_arch = "arm")]
39347#[target_feature(enable = "neon,v7")]
39348#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39349#[rustc_legacy_const_generics(1)]
39350#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39351pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39352 static_assert!(N >= 1 && N <= 16);
39353 unsafe extern "unadjusted" {
39354 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
39355 fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
39356 }
39357 unsafe { _vqrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
39358}
39359#[doc = "Signed saturating rounded shift right narrow"]
39360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39361#[inline]
39362#[cfg(target_arch = "arm")]
39363#[target_feature(enable = "neon,v7")]
39364#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39365#[rustc_legacy_const_generics(1)]
39366#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39367pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39368 static_assert!(N >= 1 && N <= 32);
39369 unsafe extern "unadjusted" {
39370 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
39371 fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
39372 }
39373 unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
39374}
39375#[doc = "Signed saturating rounded shift right narrow"]
39376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
39377#[inline]
39378#[target_feature(enable = "neon")]
39379#[cfg(not(target_arch = "arm"))]
39380#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39381#[rustc_legacy_const_generics(1)]
39382#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39383pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
39384 static_assert!(N >= 1 && N <= 8);
39385 unsafe extern "unadjusted" {
39386 #[cfg_attr(
39387 any(target_arch = "aarch64", target_arch = "arm64ec"),
39388 link_name = "llvm.aarch64.neon.sqrshrn.v8i8"
39389 )]
39390 fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
39391 }
39392 unsafe { _vqrshrn_n_s16(a, N) }
39393}
39394#[doc = "Signed saturating rounded shift right narrow"]
39395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
39396#[inline]
39397#[target_feature(enable = "neon")]
39398#[cfg(not(target_arch = "arm"))]
39399#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39400#[rustc_legacy_const_generics(1)]
39401#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39402pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
39403 static_assert!(N >= 1 && N <= 16);
39404 unsafe extern "unadjusted" {
39405 #[cfg_attr(
39406 any(target_arch = "aarch64", target_arch = "arm64ec"),
39407 link_name = "llvm.aarch64.neon.sqrshrn.v4i16"
39408 )]
39409 fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
39410 }
39411 unsafe { _vqrshrn_n_s32(a, N) }
39412}
39413#[doc = "Signed saturating rounded shift right narrow"]
39414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
39415#[inline]
39416#[target_feature(enable = "neon")]
39417#[cfg(not(target_arch = "arm"))]
39418#[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
39419#[rustc_legacy_const_generics(1)]
39420#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39421pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
39422 static_assert!(N >= 1 && N <= 32);
39423 unsafe extern "unadjusted" {
39424 #[cfg_attr(
39425 any(target_arch = "aarch64", target_arch = "arm64ec"),
39426 link_name = "llvm.aarch64.neon.sqrshrn.v2i32"
39427 )]
39428 fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
39429 }
39430 unsafe { _vqrshrn_n_s64(a, N) }
39431}
39432#[doc = "Unsigned signed saturating rounded shift right narrow"]
39433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39434#[inline]
39435#[cfg(target_arch = "arm")]
39436#[target_feature(enable = "neon,v7")]
39437#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39438#[rustc_legacy_const_generics(1)]
39439#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39440pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39441 static_assert!(N >= 1 && N <= 8);
39442 unsafe extern "unadjusted" {
39443 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")]
39444 fn _vqrshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
39445 }
39446 unsafe {
39447 _vqrshrn_n_u16(
39448 a,
39449 const {
39450 uint16x8_t([
39451 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
39452 -N as u16,
39453 ])
39454 },
39455 )
39456 }
39457}
39458#[doc = "Unsigned signed saturating rounded shift right narrow"]
39459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39460#[inline]
39461#[cfg(target_arch = "arm")]
39462#[target_feature(enable = "neon,v7")]
39463#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39464#[rustc_legacy_const_generics(1)]
39465#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39466pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39467 static_assert!(N >= 1 && N <= 16);
39468 unsafe extern "unadjusted" {
39469 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")]
39470 fn _vqrshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
39471 }
39472 unsafe {
39473 _vqrshrn_n_u32(
39474 a,
39475 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
39476 )
39477 }
39478}
39479#[doc = "Unsigned signed saturating rounded shift right narrow"]
39480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39481#[inline]
39482#[cfg(target_arch = "arm")]
39483#[target_feature(enable = "neon,v7")]
39484#[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
39485#[rustc_legacy_const_generics(1)]
39486#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39487pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39488 static_assert!(N >= 1 && N <= 32);
39489 unsafe extern "unadjusted" {
39490 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")]
39491 fn _vqrshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
39492 }
39493 unsafe { _vqrshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
39494}
39495#[doc = "Unsigned signed saturating rounded shift right narrow"]
39496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
39497#[inline]
39498#[target_feature(enable = "neon")]
39499#[cfg(not(target_arch = "arm"))]
39500#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39501#[rustc_legacy_const_generics(1)]
39502#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39503pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
39504 static_assert!(N >= 1 && N <= 8);
39505 unsafe extern "unadjusted" {
39506 #[cfg_attr(
39507 any(target_arch = "aarch64", target_arch = "arm64ec"),
39508 link_name = "llvm.aarch64.neon.uqrshrn.v8i8"
39509 )]
39510 fn _vqrshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
39511 }
39512 unsafe { _vqrshrn_n_u16(a, N) }
39513}
39514#[doc = "Unsigned signed saturating rounded shift right narrow"]
39515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
39516#[inline]
39517#[target_feature(enable = "neon")]
39518#[cfg(not(target_arch = "arm"))]
39519#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39520#[rustc_legacy_const_generics(1)]
39521#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39522pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
39523 static_assert!(N >= 1 && N <= 16);
39524 unsafe extern "unadjusted" {
39525 #[cfg_attr(
39526 any(target_arch = "aarch64", target_arch = "arm64ec"),
39527 link_name = "llvm.aarch64.neon.uqrshrn.v4i16"
39528 )]
39529 fn _vqrshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
39530 }
39531 unsafe { _vqrshrn_n_u32(a, N) }
39532}
39533#[doc = "Unsigned signed saturating rounded shift right narrow"]
39534#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
39535#[inline]
39536#[target_feature(enable = "neon")]
39537#[cfg(not(target_arch = "arm"))]
39538#[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
39539#[rustc_legacy_const_generics(1)]
39540#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39541pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
39542 static_assert!(N >= 1 && N <= 32);
39543 unsafe extern "unadjusted" {
39544 #[cfg_attr(
39545 any(target_arch = "aarch64", target_arch = "arm64ec"),
39546 link_name = "llvm.aarch64.neon.uqrshrn.v2i32"
39547 )]
39548 fn _vqrshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
39549 }
39550 unsafe { _vqrshrn_n_u64(a, N) }
39551}
39552#[doc = "Signed saturating rounded shift right unsigned narrow"]
39553#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39554#[inline]
39555#[cfg(target_arch = "arm")]
39556#[target_feature(enable = "neon,v7")]
39557#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39558#[rustc_legacy_const_generics(1)]
39559#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39560pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39561 static_assert!(N >= 1 && N <= 8);
39562 unsafe extern "unadjusted" {
39563 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
39564 fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
39565 }
39566 unsafe { _vqrshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
39567}
39568#[doc = "Signed saturating rounded shift right unsigned narrow"]
39569#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39570#[inline]
39571#[cfg(target_arch = "arm")]
39572#[target_feature(enable = "neon,v7")]
39573#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39574#[rustc_legacy_const_generics(1)]
39575#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39576pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39577 static_assert!(N >= 1 && N <= 16);
39578 unsafe extern "unadjusted" {
39579 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
39580 fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
39581 }
39582 unsafe { _vqrshrun_n_s32(a, const { int32x4_t([-N; 4]) }) }
39583}
39584#[doc = "Signed saturating rounded shift right unsigned narrow"]
39585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39586#[inline]
39587#[cfg(target_arch = "arm")]
39588#[target_feature(enable = "neon,v7")]
39589#[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
39590#[rustc_legacy_const_generics(1)]
39591#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
39592pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39593 static_assert!(N >= 1 && N <= 32);
39594 unsafe extern "unadjusted" {
39595 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
39596 fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
39597 }
39598 unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
39599}
39600#[doc = "Signed saturating rounded shift right unsigned narrow"]
39601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
39602#[inline]
39603#[target_feature(enable = "neon")]
39604#[cfg(not(target_arch = "arm"))]
39605#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39606#[rustc_legacy_const_generics(1)]
39607#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39608pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
39609 static_assert!(N >= 1 && N <= 8);
39610 unsafe extern "unadjusted" {
39611 #[cfg_attr(
39612 any(target_arch = "aarch64", target_arch = "arm64ec"),
39613 link_name = "llvm.aarch64.neon.sqrshrun.v8i8"
39614 )]
39615 fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
39616 }
39617 unsafe { _vqrshrun_n_s16(a, N) }
39618}
39619#[doc = "Signed saturating rounded shift right unsigned narrow"]
39620#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
39621#[inline]
39622#[target_feature(enable = "neon")]
39623#[cfg(not(target_arch = "arm"))]
39624#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39625#[rustc_legacy_const_generics(1)]
39626#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39627pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
39628 static_assert!(N >= 1 && N <= 16);
39629 unsafe extern "unadjusted" {
39630 #[cfg_attr(
39631 any(target_arch = "aarch64", target_arch = "arm64ec"),
39632 link_name = "llvm.aarch64.neon.sqrshrun.v4i16"
39633 )]
39634 fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
39635 }
39636 unsafe { _vqrshrun_n_s32(a, N) }
39637}
39638#[doc = "Signed saturating rounded shift right unsigned narrow"]
39639#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
39640#[inline]
39641#[target_feature(enable = "neon")]
39642#[cfg(not(target_arch = "arm"))]
39643#[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
39644#[rustc_legacy_const_generics(1)]
39645#[stable(feature = "neon_intrinsics", since = "1.59.0")]
39646pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
39647 static_assert!(N >= 1 && N <= 32);
39648 unsafe extern "unadjusted" {
39649 #[cfg_attr(
39650 any(target_arch = "aarch64", target_arch = "arm64ec"),
39651 link_name = "llvm.aarch64.neon.sqrshrun.v2i32"
39652 )]
39653 fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
39654 }
39655 unsafe { _vqrshrun_n_s64(a, N) }
39656}
39657#[doc = "Signed saturating shift left"]
39658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
39659#[inline]
39660#[target_feature(enable = "neon")]
39661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39663#[cfg_attr(
39664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39665 assert_instr(sqshl, N = 2)
39666)]
39667#[rustc_legacy_const_generics(1)]
39668#[cfg_attr(
39669 not(target_arch = "arm"),
39670 stable(feature = "neon_intrinsics", since = "1.59.0")
39671)]
39672#[cfg_attr(
39673 target_arch = "arm",
39674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39675)]
39676pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
39677 static_assert_uimm_bits!(N, 3);
39678 vqshl_s8(a, vdup_n_s8(N as _))
39679}
39680#[doc = "Signed saturating shift left"]
39681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
39682#[inline]
39683#[target_feature(enable = "neon")]
39684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39686#[cfg_attr(
39687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39688 assert_instr(sqshl, N = 2)
39689)]
39690#[rustc_legacy_const_generics(1)]
39691#[cfg_attr(
39692 not(target_arch = "arm"),
39693 stable(feature = "neon_intrinsics", since = "1.59.0")
39694)]
39695#[cfg_attr(
39696 target_arch = "arm",
39697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39698)]
39699pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
39700 static_assert_uimm_bits!(N, 3);
39701 vqshlq_s8(a, vdupq_n_s8(N as _))
39702}
39703#[doc = "Signed saturating shift left"]
39704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
39705#[inline]
39706#[target_feature(enable = "neon")]
39707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39709#[cfg_attr(
39710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39711 assert_instr(sqshl, N = 2)
39712)]
39713#[rustc_legacy_const_generics(1)]
39714#[cfg_attr(
39715 not(target_arch = "arm"),
39716 stable(feature = "neon_intrinsics", since = "1.59.0")
39717)]
39718#[cfg_attr(
39719 target_arch = "arm",
39720 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39721)]
39722pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
39723 static_assert_uimm_bits!(N, 4);
39724 vqshl_s16(a, vdup_n_s16(N as _))
39725}
39726#[doc = "Signed saturating shift left"]
39727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
39728#[inline]
39729#[target_feature(enable = "neon")]
39730#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39731#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39732#[cfg_attr(
39733 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39734 assert_instr(sqshl, N = 2)
39735)]
39736#[rustc_legacy_const_generics(1)]
39737#[cfg_attr(
39738 not(target_arch = "arm"),
39739 stable(feature = "neon_intrinsics", since = "1.59.0")
39740)]
39741#[cfg_attr(
39742 target_arch = "arm",
39743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39744)]
39745pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
39746 static_assert_uimm_bits!(N, 4);
39747 vqshlq_s16(a, vdupq_n_s16(N as _))
39748}
39749#[doc = "Signed saturating shift left"]
39750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
39751#[inline]
39752#[target_feature(enable = "neon")]
39753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39755#[cfg_attr(
39756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39757 assert_instr(sqshl, N = 2)
39758)]
39759#[rustc_legacy_const_generics(1)]
39760#[cfg_attr(
39761 not(target_arch = "arm"),
39762 stable(feature = "neon_intrinsics", since = "1.59.0")
39763)]
39764#[cfg_attr(
39765 target_arch = "arm",
39766 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39767)]
39768pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
39769 static_assert_uimm_bits!(N, 5);
39770 vqshl_s32(a, vdup_n_s32(N as _))
39771}
39772#[doc = "Signed saturating shift left"]
39773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
39774#[inline]
39775#[target_feature(enable = "neon")]
39776#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39777#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39778#[cfg_attr(
39779 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39780 assert_instr(sqshl, N = 2)
39781)]
39782#[rustc_legacy_const_generics(1)]
39783#[cfg_attr(
39784 not(target_arch = "arm"),
39785 stable(feature = "neon_intrinsics", since = "1.59.0")
39786)]
39787#[cfg_attr(
39788 target_arch = "arm",
39789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39790)]
39791pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
39792 static_assert_uimm_bits!(N, 5);
39793 vqshlq_s32(a, vdupq_n_s32(N as _))
39794}
39795#[doc = "Signed saturating shift left"]
39796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
39797#[inline]
39798#[target_feature(enable = "neon")]
39799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39800#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39801#[cfg_attr(
39802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39803 assert_instr(sqshl, N = 2)
39804)]
39805#[rustc_legacy_const_generics(1)]
39806#[cfg_attr(
39807 not(target_arch = "arm"),
39808 stable(feature = "neon_intrinsics", since = "1.59.0")
39809)]
39810#[cfg_attr(
39811 target_arch = "arm",
39812 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39813)]
39814pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
39815 static_assert_uimm_bits!(N, 6);
39816 vqshl_s64(a, vdup_n_s64(N as _))
39817}
39818#[doc = "Signed saturating shift left"]
39819#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
39820#[inline]
39821#[target_feature(enable = "neon")]
39822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39823#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39824#[cfg_attr(
39825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39826 assert_instr(sqshl, N = 2)
39827)]
39828#[rustc_legacy_const_generics(1)]
39829#[cfg_attr(
39830 not(target_arch = "arm"),
39831 stable(feature = "neon_intrinsics", since = "1.59.0")
39832)]
39833#[cfg_attr(
39834 target_arch = "arm",
39835 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39836)]
39837pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
39838 static_assert_uimm_bits!(N, 6);
39839 vqshlq_s64(a, vdupq_n_s64(N as _))
39840}
39841#[doc = "Unsigned saturating shift left"]
39842#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
39843#[inline]
39844#[target_feature(enable = "neon")]
39845#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39846#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39847#[cfg_attr(
39848 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39849 assert_instr(uqshl, N = 2)
39850)]
39851#[rustc_legacy_const_generics(1)]
39852#[cfg_attr(
39853 not(target_arch = "arm"),
39854 stable(feature = "neon_intrinsics", since = "1.59.0")
39855)]
39856#[cfg_attr(
39857 target_arch = "arm",
39858 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39859)]
39860pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
39861 static_assert_uimm_bits!(N, 3);
39862 vqshl_u8(a, vdup_n_s8(N as _))
39863}
39864#[doc = "Unsigned saturating shift left"]
39865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
39866#[inline]
39867#[target_feature(enable = "neon")]
39868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39870#[cfg_attr(
39871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39872 assert_instr(uqshl, N = 2)
39873)]
39874#[rustc_legacy_const_generics(1)]
39875#[cfg_attr(
39876 not(target_arch = "arm"),
39877 stable(feature = "neon_intrinsics", since = "1.59.0")
39878)]
39879#[cfg_attr(
39880 target_arch = "arm",
39881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39882)]
39883pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
39884 static_assert_uimm_bits!(N, 3);
39885 vqshlq_u8(a, vdupq_n_s8(N as _))
39886}
39887#[doc = "Unsigned saturating shift left"]
39888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
39889#[inline]
39890#[target_feature(enable = "neon")]
39891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39893#[cfg_attr(
39894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39895 assert_instr(uqshl, N = 2)
39896)]
39897#[rustc_legacy_const_generics(1)]
39898#[cfg_attr(
39899 not(target_arch = "arm"),
39900 stable(feature = "neon_intrinsics", since = "1.59.0")
39901)]
39902#[cfg_attr(
39903 target_arch = "arm",
39904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39905)]
39906pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
39907 static_assert_uimm_bits!(N, 4);
39908 vqshl_u16(a, vdup_n_s16(N as _))
39909}
39910#[doc = "Unsigned saturating shift left"]
39911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
39912#[inline]
39913#[target_feature(enable = "neon")]
39914#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39916#[cfg_attr(
39917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39918 assert_instr(uqshl, N = 2)
39919)]
39920#[rustc_legacy_const_generics(1)]
39921#[cfg_attr(
39922 not(target_arch = "arm"),
39923 stable(feature = "neon_intrinsics", since = "1.59.0")
39924)]
39925#[cfg_attr(
39926 target_arch = "arm",
39927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39928)]
39929pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
39930 static_assert_uimm_bits!(N, 4);
39931 vqshlq_u16(a, vdupq_n_s16(N as _))
39932}
39933#[doc = "Unsigned saturating shift left"]
39934#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
39935#[inline]
39936#[target_feature(enable = "neon")]
39937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39939#[cfg_attr(
39940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39941 assert_instr(uqshl, N = 2)
39942)]
39943#[rustc_legacy_const_generics(1)]
39944#[cfg_attr(
39945 not(target_arch = "arm"),
39946 stable(feature = "neon_intrinsics", since = "1.59.0")
39947)]
39948#[cfg_attr(
39949 target_arch = "arm",
39950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39951)]
39952pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
39953 static_assert_uimm_bits!(N, 5);
39954 vqshl_u32(a, vdup_n_s32(N as _))
39955}
39956#[doc = "Unsigned saturating shift left"]
39957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
39958#[inline]
39959#[target_feature(enable = "neon")]
39960#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39962#[cfg_attr(
39963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39964 assert_instr(uqshl, N = 2)
39965)]
39966#[rustc_legacy_const_generics(1)]
39967#[cfg_attr(
39968 not(target_arch = "arm"),
39969 stable(feature = "neon_intrinsics", since = "1.59.0")
39970)]
39971#[cfg_attr(
39972 target_arch = "arm",
39973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39974)]
39975pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
39976 static_assert_uimm_bits!(N, 5);
39977 vqshlq_u32(a, vdupq_n_s32(N as _))
39978}
39979#[doc = "Unsigned saturating shift left"]
39980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
39981#[inline]
39982#[target_feature(enable = "neon")]
39983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
39984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
39985#[cfg_attr(
39986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
39987 assert_instr(uqshl, N = 2)
39988)]
39989#[rustc_legacy_const_generics(1)]
39990#[cfg_attr(
39991 not(target_arch = "arm"),
39992 stable(feature = "neon_intrinsics", since = "1.59.0")
39993)]
39994#[cfg_attr(
39995 target_arch = "arm",
39996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
39997)]
39998pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
39999 static_assert_uimm_bits!(N, 6);
40000 vqshl_u64(a, vdup_n_s64(N as _))
40001}
40002#[doc = "Unsigned saturating shift left"]
40003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
40004#[inline]
40005#[target_feature(enable = "neon")]
40006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
40008#[cfg_attr(
40009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40010 assert_instr(uqshl, N = 2)
40011)]
40012#[rustc_legacy_const_generics(1)]
40013#[cfg_attr(
40014 not(target_arch = "arm"),
40015 stable(feature = "neon_intrinsics", since = "1.59.0")
40016)]
40017#[cfg_attr(
40018 target_arch = "arm",
40019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40020)]
40021pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
40022 static_assert_uimm_bits!(N, 6);
40023 vqshlq_u64(a, vdupq_n_s64(N as _))
40024}
40025#[doc = "Signed saturating shift left"]
40026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
40027#[inline]
40028#[target_feature(enable = "neon")]
40029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40030#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40031#[cfg_attr(
40032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40033 assert_instr(sqshl)
40034)]
40035#[cfg_attr(
40036 not(target_arch = "arm"),
40037 stable(feature = "neon_intrinsics", since = "1.59.0")
40038)]
40039#[cfg_attr(
40040 target_arch = "arm",
40041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40042)]
40043pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
40044 unsafe extern "unadjusted" {
40045 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")]
40046 #[cfg_attr(
40047 any(target_arch = "aarch64", target_arch = "arm64ec"),
40048 link_name = "llvm.aarch64.neon.sqshl.v8i8"
40049 )]
40050 fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
40051 }
40052 unsafe { _vqshl_s8(a, b) }
40053}
40054#[doc = "Signed saturating shift left"]
40055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
40056#[inline]
40057#[target_feature(enable = "neon")]
40058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40060#[cfg_attr(
40061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40062 assert_instr(sqshl)
40063)]
40064#[cfg_attr(
40065 not(target_arch = "arm"),
40066 stable(feature = "neon_intrinsics", since = "1.59.0")
40067)]
40068#[cfg_attr(
40069 target_arch = "arm",
40070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40071)]
40072pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
40073 unsafe extern "unadjusted" {
40074 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")]
40075 #[cfg_attr(
40076 any(target_arch = "aarch64", target_arch = "arm64ec"),
40077 link_name = "llvm.aarch64.neon.sqshl.v16i8"
40078 )]
40079 fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
40080 }
40081 unsafe { _vqshlq_s8(a, b) }
40082}
40083#[doc = "Signed saturating shift left"]
40084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
40085#[inline]
40086#[target_feature(enable = "neon")]
40087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40089#[cfg_attr(
40090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40091 assert_instr(sqshl)
40092)]
40093#[cfg_attr(
40094 not(target_arch = "arm"),
40095 stable(feature = "neon_intrinsics", since = "1.59.0")
40096)]
40097#[cfg_attr(
40098 target_arch = "arm",
40099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40100)]
40101pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
40102 unsafe extern "unadjusted" {
40103 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")]
40104 #[cfg_attr(
40105 any(target_arch = "aarch64", target_arch = "arm64ec"),
40106 link_name = "llvm.aarch64.neon.sqshl.v4i16"
40107 )]
40108 fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
40109 }
40110 unsafe { _vqshl_s16(a, b) }
40111}
40112#[doc = "Signed saturating shift left"]
40113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
40114#[inline]
40115#[target_feature(enable = "neon")]
40116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40118#[cfg_attr(
40119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40120 assert_instr(sqshl)
40121)]
40122#[cfg_attr(
40123 not(target_arch = "arm"),
40124 stable(feature = "neon_intrinsics", since = "1.59.0")
40125)]
40126#[cfg_attr(
40127 target_arch = "arm",
40128 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40129)]
40130pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
40131 unsafe extern "unadjusted" {
40132 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")]
40133 #[cfg_attr(
40134 any(target_arch = "aarch64", target_arch = "arm64ec"),
40135 link_name = "llvm.aarch64.neon.sqshl.v8i16"
40136 )]
40137 fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
40138 }
40139 unsafe { _vqshlq_s16(a, b) }
40140}
40141#[doc = "Signed saturating shift left"]
40142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
40143#[inline]
40144#[target_feature(enable = "neon")]
40145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40147#[cfg_attr(
40148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40149 assert_instr(sqshl)
40150)]
40151#[cfg_attr(
40152 not(target_arch = "arm"),
40153 stable(feature = "neon_intrinsics", since = "1.59.0")
40154)]
40155#[cfg_attr(
40156 target_arch = "arm",
40157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40158)]
40159pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
40160 unsafe extern "unadjusted" {
40161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")]
40162 #[cfg_attr(
40163 any(target_arch = "aarch64", target_arch = "arm64ec"),
40164 link_name = "llvm.aarch64.neon.sqshl.v2i32"
40165 )]
40166 fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
40167 }
40168 unsafe { _vqshl_s32(a, b) }
40169}
40170#[doc = "Signed saturating shift left"]
40171#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
40172#[inline]
40173#[target_feature(enable = "neon")]
40174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40176#[cfg_attr(
40177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40178 assert_instr(sqshl)
40179)]
40180#[cfg_attr(
40181 not(target_arch = "arm"),
40182 stable(feature = "neon_intrinsics", since = "1.59.0")
40183)]
40184#[cfg_attr(
40185 target_arch = "arm",
40186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40187)]
40188pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
40189 unsafe extern "unadjusted" {
40190 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")]
40191 #[cfg_attr(
40192 any(target_arch = "aarch64", target_arch = "arm64ec"),
40193 link_name = "llvm.aarch64.neon.sqshl.v4i32"
40194 )]
40195 fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
40196 }
40197 unsafe { _vqshlq_s32(a, b) }
40198}
40199#[doc = "Signed saturating shift left"]
40200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
40201#[inline]
40202#[target_feature(enable = "neon")]
40203#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40204#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40205#[cfg_attr(
40206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40207 assert_instr(sqshl)
40208)]
40209#[cfg_attr(
40210 not(target_arch = "arm"),
40211 stable(feature = "neon_intrinsics", since = "1.59.0")
40212)]
40213#[cfg_attr(
40214 target_arch = "arm",
40215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40216)]
40217pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
40218 unsafe extern "unadjusted" {
40219 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")]
40220 #[cfg_attr(
40221 any(target_arch = "aarch64", target_arch = "arm64ec"),
40222 link_name = "llvm.aarch64.neon.sqshl.v1i64"
40223 )]
40224 fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
40225 }
40226 unsafe { _vqshl_s64(a, b) }
40227}
40228#[doc = "Signed saturating shift left"]
40229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
40230#[inline]
40231#[target_feature(enable = "neon")]
40232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40234#[cfg_attr(
40235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40236 assert_instr(sqshl)
40237)]
40238#[cfg_attr(
40239 not(target_arch = "arm"),
40240 stable(feature = "neon_intrinsics", since = "1.59.0")
40241)]
40242#[cfg_attr(
40243 target_arch = "arm",
40244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40245)]
40246pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
40247 unsafe extern "unadjusted" {
40248 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")]
40249 #[cfg_attr(
40250 any(target_arch = "aarch64", target_arch = "arm64ec"),
40251 link_name = "llvm.aarch64.neon.sqshl.v2i64"
40252 )]
40253 fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
40254 }
40255 unsafe { _vqshlq_s64(a, b) }
40256}
40257#[doc = "Unsigned saturating shift left"]
40258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
40259#[inline]
40260#[target_feature(enable = "neon")]
40261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40263#[cfg_attr(
40264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40265 assert_instr(uqshl)
40266)]
40267#[cfg_attr(
40268 not(target_arch = "arm"),
40269 stable(feature = "neon_intrinsics", since = "1.59.0")
40270)]
40271#[cfg_attr(
40272 target_arch = "arm",
40273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40274)]
40275pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
40276 unsafe extern "unadjusted" {
40277 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")]
40278 #[cfg_attr(
40279 any(target_arch = "aarch64", target_arch = "arm64ec"),
40280 link_name = "llvm.aarch64.neon.uqshl.v8i8"
40281 )]
40282 fn _vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
40283 }
40284 unsafe { _vqshl_u8(a, b) }
40285}
40286#[doc = "Unsigned saturating shift left"]
40287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
40288#[inline]
40289#[target_feature(enable = "neon")]
40290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40291#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40292#[cfg_attr(
40293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40294 assert_instr(uqshl)
40295)]
40296#[cfg_attr(
40297 not(target_arch = "arm"),
40298 stable(feature = "neon_intrinsics", since = "1.59.0")
40299)]
40300#[cfg_attr(
40301 target_arch = "arm",
40302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40303)]
40304pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
40305 unsafe extern "unadjusted" {
40306 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")]
40307 #[cfg_attr(
40308 any(target_arch = "aarch64", target_arch = "arm64ec"),
40309 link_name = "llvm.aarch64.neon.uqshl.v16i8"
40310 )]
40311 fn _vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
40312 }
40313 unsafe { _vqshlq_u8(a, b) }
40314}
40315#[doc = "Unsigned saturating shift left"]
40316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
40317#[inline]
40318#[target_feature(enable = "neon")]
40319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40321#[cfg_attr(
40322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40323 assert_instr(uqshl)
40324)]
40325#[cfg_attr(
40326 not(target_arch = "arm"),
40327 stable(feature = "neon_intrinsics", since = "1.59.0")
40328)]
40329#[cfg_attr(
40330 target_arch = "arm",
40331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40332)]
40333pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
40334 unsafe extern "unadjusted" {
40335 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")]
40336 #[cfg_attr(
40337 any(target_arch = "aarch64", target_arch = "arm64ec"),
40338 link_name = "llvm.aarch64.neon.uqshl.v4i16"
40339 )]
40340 fn _vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
40341 }
40342 unsafe { _vqshl_u16(a, b) }
40343}
40344#[doc = "Unsigned saturating shift left"]
40345#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
40346#[inline]
40347#[target_feature(enable = "neon")]
40348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40350#[cfg_attr(
40351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40352 assert_instr(uqshl)
40353)]
40354#[cfg_attr(
40355 not(target_arch = "arm"),
40356 stable(feature = "neon_intrinsics", since = "1.59.0")
40357)]
40358#[cfg_attr(
40359 target_arch = "arm",
40360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40361)]
40362pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
40363 unsafe extern "unadjusted" {
40364 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")]
40365 #[cfg_attr(
40366 any(target_arch = "aarch64", target_arch = "arm64ec"),
40367 link_name = "llvm.aarch64.neon.uqshl.v8i16"
40368 )]
40369 fn _vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
40370 }
40371 unsafe { _vqshlq_u16(a, b) }
40372}
40373#[doc = "Unsigned saturating shift left"]
40374#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
40375#[inline]
40376#[target_feature(enable = "neon")]
40377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40379#[cfg_attr(
40380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40381 assert_instr(uqshl)
40382)]
40383#[cfg_attr(
40384 not(target_arch = "arm"),
40385 stable(feature = "neon_intrinsics", since = "1.59.0")
40386)]
40387#[cfg_attr(
40388 target_arch = "arm",
40389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40390)]
40391pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
40392 unsafe extern "unadjusted" {
40393 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")]
40394 #[cfg_attr(
40395 any(target_arch = "aarch64", target_arch = "arm64ec"),
40396 link_name = "llvm.aarch64.neon.uqshl.v2i32"
40397 )]
40398 fn _vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
40399 }
40400 unsafe { _vqshl_u32(a, b) }
40401}
40402#[doc = "Unsigned saturating shift left"]
40403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
40404#[inline]
40405#[target_feature(enable = "neon")]
40406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40408#[cfg_attr(
40409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40410 assert_instr(uqshl)
40411)]
40412#[cfg_attr(
40413 not(target_arch = "arm"),
40414 stable(feature = "neon_intrinsics", since = "1.59.0")
40415)]
40416#[cfg_attr(
40417 target_arch = "arm",
40418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40419)]
40420pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
40421 unsafe extern "unadjusted" {
40422 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")]
40423 #[cfg_attr(
40424 any(target_arch = "aarch64", target_arch = "arm64ec"),
40425 link_name = "llvm.aarch64.neon.uqshl.v4i32"
40426 )]
40427 fn _vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
40428 }
40429 unsafe { _vqshlq_u32(a, b) }
40430}
40431#[doc = "Unsigned saturating shift left"]
40432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
40433#[inline]
40434#[target_feature(enable = "neon")]
40435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40437#[cfg_attr(
40438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40439 assert_instr(uqshl)
40440)]
40441#[cfg_attr(
40442 not(target_arch = "arm"),
40443 stable(feature = "neon_intrinsics", since = "1.59.0")
40444)]
40445#[cfg_attr(
40446 target_arch = "arm",
40447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40448)]
40449pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
40450 unsafe extern "unadjusted" {
40451 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")]
40452 #[cfg_attr(
40453 any(target_arch = "aarch64", target_arch = "arm64ec"),
40454 link_name = "llvm.aarch64.neon.uqshl.v1i64"
40455 )]
40456 fn _vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
40457 }
40458 unsafe { _vqshl_u64(a, b) }
40459}
40460#[doc = "Unsigned saturating shift left"]
40461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
40462#[inline]
40463#[target_feature(enable = "neon")]
40464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
40465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
40466#[cfg_attr(
40467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
40468 assert_instr(uqshl)
40469)]
40470#[cfg_attr(
40471 not(target_arch = "arm"),
40472 stable(feature = "neon_intrinsics", since = "1.59.0")
40473)]
40474#[cfg_attr(
40475 target_arch = "arm",
40476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
40477)]
40478pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
40479 unsafe extern "unadjusted" {
40480 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")]
40481 #[cfg_attr(
40482 any(target_arch = "aarch64", target_arch = "arm64ec"),
40483 link_name = "llvm.aarch64.neon.uqshl.v2i64"
40484 )]
40485 fn _vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
40486 }
40487 unsafe { _vqshlq_u64(a, b) }
40488}
40489#[doc = "Signed saturating shift left unsigned"]
40490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40491#[inline]
40492#[cfg(target_arch = "arm")]
40493#[target_feature(enable = "neon,v7")]
40494#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40495#[rustc_legacy_const_generics(1)]
40496#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40497pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40498 static_assert_uimm_bits!(N, 3);
40499 unsafe extern "unadjusted" {
40500 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
40501 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40502 }
40503 unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
40504}
40505#[doc = "Signed saturating shift left unsigned"]
40506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40507#[inline]
40508#[cfg(target_arch = "arm")]
40509#[target_feature(enable = "neon,v7")]
40510#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40511#[rustc_legacy_const_generics(1)]
40512#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40513pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40514 static_assert_uimm_bits!(N, 3);
40515 unsafe extern "unadjusted" {
40516 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
40517 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40518 }
40519 unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
40520}
40521#[doc = "Signed saturating shift left unsigned"]
40522#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40523#[inline]
40524#[cfg(target_arch = "arm")]
40525#[target_feature(enable = "neon,v7")]
40526#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40527#[rustc_legacy_const_generics(1)]
40528#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40529pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40530 static_assert_uimm_bits!(N, 4);
40531 unsafe extern "unadjusted" {
40532 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
40533 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40534 }
40535 unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
40536}
40537#[doc = "Signed saturating shift left unsigned"]
40538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40539#[inline]
40540#[cfg(target_arch = "arm")]
40541#[target_feature(enable = "neon,v7")]
40542#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40543#[rustc_legacy_const_generics(1)]
40544#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40545pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
40546 static_assert_uimm_bits!(N, 4);
40547 unsafe extern "unadjusted" {
40548 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
40549 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
40550 }
40551 unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
40552}
40553#[doc = "Signed saturating shift left unsigned"]
40554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
40555#[inline]
40556#[cfg(target_arch = "arm")]
40557#[target_feature(enable = "neon,v7")]
40558#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40559#[rustc_legacy_const_generics(1)]
40560#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40561pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
40562 static_assert_uimm_bits!(N, 5);
40563 unsafe extern "unadjusted" {
40564 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
40565 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
40566 }
40567 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
40568}
40569#[doc = "Signed saturating shift left unsigned"]
40570#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
40571#[inline]
40572#[cfg(target_arch = "arm")]
40573#[target_feature(enable = "neon,v7")]
40574#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40575#[rustc_legacy_const_generics(1)]
40576#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40577pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
40578 static_assert_uimm_bits!(N, 5);
40579 unsafe extern "unadjusted" {
40580 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
40581 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
40582 }
40583 unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
40584}
40585#[doc = "Signed saturating shift left unsigned"]
40586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
40587#[inline]
40588#[cfg(target_arch = "arm")]
40589#[target_feature(enable = "neon,v7")]
40590#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40591#[rustc_legacy_const_generics(1)]
40592#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40593pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
40594 static_assert_uimm_bits!(N, 6);
40595 unsafe extern "unadjusted" {
40596 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")]
40597 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
40598 }
40599 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
40600}
40601#[doc = "Signed saturating shift left unsigned"]
40602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
40603#[inline]
40604#[cfg(target_arch = "arm")]
40605#[target_feature(enable = "neon,v7")]
40606#[cfg_attr(test, assert_instr(vqshlu, N = 2))]
40607#[rustc_legacy_const_generics(1)]
40608#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40609pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
40610 static_assert_uimm_bits!(N, 6);
40611 unsafe extern "unadjusted" {
40612 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
40613 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
40614 }
40615 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
40616}
40617#[doc = "Signed saturating shift left unsigned"]
40618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
40619#[inline]
40620#[target_feature(enable = "neon")]
40621#[cfg(not(target_arch = "arm"))]
40622#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40623#[rustc_legacy_const_generics(1)]
40624#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40625pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
40626 static_assert_uimm_bits!(N, 3);
40627 unsafe extern "unadjusted" {
40628 #[cfg_attr(
40629 any(target_arch = "aarch64", target_arch = "arm64ec"),
40630 link_name = "llvm.aarch64.neon.sqshlu.v8i8"
40631 )]
40632 fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
40633 }
40634 unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
40635}
40636#[doc = "Signed saturating shift left unsigned"]
40637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
40638#[inline]
40639#[target_feature(enable = "neon")]
40640#[cfg(not(target_arch = "arm"))]
40641#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40642#[rustc_legacy_const_generics(1)]
40643#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40644pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
40645 static_assert_uimm_bits!(N, 3);
40646 unsafe extern "unadjusted" {
40647 #[cfg_attr(
40648 any(target_arch = "aarch64", target_arch = "arm64ec"),
40649 link_name = "llvm.aarch64.neon.sqshlu.v16i8"
40650 )]
40651 fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
40652 }
40653 unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
40654}
40655#[doc = "Signed saturating shift left unsigned"]
40656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
40657#[inline]
40658#[target_feature(enable = "neon")]
40659#[cfg(not(target_arch = "arm"))]
40660#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40661#[rustc_legacy_const_generics(1)]
40662#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40663pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
40664 static_assert_uimm_bits!(N, 4);
40665 unsafe extern "unadjusted" {
40666 #[cfg_attr(
40667 any(target_arch = "aarch64", target_arch = "arm64ec"),
40668 link_name = "llvm.aarch64.neon.sqshlu.v4i16"
40669 )]
40670 fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
40671 }
40672 unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
40673}
40674#[doc = "Signed saturating shift left unsigned"]
40675#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
40676#[inline]
40677#[target_feature(enable = "neon")]
40678#[cfg(not(target_arch = "arm"))]
40679#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40680#[rustc_legacy_const_generics(1)]
40681#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40682pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
40683 static_assert_uimm_bits!(N, 4);
40684 unsafe extern "unadjusted" {
40685 #[cfg_attr(
40686 any(target_arch = "aarch64", target_arch = "arm64ec"),
40687 link_name = "llvm.aarch64.neon.sqshlu.v8i16"
40688 )]
40689 fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
40690 }
40691 unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
40692}
40693#[doc = "Signed saturating shift left unsigned"]
40694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
40695#[inline]
40696#[target_feature(enable = "neon")]
40697#[cfg(not(target_arch = "arm"))]
40698#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40699#[rustc_legacy_const_generics(1)]
40700#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40701pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
40702 static_assert_uimm_bits!(N, 5);
40703 unsafe extern "unadjusted" {
40704 #[cfg_attr(
40705 any(target_arch = "aarch64", target_arch = "arm64ec"),
40706 link_name = "llvm.aarch64.neon.sqshlu.v2i32"
40707 )]
40708 fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
40709 }
40710 unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
40711}
40712#[doc = "Signed saturating shift left unsigned"]
40713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
40714#[inline]
40715#[target_feature(enable = "neon")]
40716#[cfg(not(target_arch = "arm"))]
40717#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40718#[rustc_legacy_const_generics(1)]
40719#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40720pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
40721 static_assert_uimm_bits!(N, 5);
40722 unsafe extern "unadjusted" {
40723 #[cfg_attr(
40724 any(target_arch = "aarch64", target_arch = "arm64ec"),
40725 link_name = "llvm.aarch64.neon.sqshlu.v4i32"
40726 )]
40727 fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
40728 }
40729 unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
40730}
40731#[doc = "Signed saturating shift left unsigned"]
40732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
40733#[inline]
40734#[target_feature(enable = "neon")]
40735#[cfg(not(target_arch = "arm"))]
40736#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40737#[rustc_legacy_const_generics(1)]
40738#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40739pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
40740 static_assert_uimm_bits!(N, 6);
40741 unsafe extern "unadjusted" {
40742 #[cfg_attr(
40743 any(target_arch = "aarch64", target_arch = "arm64ec"),
40744 link_name = "llvm.aarch64.neon.sqshlu.v1i64"
40745 )]
40746 fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> uint64x1_t;
40747 }
40748 unsafe { _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }) }
40749}
40750#[doc = "Signed saturating shift left unsigned"]
40751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
40752#[inline]
40753#[target_feature(enable = "neon")]
40754#[cfg(not(target_arch = "arm"))]
40755#[cfg_attr(test, assert_instr(sqshlu, N = 2))]
40756#[rustc_legacy_const_generics(1)]
40757#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40758pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
40759 static_assert_uimm_bits!(N, 6);
40760 unsafe extern "unadjusted" {
40761 #[cfg_attr(
40762 any(target_arch = "aarch64", target_arch = "arm64ec"),
40763 link_name = "llvm.aarch64.neon.sqshlu.v2i64"
40764 )]
40765 fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
40766 }
40767 unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
40768}
40769#[doc = "Signed saturating shift right narrow"]
40770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
40771#[inline]
40772#[cfg(target_arch = "arm")]
40773#[target_feature(enable = "neon,v7")]
40774#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40775#[rustc_legacy_const_generics(1)]
40776#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40777pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
40778 static_assert!(N >= 1 && N <= 8);
40779 unsafe extern "unadjusted" {
40780 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
40781 fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
40782 }
40783 unsafe { _vqshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
40784}
40785#[doc = "Signed saturating shift right narrow"]
40786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
40787#[inline]
40788#[cfg(target_arch = "arm")]
40789#[target_feature(enable = "neon,v7")]
40790#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40791#[rustc_legacy_const_generics(1)]
40792#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40793pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
40794 static_assert!(N >= 1 && N <= 16);
40795 unsafe extern "unadjusted" {
40796 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
40797 fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
40798 }
40799 unsafe { _vqshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
40800}
40801#[doc = "Signed saturating shift right narrow"]
40802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
40803#[inline]
40804#[cfg(target_arch = "arm")]
40805#[target_feature(enable = "neon,v7")]
40806#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40807#[rustc_legacy_const_generics(1)]
40808#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40809pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
40810 static_assert!(N >= 1 && N <= 32);
40811 unsafe extern "unadjusted" {
40812 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
40813 fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
40814 }
40815 unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
40816}
40817#[doc = "Signed saturating shift right narrow"]
40818#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
40819#[inline]
40820#[target_feature(enable = "neon")]
40821#[cfg(not(target_arch = "arm"))]
40822#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
40823#[rustc_legacy_const_generics(1)]
40824#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40825pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
40826 static_assert!(N >= 1 && N <= 8);
40827 unsafe extern "unadjusted" {
40828 #[cfg_attr(
40829 any(target_arch = "aarch64", target_arch = "arm64ec"),
40830 link_name = "llvm.aarch64.neon.sqshrn.v8i8"
40831 )]
40832 fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
40833 }
40834 unsafe { _vqshrn_n_s16(a, N) }
40835}
40836#[doc = "Signed saturating shift right narrow"]
40837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
40838#[inline]
40839#[target_feature(enable = "neon")]
40840#[cfg(not(target_arch = "arm"))]
40841#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
40842#[rustc_legacy_const_generics(1)]
40843#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40844pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
40845 static_assert!(N >= 1 && N <= 16);
40846 unsafe extern "unadjusted" {
40847 #[cfg_attr(
40848 any(target_arch = "aarch64", target_arch = "arm64ec"),
40849 link_name = "llvm.aarch64.neon.sqshrn.v4i16"
40850 )]
40851 fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
40852 }
40853 unsafe { _vqshrn_n_s32(a, N) }
40854}
40855#[doc = "Signed saturating shift right narrow"]
40856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
40857#[inline]
40858#[target_feature(enable = "neon")]
40859#[cfg(not(target_arch = "arm"))]
40860#[cfg_attr(test, assert_instr(sqshrn, N = 2))]
40861#[rustc_legacy_const_generics(1)]
40862#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40863pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
40864 static_assert!(N >= 1 && N <= 32);
40865 unsafe extern "unadjusted" {
40866 #[cfg_attr(
40867 any(target_arch = "aarch64", target_arch = "arm64ec"),
40868 link_name = "llvm.aarch64.neon.sqshrn.v2i32"
40869 )]
40870 fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
40871 }
40872 unsafe { _vqshrn_n_s64(a, N) }
40873}
40874#[doc = "Unsigned saturating shift right narrow"]
40875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
40876#[inline]
40877#[cfg(target_arch = "arm")]
40878#[target_feature(enable = "neon,v7")]
40879#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40880#[rustc_legacy_const_generics(1)]
40881#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40882pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
40883 static_assert!(N >= 1 && N <= 8);
40884 unsafe extern "unadjusted" {
40885 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")]
40886 fn _vqshrn_n_u16(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t;
40887 }
40888 unsafe {
40889 _vqshrn_n_u16(
40890 a,
40891 const {
40892 uint16x8_t([
40893 -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16,
40894 -N as u16,
40895 ])
40896 },
40897 )
40898 }
40899}
40900#[doc = "Unsigned saturating shift right narrow"]
40901#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
40902#[inline]
40903#[cfg(target_arch = "arm")]
40904#[target_feature(enable = "neon,v7")]
40905#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40906#[rustc_legacy_const_generics(1)]
40907#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40908pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
40909 static_assert!(N >= 1 && N <= 16);
40910 unsafe extern "unadjusted" {
40911 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")]
40912 fn _vqshrn_n_u32(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t;
40913 }
40914 unsafe {
40915 _vqshrn_n_u32(
40916 a,
40917 const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) },
40918 )
40919 }
40920}
40921#[doc = "Unsigned saturating shift right narrow"]
40922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
40923#[inline]
40924#[cfg(target_arch = "arm")]
40925#[target_feature(enable = "neon,v7")]
40926#[cfg_attr(test, assert_instr(vqshrn, N = 2))]
40927#[rustc_legacy_const_generics(1)]
40928#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
40929pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
40930 static_assert!(N >= 1 && N <= 32);
40931 unsafe extern "unadjusted" {
40932 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")]
40933 fn _vqshrn_n_u64(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t;
40934 }
40935 unsafe { _vqshrn_n_u64(a, const { uint64x2_t([-N as u64, -N as u64]) }) }
40936}
40937#[doc = "Unsigned saturating shift right narrow"]
40938#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
40939#[inline]
40940#[target_feature(enable = "neon")]
40941#[cfg(not(target_arch = "arm"))]
40942#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
40943#[rustc_legacy_const_generics(1)]
40944#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40945pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
40946 static_assert!(N >= 1 && N <= 8);
40947 unsafe extern "unadjusted" {
40948 #[cfg_attr(
40949 any(target_arch = "aarch64", target_arch = "arm64ec"),
40950 link_name = "llvm.aarch64.neon.uqshrn.v8i8"
40951 )]
40952 fn _vqshrn_n_u16(a: uint16x8_t, n: i32) -> uint8x8_t;
40953 }
40954 unsafe { _vqshrn_n_u16(a, N) }
40955}
40956#[doc = "Unsigned saturating shift right narrow"]
40957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
40958#[inline]
40959#[target_feature(enable = "neon")]
40960#[cfg(not(target_arch = "arm"))]
40961#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
40962#[rustc_legacy_const_generics(1)]
40963#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40964pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
40965 static_assert!(N >= 1 && N <= 16);
40966 unsafe extern "unadjusted" {
40967 #[cfg_attr(
40968 any(target_arch = "aarch64", target_arch = "arm64ec"),
40969 link_name = "llvm.aarch64.neon.uqshrn.v4i16"
40970 )]
40971 fn _vqshrn_n_u32(a: uint32x4_t, n: i32) -> uint16x4_t;
40972 }
40973 unsafe { _vqshrn_n_u32(a, N) }
40974}
40975#[doc = "Unsigned saturating shift right narrow"]
40976#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
40977#[inline]
40978#[target_feature(enable = "neon")]
40979#[cfg(not(target_arch = "arm"))]
40980#[cfg_attr(test, assert_instr(uqshrn, N = 2))]
40981#[rustc_legacy_const_generics(1)]
40982#[stable(feature = "neon_intrinsics", since = "1.59.0")]
40983pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
40984 static_assert!(N >= 1 && N <= 32);
40985 unsafe extern "unadjusted" {
40986 #[cfg_attr(
40987 any(target_arch = "aarch64", target_arch = "arm64ec"),
40988 link_name = "llvm.aarch64.neon.uqshrn.v2i32"
40989 )]
40990 fn _vqshrn_n_u64(a: uint64x2_t, n: i32) -> uint32x2_t;
40991 }
40992 unsafe { _vqshrn_n_u64(a, N) }
40993}
40994#[doc = "Signed saturating shift right unsigned narrow"]
40995#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
40996#[inline]
40997#[cfg(target_arch = "arm")]
40998#[target_feature(enable = "neon,v7")]
40999#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41000#[rustc_legacy_const_generics(1)]
41001#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41002pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41003 static_assert!(N >= 1 && N <= 8);
41004 unsafe extern "unadjusted" {
41005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
41006 fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
41007 }
41008 unsafe { _vqshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
41009}
41010#[doc = "Signed saturating shift right unsigned narrow"]
41011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41012#[inline]
41013#[cfg(target_arch = "arm")]
41014#[target_feature(enable = "neon,v7")]
41015#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41016#[rustc_legacy_const_generics(1)]
41017#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41018pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41019 static_assert!(N >= 1 && N <= 16);
41020 unsafe extern "unadjusted" {
41021 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
41022 fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
41023 }
41024 unsafe { _vqshrun_n_s32(a, const { int32x4_t([-N; 4]) }) }
41025}
41026#[doc = "Signed saturating shift right unsigned narrow"]
41027#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41028#[inline]
41029#[cfg(target_arch = "arm")]
41030#[target_feature(enable = "neon,v7")]
41031#[cfg_attr(test, assert_instr(vqshrun, N = 2))]
41032#[rustc_legacy_const_generics(1)]
41033#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
41034pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41035 static_assert!(N >= 1 && N <= 32);
41036 unsafe extern "unadjusted" {
41037 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
41038 fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
41039 }
41040 unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
41041}
41042#[doc = "Signed saturating shift right unsigned narrow"]
41043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
41044#[inline]
41045#[target_feature(enable = "neon")]
41046#[cfg(not(target_arch = "arm"))]
41047#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41048#[rustc_legacy_const_generics(1)]
41049#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41050pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
41051 static_assert!(N >= 1 && N <= 8);
41052 unsafe extern "unadjusted" {
41053 #[cfg_attr(
41054 any(target_arch = "aarch64", target_arch = "arm64ec"),
41055 link_name = "llvm.aarch64.neon.sqshrun.v8i8"
41056 )]
41057 fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> uint8x8_t;
41058 }
41059 unsafe { _vqshrun_n_s16(a, N) }
41060}
41061#[doc = "Signed saturating shift right unsigned narrow"]
41062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
41063#[inline]
41064#[target_feature(enable = "neon")]
41065#[cfg(not(target_arch = "arm"))]
41066#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41067#[rustc_legacy_const_generics(1)]
41068#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41069pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
41070 static_assert!(N >= 1 && N <= 16);
41071 unsafe extern "unadjusted" {
41072 #[cfg_attr(
41073 any(target_arch = "aarch64", target_arch = "arm64ec"),
41074 link_name = "llvm.aarch64.neon.sqshrun.v4i16"
41075 )]
41076 fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> uint16x4_t;
41077 }
41078 unsafe { _vqshrun_n_s32(a, N) }
41079}
41080#[doc = "Signed saturating shift right unsigned narrow"]
41081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
41082#[inline]
41083#[target_feature(enable = "neon")]
41084#[cfg(not(target_arch = "arm"))]
41085#[cfg_attr(test, assert_instr(sqshrun, N = 2))]
41086#[rustc_legacy_const_generics(1)]
41087#[stable(feature = "neon_intrinsics", since = "1.59.0")]
41088pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
41089 static_assert!(N >= 1 && N <= 32);
41090 unsafe extern "unadjusted" {
41091 #[cfg_attr(
41092 any(target_arch = "aarch64", target_arch = "arm64ec"),
41093 link_name = "llvm.aarch64.neon.sqshrun.v2i32"
41094 )]
41095 fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> uint32x2_t;
41096 }
41097 unsafe { _vqshrun_n_s64(a, N) }
41098}
41099#[doc = "Saturating subtract"]
41100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
41101#[inline]
41102#[target_feature(enable = "neon")]
41103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41104#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41105#[cfg_attr(
41106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41107 assert_instr(sqsub)
41108)]
41109#[cfg_attr(
41110 not(target_arch = "arm"),
41111 stable(feature = "neon_intrinsics", since = "1.59.0")
41112)]
41113#[cfg_attr(
41114 target_arch = "arm",
41115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41116)]
41117pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
41118 unsafe extern "unadjusted" {
41119 #[cfg_attr(
41120 any(target_arch = "aarch64", target_arch = "arm64ec"),
41121 link_name = "llvm.aarch64.neon.sqsub.v8i8"
41122 )]
41123 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")]
41124 fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
41125 }
41126 unsafe { _vqsub_s8(a, b) }
41127}
41128#[doc = "Saturating subtract"]
41129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
41130#[inline]
41131#[target_feature(enable = "neon")]
41132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41133#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
41134#[cfg_attr(
41135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41136 assert_instr(sqsub)
41137)]
41138#[cfg_attr(
41139 not(target_arch = "arm"),
41140 stable(feature = "neon_intrinsics", since = "1.59.0")
41141)]
41142#[cfg_attr(
41143 target_arch = "arm",
41144 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41145)]
41146pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
41147 unsafe extern "unadjusted" {
41148 #[cfg_attr(
41149 any(target_arch = "aarch64", target_arch = "arm64ec"),
41150 link_name = "llvm.aarch64.neon.sqsub.v16i8"
41151 )]
41152 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")]
41153 fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
41154 }
41155 unsafe { _vqsubq_s8(a, b) }
41156}
41157#[doc = "Saturating subtract"]
41158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
41159#[inline]
41160#[target_feature(enable = "neon")]
41161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41162#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41163#[cfg_attr(
41164 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41165 assert_instr(sqsub)
41166)]
41167#[cfg_attr(
41168 not(target_arch = "arm"),
41169 stable(feature = "neon_intrinsics", since = "1.59.0")
41170)]
41171#[cfg_attr(
41172 target_arch = "arm",
41173 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41174)]
41175pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
41176 unsafe extern "unadjusted" {
41177 #[cfg_attr(
41178 any(target_arch = "aarch64", target_arch = "arm64ec"),
41179 link_name = "llvm.aarch64.neon.sqsub.v4i16"
41180 )]
41181 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")]
41182 fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
41183 }
41184 unsafe { _vqsub_s16(a, b) }
41185}
41186#[doc = "Saturating subtract"]
41187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
41188#[inline]
41189#[target_feature(enable = "neon")]
41190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41191#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
41192#[cfg_attr(
41193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41194 assert_instr(sqsub)
41195)]
41196#[cfg_attr(
41197 not(target_arch = "arm"),
41198 stable(feature = "neon_intrinsics", since = "1.59.0")
41199)]
41200#[cfg_attr(
41201 target_arch = "arm",
41202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41203)]
41204pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
41205 unsafe extern "unadjusted" {
41206 #[cfg_attr(
41207 any(target_arch = "aarch64", target_arch = "arm64ec"),
41208 link_name = "llvm.aarch64.neon.sqsub.v8i16"
41209 )]
41210 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")]
41211 fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
41212 }
41213 unsafe { _vqsubq_s16(a, b) }
41214}
41215#[doc = "Saturating subtract"]
41216#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
41217#[inline]
41218#[target_feature(enable = "neon")]
41219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41220#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41221#[cfg_attr(
41222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41223 assert_instr(sqsub)
41224)]
41225#[cfg_attr(
41226 not(target_arch = "arm"),
41227 stable(feature = "neon_intrinsics", since = "1.59.0")
41228)]
41229#[cfg_attr(
41230 target_arch = "arm",
41231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41232)]
41233pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
41234 unsafe extern "unadjusted" {
41235 #[cfg_attr(
41236 any(target_arch = "aarch64", target_arch = "arm64ec"),
41237 link_name = "llvm.aarch64.neon.sqsub.v2i32"
41238 )]
41239 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")]
41240 fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
41241 }
41242 unsafe { _vqsub_s32(a, b) }
41243}
41244#[doc = "Saturating subtract"]
41245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
41246#[inline]
41247#[target_feature(enable = "neon")]
41248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41249#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
41250#[cfg_attr(
41251 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41252 assert_instr(sqsub)
41253)]
41254#[cfg_attr(
41255 not(target_arch = "arm"),
41256 stable(feature = "neon_intrinsics", since = "1.59.0")
41257)]
41258#[cfg_attr(
41259 target_arch = "arm",
41260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41261)]
41262pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
41263 unsafe extern "unadjusted" {
41264 #[cfg_attr(
41265 any(target_arch = "aarch64", target_arch = "arm64ec"),
41266 link_name = "llvm.aarch64.neon.sqsub.v4i32"
41267 )]
41268 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")]
41269 fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
41270 }
41271 unsafe { _vqsubq_s32(a, b) }
41272}
41273#[doc = "Saturating subtract"]
41274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
41275#[inline]
41276#[target_feature(enable = "neon")]
41277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41278#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41279#[cfg_attr(
41280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41281 assert_instr(sqsub)
41282)]
41283#[cfg_attr(
41284 not(target_arch = "arm"),
41285 stable(feature = "neon_intrinsics", since = "1.59.0")
41286)]
41287#[cfg_attr(
41288 target_arch = "arm",
41289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41290)]
41291pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
41292 unsafe extern "unadjusted" {
41293 #[cfg_attr(
41294 any(target_arch = "aarch64", target_arch = "arm64ec"),
41295 link_name = "llvm.aarch64.neon.sqsub.v1i64"
41296 )]
41297 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")]
41298 fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
41299 }
41300 unsafe { _vqsub_s64(a, b) }
41301}
41302#[doc = "Saturating subtract"]
41303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
41304#[inline]
41305#[target_feature(enable = "neon")]
41306#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41307#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
41308#[cfg_attr(
41309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41310 assert_instr(sqsub)
41311)]
41312#[cfg_attr(
41313 not(target_arch = "arm"),
41314 stable(feature = "neon_intrinsics", since = "1.59.0")
41315)]
41316#[cfg_attr(
41317 target_arch = "arm",
41318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41319)]
41320pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
41321 unsafe extern "unadjusted" {
41322 #[cfg_attr(
41323 any(target_arch = "aarch64", target_arch = "arm64ec"),
41324 link_name = "llvm.aarch64.neon.sqsub.v2i64"
41325 )]
41326 #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")]
41327 fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
41328 }
41329 unsafe { _vqsubq_s64(a, b) }
41330}
41331#[doc = "Saturating subtract"]
41332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
41333#[inline]
41334#[target_feature(enable = "neon")]
41335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41336#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41337#[cfg_attr(
41338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41339 assert_instr(uqsub)
41340)]
41341#[cfg_attr(
41342 not(target_arch = "arm"),
41343 stable(feature = "neon_intrinsics", since = "1.59.0")
41344)]
41345#[cfg_attr(
41346 target_arch = "arm",
41347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41348)]
41349pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
41350 unsafe extern "unadjusted" {
41351 #[cfg_attr(
41352 any(target_arch = "aarch64", target_arch = "arm64ec"),
41353 link_name = "llvm.aarch64.neon.uqsub.v8i8"
41354 )]
41355 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")]
41356 fn _vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
41357 }
41358 unsafe { _vqsub_u8(a, b) }
41359}
41360#[doc = "Saturating subtract"]
41361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
41362#[inline]
41363#[target_feature(enable = "neon")]
41364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41365#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
41366#[cfg_attr(
41367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41368 assert_instr(uqsub)
41369)]
41370#[cfg_attr(
41371 not(target_arch = "arm"),
41372 stable(feature = "neon_intrinsics", since = "1.59.0")
41373)]
41374#[cfg_attr(
41375 target_arch = "arm",
41376 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41377)]
41378pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
41379 unsafe extern "unadjusted" {
41380 #[cfg_attr(
41381 any(target_arch = "aarch64", target_arch = "arm64ec"),
41382 link_name = "llvm.aarch64.neon.uqsub.v16i8"
41383 )]
41384 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")]
41385 fn _vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
41386 }
41387 unsafe { _vqsubq_u8(a, b) }
41388}
41389#[doc = "Saturating subtract"]
41390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
41391#[inline]
41392#[target_feature(enable = "neon")]
41393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41394#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41395#[cfg_attr(
41396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41397 assert_instr(uqsub)
41398)]
41399#[cfg_attr(
41400 not(target_arch = "arm"),
41401 stable(feature = "neon_intrinsics", since = "1.59.0")
41402)]
41403#[cfg_attr(
41404 target_arch = "arm",
41405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41406)]
41407pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
41408 unsafe extern "unadjusted" {
41409 #[cfg_attr(
41410 any(target_arch = "aarch64", target_arch = "arm64ec"),
41411 link_name = "llvm.aarch64.neon.uqsub.v4i16"
41412 )]
41413 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")]
41414 fn _vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
41415 }
41416 unsafe { _vqsub_u16(a, b) }
41417}
41418#[doc = "Saturating subtract"]
41419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
41420#[inline]
41421#[target_feature(enable = "neon")]
41422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41423#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
41424#[cfg_attr(
41425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41426 assert_instr(uqsub)
41427)]
41428#[cfg_attr(
41429 not(target_arch = "arm"),
41430 stable(feature = "neon_intrinsics", since = "1.59.0")
41431)]
41432#[cfg_attr(
41433 target_arch = "arm",
41434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41435)]
41436pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
41437 unsafe extern "unadjusted" {
41438 #[cfg_attr(
41439 any(target_arch = "aarch64", target_arch = "arm64ec"),
41440 link_name = "llvm.aarch64.neon.uqsub.v8i16"
41441 )]
41442 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")]
41443 fn _vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
41444 }
41445 unsafe { _vqsubq_u16(a, b) }
41446}
41447#[doc = "Saturating subtract"]
41448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
41449#[inline]
41450#[target_feature(enable = "neon")]
41451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41452#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41453#[cfg_attr(
41454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41455 assert_instr(uqsub)
41456)]
41457#[cfg_attr(
41458 not(target_arch = "arm"),
41459 stable(feature = "neon_intrinsics", since = "1.59.0")
41460)]
41461#[cfg_attr(
41462 target_arch = "arm",
41463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41464)]
41465pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
41466 unsafe extern "unadjusted" {
41467 #[cfg_attr(
41468 any(target_arch = "aarch64", target_arch = "arm64ec"),
41469 link_name = "llvm.aarch64.neon.uqsub.v2i32"
41470 )]
41471 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")]
41472 fn _vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
41473 }
41474 unsafe { _vqsub_u32(a, b) }
41475}
41476#[doc = "Saturating subtract"]
41477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
41478#[inline]
41479#[target_feature(enable = "neon")]
41480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41481#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
41482#[cfg_attr(
41483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41484 assert_instr(uqsub)
41485)]
41486#[cfg_attr(
41487 not(target_arch = "arm"),
41488 stable(feature = "neon_intrinsics", since = "1.59.0")
41489)]
41490#[cfg_attr(
41491 target_arch = "arm",
41492 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41493)]
41494pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
41495 unsafe extern "unadjusted" {
41496 #[cfg_attr(
41497 any(target_arch = "aarch64", target_arch = "arm64ec"),
41498 link_name = "llvm.aarch64.neon.uqsub.v4i32"
41499 )]
41500 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")]
41501 fn _vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
41502 }
41503 unsafe { _vqsubq_u32(a, b) }
41504}
41505#[doc = "Saturating subtract"]
41506#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
41507#[inline]
41508#[target_feature(enable = "neon")]
41509#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41510#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41511#[cfg_attr(
41512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41513 assert_instr(uqsub)
41514)]
41515#[cfg_attr(
41516 not(target_arch = "arm"),
41517 stable(feature = "neon_intrinsics", since = "1.59.0")
41518)]
41519#[cfg_attr(
41520 target_arch = "arm",
41521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41522)]
41523pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
41524 unsafe extern "unadjusted" {
41525 #[cfg_attr(
41526 any(target_arch = "aarch64", target_arch = "arm64ec"),
41527 link_name = "llvm.aarch64.neon.uqsub.v1i64"
41528 )]
41529 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")]
41530 fn _vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t;
41531 }
41532 unsafe { _vqsub_u64(a, b) }
41533}
41534#[doc = "Saturating subtract"]
41535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
41536#[inline]
41537#[target_feature(enable = "neon")]
41538#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41539#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
41540#[cfg_attr(
41541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41542 assert_instr(uqsub)
41543)]
41544#[cfg_attr(
41545 not(target_arch = "arm"),
41546 stable(feature = "neon_intrinsics", since = "1.59.0")
41547)]
41548#[cfg_attr(
41549 target_arch = "arm",
41550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41551)]
41552pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
41553 unsafe extern "unadjusted" {
41554 #[cfg_attr(
41555 any(target_arch = "aarch64", target_arch = "arm64ec"),
41556 link_name = "llvm.aarch64.neon.uqsub.v2i64"
41557 )]
41558 #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")]
41559 fn _vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t;
41560 }
41561 unsafe { _vqsubq_u64(a, b) }
41562}
41563#[doc = "Rounding Add returning High Narrow (high half)."]
41564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
41565#[inline]
41566#[target_feature(enable = "neon")]
41567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41569#[cfg_attr(
41570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41571 assert_instr(raddhn2)
41572)]
41573#[cfg_attr(
41574 not(target_arch = "arm"),
41575 stable(feature = "neon_intrinsics", since = "1.59.0")
41576)]
41577#[cfg_attr(
41578 target_arch = "arm",
41579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41580)]
41581pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
41582 let x = vraddhn_s16(b, c);
41583 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
41584}
41585#[doc = "Rounding Add returning High Narrow (high half)."]
41586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
41587#[inline]
41588#[target_feature(enable = "neon")]
41589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41590#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41591#[cfg_attr(
41592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41593 assert_instr(raddhn2)
41594)]
41595#[cfg_attr(
41596 not(target_arch = "arm"),
41597 stable(feature = "neon_intrinsics", since = "1.59.0")
41598)]
41599#[cfg_attr(
41600 target_arch = "arm",
41601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41602)]
41603pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
41604 let x = vraddhn_s32(b, c);
41605 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) }
41606}
41607#[doc = "Rounding Add returning High Narrow (high half)."]
41608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
41609#[inline]
41610#[target_feature(enable = "neon")]
41611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41612#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41613#[cfg_attr(
41614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41615 assert_instr(raddhn2)
41616)]
41617#[cfg_attr(
41618 not(target_arch = "arm"),
41619 stable(feature = "neon_intrinsics", since = "1.59.0")
41620)]
41621#[cfg_attr(
41622 target_arch = "arm",
41623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41624)]
41625pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
41626 let x = vraddhn_s64(b, c);
41627 unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
41628}
41629#[doc = "Rounding Add returning High Narrow (high half)."]
41630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
41631#[inline]
41632#[target_feature(enable = "neon")]
41633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41634#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41635#[cfg_attr(
41636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41637 assert_instr(raddhn2)
41638)]
41639#[cfg_attr(
41640 not(target_arch = "arm"),
41641 stable(feature = "neon_intrinsics", since = "1.59.0")
41642)]
41643#[cfg_attr(
41644 target_arch = "arm",
41645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41646)]
41647pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
41648 unsafe {
41649 let x: uint8x8_t = transmute(vraddhn_s16(transmute(b), transmute(c)));
41650 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
41651 }
41652}
41653#[doc = "Rounding Add returning High Narrow (high half)."]
41654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
41655#[inline]
41656#[target_feature(enable = "neon")]
41657#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41658#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41659#[cfg_attr(
41660 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41661 assert_instr(raddhn2)
41662)]
41663#[cfg_attr(
41664 not(target_arch = "arm"),
41665 stable(feature = "neon_intrinsics", since = "1.59.0")
41666)]
41667#[cfg_attr(
41668 target_arch = "arm",
41669 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41670)]
41671pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
41672 unsafe {
41673 let x: uint16x4_t = transmute(vraddhn_s32(transmute(b), transmute(c)));
41674 simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7])
41675 }
41676}
41677#[doc = "Rounding Add returning High Narrow (high half)."]
41678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
41679#[inline]
41680#[target_feature(enable = "neon")]
41681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41682#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41683#[cfg_attr(
41684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41685 assert_instr(raddhn2)
41686)]
41687#[cfg_attr(
41688 not(target_arch = "arm"),
41689 stable(feature = "neon_intrinsics", since = "1.59.0")
41690)]
41691#[cfg_attr(
41692 target_arch = "arm",
41693 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41694)]
41695pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
41696 unsafe {
41697 let x: uint32x2_t = transmute(vraddhn_s64(transmute(b), transmute(c)));
41698 simd_shuffle!(a, x, [0, 1, 2, 3])
41699 }
41700}
41701#[doc = "Rounding Add returning High Narrow."]
41702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
41703#[inline]
41704#[target_feature(enable = "neon")]
41705#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41706#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41707#[cfg_attr(
41708 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41709 assert_instr(raddhn)
41710)]
41711#[cfg_attr(
41712 not(target_arch = "arm"),
41713 stable(feature = "neon_intrinsics", since = "1.59.0")
41714)]
41715#[cfg_attr(
41716 target_arch = "arm",
41717 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41718)]
41719pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
41720 unsafe extern "unadjusted" {
41721 #[cfg_attr(
41722 any(target_arch = "aarch64", target_arch = "arm64ec"),
41723 link_name = "llvm.aarch64.neon.raddhn.v8i8"
41724 )]
41725 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v8i8")]
41726 fn _vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
41727 }
41728 unsafe { _vraddhn_s16(a, b) }
41729}
41730#[doc = "Rounding Add returning High Narrow."]
41731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
41732#[inline]
41733#[target_feature(enable = "neon")]
41734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41735#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41736#[cfg_attr(
41737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41738 assert_instr(raddhn)
41739)]
41740#[cfg_attr(
41741 not(target_arch = "arm"),
41742 stable(feature = "neon_intrinsics", since = "1.59.0")
41743)]
41744#[cfg_attr(
41745 target_arch = "arm",
41746 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41747)]
41748pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
41749 unsafe extern "unadjusted" {
41750 #[cfg_attr(
41751 any(target_arch = "aarch64", target_arch = "arm64ec"),
41752 link_name = "llvm.aarch64.neon.raddhn.v4i16"
41753 )]
41754 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v4i16")]
41755 fn _vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
41756 }
41757 unsafe { _vraddhn_s32(a, b) }
41758}
41759#[doc = "Rounding Add returning High Narrow."]
41760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
41761#[inline]
41762#[target_feature(enable = "neon")]
41763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41764#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41765#[cfg_attr(
41766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41767 assert_instr(raddhn)
41768)]
41769#[cfg_attr(
41770 not(target_arch = "arm"),
41771 stable(feature = "neon_intrinsics", since = "1.59.0")
41772)]
41773#[cfg_attr(
41774 target_arch = "arm",
41775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41776)]
41777pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
41778 unsafe extern "unadjusted" {
41779 #[cfg_attr(
41780 any(target_arch = "aarch64", target_arch = "arm64ec"),
41781 link_name = "llvm.aarch64.neon.raddhn.v2i32"
41782 )]
41783 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vraddhn.v2i32")]
41784 fn _vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
41785 }
41786 unsafe { _vraddhn_s64(a, b) }
41787}
41788#[doc = "Rounding Add returning High Narrow."]
41789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
41790#[inline]
41791#[cfg(target_endian = "little")]
41792#[target_feature(enable = "neon")]
41793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41794#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41795#[cfg_attr(
41796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41797 assert_instr(raddhn)
41798)]
41799#[cfg_attr(
41800 not(target_arch = "arm"),
41801 stable(feature = "neon_intrinsics", since = "1.59.0")
41802)]
41803#[cfg_attr(
41804 target_arch = "arm",
41805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41806)]
41807pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
41808 unsafe { transmute(vraddhn_s16(transmute(a), transmute(b))) }
41809}
41810#[doc = "Rounding Add returning High Narrow."]
41811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
41812#[inline]
41813#[cfg(target_endian = "big")]
41814#[target_feature(enable = "neon")]
41815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
41817#[cfg_attr(
41818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41819 assert_instr(raddhn)
41820)]
41821#[cfg_attr(
41822 not(target_arch = "arm"),
41823 stable(feature = "neon_intrinsics", since = "1.59.0")
41824)]
41825#[cfg_attr(
41826 target_arch = "arm",
41827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41828)]
41829pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
41830 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
41831 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
41832 unsafe {
41833 let ret_val: uint8x8_t = transmute(vraddhn_s16(transmute(a), transmute(b)));
41834 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
41835 }
41836}
41837#[doc = "Rounding Add returning High Narrow."]
41838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
41839#[inline]
41840#[cfg(target_endian = "little")]
41841#[target_feature(enable = "neon")]
41842#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41843#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41844#[cfg_attr(
41845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41846 assert_instr(raddhn)
41847)]
41848#[cfg_attr(
41849 not(target_arch = "arm"),
41850 stable(feature = "neon_intrinsics", since = "1.59.0")
41851)]
41852#[cfg_attr(
41853 target_arch = "arm",
41854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41855)]
41856pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
41857 unsafe { transmute(vraddhn_s32(transmute(a), transmute(b))) }
41858}
41859#[doc = "Rounding Add returning High Narrow."]
41860#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
41861#[inline]
41862#[cfg(target_endian = "big")]
41863#[target_feature(enable = "neon")]
41864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41865#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
41866#[cfg_attr(
41867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41868 assert_instr(raddhn)
41869)]
41870#[cfg_attr(
41871 not(target_arch = "arm"),
41872 stable(feature = "neon_intrinsics", since = "1.59.0")
41873)]
41874#[cfg_attr(
41875 target_arch = "arm",
41876 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41877)]
41878pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
41879 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
41880 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
41881 unsafe {
41882 let ret_val: uint16x4_t = transmute(vraddhn_s32(transmute(a), transmute(b)));
41883 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
41884 }
41885}
41886#[doc = "Rounding Add returning High Narrow."]
41887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
41888#[inline]
41889#[cfg(target_endian = "little")]
41890#[target_feature(enable = "neon")]
41891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41892#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41893#[cfg_attr(
41894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41895 assert_instr(raddhn)
41896)]
41897#[cfg_attr(
41898 not(target_arch = "arm"),
41899 stable(feature = "neon_intrinsics", since = "1.59.0")
41900)]
41901#[cfg_attr(
41902 target_arch = "arm",
41903 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41904)]
41905pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
41906 unsafe { transmute(vraddhn_s64(transmute(a), transmute(b))) }
41907}
41908#[doc = "Rounding Add returning High Narrow."]
41909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
41910#[inline]
41911#[cfg(target_endian = "big")]
41912#[target_feature(enable = "neon")]
41913#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41914#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
41915#[cfg_attr(
41916 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41917 assert_instr(raddhn)
41918)]
41919#[cfg_attr(
41920 not(target_arch = "arm"),
41921 stable(feature = "neon_intrinsics", since = "1.59.0")
41922)]
41923#[cfg_attr(
41924 target_arch = "arm",
41925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41926)]
41927pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
41928 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
41929 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
41930 unsafe {
41931 let ret_val: uint32x2_t = transmute(vraddhn_s64(transmute(a), transmute(b)));
41932 simd_shuffle!(ret_val, ret_val, [1, 0])
41933 }
41934}
41935#[doc = "Reciprocal estimate."]
41936#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
41937#[inline]
41938#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
41939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
41940#[cfg_attr(
41941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41942 assert_instr(frecpe)
41943)]
41944#[target_feature(enable = "neon,fp16")]
41945#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
41946pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
41947 unsafe extern "unadjusted" {
41948 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f16")]
41949 #[cfg_attr(
41950 any(target_arch = "aarch64", target_arch = "arm64ec"),
41951 link_name = "llvm.aarch64.neon.frecpe.v4f16"
41952 )]
41953 fn _vrecpe_f16(a: float16x4_t) -> float16x4_t;
41954 }
41955 unsafe { _vrecpe_f16(a) }
41956}
41957#[doc = "Reciprocal estimate."]
41958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
41959#[inline]
41960#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
41961#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
41962#[cfg_attr(
41963 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41964 assert_instr(frecpe)
41965)]
41966#[target_feature(enable = "neon,fp16")]
41967#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
41968pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
41969 unsafe extern "unadjusted" {
41970 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v8f16")]
41971 #[cfg_attr(
41972 any(target_arch = "aarch64", target_arch = "arm64ec"),
41973 link_name = "llvm.aarch64.neon.frecpe.v8f16"
41974 )]
41975 fn _vrecpeq_f16(a: float16x8_t) -> float16x8_t;
41976 }
41977 unsafe { _vrecpeq_f16(a) }
41978}
41979#[doc = "Reciprocal estimate."]
41980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
41981#[inline]
41982#[target_feature(enable = "neon")]
41983#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
41984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
41985#[cfg_attr(
41986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
41987 assert_instr(frecpe)
41988)]
41989#[cfg_attr(
41990 not(target_arch = "arm"),
41991 stable(feature = "neon_intrinsics", since = "1.59.0")
41992)]
41993#[cfg_attr(
41994 target_arch = "arm",
41995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
41996)]
41997pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
41998 unsafe extern "unadjusted" {
41999 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")]
42000 #[cfg_attr(
42001 any(target_arch = "aarch64", target_arch = "arm64ec"),
42002 link_name = "llvm.aarch64.neon.frecpe.v2f32"
42003 )]
42004 fn _vrecpe_f32(a: float32x2_t) -> float32x2_t;
42005 }
42006 unsafe { _vrecpe_f32(a) }
42007}
42008#[doc = "Reciprocal estimate."]
42009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
42010#[inline]
42011#[target_feature(enable = "neon")]
42012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42014#[cfg_attr(
42015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42016 assert_instr(frecpe)
42017)]
42018#[cfg_attr(
42019 not(target_arch = "arm"),
42020 stable(feature = "neon_intrinsics", since = "1.59.0")
42021)]
42022#[cfg_attr(
42023 target_arch = "arm",
42024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42025)]
42026pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
42027 unsafe extern "unadjusted" {
42028 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")]
42029 #[cfg_attr(
42030 any(target_arch = "aarch64", target_arch = "arm64ec"),
42031 link_name = "llvm.aarch64.neon.frecpe.v4f32"
42032 )]
42033 fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t;
42034 }
42035 unsafe { _vrecpeq_f32(a) }
42036}
42037#[doc = "Unsigned reciprocal estimate"]
42038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
42039#[inline]
42040#[target_feature(enable = "neon")]
42041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42043#[cfg_attr(
42044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42045 assert_instr(urecpe)
42046)]
42047#[cfg_attr(
42048 not(target_arch = "arm"),
42049 stable(feature = "neon_intrinsics", since = "1.59.0")
42050)]
42051#[cfg_attr(
42052 target_arch = "arm",
42053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42054)]
42055pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
42056 unsafe extern "unadjusted" {
42057 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")]
42058 #[cfg_attr(
42059 any(target_arch = "aarch64", target_arch = "arm64ec"),
42060 link_name = "llvm.aarch64.neon.urecpe.v2i32"
42061 )]
42062 fn _vrecpe_u32(a: uint32x2_t) -> uint32x2_t;
42063 }
42064 unsafe { _vrecpe_u32(a) }
42065}
42066#[doc = "Unsigned reciprocal estimate"]
42067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
42068#[inline]
42069#[target_feature(enable = "neon")]
42070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
42072#[cfg_attr(
42073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42074 assert_instr(urecpe)
42075)]
42076#[cfg_attr(
42077 not(target_arch = "arm"),
42078 stable(feature = "neon_intrinsics", since = "1.59.0")
42079)]
42080#[cfg_attr(
42081 target_arch = "arm",
42082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42083)]
42084pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
42085 unsafe extern "unadjusted" {
42086 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")]
42087 #[cfg_attr(
42088 any(target_arch = "aarch64", target_arch = "arm64ec"),
42089 link_name = "llvm.aarch64.neon.urecpe.v4i32"
42090 )]
42091 fn _vrecpeq_u32(a: uint32x4_t) -> uint32x4_t;
42092 }
42093 unsafe { _vrecpeq_u32(a) }
42094}
42095#[doc = "Floating-point reciprocal step"]
42096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
42097#[inline]
42098#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42100#[cfg_attr(
42101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42102 assert_instr(frecps)
42103)]
42104#[target_feature(enable = "neon,fp16")]
42105#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42106pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
42107 unsafe extern "unadjusted" {
42108 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f16")]
42109 #[cfg_attr(
42110 any(target_arch = "aarch64", target_arch = "arm64ec"),
42111 link_name = "llvm.aarch64.neon.frecps.v4f16"
42112 )]
42113 fn _vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
42114 }
42115 unsafe { _vrecps_f16(a, b) }
42116}
42117#[doc = "Floating-point reciprocal step"]
42118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
42119#[inline]
42120#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
42121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42122#[cfg_attr(
42123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42124 assert_instr(frecps)
42125)]
42126#[target_feature(enable = "neon,fp16")]
42127#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42128pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
42129 unsafe extern "unadjusted" {
42130 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v8f16")]
42131 #[cfg_attr(
42132 any(target_arch = "aarch64", target_arch = "arm64ec"),
42133 link_name = "llvm.aarch64.neon.frecps.v8f16"
42134 )]
42135 fn _vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
42136 }
42137 unsafe { _vrecpsq_f16(a, b) }
42138}
42139#[doc = "Floating-point reciprocal step"]
42140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
42141#[inline]
42142#[target_feature(enable = "neon")]
42143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42144#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42145#[cfg_attr(
42146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42147 assert_instr(frecps)
42148)]
42149#[cfg_attr(
42150 not(target_arch = "arm"),
42151 stable(feature = "neon_intrinsics", since = "1.59.0")
42152)]
42153#[cfg_attr(
42154 target_arch = "arm",
42155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42156)]
42157pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
42158 unsafe extern "unadjusted" {
42159 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")]
42160 #[cfg_attr(
42161 any(target_arch = "aarch64", target_arch = "arm64ec"),
42162 link_name = "llvm.aarch64.neon.frecps.v2f32"
42163 )]
42164 fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
42165 }
42166 unsafe { _vrecps_f32(a, b) }
42167}
42168#[doc = "Floating-point reciprocal step"]
42169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
42170#[inline]
42171#[target_feature(enable = "neon")]
42172#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
42174#[cfg_attr(
42175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42176 assert_instr(frecps)
42177)]
42178#[cfg_attr(
42179 not(target_arch = "arm"),
42180 stable(feature = "neon_intrinsics", since = "1.59.0")
42181)]
42182#[cfg_attr(
42183 target_arch = "arm",
42184 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
42185)]
42186pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
42187 unsafe extern "unadjusted" {
42188 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")]
42189 #[cfg_attr(
42190 any(target_arch = "aarch64", target_arch = "arm64ec"),
42191 link_name = "llvm.aarch64.neon.frecps.v4f32"
42192 )]
42193 fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
42194 }
42195 unsafe { _vrecpsq_f32(a, b) }
42196}
42197#[doc = "Vector reinterpret cast operation"]
42198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42199#[inline]
42200#[cfg(target_endian = "little")]
42201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42203#[cfg_attr(
42204 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42205 assert_instr(nop)
42206)]
42207#[target_feature(enable = "neon,fp16")]
42208#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42209pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42210 unsafe { transmute(a) }
42211}
42212#[doc = "Vector reinterpret cast operation"]
42213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
42214#[inline]
42215#[cfg(target_endian = "big")]
42216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42218#[cfg_attr(
42219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42220 assert_instr(nop)
42221)]
42222#[target_feature(enable = "neon,fp16")]
42223#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42224pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
42225 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42226 unsafe {
42227 let ret_val: float32x2_t = transmute(a);
42228 simd_shuffle!(ret_val, ret_val, [1, 0])
42229 }
42230}
42231#[doc = "Vector reinterpret cast operation"]
42232#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42233#[inline]
42234#[cfg(target_endian = "little")]
42235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42237#[cfg_attr(
42238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42239 assert_instr(nop)
42240)]
42241#[target_feature(enable = "neon,fp16")]
42242#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42243pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42244 unsafe { transmute(a) }
42245}
42246#[doc = "Vector reinterpret cast operation"]
42247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
42248#[inline]
42249#[cfg(target_endian = "big")]
42250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42252#[cfg_attr(
42253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42254 assert_instr(nop)
42255)]
42256#[target_feature(enable = "neon,fp16")]
42257#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42258pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
42259 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42260 unsafe {
42261 let ret_val: int8x8_t = transmute(a);
42262 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42263 }
42264}
42265#[doc = "Vector reinterpret cast operation"]
42266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42267#[inline]
42268#[cfg(target_endian = "little")]
42269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42271#[cfg_attr(
42272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42273 assert_instr(nop)
42274)]
42275#[target_feature(enable = "neon,fp16")]
42276#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42277pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42278 unsafe { transmute(a) }
42279}
42280#[doc = "Vector reinterpret cast operation"]
42281#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
42282#[inline]
42283#[cfg(target_endian = "big")]
42284#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42285#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42286#[cfg_attr(
42287 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42288 assert_instr(nop)
42289)]
42290#[target_feature(enable = "neon,fp16")]
42291#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42292pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
42293 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42294 unsafe {
42295 let ret_val: int16x4_t = transmute(a);
42296 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42297 }
42298}
42299#[doc = "Vector reinterpret cast operation"]
42300#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42301#[inline]
42302#[cfg(target_endian = "little")]
42303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42305#[cfg_attr(
42306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42307 assert_instr(nop)
42308)]
42309#[target_feature(enable = "neon,fp16")]
42310#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42311pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42312 unsafe { transmute(a) }
42313}
42314#[doc = "Vector reinterpret cast operation"]
42315#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
42316#[inline]
42317#[cfg(target_endian = "big")]
42318#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42319#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42320#[cfg_attr(
42321 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42322 assert_instr(nop)
42323)]
42324#[target_feature(enable = "neon,fp16")]
42325#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42326pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
42327 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42328 unsafe {
42329 let ret_val: int32x2_t = transmute(a);
42330 simd_shuffle!(ret_val, ret_val, [1, 0])
42331 }
42332}
42333#[doc = "Vector reinterpret cast operation"]
42334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42335#[inline]
42336#[cfg(target_endian = "little")]
42337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42339#[cfg_attr(
42340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42341 assert_instr(nop)
42342)]
42343#[target_feature(enable = "neon,fp16")]
42344#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42345pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42346 unsafe { transmute(a) }
42347}
42348#[doc = "Vector reinterpret cast operation"]
42349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
42350#[inline]
42351#[cfg(target_endian = "big")]
42352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42353#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42354#[cfg_attr(
42355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42356 assert_instr(nop)
42357)]
42358#[target_feature(enable = "neon,fp16")]
42359#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42360pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
42361 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42362 unsafe { transmute(a) }
42363}
42364#[doc = "Vector reinterpret cast operation"]
42365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42366#[inline]
42367#[cfg(target_endian = "little")]
42368#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42369#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42370#[cfg_attr(
42371 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42372 assert_instr(nop)
42373)]
42374#[target_feature(enable = "neon,fp16")]
42375#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42376pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42377 unsafe { transmute(a) }
42378}
42379#[doc = "Vector reinterpret cast operation"]
42380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
42381#[inline]
42382#[cfg(target_endian = "big")]
42383#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42384#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42385#[cfg_attr(
42386 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42387 assert_instr(nop)
42388)]
42389#[target_feature(enable = "neon,fp16")]
42390#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42391pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
42392 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42393 unsafe {
42394 let ret_val: uint8x8_t = transmute(a);
42395 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42396 }
42397}
42398#[doc = "Vector reinterpret cast operation"]
42399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42400#[inline]
42401#[cfg(target_endian = "little")]
42402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42404#[cfg_attr(
42405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42406 assert_instr(nop)
42407)]
42408#[target_feature(enable = "neon,fp16")]
42409#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42410pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42411 unsafe { transmute(a) }
42412}
42413#[doc = "Vector reinterpret cast operation"]
42414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
42415#[inline]
42416#[cfg(target_endian = "big")]
42417#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42418#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42419#[cfg_attr(
42420 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42421 assert_instr(nop)
42422)]
42423#[target_feature(enable = "neon,fp16")]
42424#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42425pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
42426 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42427 unsafe {
42428 let ret_val: uint16x4_t = transmute(a);
42429 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42430 }
42431}
42432#[doc = "Vector reinterpret cast operation"]
42433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42434#[inline]
42435#[cfg(target_endian = "little")]
42436#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42437#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42438#[cfg_attr(
42439 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42440 assert_instr(nop)
42441)]
42442#[target_feature(enable = "neon,fp16")]
42443#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42444pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42445 unsafe { transmute(a) }
42446}
42447#[doc = "Vector reinterpret cast operation"]
42448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
42449#[inline]
42450#[cfg(target_endian = "big")]
42451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42453#[cfg_attr(
42454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42455 assert_instr(nop)
42456)]
42457#[target_feature(enable = "neon,fp16")]
42458#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42459pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
42460 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42461 unsafe {
42462 let ret_val: uint32x2_t = transmute(a);
42463 simd_shuffle!(ret_val, ret_val, [1, 0])
42464 }
42465}
42466#[doc = "Vector reinterpret cast operation"]
42467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42468#[inline]
42469#[cfg(target_endian = "little")]
42470#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42471#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42472#[cfg_attr(
42473 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42474 assert_instr(nop)
42475)]
42476#[target_feature(enable = "neon,fp16")]
42477#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42478pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42479 unsafe { transmute(a) }
42480}
42481#[doc = "Vector reinterpret cast operation"]
42482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
42483#[inline]
42484#[cfg(target_endian = "big")]
42485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42487#[cfg_attr(
42488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42489 assert_instr(nop)
42490)]
42491#[target_feature(enable = "neon,fp16")]
42492#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42493pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
42494 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42495 unsafe { transmute(a) }
42496}
42497#[doc = "Vector reinterpret cast operation"]
42498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42499#[inline]
42500#[cfg(target_endian = "little")]
42501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42503#[cfg_attr(
42504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42505 assert_instr(nop)
42506)]
42507#[target_feature(enable = "neon,fp16")]
42508#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42509pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42510 unsafe { transmute(a) }
42511}
42512#[doc = "Vector reinterpret cast operation"]
42513#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
42514#[inline]
42515#[cfg(target_endian = "big")]
42516#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42518#[cfg_attr(
42519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42520 assert_instr(nop)
42521)]
42522#[target_feature(enable = "neon,fp16")]
42523#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42524pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
42525 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42526 unsafe {
42527 let ret_val: poly8x8_t = transmute(a);
42528 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42529 }
42530}
42531#[doc = "Vector reinterpret cast operation"]
42532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42533#[inline]
42534#[cfg(target_endian = "little")]
42535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42537#[cfg_attr(
42538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42539 assert_instr(nop)
42540)]
42541#[target_feature(enable = "neon,fp16")]
42542#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42543pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42544 unsafe { transmute(a) }
42545}
42546#[doc = "Vector reinterpret cast operation"]
42547#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
42548#[inline]
42549#[cfg(target_endian = "big")]
42550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42552#[cfg_attr(
42553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42554 assert_instr(nop)
42555)]
42556#[target_feature(enable = "neon,fp16")]
42557#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42558pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
42559 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
42560 unsafe {
42561 let ret_val: poly16x4_t = transmute(a);
42562 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42563 }
42564}
42565#[doc = "Vector reinterpret cast operation"]
42566#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
42567#[inline]
42568#[cfg(target_endian = "little")]
42569#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42570#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42571#[cfg_attr(
42572 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42573 assert_instr(nop)
42574)]
42575#[target_feature(enable = "neon,fp16")]
42576#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42577pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
42578 unsafe { transmute(a) }
42579}
42580#[doc = "Vector reinterpret cast operation"]
42581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
42582#[inline]
42583#[cfg(target_endian = "big")]
42584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42586#[cfg_attr(
42587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42588 assert_instr(nop)
42589)]
42590#[target_feature(enable = "neon,fp16")]
42591#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42592pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
42593 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42594 unsafe {
42595 let ret_val: float32x4_t = transmute(a);
42596 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42597 }
42598}
42599#[doc = "Vector reinterpret cast operation"]
42600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
42601#[inline]
42602#[cfg(target_endian = "little")]
42603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42605#[cfg_attr(
42606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42607 assert_instr(nop)
42608)]
42609#[target_feature(enable = "neon,fp16")]
42610#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42611pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
42612 unsafe { transmute(a) }
42613}
42614#[doc = "Vector reinterpret cast operation"]
42615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
42616#[inline]
42617#[cfg(target_endian = "big")]
42618#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42619#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42620#[cfg_attr(
42621 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42622 assert_instr(nop)
42623)]
42624#[target_feature(enable = "neon,fp16")]
42625#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42626pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
42627 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42628 unsafe {
42629 let ret_val: int8x16_t = transmute(a);
42630 simd_shuffle!(
42631 ret_val,
42632 ret_val,
42633 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42634 )
42635 }
42636}
42637#[doc = "Vector reinterpret cast operation"]
42638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
42639#[inline]
42640#[cfg(target_endian = "little")]
42641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42643#[cfg_attr(
42644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42645 assert_instr(nop)
42646)]
42647#[target_feature(enable = "neon,fp16")]
42648#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42649pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
42650 unsafe { transmute(a) }
42651}
42652#[doc = "Vector reinterpret cast operation"]
42653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
42654#[inline]
42655#[cfg(target_endian = "big")]
42656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42658#[cfg_attr(
42659 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42660 assert_instr(nop)
42661)]
42662#[target_feature(enable = "neon,fp16")]
42663#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42664pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
42665 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42666 unsafe {
42667 let ret_val: int16x8_t = transmute(a);
42668 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42669 }
42670}
42671#[doc = "Vector reinterpret cast operation"]
42672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
42673#[inline]
42674#[cfg(target_endian = "little")]
42675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42677#[cfg_attr(
42678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42679 assert_instr(nop)
42680)]
42681#[target_feature(enable = "neon,fp16")]
42682#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42683pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
42684 unsafe { transmute(a) }
42685}
42686#[doc = "Vector reinterpret cast operation"]
42687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
42688#[inline]
42689#[cfg(target_endian = "big")]
42690#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42691#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42692#[cfg_attr(
42693 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42694 assert_instr(nop)
42695)]
42696#[target_feature(enable = "neon,fp16")]
42697#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42698pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
42699 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42700 unsafe {
42701 let ret_val: int32x4_t = transmute(a);
42702 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42703 }
42704}
42705#[doc = "Vector reinterpret cast operation"]
42706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
42707#[inline]
42708#[cfg(target_endian = "little")]
42709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42711#[cfg_attr(
42712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42713 assert_instr(nop)
42714)]
42715#[target_feature(enable = "neon,fp16")]
42716#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42717pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
42718 unsafe { transmute(a) }
42719}
42720#[doc = "Vector reinterpret cast operation"]
42721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
42722#[inline]
42723#[cfg(target_endian = "big")]
42724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42726#[cfg_attr(
42727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42728 assert_instr(nop)
42729)]
42730#[target_feature(enable = "neon,fp16")]
42731#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42732pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
42733 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42734 unsafe {
42735 let ret_val: int64x2_t = transmute(a);
42736 simd_shuffle!(ret_val, ret_val, [1, 0])
42737 }
42738}
42739#[doc = "Vector reinterpret cast operation"]
42740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
42741#[inline]
42742#[cfg(target_endian = "little")]
42743#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42744#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42745#[cfg_attr(
42746 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42747 assert_instr(nop)
42748)]
42749#[target_feature(enable = "neon,fp16")]
42750#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42751pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
42752 unsafe { transmute(a) }
42753}
42754#[doc = "Vector reinterpret cast operation"]
42755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
42756#[inline]
42757#[cfg(target_endian = "big")]
42758#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42759#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42760#[cfg_attr(
42761 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42762 assert_instr(nop)
42763)]
42764#[target_feature(enable = "neon,fp16")]
42765#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42766pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
42767 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42768 unsafe {
42769 let ret_val: uint8x16_t = transmute(a);
42770 simd_shuffle!(
42771 ret_val,
42772 ret_val,
42773 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42774 )
42775 }
42776}
42777#[doc = "Vector reinterpret cast operation"]
42778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
42779#[inline]
42780#[cfg(target_endian = "little")]
42781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42783#[cfg_attr(
42784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42785 assert_instr(nop)
42786)]
42787#[target_feature(enable = "neon,fp16")]
42788#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42789pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
42790 unsafe { transmute(a) }
42791}
42792#[doc = "Vector reinterpret cast operation"]
42793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
42794#[inline]
42795#[cfg(target_endian = "big")]
42796#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42797#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42798#[cfg_attr(
42799 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42800 assert_instr(nop)
42801)]
42802#[target_feature(enable = "neon,fp16")]
42803#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42804pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
42805 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42806 unsafe {
42807 let ret_val: uint16x8_t = transmute(a);
42808 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42809 }
42810}
42811#[doc = "Vector reinterpret cast operation"]
42812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
42813#[inline]
42814#[cfg(target_endian = "little")]
42815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42817#[cfg_attr(
42818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42819 assert_instr(nop)
42820)]
42821#[target_feature(enable = "neon,fp16")]
42822#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42823pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
42824 unsafe { transmute(a) }
42825}
42826#[doc = "Vector reinterpret cast operation"]
42827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
42828#[inline]
42829#[cfg(target_endian = "big")]
42830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42831#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42832#[cfg_attr(
42833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42834 assert_instr(nop)
42835)]
42836#[target_feature(enable = "neon,fp16")]
42837#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42838pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
42839 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42840 unsafe {
42841 let ret_val: uint32x4_t = transmute(a);
42842 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42843 }
42844}
42845#[doc = "Vector reinterpret cast operation"]
42846#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
42847#[inline]
42848#[cfg(target_endian = "little")]
42849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42851#[cfg_attr(
42852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42853 assert_instr(nop)
42854)]
42855#[target_feature(enable = "neon,fp16")]
42856#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42857pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
42858 unsafe { transmute(a) }
42859}
42860#[doc = "Vector reinterpret cast operation"]
42861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
42862#[inline]
42863#[cfg(target_endian = "big")]
42864#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42865#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42866#[cfg_attr(
42867 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42868 assert_instr(nop)
42869)]
42870#[target_feature(enable = "neon,fp16")]
42871#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42872pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
42873 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42874 unsafe {
42875 let ret_val: uint64x2_t = transmute(a);
42876 simd_shuffle!(ret_val, ret_val, [1, 0])
42877 }
42878}
42879#[doc = "Vector reinterpret cast operation"]
42880#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
42881#[inline]
42882#[cfg(target_endian = "little")]
42883#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42884#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42885#[cfg_attr(
42886 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42887 assert_instr(nop)
42888)]
42889#[target_feature(enable = "neon,fp16")]
42890#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42891pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
42892 unsafe { transmute(a) }
42893}
42894#[doc = "Vector reinterpret cast operation"]
42895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
42896#[inline]
42897#[cfg(target_endian = "big")]
42898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42900#[cfg_attr(
42901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42902 assert_instr(nop)
42903)]
42904#[target_feature(enable = "neon,fp16")]
42905#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42906pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
42907 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42908 unsafe {
42909 let ret_val: poly8x16_t = transmute(a);
42910 simd_shuffle!(
42911 ret_val,
42912 ret_val,
42913 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
42914 )
42915 }
42916}
42917#[doc = "Vector reinterpret cast operation"]
42918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
42919#[inline]
42920#[cfg(target_endian = "little")]
42921#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42922#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42923#[cfg_attr(
42924 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42925 assert_instr(nop)
42926)]
42927#[target_feature(enable = "neon,fp16")]
42928#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42929pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
42930 unsafe { transmute(a) }
42931}
42932#[doc = "Vector reinterpret cast operation"]
42933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
42934#[inline]
42935#[cfg(target_endian = "big")]
42936#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42938#[cfg_attr(
42939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42940 assert_instr(nop)
42941)]
42942#[target_feature(enable = "neon,fp16")]
42943#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42944pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
42945 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
42946 unsafe {
42947 let ret_val: poly16x8_t = transmute(a);
42948 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
42949 }
42950}
42951#[doc = "Vector reinterpret cast operation"]
42952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
42953#[inline]
42954#[cfg(target_endian = "little")]
42955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42957#[cfg_attr(
42958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42959 assert_instr(nop)
42960)]
42961#[target_feature(enable = "neon,fp16")]
42962#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42963pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
42964 unsafe { transmute(a) }
42965}
42966#[doc = "Vector reinterpret cast operation"]
42967#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
42968#[inline]
42969#[cfg(target_endian = "big")]
42970#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42971#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42972#[cfg_attr(
42973 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42974 assert_instr(nop)
42975)]
42976#[target_feature(enable = "neon,fp16")]
42977#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42978pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
42979 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
42980 unsafe {
42981 let ret_val: float16x4_t = transmute(a);
42982 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
42983 }
42984}
42985#[doc = "Vector reinterpret cast operation"]
42986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
42987#[inline]
42988#[cfg(target_endian = "little")]
42989#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
42990#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
42991#[cfg_attr(
42992 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
42993 assert_instr(nop)
42994)]
42995#[target_feature(enable = "neon,fp16")]
42996#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
42997pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
42998 unsafe { transmute(a) }
42999}
43000#[doc = "Vector reinterpret cast operation"]
43001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
43002#[inline]
43003#[cfg(target_endian = "big")]
43004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43006#[cfg_attr(
43007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43008 assert_instr(nop)
43009)]
43010#[target_feature(enable = "neon,fp16")]
43011#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43012pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
43013 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43014 unsafe {
43015 let ret_val: float16x8_t = transmute(a);
43016 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43017 }
43018}
43019#[doc = "Vector reinterpret cast operation"]
43020#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43021#[inline]
43022#[cfg(target_endian = "little")]
43023#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43025#[cfg_attr(
43026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43027 assert_instr(nop)
43028)]
43029#[target_feature(enable = "neon,fp16")]
43030#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43031pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43032 unsafe { transmute(a) }
43033}
43034#[doc = "Vector reinterpret cast operation"]
43035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
43036#[inline]
43037#[cfg(target_endian = "big")]
43038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43040#[cfg_attr(
43041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43042 assert_instr(nop)
43043)]
43044#[target_feature(enable = "neon,fp16")]
43045#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43046pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
43047 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43048 unsafe {
43049 let ret_val: float16x4_t = transmute(a);
43050 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43051 }
43052}
43053#[doc = "Vector reinterpret cast operation"]
43054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43055#[inline]
43056#[cfg(target_endian = "little")]
43057#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43058#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43059#[cfg_attr(
43060 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43061 assert_instr(nop)
43062)]
43063#[target_feature(enable = "neon,fp16")]
43064#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43065pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43066 unsafe { transmute(a) }
43067}
43068#[doc = "Vector reinterpret cast operation"]
43069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
43070#[inline]
43071#[cfg(target_endian = "big")]
43072#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43073#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43074#[cfg_attr(
43075 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43076 assert_instr(nop)
43077)]
43078#[target_feature(enable = "neon,fp16")]
43079#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43080pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
43081 let a: int8x16_t =
43082 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43083 unsafe {
43084 let ret_val: float16x8_t = transmute(a);
43085 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43086 }
43087}
43088#[doc = "Vector reinterpret cast operation"]
43089#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43090#[inline]
43091#[cfg(target_endian = "little")]
43092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43094#[cfg_attr(
43095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43096 assert_instr(nop)
43097)]
43098#[target_feature(enable = "neon,fp16")]
43099#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43100pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43101 unsafe { transmute(a) }
43102}
43103#[doc = "Vector reinterpret cast operation"]
43104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
43105#[inline]
43106#[cfg(target_endian = "big")]
43107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43109#[cfg_attr(
43110 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43111 assert_instr(nop)
43112)]
43113#[target_feature(enable = "neon,fp16")]
43114#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43115pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
43116 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43117 unsafe {
43118 let ret_val: float16x4_t = transmute(a);
43119 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43120 }
43121}
43122#[doc = "Vector reinterpret cast operation"]
43123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43124#[inline]
43125#[cfg(target_endian = "little")]
43126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43128#[cfg_attr(
43129 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43130 assert_instr(nop)
43131)]
43132#[target_feature(enable = "neon,fp16")]
43133#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43134pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43135 unsafe { transmute(a) }
43136}
43137#[doc = "Vector reinterpret cast operation"]
43138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
43139#[inline]
43140#[cfg(target_endian = "big")]
43141#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43143#[cfg_attr(
43144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43145 assert_instr(nop)
43146)]
43147#[target_feature(enable = "neon,fp16")]
43148#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43149pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
43150 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43151 unsafe {
43152 let ret_val: float16x8_t = transmute(a);
43153 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43154 }
43155}
43156#[doc = "Vector reinterpret cast operation"]
43157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43158#[inline]
43159#[cfg(target_endian = "little")]
43160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43162#[cfg_attr(
43163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43164 assert_instr(nop)
43165)]
43166#[target_feature(enable = "neon,fp16")]
43167#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43168pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43169 unsafe { transmute(a) }
43170}
43171#[doc = "Vector reinterpret cast operation"]
43172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
43173#[inline]
43174#[cfg(target_endian = "big")]
43175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43176#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43177#[cfg_attr(
43178 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43179 assert_instr(nop)
43180)]
43181#[target_feature(enable = "neon,fp16")]
43182#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43183pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
43184 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43185 unsafe {
43186 let ret_val: float16x4_t = transmute(a);
43187 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43188 }
43189}
43190#[doc = "Vector reinterpret cast operation"]
43191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43192#[inline]
43193#[cfg(target_endian = "little")]
43194#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43195#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43196#[cfg_attr(
43197 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43198 assert_instr(nop)
43199)]
43200#[target_feature(enable = "neon,fp16")]
43201#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43202pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43203 unsafe { transmute(a) }
43204}
43205#[doc = "Vector reinterpret cast operation"]
43206#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
43207#[inline]
43208#[cfg(target_endian = "big")]
43209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43211#[cfg_attr(
43212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43213 assert_instr(nop)
43214)]
43215#[target_feature(enable = "neon,fp16")]
43216#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43217pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
43218 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43219 unsafe {
43220 let ret_val: float16x8_t = transmute(a);
43221 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43222 }
43223}
43224#[doc = "Vector reinterpret cast operation"]
43225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43226#[inline]
43227#[cfg(target_endian = "little")]
43228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43230#[cfg_attr(
43231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43232 assert_instr(nop)
43233)]
43234#[target_feature(enable = "neon,fp16")]
43235#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43236pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43237 unsafe { transmute(a) }
43238}
43239#[doc = "Vector reinterpret cast operation"]
43240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
43241#[inline]
43242#[cfg(target_endian = "big")]
43243#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43244#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43245#[cfg_attr(
43246 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43247 assert_instr(nop)
43248)]
43249#[target_feature(enable = "neon,fp16")]
43250#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43251pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
43252 unsafe {
43253 let ret_val: float16x4_t = transmute(a);
43254 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43255 }
43256}
43257#[doc = "Vector reinterpret cast operation"]
43258#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43259#[inline]
43260#[cfg(target_endian = "little")]
43261#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43262#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43263#[cfg_attr(
43264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43265 assert_instr(nop)
43266)]
43267#[target_feature(enable = "neon,fp16")]
43268#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43269pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43270 unsafe { transmute(a) }
43271}
43272#[doc = "Vector reinterpret cast operation"]
43273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
43274#[inline]
43275#[cfg(target_endian = "big")]
43276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43277#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43278#[cfg_attr(
43279 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43280 assert_instr(nop)
43281)]
43282#[target_feature(enable = "neon,fp16")]
43283#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43284pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
43285 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43286 unsafe {
43287 let ret_val: float16x8_t = transmute(a);
43288 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43289 }
43290}
43291#[doc = "Vector reinterpret cast operation"]
43292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43293#[inline]
43294#[cfg(target_endian = "little")]
43295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43297#[cfg_attr(
43298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43299 assert_instr(nop)
43300)]
43301#[target_feature(enable = "neon,fp16")]
43302#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43303pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43304 unsafe { transmute(a) }
43305}
43306#[doc = "Vector reinterpret cast operation"]
43307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
43308#[inline]
43309#[cfg(target_endian = "big")]
43310#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43311#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43312#[cfg_attr(
43313 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43314 assert_instr(nop)
43315)]
43316#[target_feature(enable = "neon,fp16")]
43317#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43318pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
43319 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43320 unsafe {
43321 let ret_val: float16x4_t = transmute(a);
43322 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43323 }
43324}
43325#[doc = "Vector reinterpret cast operation"]
43326#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43327#[inline]
43328#[cfg(target_endian = "little")]
43329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43331#[cfg_attr(
43332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43333 assert_instr(nop)
43334)]
43335#[target_feature(enable = "neon,fp16")]
43336#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43337pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43338 unsafe { transmute(a) }
43339}
43340#[doc = "Vector reinterpret cast operation"]
43341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
43342#[inline]
43343#[cfg(target_endian = "big")]
43344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43346#[cfg_attr(
43347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43348 assert_instr(nop)
43349)]
43350#[target_feature(enable = "neon,fp16")]
43351#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43352pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
43353 let a: uint8x16_t =
43354 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43355 unsafe {
43356 let ret_val: float16x8_t = transmute(a);
43357 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43358 }
43359}
43360#[doc = "Vector reinterpret cast operation"]
43361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43362#[inline]
43363#[cfg(target_endian = "little")]
43364#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43365#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43366#[cfg_attr(
43367 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43368 assert_instr(nop)
43369)]
43370#[target_feature(enable = "neon,fp16")]
43371#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43372pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43373 unsafe { transmute(a) }
43374}
43375#[doc = "Vector reinterpret cast operation"]
43376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
43377#[inline]
43378#[cfg(target_endian = "big")]
43379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43381#[cfg_attr(
43382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43383 assert_instr(nop)
43384)]
43385#[target_feature(enable = "neon,fp16")]
43386#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43387pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
43388 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43389 unsafe {
43390 let ret_val: float16x4_t = transmute(a);
43391 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43392 }
43393}
43394#[doc = "Vector reinterpret cast operation"]
43395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43396#[inline]
43397#[cfg(target_endian = "little")]
43398#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43399#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43400#[cfg_attr(
43401 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43402 assert_instr(nop)
43403)]
43404#[target_feature(enable = "neon,fp16")]
43405#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43406pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43407 unsafe { transmute(a) }
43408}
43409#[doc = "Vector reinterpret cast operation"]
43410#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
43411#[inline]
43412#[cfg(target_endian = "big")]
43413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43415#[cfg_attr(
43416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43417 assert_instr(nop)
43418)]
43419#[target_feature(enable = "neon,fp16")]
43420#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43421pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
43422 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43423 unsafe {
43424 let ret_val: float16x8_t = transmute(a);
43425 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43426 }
43427}
43428#[doc = "Vector reinterpret cast operation"]
43429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43430#[inline]
43431#[cfg(target_endian = "little")]
43432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43434#[cfg_attr(
43435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43436 assert_instr(nop)
43437)]
43438#[target_feature(enable = "neon,fp16")]
43439#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43440pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43441 unsafe { transmute(a) }
43442}
43443#[doc = "Vector reinterpret cast operation"]
43444#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
43445#[inline]
43446#[cfg(target_endian = "big")]
43447#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43449#[cfg_attr(
43450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43451 assert_instr(nop)
43452)]
43453#[target_feature(enable = "neon,fp16")]
43454#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43455pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
43456 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43457 unsafe {
43458 let ret_val: float16x4_t = transmute(a);
43459 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43460 }
43461}
43462#[doc = "Vector reinterpret cast operation"]
43463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43464#[inline]
43465#[cfg(target_endian = "little")]
43466#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43467#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43468#[cfg_attr(
43469 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43470 assert_instr(nop)
43471)]
43472#[target_feature(enable = "neon,fp16")]
43473#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43474pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43475 unsafe { transmute(a) }
43476}
43477#[doc = "Vector reinterpret cast operation"]
43478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
43479#[inline]
43480#[cfg(target_endian = "big")]
43481#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43482#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43483#[cfg_attr(
43484 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43485 assert_instr(nop)
43486)]
43487#[target_feature(enable = "neon,fp16")]
43488#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43489pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
43490 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43491 unsafe {
43492 let ret_val: float16x8_t = transmute(a);
43493 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43494 }
43495}
43496#[doc = "Vector reinterpret cast operation"]
43497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43498#[inline]
43499#[cfg(target_endian = "little")]
43500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43501#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43502#[cfg_attr(
43503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43504 assert_instr(nop)
43505)]
43506#[target_feature(enable = "neon,fp16")]
43507#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43508pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43509 unsafe { transmute(a) }
43510}
43511#[doc = "Vector reinterpret cast operation"]
43512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
43513#[inline]
43514#[cfg(target_endian = "big")]
43515#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43516#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43517#[cfg_attr(
43518 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43519 assert_instr(nop)
43520)]
43521#[target_feature(enable = "neon,fp16")]
43522#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43523pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
43524 unsafe {
43525 let ret_val: float16x4_t = transmute(a);
43526 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43527 }
43528}
43529#[doc = "Vector reinterpret cast operation"]
43530#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43531#[inline]
43532#[cfg(target_endian = "little")]
43533#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43534#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43535#[cfg_attr(
43536 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43537 assert_instr(nop)
43538)]
43539#[target_feature(enable = "neon,fp16")]
43540#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43541pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43542 unsafe { transmute(a) }
43543}
43544#[doc = "Vector reinterpret cast operation"]
43545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
43546#[inline]
43547#[cfg(target_endian = "big")]
43548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43550#[cfg_attr(
43551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43552 assert_instr(nop)
43553)]
43554#[target_feature(enable = "neon,fp16")]
43555#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43556pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
43557 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43558 unsafe {
43559 let ret_val: float16x8_t = transmute(a);
43560 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43561 }
43562}
43563#[doc = "Vector reinterpret cast operation"]
43564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
43565#[inline]
43566#[cfg(target_endian = "little")]
43567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43569#[cfg_attr(
43570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43571 assert_instr(nop)
43572)]
43573#[target_feature(enable = "neon,fp16")]
43574#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43575pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
43576 unsafe { transmute(a) }
43577}
43578#[doc = "Vector reinterpret cast operation"]
43579#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
43580#[inline]
43581#[cfg(target_endian = "big")]
43582#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43583#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43584#[cfg_attr(
43585 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43586 assert_instr(nop)
43587)]
43588#[target_feature(enable = "neon,fp16")]
43589#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43590pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
43591 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43592 unsafe {
43593 let ret_val: float16x4_t = transmute(a);
43594 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43595 }
43596}
43597#[doc = "Vector reinterpret cast operation"]
43598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
43599#[inline]
43600#[cfg(target_endian = "little")]
43601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43603#[cfg_attr(
43604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43605 assert_instr(nop)
43606)]
43607#[target_feature(enable = "neon,fp16")]
43608#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43609pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
43610 unsafe { transmute(a) }
43611}
43612#[doc = "Vector reinterpret cast operation"]
43613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
43614#[inline]
43615#[cfg(target_endian = "big")]
43616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43618#[cfg_attr(
43619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43620 assert_instr(nop)
43621)]
43622#[target_feature(enable = "neon,fp16")]
43623#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43624pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
43625 let a: poly8x16_t =
43626 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
43627 unsafe {
43628 let ret_val: float16x8_t = transmute(a);
43629 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43630 }
43631}
43632#[doc = "Vector reinterpret cast operation"]
43633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
43634#[inline]
43635#[cfg(target_endian = "little")]
43636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43638#[cfg_attr(
43639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43640 assert_instr(nop)
43641)]
43642#[target_feature(enable = "neon,fp16")]
43643#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43644pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
43645 unsafe { transmute(a) }
43646}
43647#[doc = "Vector reinterpret cast operation"]
43648#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
43649#[inline]
43650#[cfg(target_endian = "big")]
43651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43653#[cfg_attr(
43654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43655 assert_instr(nop)
43656)]
43657#[target_feature(enable = "neon,fp16")]
43658#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43659pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
43660 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43661 unsafe {
43662 let ret_val: float16x4_t = transmute(a);
43663 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43664 }
43665}
43666#[doc = "Vector reinterpret cast operation"]
43667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
43668#[inline]
43669#[cfg(target_endian = "little")]
43670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43672#[cfg_attr(
43673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43674 assert_instr(nop)
43675)]
43676#[target_feature(enable = "neon,fp16")]
43677#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43678pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
43679 unsafe { transmute(a) }
43680}
43681#[doc = "Vector reinterpret cast operation"]
43682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
43683#[inline]
43684#[cfg(target_endian = "big")]
43685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43687#[cfg_attr(
43688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43689 assert_instr(nop)
43690)]
43691#[target_feature(enable = "neon,fp16")]
43692#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43693pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
43694 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43695 unsafe {
43696 let ret_val: float16x8_t = transmute(a);
43697 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43698 }
43699}
43700#[doc = "Vector reinterpret cast operation"]
43701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
43702#[inline]
43703#[cfg(target_endian = "little")]
43704#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43706#[cfg_attr(
43707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43708 assert_instr(nop)
43709)]
43710#[target_feature(enable = "neon,fp16")]
43711#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43712pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
43713 unsafe { transmute(a) }
43714}
43715#[doc = "Vector reinterpret cast operation"]
43716#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
43717#[inline]
43718#[cfg(target_endian = "big")]
43719#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43720#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43721#[cfg_attr(
43722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43723 assert_instr(nop)
43724)]
43725#[target_feature(enable = "neon,fp16")]
43726#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43727pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
43728 unsafe {
43729 let ret_val: float16x8_t = transmute(a);
43730 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43731 }
43732}
43733#[doc = "Vector reinterpret cast operation"]
43734#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
43735#[inline]
43736#[cfg(target_endian = "little")]
43737#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43739#[cfg_attr(
43740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43741 assert_instr(nop)
43742)]
43743#[target_feature(enable = "neon,fp16")]
43744#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43745pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
43746 unsafe { transmute(a) }
43747}
43748#[doc = "Vector reinterpret cast operation"]
43749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
43750#[inline]
43751#[cfg(target_endian = "big")]
43752#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43754#[cfg_attr(
43755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43756 assert_instr(nop)
43757)]
43758#[target_feature(enable = "neon,fp16")]
43759#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43760pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
43761 let a: float16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
43762 unsafe { transmute(a) }
43763}
43764#[doc = "Vector reinterpret cast operation"]
43765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
43766#[inline]
43767#[cfg(target_endian = "little")]
43768#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43770#[cfg_attr(
43771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43772 assert_instr(nop)
43773)]
43774#[target_feature(enable = "neon,fp16")]
43775#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43776pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
43777 unsafe { transmute(a) }
43778}
43779#[doc = "Vector reinterpret cast operation"]
43780#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
43781#[inline]
43782#[cfg(target_endian = "big")]
43783#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43785#[cfg_attr(
43786 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43787 assert_instr(nop)
43788)]
43789#[target_feature(enable = "neon,fp16")]
43790#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43791pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
43792 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43793 unsafe { transmute(a) }
43794}
43795#[doc = "Vector reinterpret cast operation"]
43796#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
43797#[inline]
43798#[cfg(target_endian = "little")]
43799#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43800#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43801#[cfg_attr(
43802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43803 assert_instr(nop)
43804)]
43805#[target_feature(enable = "neon,fp16")]
43806#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43807pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
43808 unsafe { transmute(a) }
43809}
43810#[doc = "Vector reinterpret cast operation"]
43811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
43812#[inline]
43813#[cfg(target_endian = "big")]
43814#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43815#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43816#[cfg_attr(
43817 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43818 assert_instr(nop)
43819)]
43820#[target_feature(enable = "neon,fp16")]
43821#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43822pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
43823 let a: float16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
43824 unsafe {
43825 let ret_val: poly64x2_t = transmute(a);
43826 simd_shuffle!(ret_val, ret_val, [1, 0])
43827 }
43828}
43829#[doc = "Vector reinterpret cast operation"]
43830#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
43831#[inline]
43832#[cfg(target_endian = "little")]
43833#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43835#[cfg_attr(
43836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43837 assert_instr(nop)
43838)]
43839#[target_feature(enable = "neon,fp16")]
43840#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43841pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
43842 unsafe { transmute(a) }
43843}
43844#[doc = "Vector reinterpret cast operation"]
43845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
43846#[inline]
43847#[cfg(target_endian = "big")]
43848#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43850#[cfg_attr(
43851 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43852 assert_instr(nop)
43853)]
43854#[target_feature(enable = "neon,fp16")]
43855#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43856pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
43857 unsafe {
43858 let ret_val: float16x4_t = transmute(a);
43859 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43860 }
43861}
43862#[doc = "Vector reinterpret cast operation"]
43863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
43864#[inline]
43865#[cfg(target_endian = "little")]
43866#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43868#[cfg_attr(
43869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43870 assert_instr(nop)
43871)]
43872#[target_feature(enable = "neon,fp16")]
43873#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43874pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
43875 unsafe { transmute(a) }
43876}
43877#[doc = "Vector reinterpret cast operation"]
43878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
43879#[inline]
43880#[cfg(target_endian = "big")]
43881#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
43882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43883#[cfg_attr(
43884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43885 assert_instr(nop)
43886)]
43887#[target_feature(enable = "neon,fp16")]
43888#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
43889pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
43890 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43891 unsafe {
43892 let ret_val: float16x8_t = transmute(a);
43893 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43894 }
43895}
43896#[doc = "Vector reinterpret cast operation"]
43897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
43898#[inline]
43899#[cfg(target_endian = "little")]
43900#[target_feature(enable = "neon")]
43901#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43902#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43903#[cfg_attr(
43904 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43905 assert_instr(nop)
43906)]
43907#[cfg_attr(
43908 not(target_arch = "arm"),
43909 stable(feature = "neon_intrinsics", since = "1.59.0")
43910)]
43911#[cfg_attr(
43912 target_arch = "arm",
43913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43914)]
43915pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
43916 unsafe { transmute(a) }
43917}
43918#[doc = "Vector reinterpret cast operation"]
43919#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
43920#[inline]
43921#[cfg(target_endian = "big")]
43922#[target_feature(enable = "neon")]
43923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43925#[cfg_attr(
43926 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43927 assert_instr(nop)
43928)]
43929#[cfg_attr(
43930 not(target_arch = "arm"),
43931 stable(feature = "neon_intrinsics", since = "1.59.0")
43932)]
43933#[cfg_attr(
43934 target_arch = "arm",
43935 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43936)]
43937pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
43938 unsafe {
43939 let ret_val: float32x4_t = transmute(a);
43940 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
43941 }
43942}
43943#[doc = "Vector reinterpret cast operation"]
43944#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
43945#[inline]
43946#[cfg(target_endian = "little")]
43947#[target_feature(enable = "neon")]
43948#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43949#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43950#[cfg_attr(
43951 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43952 assert_instr(nop)
43953)]
43954#[cfg_attr(
43955 not(target_arch = "arm"),
43956 stable(feature = "neon_intrinsics", since = "1.59.0")
43957)]
43958#[cfg_attr(
43959 target_arch = "arm",
43960 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43961)]
43962pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
43963 unsafe { transmute(a) }
43964}
43965#[doc = "Vector reinterpret cast operation"]
43966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
43967#[inline]
43968#[cfg(target_endian = "big")]
43969#[target_feature(enable = "neon")]
43970#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43971#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43972#[cfg_attr(
43973 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
43974 assert_instr(nop)
43975)]
43976#[cfg_attr(
43977 not(target_arch = "arm"),
43978 stable(feature = "neon_intrinsics", since = "1.59.0")
43979)]
43980#[cfg_attr(
43981 target_arch = "arm",
43982 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
43983)]
43984pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
43985 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
43986 unsafe {
43987 let ret_val: int8x8_t = transmute(a);
43988 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
43989 }
43990}
43991#[doc = "Vector reinterpret cast operation"]
43992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
43993#[inline]
43994#[cfg(target_endian = "little")]
43995#[target_feature(enable = "neon")]
43996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
43997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
43998#[cfg_attr(
43999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44000 assert_instr(nop)
44001)]
44002#[cfg_attr(
44003 not(target_arch = "arm"),
44004 stable(feature = "neon_intrinsics", since = "1.59.0")
44005)]
44006#[cfg_attr(
44007 target_arch = "arm",
44008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44009)]
44010pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44011 unsafe { transmute(a) }
44012}
44013#[doc = "Vector reinterpret cast operation"]
44014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
44015#[inline]
44016#[cfg(target_endian = "big")]
44017#[target_feature(enable = "neon")]
44018#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44019#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44020#[cfg_attr(
44021 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44022 assert_instr(nop)
44023)]
44024#[cfg_attr(
44025 not(target_arch = "arm"),
44026 stable(feature = "neon_intrinsics", since = "1.59.0")
44027)]
44028#[cfg_attr(
44029 target_arch = "arm",
44030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44031)]
44032pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
44033 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44034 unsafe {
44035 let ret_val: int16x4_t = transmute(a);
44036 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44037 }
44038}
44039#[doc = "Vector reinterpret cast operation"]
44040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44041#[inline]
44042#[cfg(target_endian = "little")]
44043#[target_feature(enable = "neon")]
44044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44046#[cfg_attr(
44047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44048 assert_instr(nop)
44049)]
44050#[cfg_attr(
44051 not(target_arch = "arm"),
44052 stable(feature = "neon_intrinsics", since = "1.59.0")
44053)]
44054#[cfg_attr(
44055 target_arch = "arm",
44056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44057)]
44058pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44059 unsafe { transmute(a) }
44060}
44061#[doc = "Vector reinterpret cast operation"]
44062#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
44063#[inline]
44064#[cfg(target_endian = "big")]
44065#[target_feature(enable = "neon")]
44066#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44068#[cfg_attr(
44069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44070 assert_instr(nop)
44071)]
44072#[cfg_attr(
44073 not(target_arch = "arm"),
44074 stable(feature = "neon_intrinsics", since = "1.59.0")
44075)]
44076#[cfg_attr(
44077 target_arch = "arm",
44078 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44079)]
44080pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
44081 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44082 unsafe {
44083 let ret_val: int32x2_t = transmute(a);
44084 simd_shuffle!(ret_val, ret_val, [1, 0])
44085 }
44086}
44087#[doc = "Vector reinterpret cast operation"]
44088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44089#[inline]
44090#[cfg(target_endian = "little")]
44091#[target_feature(enable = "neon")]
44092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44094#[cfg_attr(
44095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44096 assert_instr(nop)
44097)]
44098#[cfg_attr(
44099 not(target_arch = "arm"),
44100 stable(feature = "neon_intrinsics", since = "1.59.0")
44101)]
44102#[cfg_attr(
44103 target_arch = "arm",
44104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44105)]
44106pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44107 unsafe { transmute(a) }
44108}
44109#[doc = "Vector reinterpret cast operation"]
44110#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
44111#[inline]
44112#[cfg(target_endian = "big")]
44113#[target_feature(enable = "neon")]
44114#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44115#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44116#[cfg_attr(
44117 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44118 assert_instr(nop)
44119)]
44120#[cfg_attr(
44121 not(target_arch = "arm"),
44122 stable(feature = "neon_intrinsics", since = "1.59.0")
44123)]
44124#[cfg_attr(
44125 target_arch = "arm",
44126 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44127)]
44128pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
44129 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44130 unsafe { transmute(a) }
44131}
44132#[doc = "Vector reinterpret cast operation"]
44133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44134#[inline]
44135#[cfg(target_endian = "little")]
44136#[target_feature(enable = "neon")]
44137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44139#[cfg_attr(
44140 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44141 assert_instr(nop)
44142)]
44143#[cfg_attr(
44144 not(target_arch = "arm"),
44145 stable(feature = "neon_intrinsics", since = "1.59.0")
44146)]
44147#[cfg_attr(
44148 target_arch = "arm",
44149 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44150)]
44151pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44152 unsafe { transmute(a) }
44153}
44154#[doc = "Vector reinterpret cast operation"]
44155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
44156#[inline]
44157#[cfg(target_endian = "big")]
44158#[target_feature(enable = "neon")]
44159#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44160#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44161#[cfg_attr(
44162 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44163 assert_instr(nop)
44164)]
44165#[cfg_attr(
44166 not(target_arch = "arm"),
44167 stable(feature = "neon_intrinsics", since = "1.59.0")
44168)]
44169#[cfg_attr(
44170 target_arch = "arm",
44171 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44172)]
44173pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
44174 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44175 unsafe {
44176 let ret_val: uint8x8_t = transmute(a);
44177 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44178 }
44179}
44180#[doc = "Vector reinterpret cast operation"]
44181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44182#[inline]
44183#[cfg(target_endian = "little")]
44184#[target_feature(enable = "neon")]
44185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44187#[cfg_attr(
44188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44189 assert_instr(nop)
44190)]
44191#[cfg_attr(
44192 not(target_arch = "arm"),
44193 stable(feature = "neon_intrinsics", since = "1.59.0")
44194)]
44195#[cfg_attr(
44196 target_arch = "arm",
44197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44198)]
44199pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44200 unsafe { transmute(a) }
44201}
44202#[doc = "Vector reinterpret cast operation"]
44203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
44204#[inline]
44205#[cfg(target_endian = "big")]
44206#[target_feature(enable = "neon")]
44207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44209#[cfg_attr(
44210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44211 assert_instr(nop)
44212)]
44213#[cfg_attr(
44214 not(target_arch = "arm"),
44215 stable(feature = "neon_intrinsics", since = "1.59.0")
44216)]
44217#[cfg_attr(
44218 target_arch = "arm",
44219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44220)]
44221pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
44222 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44223 unsafe {
44224 let ret_val: uint16x4_t = transmute(a);
44225 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44226 }
44227}
44228#[doc = "Vector reinterpret cast operation"]
44229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44230#[inline]
44231#[cfg(target_endian = "little")]
44232#[target_feature(enable = "neon")]
44233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44235#[cfg_attr(
44236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44237 assert_instr(nop)
44238)]
44239#[cfg_attr(
44240 not(target_arch = "arm"),
44241 stable(feature = "neon_intrinsics", since = "1.59.0")
44242)]
44243#[cfg_attr(
44244 target_arch = "arm",
44245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44246)]
44247pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44248 unsafe { transmute(a) }
44249}
44250#[doc = "Vector reinterpret cast operation"]
44251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
44252#[inline]
44253#[cfg(target_endian = "big")]
44254#[target_feature(enable = "neon")]
44255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44257#[cfg_attr(
44258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44259 assert_instr(nop)
44260)]
44261#[cfg_attr(
44262 not(target_arch = "arm"),
44263 stable(feature = "neon_intrinsics", since = "1.59.0")
44264)]
44265#[cfg_attr(
44266 target_arch = "arm",
44267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44268)]
44269pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
44270 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44271 unsafe {
44272 let ret_val: uint32x2_t = transmute(a);
44273 simd_shuffle!(ret_val, ret_val, [1, 0])
44274 }
44275}
44276#[doc = "Vector reinterpret cast operation"]
44277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44278#[inline]
44279#[cfg(target_endian = "little")]
44280#[target_feature(enable = "neon")]
44281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44283#[cfg_attr(
44284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44285 assert_instr(nop)
44286)]
44287#[cfg_attr(
44288 not(target_arch = "arm"),
44289 stable(feature = "neon_intrinsics", since = "1.59.0")
44290)]
44291#[cfg_attr(
44292 target_arch = "arm",
44293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44294)]
44295pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44296 unsafe { transmute(a) }
44297}
44298#[doc = "Vector reinterpret cast operation"]
44299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
44300#[inline]
44301#[cfg(target_endian = "big")]
44302#[target_feature(enable = "neon")]
44303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44305#[cfg_attr(
44306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44307 assert_instr(nop)
44308)]
44309#[cfg_attr(
44310 not(target_arch = "arm"),
44311 stable(feature = "neon_intrinsics", since = "1.59.0")
44312)]
44313#[cfg_attr(
44314 target_arch = "arm",
44315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44316)]
44317pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
44318 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44319 unsafe { transmute(a) }
44320}
44321#[doc = "Vector reinterpret cast operation"]
44322#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44323#[inline]
44324#[cfg(target_endian = "little")]
44325#[target_feature(enable = "neon")]
44326#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44327#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44328#[cfg_attr(
44329 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44330 assert_instr(nop)
44331)]
44332#[cfg_attr(
44333 not(target_arch = "arm"),
44334 stable(feature = "neon_intrinsics", since = "1.59.0")
44335)]
44336#[cfg_attr(
44337 target_arch = "arm",
44338 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44339)]
44340pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44341 unsafe { transmute(a) }
44342}
44343#[doc = "Vector reinterpret cast operation"]
44344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
44345#[inline]
44346#[cfg(target_endian = "big")]
44347#[target_feature(enable = "neon")]
44348#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44349#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44350#[cfg_attr(
44351 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44352 assert_instr(nop)
44353)]
44354#[cfg_attr(
44355 not(target_arch = "arm"),
44356 stable(feature = "neon_intrinsics", since = "1.59.0")
44357)]
44358#[cfg_attr(
44359 target_arch = "arm",
44360 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44361)]
44362pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
44363 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44364 unsafe {
44365 let ret_val: poly8x8_t = transmute(a);
44366 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44367 }
44368}
44369#[doc = "Vector reinterpret cast operation"]
44370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44371#[inline]
44372#[cfg(target_endian = "little")]
44373#[target_feature(enable = "neon")]
44374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44376#[cfg_attr(
44377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44378 assert_instr(nop)
44379)]
44380#[cfg_attr(
44381 not(target_arch = "arm"),
44382 stable(feature = "neon_intrinsics", since = "1.59.0")
44383)]
44384#[cfg_attr(
44385 target_arch = "arm",
44386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44387)]
44388pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44389 unsafe { transmute(a) }
44390}
44391#[doc = "Vector reinterpret cast operation"]
44392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
44393#[inline]
44394#[cfg(target_endian = "big")]
44395#[target_feature(enable = "neon")]
44396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44398#[cfg_attr(
44399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44400 assert_instr(nop)
44401)]
44402#[cfg_attr(
44403 not(target_arch = "arm"),
44404 stable(feature = "neon_intrinsics", since = "1.59.0")
44405)]
44406#[cfg_attr(
44407 target_arch = "arm",
44408 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44409)]
44410pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
44411 let a: float32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
44412 unsafe {
44413 let ret_val: poly16x4_t = transmute(a);
44414 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44415 }
44416}
44417#[doc = "Vector reinterpret cast operation"]
44418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44419#[inline]
44420#[cfg(target_endian = "little")]
44421#[target_feature(enable = "neon")]
44422#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44424#[cfg_attr(
44425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44426 assert_instr(nop)
44427)]
44428#[cfg_attr(
44429 not(target_arch = "arm"),
44430 stable(feature = "neon_intrinsics", since = "1.59.0")
44431)]
44432#[cfg_attr(
44433 target_arch = "arm",
44434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44435)]
44436pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44437 unsafe { transmute(a) }
44438}
44439#[doc = "Vector reinterpret cast operation"]
44440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
44441#[inline]
44442#[cfg(target_endian = "big")]
44443#[target_feature(enable = "neon")]
44444#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44445#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44446#[cfg_attr(
44447 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44448 assert_instr(nop)
44449)]
44450#[cfg_attr(
44451 not(target_arch = "arm"),
44452 stable(feature = "neon_intrinsics", since = "1.59.0")
44453)]
44454#[cfg_attr(
44455 target_arch = "arm",
44456 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44457)]
44458pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
44459 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44460 unsafe { transmute(a) }
44461}
44462#[doc = "Vector reinterpret cast operation"]
44463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44464#[inline]
44465#[cfg(target_endian = "little")]
44466#[target_feature(enable = "neon")]
44467#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44468#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44469#[cfg_attr(
44470 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44471 assert_instr(nop)
44472)]
44473#[cfg_attr(
44474 not(target_arch = "arm"),
44475 stable(feature = "neon_intrinsics", since = "1.59.0")
44476)]
44477#[cfg_attr(
44478 target_arch = "arm",
44479 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44480)]
44481pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44482 unsafe { transmute(a) }
44483}
44484#[doc = "Vector reinterpret cast operation"]
44485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
44486#[inline]
44487#[cfg(target_endian = "big")]
44488#[target_feature(enable = "neon")]
44489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44491#[cfg_attr(
44492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44493 assert_instr(nop)
44494)]
44495#[cfg_attr(
44496 not(target_arch = "arm"),
44497 stable(feature = "neon_intrinsics", since = "1.59.0")
44498)]
44499#[cfg_attr(
44500 target_arch = "arm",
44501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44502)]
44503pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
44504 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44505 unsafe {
44506 let ret_val: int8x16_t = transmute(a);
44507 simd_shuffle!(
44508 ret_val,
44509 ret_val,
44510 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44511 )
44512 }
44513}
44514#[doc = "Vector reinterpret cast operation"]
44515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44516#[inline]
44517#[cfg(target_endian = "little")]
44518#[target_feature(enable = "neon")]
44519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44521#[cfg_attr(
44522 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44523 assert_instr(nop)
44524)]
44525#[cfg_attr(
44526 not(target_arch = "arm"),
44527 stable(feature = "neon_intrinsics", since = "1.59.0")
44528)]
44529#[cfg_attr(
44530 target_arch = "arm",
44531 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44532)]
44533pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44534 unsafe { transmute(a) }
44535}
44536#[doc = "Vector reinterpret cast operation"]
44537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
44538#[inline]
44539#[cfg(target_endian = "big")]
44540#[target_feature(enable = "neon")]
44541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44543#[cfg_attr(
44544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44545 assert_instr(nop)
44546)]
44547#[cfg_attr(
44548 not(target_arch = "arm"),
44549 stable(feature = "neon_intrinsics", since = "1.59.0")
44550)]
44551#[cfg_attr(
44552 target_arch = "arm",
44553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44554)]
44555pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
44556 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44557 unsafe {
44558 let ret_val: int16x8_t = transmute(a);
44559 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44560 }
44561}
44562#[doc = "Vector reinterpret cast operation"]
44563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
44564#[inline]
44565#[cfg(target_endian = "little")]
44566#[target_feature(enable = "neon")]
44567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44569#[cfg_attr(
44570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44571 assert_instr(nop)
44572)]
44573#[cfg_attr(
44574 not(target_arch = "arm"),
44575 stable(feature = "neon_intrinsics", since = "1.59.0")
44576)]
44577#[cfg_attr(
44578 target_arch = "arm",
44579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44580)]
44581pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
44582 unsafe { transmute(a) }
44583}
44584#[doc = "Vector reinterpret cast operation"]
44585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
44586#[inline]
44587#[cfg(target_endian = "big")]
44588#[target_feature(enable = "neon")]
44589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44591#[cfg_attr(
44592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44593 assert_instr(nop)
44594)]
44595#[cfg_attr(
44596 not(target_arch = "arm"),
44597 stable(feature = "neon_intrinsics", since = "1.59.0")
44598)]
44599#[cfg_attr(
44600 target_arch = "arm",
44601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44602)]
44603pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
44604 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44605 unsafe {
44606 let ret_val: int32x4_t = transmute(a);
44607 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44608 }
44609}
44610#[doc = "Vector reinterpret cast operation"]
44611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
44612#[inline]
44613#[cfg(target_endian = "little")]
44614#[target_feature(enable = "neon")]
44615#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44616#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44617#[cfg_attr(
44618 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44619 assert_instr(nop)
44620)]
44621#[cfg_attr(
44622 not(target_arch = "arm"),
44623 stable(feature = "neon_intrinsics", since = "1.59.0")
44624)]
44625#[cfg_attr(
44626 target_arch = "arm",
44627 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44628)]
44629pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
44630 unsafe { transmute(a) }
44631}
44632#[doc = "Vector reinterpret cast operation"]
44633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
44634#[inline]
44635#[cfg(target_endian = "big")]
44636#[target_feature(enable = "neon")]
44637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44639#[cfg_attr(
44640 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44641 assert_instr(nop)
44642)]
44643#[cfg_attr(
44644 not(target_arch = "arm"),
44645 stable(feature = "neon_intrinsics", since = "1.59.0")
44646)]
44647#[cfg_attr(
44648 target_arch = "arm",
44649 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44650)]
44651pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
44652 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44653 unsafe {
44654 let ret_val: int64x2_t = transmute(a);
44655 simd_shuffle!(ret_val, ret_val, [1, 0])
44656 }
44657}
44658#[doc = "Vector reinterpret cast operation"]
44659#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
44660#[inline]
44661#[cfg(target_endian = "little")]
44662#[target_feature(enable = "neon")]
44663#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44664#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44665#[cfg_attr(
44666 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44667 assert_instr(nop)
44668)]
44669#[cfg_attr(
44670 not(target_arch = "arm"),
44671 stable(feature = "neon_intrinsics", since = "1.59.0")
44672)]
44673#[cfg_attr(
44674 target_arch = "arm",
44675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44676)]
44677pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
44678 unsafe { transmute(a) }
44679}
44680#[doc = "Vector reinterpret cast operation"]
44681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
44682#[inline]
44683#[cfg(target_endian = "big")]
44684#[target_feature(enable = "neon")]
44685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44686#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44687#[cfg_attr(
44688 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44689 assert_instr(nop)
44690)]
44691#[cfg_attr(
44692 not(target_arch = "arm"),
44693 stable(feature = "neon_intrinsics", since = "1.59.0")
44694)]
44695#[cfg_attr(
44696 target_arch = "arm",
44697 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44698)]
44699pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
44700 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44701 unsafe {
44702 let ret_val: uint8x16_t = transmute(a);
44703 simd_shuffle!(
44704 ret_val,
44705 ret_val,
44706 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44707 )
44708 }
44709}
44710#[doc = "Vector reinterpret cast operation"]
44711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
44712#[inline]
44713#[cfg(target_endian = "little")]
44714#[target_feature(enable = "neon")]
44715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44717#[cfg_attr(
44718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44719 assert_instr(nop)
44720)]
44721#[cfg_attr(
44722 not(target_arch = "arm"),
44723 stable(feature = "neon_intrinsics", since = "1.59.0")
44724)]
44725#[cfg_attr(
44726 target_arch = "arm",
44727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44728)]
44729pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
44730 unsafe { transmute(a) }
44731}
44732#[doc = "Vector reinterpret cast operation"]
44733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
44734#[inline]
44735#[cfg(target_endian = "big")]
44736#[target_feature(enable = "neon")]
44737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44739#[cfg_attr(
44740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44741 assert_instr(nop)
44742)]
44743#[cfg_attr(
44744 not(target_arch = "arm"),
44745 stable(feature = "neon_intrinsics", since = "1.59.0")
44746)]
44747#[cfg_attr(
44748 target_arch = "arm",
44749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44750)]
44751pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
44752 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44753 unsafe {
44754 let ret_val: uint16x8_t = transmute(a);
44755 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44756 }
44757}
44758#[doc = "Vector reinterpret cast operation"]
44759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
44760#[inline]
44761#[cfg(target_endian = "little")]
44762#[target_feature(enable = "neon")]
44763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44765#[cfg_attr(
44766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44767 assert_instr(nop)
44768)]
44769#[cfg_attr(
44770 not(target_arch = "arm"),
44771 stable(feature = "neon_intrinsics", since = "1.59.0")
44772)]
44773#[cfg_attr(
44774 target_arch = "arm",
44775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44776)]
44777pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
44778 unsafe { transmute(a) }
44779}
44780#[doc = "Vector reinterpret cast operation"]
44781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
44782#[inline]
44783#[cfg(target_endian = "big")]
44784#[target_feature(enable = "neon")]
44785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44787#[cfg_attr(
44788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44789 assert_instr(nop)
44790)]
44791#[cfg_attr(
44792 not(target_arch = "arm"),
44793 stable(feature = "neon_intrinsics", since = "1.59.0")
44794)]
44795#[cfg_attr(
44796 target_arch = "arm",
44797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44798)]
44799pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
44800 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44801 unsafe {
44802 let ret_val: uint32x4_t = transmute(a);
44803 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
44804 }
44805}
44806#[doc = "Vector reinterpret cast operation"]
44807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
44808#[inline]
44809#[cfg(target_endian = "little")]
44810#[target_feature(enable = "neon")]
44811#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44812#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44813#[cfg_attr(
44814 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44815 assert_instr(nop)
44816)]
44817#[cfg_attr(
44818 not(target_arch = "arm"),
44819 stable(feature = "neon_intrinsics", since = "1.59.0")
44820)]
44821#[cfg_attr(
44822 target_arch = "arm",
44823 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44824)]
44825pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
44826 unsafe { transmute(a) }
44827}
44828#[doc = "Vector reinterpret cast operation"]
44829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
44830#[inline]
44831#[cfg(target_endian = "big")]
44832#[target_feature(enable = "neon")]
44833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44835#[cfg_attr(
44836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44837 assert_instr(nop)
44838)]
44839#[cfg_attr(
44840 not(target_arch = "arm"),
44841 stable(feature = "neon_intrinsics", since = "1.59.0")
44842)]
44843#[cfg_attr(
44844 target_arch = "arm",
44845 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44846)]
44847pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
44848 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44849 unsafe {
44850 let ret_val: uint64x2_t = transmute(a);
44851 simd_shuffle!(ret_val, ret_val, [1, 0])
44852 }
44853}
44854#[doc = "Vector reinterpret cast operation"]
44855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
44856#[inline]
44857#[cfg(target_endian = "little")]
44858#[target_feature(enable = "neon")]
44859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44861#[cfg_attr(
44862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44863 assert_instr(nop)
44864)]
44865#[cfg_attr(
44866 not(target_arch = "arm"),
44867 stable(feature = "neon_intrinsics", since = "1.59.0")
44868)]
44869#[cfg_attr(
44870 target_arch = "arm",
44871 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44872)]
44873pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
44874 unsafe { transmute(a) }
44875}
44876#[doc = "Vector reinterpret cast operation"]
44877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
44878#[inline]
44879#[cfg(target_endian = "big")]
44880#[target_feature(enable = "neon")]
44881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44883#[cfg_attr(
44884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44885 assert_instr(nop)
44886)]
44887#[cfg_attr(
44888 not(target_arch = "arm"),
44889 stable(feature = "neon_intrinsics", since = "1.59.0")
44890)]
44891#[cfg_attr(
44892 target_arch = "arm",
44893 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44894)]
44895pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
44896 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44897 unsafe {
44898 let ret_val: poly8x16_t = transmute(a);
44899 simd_shuffle!(
44900 ret_val,
44901 ret_val,
44902 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
44903 )
44904 }
44905}
44906#[doc = "Vector reinterpret cast operation"]
44907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
44908#[inline]
44909#[cfg(target_endian = "little")]
44910#[target_feature(enable = "neon")]
44911#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44912#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44913#[cfg_attr(
44914 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44915 assert_instr(nop)
44916)]
44917#[cfg_attr(
44918 not(target_arch = "arm"),
44919 stable(feature = "neon_intrinsics", since = "1.59.0")
44920)]
44921#[cfg_attr(
44922 target_arch = "arm",
44923 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44924)]
44925pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
44926 unsafe { transmute(a) }
44927}
44928#[doc = "Vector reinterpret cast operation"]
44929#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
44930#[inline]
44931#[cfg(target_endian = "big")]
44932#[target_feature(enable = "neon")]
44933#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44934#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44935#[cfg_attr(
44936 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44937 assert_instr(nop)
44938)]
44939#[cfg_attr(
44940 not(target_arch = "arm"),
44941 stable(feature = "neon_intrinsics", since = "1.59.0")
44942)]
44943#[cfg_attr(
44944 target_arch = "arm",
44945 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44946)]
44947pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
44948 let a: float32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
44949 unsafe {
44950 let ret_val: poly16x8_t = transmute(a);
44951 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
44952 }
44953}
44954#[doc = "Vector reinterpret cast operation"]
44955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
44956#[inline]
44957#[cfg(target_endian = "little")]
44958#[target_feature(enable = "neon")]
44959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44961#[cfg_attr(
44962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44963 assert_instr(nop)
44964)]
44965#[cfg_attr(
44966 not(target_arch = "arm"),
44967 stable(feature = "neon_intrinsics", since = "1.59.0")
44968)]
44969#[cfg_attr(
44970 target_arch = "arm",
44971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44972)]
44973pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
44974 unsafe { transmute(a) }
44975}
44976#[doc = "Vector reinterpret cast operation"]
44977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
44978#[inline]
44979#[cfg(target_endian = "big")]
44980#[target_feature(enable = "neon")]
44981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
44982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
44983#[cfg_attr(
44984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
44985 assert_instr(nop)
44986)]
44987#[cfg_attr(
44988 not(target_arch = "arm"),
44989 stable(feature = "neon_intrinsics", since = "1.59.0")
44990)]
44991#[cfg_attr(
44992 target_arch = "arm",
44993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
44994)]
44995pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
44996 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
44997 unsafe {
44998 let ret_val: float32x2_t = transmute(a);
44999 simd_shuffle!(ret_val, ret_val, [1, 0])
45000 }
45001}
45002#[doc = "Vector reinterpret cast operation"]
45003#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45004#[inline]
45005#[cfg(target_endian = "little")]
45006#[target_feature(enable = "neon")]
45007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45009#[cfg_attr(
45010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45011 assert_instr(nop)
45012)]
45013#[cfg_attr(
45014 not(target_arch = "arm"),
45015 stable(feature = "neon_intrinsics", since = "1.59.0")
45016)]
45017#[cfg_attr(
45018 target_arch = "arm",
45019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45020)]
45021pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45022 unsafe { transmute(a) }
45023}
45024#[doc = "Vector reinterpret cast operation"]
45025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
45026#[inline]
45027#[cfg(target_endian = "big")]
45028#[target_feature(enable = "neon")]
45029#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45030#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45031#[cfg_attr(
45032 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45033 assert_instr(nop)
45034)]
45035#[cfg_attr(
45036 not(target_arch = "arm"),
45037 stable(feature = "neon_intrinsics", since = "1.59.0")
45038)]
45039#[cfg_attr(
45040 target_arch = "arm",
45041 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45042)]
45043pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
45044 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45045 unsafe {
45046 let ret_val: int16x4_t = transmute(a);
45047 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45048 }
45049}
45050#[doc = "Vector reinterpret cast operation"]
45051#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45052#[inline]
45053#[cfg(target_endian = "little")]
45054#[target_feature(enable = "neon")]
45055#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45056#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45057#[cfg_attr(
45058 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45059 assert_instr(nop)
45060)]
45061#[cfg_attr(
45062 not(target_arch = "arm"),
45063 stable(feature = "neon_intrinsics", since = "1.59.0")
45064)]
45065#[cfg_attr(
45066 target_arch = "arm",
45067 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45068)]
45069pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45070 unsafe { transmute(a) }
45071}
45072#[doc = "Vector reinterpret cast operation"]
45073#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
45074#[inline]
45075#[cfg(target_endian = "big")]
45076#[target_feature(enable = "neon")]
45077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45079#[cfg_attr(
45080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45081 assert_instr(nop)
45082)]
45083#[cfg_attr(
45084 not(target_arch = "arm"),
45085 stable(feature = "neon_intrinsics", since = "1.59.0")
45086)]
45087#[cfg_attr(
45088 target_arch = "arm",
45089 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45090)]
45091pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
45092 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45093 unsafe {
45094 let ret_val: int32x2_t = transmute(a);
45095 simd_shuffle!(ret_val, ret_val, [1, 0])
45096 }
45097}
45098#[doc = "Vector reinterpret cast operation"]
45099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45100#[inline]
45101#[cfg(target_endian = "little")]
45102#[target_feature(enable = "neon")]
45103#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45104#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45105#[cfg_attr(
45106 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45107 assert_instr(nop)
45108)]
45109#[cfg_attr(
45110 not(target_arch = "arm"),
45111 stable(feature = "neon_intrinsics", since = "1.59.0")
45112)]
45113#[cfg_attr(
45114 target_arch = "arm",
45115 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45116)]
45117pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45118 unsafe { transmute(a) }
45119}
45120#[doc = "Vector reinterpret cast operation"]
45121#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
45122#[inline]
45123#[cfg(target_endian = "big")]
45124#[target_feature(enable = "neon")]
45125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45127#[cfg_attr(
45128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45129 assert_instr(nop)
45130)]
45131#[cfg_attr(
45132 not(target_arch = "arm"),
45133 stable(feature = "neon_intrinsics", since = "1.59.0")
45134)]
45135#[cfg_attr(
45136 target_arch = "arm",
45137 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45138)]
45139pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
45140 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45141 unsafe { transmute(a) }
45142}
45143#[doc = "Vector reinterpret cast operation"]
45144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45145#[inline]
45146#[cfg(target_endian = "little")]
45147#[target_feature(enable = "neon")]
45148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45149#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45150#[cfg_attr(
45151 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45152 assert_instr(nop)
45153)]
45154#[cfg_attr(
45155 not(target_arch = "arm"),
45156 stable(feature = "neon_intrinsics", since = "1.59.0")
45157)]
45158#[cfg_attr(
45159 target_arch = "arm",
45160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45161)]
45162pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45163 unsafe { transmute(a) }
45164}
45165#[doc = "Vector reinterpret cast operation"]
45166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
45167#[inline]
45168#[cfg(target_endian = "big")]
45169#[target_feature(enable = "neon")]
45170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45172#[cfg_attr(
45173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45174 assert_instr(nop)
45175)]
45176#[cfg_attr(
45177 not(target_arch = "arm"),
45178 stable(feature = "neon_intrinsics", since = "1.59.0")
45179)]
45180#[cfg_attr(
45181 target_arch = "arm",
45182 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45183)]
45184pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
45185 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45186 unsafe {
45187 let ret_val: uint8x8_t = transmute(a);
45188 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45189 }
45190}
45191#[doc = "Vector reinterpret cast operation"]
45192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45193#[inline]
45194#[cfg(target_endian = "little")]
45195#[target_feature(enable = "neon")]
45196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45197#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45198#[cfg_attr(
45199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45200 assert_instr(nop)
45201)]
45202#[cfg_attr(
45203 not(target_arch = "arm"),
45204 stable(feature = "neon_intrinsics", since = "1.59.0")
45205)]
45206#[cfg_attr(
45207 target_arch = "arm",
45208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45209)]
45210pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45211 unsafe { transmute(a) }
45212}
45213#[doc = "Vector reinterpret cast operation"]
45214#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
45215#[inline]
45216#[cfg(target_endian = "big")]
45217#[target_feature(enable = "neon")]
45218#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45219#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45220#[cfg_attr(
45221 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45222 assert_instr(nop)
45223)]
45224#[cfg_attr(
45225 not(target_arch = "arm"),
45226 stable(feature = "neon_intrinsics", since = "1.59.0")
45227)]
45228#[cfg_attr(
45229 target_arch = "arm",
45230 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45231)]
45232pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
45233 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45234 unsafe {
45235 let ret_val: uint16x4_t = transmute(a);
45236 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45237 }
45238}
45239#[doc = "Vector reinterpret cast operation"]
45240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45241#[inline]
45242#[cfg(target_endian = "little")]
45243#[target_feature(enable = "neon")]
45244#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45245#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45246#[cfg_attr(
45247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45248 assert_instr(nop)
45249)]
45250#[cfg_attr(
45251 not(target_arch = "arm"),
45252 stable(feature = "neon_intrinsics", since = "1.59.0")
45253)]
45254#[cfg_attr(
45255 target_arch = "arm",
45256 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45257)]
45258pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45259 unsafe { transmute(a) }
45260}
45261#[doc = "Vector reinterpret cast operation"]
45262#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
45263#[inline]
45264#[cfg(target_endian = "big")]
45265#[target_feature(enable = "neon")]
45266#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45267#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45268#[cfg_attr(
45269 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45270 assert_instr(nop)
45271)]
45272#[cfg_attr(
45273 not(target_arch = "arm"),
45274 stable(feature = "neon_intrinsics", since = "1.59.0")
45275)]
45276#[cfg_attr(
45277 target_arch = "arm",
45278 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45279)]
45280pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
45281 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45282 unsafe {
45283 let ret_val: uint32x2_t = transmute(a);
45284 simd_shuffle!(ret_val, ret_val, [1, 0])
45285 }
45286}
45287#[doc = "Vector reinterpret cast operation"]
45288#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45289#[inline]
45290#[cfg(target_endian = "little")]
45291#[target_feature(enable = "neon")]
45292#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45293#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45294#[cfg_attr(
45295 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45296 assert_instr(nop)
45297)]
45298#[cfg_attr(
45299 not(target_arch = "arm"),
45300 stable(feature = "neon_intrinsics", since = "1.59.0")
45301)]
45302#[cfg_attr(
45303 target_arch = "arm",
45304 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45305)]
45306pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45307 unsafe { transmute(a) }
45308}
45309#[doc = "Vector reinterpret cast operation"]
45310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
45311#[inline]
45312#[cfg(target_endian = "big")]
45313#[target_feature(enable = "neon")]
45314#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45315#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45316#[cfg_attr(
45317 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45318 assert_instr(nop)
45319)]
45320#[cfg_attr(
45321 not(target_arch = "arm"),
45322 stable(feature = "neon_intrinsics", since = "1.59.0")
45323)]
45324#[cfg_attr(
45325 target_arch = "arm",
45326 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45327)]
45328pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
45329 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45330 unsafe { transmute(a) }
45331}
45332#[doc = "Vector reinterpret cast operation"]
45333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45334#[inline]
45335#[cfg(target_endian = "little")]
45336#[target_feature(enable = "neon")]
45337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45338#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45339#[cfg_attr(
45340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45341 assert_instr(nop)
45342)]
45343#[cfg_attr(
45344 not(target_arch = "arm"),
45345 stable(feature = "neon_intrinsics", since = "1.59.0")
45346)]
45347#[cfg_attr(
45348 target_arch = "arm",
45349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45350)]
45351pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45352 unsafe { transmute(a) }
45353}
45354#[doc = "Vector reinterpret cast operation"]
45355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
45356#[inline]
45357#[cfg(target_endian = "big")]
45358#[target_feature(enable = "neon")]
45359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45361#[cfg_attr(
45362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45363 assert_instr(nop)
45364)]
45365#[cfg_attr(
45366 not(target_arch = "arm"),
45367 stable(feature = "neon_intrinsics", since = "1.59.0")
45368)]
45369#[cfg_attr(
45370 target_arch = "arm",
45371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45372)]
45373pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
45374 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45375 unsafe {
45376 let ret_val: poly8x8_t = transmute(a);
45377 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45378 }
45379}
45380#[doc = "Vector reinterpret cast operation"]
45381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45382#[inline]
45383#[cfg(target_endian = "little")]
45384#[target_feature(enable = "neon")]
45385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45387#[cfg_attr(
45388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45389 assert_instr(nop)
45390)]
45391#[cfg_attr(
45392 not(target_arch = "arm"),
45393 stable(feature = "neon_intrinsics", since = "1.59.0")
45394)]
45395#[cfg_attr(
45396 target_arch = "arm",
45397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45398)]
45399pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45400 unsafe { transmute(a) }
45401}
45402#[doc = "Vector reinterpret cast operation"]
45403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
45404#[inline]
45405#[cfg(target_endian = "big")]
45406#[target_feature(enable = "neon")]
45407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45409#[cfg_attr(
45410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45411 assert_instr(nop)
45412)]
45413#[cfg_attr(
45414 not(target_arch = "arm"),
45415 stable(feature = "neon_intrinsics", since = "1.59.0")
45416)]
45417#[cfg_attr(
45418 target_arch = "arm",
45419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45420)]
45421pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
45422 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
45423 unsafe {
45424 let ret_val: poly16x4_t = transmute(a);
45425 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45426 }
45427}
45428#[doc = "Vector reinterpret cast operation"]
45429#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45430#[inline]
45431#[cfg(target_endian = "little")]
45432#[target_feature(enable = "neon")]
45433#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45434#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45435#[cfg_attr(
45436 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45437 assert_instr(nop)
45438)]
45439#[cfg_attr(
45440 not(target_arch = "arm"),
45441 stable(feature = "neon_intrinsics", since = "1.59.0")
45442)]
45443#[cfg_attr(
45444 target_arch = "arm",
45445 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45446)]
45447pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45448 unsafe { transmute(a) }
45449}
45450#[doc = "Vector reinterpret cast operation"]
45451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
45452#[inline]
45453#[cfg(target_endian = "big")]
45454#[target_feature(enable = "neon")]
45455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45457#[cfg_attr(
45458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45459 assert_instr(nop)
45460)]
45461#[cfg_attr(
45462 not(target_arch = "arm"),
45463 stable(feature = "neon_intrinsics", since = "1.59.0")
45464)]
45465#[cfg_attr(
45466 target_arch = "arm",
45467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45468)]
45469pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
45470 let a: int8x16_t =
45471 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45472 unsafe {
45473 let ret_val: float32x4_t = transmute(a);
45474 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45475 }
45476}
45477#[doc = "Vector reinterpret cast operation"]
45478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45479#[inline]
45480#[cfg(target_endian = "little")]
45481#[target_feature(enable = "neon")]
45482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45483#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45484#[cfg_attr(
45485 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45486 assert_instr(nop)
45487)]
45488#[cfg_attr(
45489 not(target_arch = "arm"),
45490 stable(feature = "neon_intrinsics", since = "1.59.0")
45491)]
45492#[cfg_attr(
45493 target_arch = "arm",
45494 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45495)]
45496pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45497 unsafe { transmute(a) }
45498}
45499#[doc = "Vector reinterpret cast operation"]
45500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
45501#[inline]
45502#[cfg(target_endian = "big")]
45503#[target_feature(enable = "neon")]
45504#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45505#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45506#[cfg_attr(
45507 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45508 assert_instr(nop)
45509)]
45510#[cfg_attr(
45511 not(target_arch = "arm"),
45512 stable(feature = "neon_intrinsics", since = "1.59.0")
45513)]
45514#[cfg_attr(
45515 target_arch = "arm",
45516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45517)]
45518pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
45519 let a: int8x16_t =
45520 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45521 unsafe {
45522 let ret_val: int16x8_t = transmute(a);
45523 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45524 }
45525}
45526#[doc = "Vector reinterpret cast operation"]
45527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45528#[inline]
45529#[cfg(target_endian = "little")]
45530#[target_feature(enable = "neon")]
45531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45533#[cfg_attr(
45534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45535 assert_instr(nop)
45536)]
45537#[cfg_attr(
45538 not(target_arch = "arm"),
45539 stable(feature = "neon_intrinsics", since = "1.59.0")
45540)]
45541#[cfg_attr(
45542 target_arch = "arm",
45543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45544)]
45545pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45546 unsafe { transmute(a) }
45547}
45548#[doc = "Vector reinterpret cast operation"]
45549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
45550#[inline]
45551#[cfg(target_endian = "big")]
45552#[target_feature(enable = "neon")]
45553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45555#[cfg_attr(
45556 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45557 assert_instr(nop)
45558)]
45559#[cfg_attr(
45560 not(target_arch = "arm"),
45561 stable(feature = "neon_intrinsics", since = "1.59.0")
45562)]
45563#[cfg_attr(
45564 target_arch = "arm",
45565 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45566)]
45567pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
45568 let a: int8x16_t =
45569 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45570 unsafe {
45571 let ret_val: int32x4_t = transmute(a);
45572 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45573 }
45574}
45575#[doc = "Vector reinterpret cast operation"]
45576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
45577#[inline]
45578#[cfg(target_endian = "little")]
45579#[target_feature(enable = "neon")]
45580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45582#[cfg_attr(
45583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45584 assert_instr(nop)
45585)]
45586#[cfg_attr(
45587 not(target_arch = "arm"),
45588 stable(feature = "neon_intrinsics", since = "1.59.0")
45589)]
45590#[cfg_attr(
45591 target_arch = "arm",
45592 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45593)]
45594pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
45595 unsafe { transmute(a) }
45596}
45597#[doc = "Vector reinterpret cast operation"]
45598#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
45599#[inline]
45600#[cfg(target_endian = "big")]
45601#[target_feature(enable = "neon")]
45602#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45603#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45604#[cfg_attr(
45605 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45606 assert_instr(nop)
45607)]
45608#[cfg_attr(
45609 not(target_arch = "arm"),
45610 stable(feature = "neon_intrinsics", since = "1.59.0")
45611)]
45612#[cfg_attr(
45613 target_arch = "arm",
45614 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45615)]
45616pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
45617 let a: int8x16_t =
45618 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45619 unsafe {
45620 let ret_val: int64x2_t = transmute(a);
45621 simd_shuffle!(ret_val, ret_val, [1, 0])
45622 }
45623}
45624#[doc = "Vector reinterpret cast operation"]
45625#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
45626#[inline]
45627#[cfg(target_endian = "little")]
45628#[target_feature(enable = "neon")]
45629#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45630#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45631#[cfg_attr(
45632 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45633 assert_instr(nop)
45634)]
45635#[cfg_attr(
45636 not(target_arch = "arm"),
45637 stable(feature = "neon_intrinsics", since = "1.59.0")
45638)]
45639#[cfg_attr(
45640 target_arch = "arm",
45641 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45642)]
45643pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
45644 unsafe { transmute(a) }
45645}
45646#[doc = "Vector reinterpret cast operation"]
45647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
45648#[inline]
45649#[cfg(target_endian = "big")]
45650#[target_feature(enable = "neon")]
45651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45653#[cfg_attr(
45654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45655 assert_instr(nop)
45656)]
45657#[cfg_attr(
45658 not(target_arch = "arm"),
45659 stable(feature = "neon_intrinsics", since = "1.59.0")
45660)]
45661#[cfg_attr(
45662 target_arch = "arm",
45663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45664)]
45665pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
45666 let a: int8x16_t =
45667 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45668 unsafe {
45669 let ret_val: uint8x16_t = transmute(a);
45670 simd_shuffle!(
45671 ret_val,
45672 ret_val,
45673 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45674 )
45675 }
45676}
45677#[doc = "Vector reinterpret cast operation"]
45678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
45679#[inline]
45680#[cfg(target_endian = "little")]
45681#[target_feature(enable = "neon")]
45682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45684#[cfg_attr(
45685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45686 assert_instr(nop)
45687)]
45688#[cfg_attr(
45689 not(target_arch = "arm"),
45690 stable(feature = "neon_intrinsics", since = "1.59.0")
45691)]
45692#[cfg_attr(
45693 target_arch = "arm",
45694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45695)]
45696pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
45697 unsafe { transmute(a) }
45698}
45699#[doc = "Vector reinterpret cast operation"]
45700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
45701#[inline]
45702#[cfg(target_endian = "big")]
45703#[target_feature(enable = "neon")]
45704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45706#[cfg_attr(
45707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45708 assert_instr(nop)
45709)]
45710#[cfg_attr(
45711 not(target_arch = "arm"),
45712 stable(feature = "neon_intrinsics", since = "1.59.0")
45713)]
45714#[cfg_attr(
45715 target_arch = "arm",
45716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45717)]
45718pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
45719 let a: int8x16_t =
45720 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45721 unsafe {
45722 let ret_val: uint16x8_t = transmute(a);
45723 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45724 }
45725}
45726#[doc = "Vector reinterpret cast operation"]
45727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
45728#[inline]
45729#[cfg(target_endian = "little")]
45730#[target_feature(enable = "neon")]
45731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45733#[cfg_attr(
45734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45735 assert_instr(nop)
45736)]
45737#[cfg_attr(
45738 not(target_arch = "arm"),
45739 stable(feature = "neon_intrinsics", since = "1.59.0")
45740)]
45741#[cfg_attr(
45742 target_arch = "arm",
45743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45744)]
45745pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
45746 unsafe { transmute(a) }
45747}
45748#[doc = "Vector reinterpret cast operation"]
45749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
45750#[inline]
45751#[cfg(target_endian = "big")]
45752#[target_feature(enable = "neon")]
45753#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45754#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45755#[cfg_attr(
45756 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45757 assert_instr(nop)
45758)]
45759#[cfg_attr(
45760 not(target_arch = "arm"),
45761 stable(feature = "neon_intrinsics", since = "1.59.0")
45762)]
45763#[cfg_attr(
45764 target_arch = "arm",
45765 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45766)]
45767pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
45768 let a: int8x16_t =
45769 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45770 unsafe {
45771 let ret_val: uint32x4_t = transmute(a);
45772 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
45773 }
45774}
45775#[doc = "Vector reinterpret cast operation"]
45776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
45777#[inline]
45778#[cfg(target_endian = "little")]
45779#[target_feature(enable = "neon")]
45780#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45781#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45782#[cfg_attr(
45783 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45784 assert_instr(nop)
45785)]
45786#[cfg_attr(
45787 not(target_arch = "arm"),
45788 stable(feature = "neon_intrinsics", since = "1.59.0")
45789)]
45790#[cfg_attr(
45791 target_arch = "arm",
45792 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45793)]
45794pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
45795 unsafe { transmute(a) }
45796}
45797#[doc = "Vector reinterpret cast operation"]
45798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
45799#[inline]
45800#[cfg(target_endian = "big")]
45801#[target_feature(enable = "neon")]
45802#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45803#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45804#[cfg_attr(
45805 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45806 assert_instr(nop)
45807)]
45808#[cfg_attr(
45809 not(target_arch = "arm"),
45810 stable(feature = "neon_intrinsics", since = "1.59.0")
45811)]
45812#[cfg_attr(
45813 target_arch = "arm",
45814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45815)]
45816pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
45817 let a: int8x16_t =
45818 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45819 unsafe {
45820 let ret_val: uint64x2_t = transmute(a);
45821 simd_shuffle!(ret_val, ret_val, [1, 0])
45822 }
45823}
45824#[doc = "Vector reinterpret cast operation"]
45825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
45826#[inline]
45827#[cfg(target_endian = "little")]
45828#[target_feature(enable = "neon")]
45829#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45830#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45831#[cfg_attr(
45832 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45833 assert_instr(nop)
45834)]
45835#[cfg_attr(
45836 not(target_arch = "arm"),
45837 stable(feature = "neon_intrinsics", since = "1.59.0")
45838)]
45839#[cfg_attr(
45840 target_arch = "arm",
45841 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45842)]
45843pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
45844 unsafe { transmute(a) }
45845}
45846#[doc = "Vector reinterpret cast operation"]
45847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
45848#[inline]
45849#[cfg(target_endian = "big")]
45850#[target_feature(enable = "neon")]
45851#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45852#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45853#[cfg_attr(
45854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45855 assert_instr(nop)
45856)]
45857#[cfg_attr(
45858 not(target_arch = "arm"),
45859 stable(feature = "neon_intrinsics", since = "1.59.0")
45860)]
45861#[cfg_attr(
45862 target_arch = "arm",
45863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45864)]
45865pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
45866 let a: int8x16_t =
45867 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45868 unsafe {
45869 let ret_val: poly8x16_t = transmute(a);
45870 simd_shuffle!(
45871 ret_val,
45872 ret_val,
45873 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
45874 )
45875 }
45876}
45877#[doc = "Vector reinterpret cast operation"]
45878#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
45879#[inline]
45880#[cfg(target_endian = "little")]
45881#[target_feature(enable = "neon")]
45882#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45883#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45884#[cfg_attr(
45885 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45886 assert_instr(nop)
45887)]
45888#[cfg_attr(
45889 not(target_arch = "arm"),
45890 stable(feature = "neon_intrinsics", since = "1.59.0")
45891)]
45892#[cfg_attr(
45893 target_arch = "arm",
45894 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45895)]
45896pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
45897 unsafe { transmute(a) }
45898}
45899#[doc = "Vector reinterpret cast operation"]
45900#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
45901#[inline]
45902#[cfg(target_endian = "big")]
45903#[target_feature(enable = "neon")]
45904#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45905#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45906#[cfg_attr(
45907 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45908 assert_instr(nop)
45909)]
45910#[cfg_attr(
45911 not(target_arch = "arm"),
45912 stable(feature = "neon_intrinsics", since = "1.59.0")
45913)]
45914#[cfg_attr(
45915 target_arch = "arm",
45916 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45917)]
45918pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
45919 let a: int8x16_t =
45920 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
45921 unsafe {
45922 let ret_val: poly16x8_t = transmute(a);
45923 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
45924 }
45925}
45926#[doc = "Vector reinterpret cast operation"]
45927#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
45928#[inline]
45929#[cfg(target_endian = "little")]
45930#[target_feature(enable = "neon")]
45931#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45932#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45933#[cfg_attr(
45934 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45935 assert_instr(nop)
45936)]
45937#[cfg_attr(
45938 not(target_arch = "arm"),
45939 stable(feature = "neon_intrinsics", since = "1.59.0")
45940)]
45941#[cfg_attr(
45942 target_arch = "arm",
45943 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45944)]
45945pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
45946 unsafe { transmute(a) }
45947}
45948#[doc = "Vector reinterpret cast operation"]
45949#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
45950#[inline]
45951#[cfg(target_endian = "big")]
45952#[target_feature(enable = "neon")]
45953#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45954#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45955#[cfg_attr(
45956 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45957 assert_instr(nop)
45958)]
45959#[cfg_attr(
45960 not(target_arch = "arm"),
45961 stable(feature = "neon_intrinsics", since = "1.59.0")
45962)]
45963#[cfg_attr(
45964 target_arch = "arm",
45965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45966)]
45967pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
45968 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
45969 unsafe {
45970 let ret_val: float32x2_t = transmute(a);
45971 simd_shuffle!(ret_val, ret_val, [1, 0])
45972 }
45973}
45974#[doc = "Vector reinterpret cast operation"]
45975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
45976#[inline]
45977#[cfg(target_endian = "little")]
45978#[target_feature(enable = "neon")]
45979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
45980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
45981#[cfg_attr(
45982 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
45983 assert_instr(nop)
45984)]
45985#[cfg_attr(
45986 not(target_arch = "arm"),
45987 stable(feature = "neon_intrinsics", since = "1.59.0")
45988)]
45989#[cfg_attr(
45990 target_arch = "arm",
45991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
45992)]
45993pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
45994 unsafe { transmute(a) }
45995}
45996#[doc = "Vector reinterpret cast operation"]
45997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
45998#[inline]
45999#[cfg(target_endian = "big")]
46000#[target_feature(enable = "neon")]
46001#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46002#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46003#[cfg_attr(
46004 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46005 assert_instr(nop)
46006)]
46007#[cfg_attr(
46008 not(target_arch = "arm"),
46009 stable(feature = "neon_intrinsics", since = "1.59.0")
46010)]
46011#[cfg_attr(
46012 target_arch = "arm",
46013 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46014)]
46015pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
46016 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46017 unsafe {
46018 let ret_val: int8x8_t = transmute(a);
46019 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46020 }
46021}
46022#[doc = "Vector reinterpret cast operation"]
46023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46024#[inline]
46025#[cfg(target_endian = "little")]
46026#[target_feature(enable = "neon")]
46027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46029#[cfg_attr(
46030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46031 assert_instr(nop)
46032)]
46033#[cfg_attr(
46034 not(target_arch = "arm"),
46035 stable(feature = "neon_intrinsics", since = "1.59.0")
46036)]
46037#[cfg_attr(
46038 target_arch = "arm",
46039 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46040)]
46041pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46042 unsafe { transmute(a) }
46043}
46044#[doc = "Vector reinterpret cast operation"]
46045#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
46046#[inline]
46047#[cfg(target_endian = "big")]
46048#[target_feature(enable = "neon")]
46049#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46050#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46051#[cfg_attr(
46052 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46053 assert_instr(nop)
46054)]
46055#[cfg_attr(
46056 not(target_arch = "arm"),
46057 stable(feature = "neon_intrinsics", since = "1.59.0")
46058)]
46059#[cfg_attr(
46060 target_arch = "arm",
46061 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46062)]
46063pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
46064 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46065 unsafe {
46066 let ret_val: int32x2_t = transmute(a);
46067 simd_shuffle!(ret_val, ret_val, [1, 0])
46068 }
46069}
46070#[doc = "Vector reinterpret cast operation"]
46071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46072#[inline]
46073#[cfg(target_endian = "little")]
46074#[target_feature(enable = "neon")]
46075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46077#[cfg_attr(
46078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46079 assert_instr(nop)
46080)]
46081#[cfg_attr(
46082 not(target_arch = "arm"),
46083 stable(feature = "neon_intrinsics", since = "1.59.0")
46084)]
46085#[cfg_attr(
46086 target_arch = "arm",
46087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46088)]
46089pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46090 unsafe { transmute(a) }
46091}
46092#[doc = "Vector reinterpret cast operation"]
46093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
46094#[inline]
46095#[cfg(target_endian = "big")]
46096#[target_feature(enable = "neon")]
46097#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46099#[cfg_attr(
46100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46101 assert_instr(nop)
46102)]
46103#[cfg_attr(
46104 not(target_arch = "arm"),
46105 stable(feature = "neon_intrinsics", since = "1.59.0")
46106)]
46107#[cfg_attr(
46108 target_arch = "arm",
46109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46110)]
46111pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
46112 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46113 unsafe { transmute(a) }
46114}
46115#[doc = "Vector reinterpret cast operation"]
46116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46117#[inline]
46118#[cfg(target_endian = "little")]
46119#[target_feature(enable = "neon")]
46120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46122#[cfg_attr(
46123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46124 assert_instr(nop)
46125)]
46126#[cfg_attr(
46127 not(target_arch = "arm"),
46128 stable(feature = "neon_intrinsics", since = "1.59.0")
46129)]
46130#[cfg_attr(
46131 target_arch = "arm",
46132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46133)]
46134pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46135 unsafe { transmute(a) }
46136}
46137#[doc = "Vector reinterpret cast operation"]
46138#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
46139#[inline]
46140#[cfg(target_endian = "big")]
46141#[target_feature(enable = "neon")]
46142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46144#[cfg_attr(
46145 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46146 assert_instr(nop)
46147)]
46148#[cfg_attr(
46149 not(target_arch = "arm"),
46150 stable(feature = "neon_intrinsics", since = "1.59.0")
46151)]
46152#[cfg_attr(
46153 target_arch = "arm",
46154 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46155)]
46156pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
46157 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46158 unsafe {
46159 let ret_val: uint8x8_t = transmute(a);
46160 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46161 }
46162}
46163#[doc = "Vector reinterpret cast operation"]
46164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46165#[inline]
46166#[cfg(target_endian = "little")]
46167#[target_feature(enable = "neon")]
46168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46170#[cfg_attr(
46171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46172 assert_instr(nop)
46173)]
46174#[cfg_attr(
46175 not(target_arch = "arm"),
46176 stable(feature = "neon_intrinsics", since = "1.59.0")
46177)]
46178#[cfg_attr(
46179 target_arch = "arm",
46180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46181)]
46182pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46183 unsafe { transmute(a) }
46184}
46185#[doc = "Vector reinterpret cast operation"]
46186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
46187#[inline]
46188#[cfg(target_endian = "big")]
46189#[target_feature(enable = "neon")]
46190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46192#[cfg_attr(
46193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46194 assert_instr(nop)
46195)]
46196#[cfg_attr(
46197 not(target_arch = "arm"),
46198 stable(feature = "neon_intrinsics", since = "1.59.0")
46199)]
46200#[cfg_attr(
46201 target_arch = "arm",
46202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46203)]
46204pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
46205 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46206 unsafe {
46207 let ret_val: uint16x4_t = transmute(a);
46208 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46209 }
46210}
46211#[doc = "Vector reinterpret cast operation"]
46212#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46213#[inline]
46214#[cfg(target_endian = "little")]
46215#[target_feature(enable = "neon")]
46216#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46217#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46218#[cfg_attr(
46219 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46220 assert_instr(nop)
46221)]
46222#[cfg_attr(
46223 not(target_arch = "arm"),
46224 stable(feature = "neon_intrinsics", since = "1.59.0")
46225)]
46226#[cfg_attr(
46227 target_arch = "arm",
46228 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46229)]
46230pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46231 unsafe { transmute(a) }
46232}
46233#[doc = "Vector reinterpret cast operation"]
46234#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
46235#[inline]
46236#[cfg(target_endian = "big")]
46237#[target_feature(enable = "neon")]
46238#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46239#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46240#[cfg_attr(
46241 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46242 assert_instr(nop)
46243)]
46244#[cfg_attr(
46245 not(target_arch = "arm"),
46246 stable(feature = "neon_intrinsics", since = "1.59.0")
46247)]
46248#[cfg_attr(
46249 target_arch = "arm",
46250 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46251)]
46252pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
46253 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46254 unsafe {
46255 let ret_val: uint32x2_t = transmute(a);
46256 simd_shuffle!(ret_val, ret_val, [1, 0])
46257 }
46258}
46259#[doc = "Vector reinterpret cast operation"]
46260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46261#[inline]
46262#[cfg(target_endian = "little")]
46263#[target_feature(enable = "neon")]
46264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46266#[cfg_attr(
46267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46268 assert_instr(nop)
46269)]
46270#[cfg_attr(
46271 not(target_arch = "arm"),
46272 stable(feature = "neon_intrinsics", since = "1.59.0")
46273)]
46274#[cfg_attr(
46275 target_arch = "arm",
46276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46277)]
46278pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46279 unsafe { transmute(a) }
46280}
46281#[doc = "Vector reinterpret cast operation"]
46282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
46283#[inline]
46284#[cfg(target_endian = "big")]
46285#[target_feature(enable = "neon")]
46286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46288#[cfg_attr(
46289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46290 assert_instr(nop)
46291)]
46292#[cfg_attr(
46293 not(target_arch = "arm"),
46294 stable(feature = "neon_intrinsics", since = "1.59.0")
46295)]
46296#[cfg_attr(
46297 target_arch = "arm",
46298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46299)]
46300pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
46301 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46302 unsafe { transmute(a) }
46303}
46304#[doc = "Vector reinterpret cast operation"]
46305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46306#[inline]
46307#[cfg(target_endian = "little")]
46308#[target_feature(enable = "neon")]
46309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46310#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46311#[cfg_attr(
46312 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46313 assert_instr(nop)
46314)]
46315#[cfg_attr(
46316 not(target_arch = "arm"),
46317 stable(feature = "neon_intrinsics", since = "1.59.0")
46318)]
46319#[cfg_attr(
46320 target_arch = "arm",
46321 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46322)]
46323pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46324 unsafe { transmute(a) }
46325}
46326#[doc = "Vector reinterpret cast operation"]
46327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
46328#[inline]
46329#[cfg(target_endian = "big")]
46330#[target_feature(enable = "neon")]
46331#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46332#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46333#[cfg_attr(
46334 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46335 assert_instr(nop)
46336)]
46337#[cfg_attr(
46338 not(target_arch = "arm"),
46339 stable(feature = "neon_intrinsics", since = "1.59.0")
46340)]
46341#[cfg_attr(
46342 target_arch = "arm",
46343 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46344)]
46345pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
46346 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46347 unsafe {
46348 let ret_val: poly8x8_t = transmute(a);
46349 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46350 }
46351}
46352#[doc = "Vector reinterpret cast operation"]
46353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46354#[inline]
46355#[cfg(target_endian = "little")]
46356#[target_feature(enable = "neon")]
46357#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46358#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46359#[cfg_attr(
46360 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46361 assert_instr(nop)
46362)]
46363#[cfg_attr(
46364 not(target_arch = "arm"),
46365 stable(feature = "neon_intrinsics", since = "1.59.0")
46366)]
46367#[cfg_attr(
46368 target_arch = "arm",
46369 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46370)]
46371pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46372 unsafe { transmute(a) }
46373}
46374#[doc = "Vector reinterpret cast operation"]
46375#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
46376#[inline]
46377#[cfg(target_endian = "big")]
46378#[target_feature(enable = "neon")]
46379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46380#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46381#[cfg_attr(
46382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46383 assert_instr(nop)
46384)]
46385#[cfg_attr(
46386 not(target_arch = "arm"),
46387 stable(feature = "neon_intrinsics", since = "1.59.0")
46388)]
46389#[cfg_attr(
46390 target_arch = "arm",
46391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46392)]
46393pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
46394 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
46395 unsafe {
46396 let ret_val: poly16x4_t = transmute(a);
46397 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46398 }
46399}
46400#[doc = "Vector reinterpret cast operation"]
46401#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46402#[inline]
46403#[cfg(target_endian = "little")]
46404#[target_feature(enable = "neon")]
46405#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46406#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46407#[cfg_attr(
46408 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46409 assert_instr(nop)
46410)]
46411#[cfg_attr(
46412 not(target_arch = "arm"),
46413 stable(feature = "neon_intrinsics", since = "1.59.0")
46414)]
46415#[cfg_attr(
46416 target_arch = "arm",
46417 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46418)]
46419pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46420 unsafe { transmute(a) }
46421}
46422#[doc = "Vector reinterpret cast operation"]
46423#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
46424#[inline]
46425#[cfg(target_endian = "big")]
46426#[target_feature(enable = "neon")]
46427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46428#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46429#[cfg_attr(
46430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46431 assert_instr(nop)
46432)]
46433#[cfg_attr(
46434 not(target_arch = "arm"),
46435 stable(feature = "neon_intrinsics", since = "1.59.0")
46436)]
46437#[cfg_attr(
46438 target_arch = "arm",
46439 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46440)]
46441pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
46442 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46443 unsafe {
46444 let ret_val: float32x4_t = transmute(a);
46445 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46446 }
46447}
46448#[doc = "Vector reinterpret cast operation"]
46449#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46450#[inline]
46451#[cfg(target_endian = "little")]
46452#[target_feature(enable = "neon")]
46453#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46454#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46455#[cfg_attr(
46456 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46457 assert_instr(nop)
46458)]
46459#[cfg_attr(
46460 not(target_arch = "arm"),
46461 stable(feature = "neon_intrinsics", since = "1.59.0")
46462)]
46463#[cfg_attr(
46464 target_arch = "arm",
46465 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46466)]
46467pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46468 unsafe { transmute(a) }
46469}
46470#[doc = "Vector reinterpret cast operation"]
46471#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
46472#[inline]
46473#[cfg(target_endian = "big")]
46474#[target_feature(enable = "neon")]
46475#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46476#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46477#[cfg_attr(
46478 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46479 assert_instr(nop)
46480)]
46481#[cfg_attr(
46482 not(target_arch = "arm"),
46483 stable(feature = "neon_intrinsics", since = "1.59.0")
46484)]
46485#[cfg_attr(
46486 target_arch = "arm",
46487 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46488)]
46489pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
46490 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46491 unsafe {
46492 let ret_val: int8x16_t = transmute(a);
46493 simd_shuffle!(
46494 ret_val,
46495 ret_val,
46496 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46497 )
46498 }
46499}
46500#[doc = "Vector reinterpret cast operation"]
46501#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46502#[inline]
46503#[cfg(target_endian = "little")]
46504#[target_feature(enable = "neon")]
46505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46507#[cfg_attr(
46508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46509 assert_instr(nop)
46510)]
46511#[cfg_attr(
46512 not(target_arch = "arm"),
46513 stable(feature = "neon_intrinsics", since = "1.59.0")
46514)]
46515#[cfg_attr(
46516 target_arch = "arm",
46517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46518)]
46519pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46520 unsafe { transmute(a) }
46521}
46522#[doc = "Vector reinterpret cast operation"]
46523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
46524#[inline]
46525#[cfg(target_endian = "big")]
46526#[target_feature(enable = "neon")]
46527#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46528#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46529#[cfg_attr(
46530 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46531 assert_instr(nop)
46532)]
46533#[cfg_attr(
46534 not(target_arch = "arm"),
46535 stable(feature = "neon_intrinsics", since = "1.59.0")
46536)]
46537#[cfg_attr(
46538 target_arch = "arm",
46539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46540)]
46541pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
46542 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46543 unsafe {
46544 let ret_val: int32x4_t = transmute(a);
46545 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46546 }
46547}
46548#[doc = "Vector reinterpret cast operation"]
46549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
46550#[inline]
46551#[cfg(target_endian = "little")]
46552#[target_feature(enable = "neon")]
46553#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46554#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46555#[cfg_attr(
46556 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46557 assert_instr(nop)
46558)]
46559#[cfg_attr(
46560 not(target_arch = "arm"),
46561 stable(feature = "neon_intrinsics", since = "1.59.0")
46562)]
46563#[cfg_attr(
46564 target_arch = "arm",
46565 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46566)]
46567pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
46568 unsafe { transmute(a) }
46569}
46570#[doc = "Vector reinterpret cast operation"]
46571#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
46572#[inline]
46573#[cfg(target_endian = "big")]
46574#[target_feature(enable = "neon")]
46575#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46576#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46577#[cfg_attr(
46578 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46579 assert_instr(nop)
46580)]
46581#[cfg_attr(
46582 not(target_arch = "arm"),
46583 stable(feature = "neon_intrinsics", since = "1.59.0")
46584)]
46585#[cfg_attr(
46586 target_arch = "arm",
46587 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46588)]
46589pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
46590 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46591 unsafe {
46592 let ret_val: int64x2_t = transmute(a);
46593 simd_shuffle!(ret_val, ret_val, [1, 0])
46594 }
46595}
46596#[doc = "Vector reinterpret cast operation"]
46597#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
46598#[inline]
46599#[cfg(target_endian = "little")]
46600#[target_feature(enable = "neon")]
46601#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46602#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46603#[cfg_attr(
46604 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46605 assert_instr(nop)
46606)]
46607#[cfg_attr(
46608 not(target_arch = "arm"),
46609 stable(feature = "neon_intrinsics", since = "1.59.0")
46610)]
46611#[cfg_attr(
46612 target_arch = "arm",
46613 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46614)]
46615pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
46616 unsafe { transmute(a) }
46617}
46618#[doc = "Vector reinterpret cast operation"]
46619#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
46620#[inline]
46621#[cfg(target_endian = "big")]
46622#[target_feature(enable = "neon")]
46623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46625#[cfg_attr(
46626 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46627 assert_instr(nop)
46628)]
46629#[cfg_attr(
46630 not(target_arch = "arm"),
46631 stable(feature = "neon_intrinsics", since = "1.59.0")
46632)]
46633#[cfg_attr(
46634 target_arch = "arm",
46635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46636)]
46637pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
46638 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46639 unsafe {
46640 let ret_val: uint8x16_t = transmute(a);
46641 simd_shuffle!(
46642 ret_val,
46643 ret_val,
46644 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46645 )
46646 }
46647}
46648#[doc = "Vector reinterpret cast operation"]
46649#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
46650#[inline]
46651#[cfg(target_endian = "little")]
46652#[target_feature(enable = "neon")]
46653#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46654#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46655#[cfg_attr(
46656 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46657 assert_instr(nop)
46658)]
46659#[cfg_attr(
46660 not(target_arch = "arm"),
46661 stable(feature = "neon_intrinsics", since = "1.59.0")
46662)]
46663#[cfg_attr(
46664 target_arch = "arm",
46665 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46666)]
46667pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
46668 unsafe { transmute(a) }
46669}
46670#[doc = "Vector reinterpret cast operation"]
46671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
46672#[inline]
46673#[cfg(target_endian = "big")]
46674#[target_feature(enable = "neon")]
46675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46677#[cfg_attr(
46678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46679 assert_instr(nop)
46680)]
46681#[cfg_attr(
46682 not(target_arch = "arm"),
46683 stable(feature = "neon_intrinsics", since = "1.59.0")
46684)]
46685#[cfg_attr(
46686 target_arch = "arm",
46687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46688)]
46689pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
46690 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46691 unsafe {
46692 let ret_val: uint16x8_t = transmute(a);
46693 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46694 }
46695}
46696#[doc = "Vector reinterpret cast operation"]
46697#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
46698#[inline]
46699#[cfg(target_endian = "little")]
46700#[target_feature(enable = "neon")]
46701#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46702#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46703#[cfg_attr(
46704 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46705 assert_instr(nop)
46706)]
46707#[cfg_attr(
46708 not(target_arch = "arm"),
46709 stable(feature = "neon_intrinsics", since = "1.59.0")
46710)]
46711#[cfg_attr(
46712 target_arch = "arm",
46713 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46714)]
46715pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
46716 unsafe { transmute(a) }
46717}
46718#[doc = "Vector reinterpret cast operation"]
46719#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
46720#[inline]
46721#[cfg(target_endian = "big")]
46722#[target_feature(enable = "neon")]
46723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46725#[cfg_attr(
46726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46727 assert_instr(nop)
46728)]
46729#[cfg_attr(
46730 not(target_arch = "arm"),
46731 stable(feature = "neon_intrinsics", since = "1.59.0")
46732)]
46733#[cfg_attr(
46734 target_arch = "arm",
46735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46736)]
46737pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
46738 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46739 unsafe {
46740 let ret_val: uint32x4_t = transmute(a);
46741 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
46742 }
46743}
46744#[doc = "Vector reinterpret cast operation"]
46745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
46746#[inline]
46747#[cfg(target_endian = "little")]
46748#[target_feature(enable = "neon")]
46749#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46751#[cfg_attr(
46752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46753 assert_instr(nop)
46754)]
46755#[cfg_attr(
46756 not(target_arch = "arm"),
46757 stable(feature = "neon_intrinsics", since = "1.59.0")
46758)]
46759#[cfg_attr(
46760 target_arch = "arm",
46761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46762)]
46763pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
46764 unsafe { transmute(a) }
46765}
46766#[doc = "Vector reinterpret cast operation"]
46767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
46768#[inline]
46769#[cfg(target_endian = "big")]
46770#[target_feature(enable = "neon")]
46771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46773#[cfg_attr(
46774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46775 assert_instr(nop)
46776)]
46777#[cfg_attr(
46778 not(target_arch = "arm"),
46779 stable(feature = "neon_intrinsics", since = "1.59.0")
46780)]
46781#[cfg_attr(
46782 target_arch = "arm",
46783 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46784)]
46785pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
46786 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46787 unsafe {
46788 let ret_val: uint64x2_t = transmute(a);
46789 simd_shuffle!(ret_val, ret_val, [1, 0])
46790 }
46791}
46792#[doc = "Vector reinterpret cast operation"]
46793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
46794#[inline]
46795#[cfg(target_endian = "little")]
46796#[target_feature(enable = "neon")]
46797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46799#[cfg_attr(
46800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46801 assert_instr(nop)
46802)]
46803#[cfg_attr(
46804 not(target_arch = "arm"),
46805 stable(feature = "neon_intrinsics", since = "1.59.0")
46806)]
46807#[cfg_attr(
46808 target_arch = "arm",
46809 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46810)]
46811pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
46812 unsafe { transmute(a) }
46813}
46814#[doc = "Vector reinterpret cast operation"]
46815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
46816#[inline]
46817#[cfg(target_endian = "big")]
46818#[target_feature(enable = "neon")]
46819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46821#[cfg_attr(
46822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46823 assert_instr(nop)
46824)]
46825#[cfg_attr(
46826 not(target_arch = "arm"),
46827 stable(feature = "neon_intrinsics", since = "1.59.0")
46828)]
46829#[cfg_attr(
46830 target_arch = "arm",
46831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46832)]
46833pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
46834 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46835 unsafe {
46836 let ret_val: poly8x16_t = transmute(a);
46837 simd_shuffle!(
46838 ret_val,
46839 ret_val,
46840 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
46841 )
46842 }
46843}
46844#[doc = "Vector reinterpret cast operation"]
46845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
46846#[inline]
46847#[cfg(target_endian = "little")]
46848#[target_feature(enable = "neon")]
46849#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46851#[cfg_attr(
46852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46853 assert_instr(nop)
46854)]
46855#[cfg_attr(
46856 not(target_arch = "arm"),
46857 stable(feature = "neon_intrinsics", since = "1.59.0")
46858)]
46859#[cfg_attr(
46860 target_arch = "arm",
46861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46862)]
46863pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
46864 unsafe { transmute(a) }
46865}
46866#[doc = "Vector reinterpret cast operation"]
46867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
46868#[inline]
46869#[cfg(target_endian = "big")]
46870#[target_feature(enable = "neon")]
46871#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46872#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46873#[cfg_attr(
46874 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46875 assert_instr(nop)
46876)]
46877#[cfg_attr(
46878 not(target_arch = "arm"),
46879 stable(feature = "neon_intrinsics", since = "1.59.0")
46880)]
46881#[cfg_attr(
46882 target_arch = "arm",
46883 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46884)]
46885pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
46886 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
46887 unsafe {
46888 let ret_val: poly16x8_t = transmute(a);
46889 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46890 }
46891}
46892#[doc = "Vector reinterpret cast operation"]
46893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
46894#[inline]
46895#[cfg(target_endian = "little")]
46896#[target_feature(enable = "neon")]
46897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46899#[cfg_attr(
46900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46901 assert_instr(nop)
46902)]
46903#[cfg_attr(
46904 not(target_arch = "arm"),
46905 stable(feature = "neon_intrinsics", since = "1.59.0")
46906)]
46907#[cfg_attr(
46908 target_arch = "arm",
46909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46910)]
46911pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
46912 unsafe { transmute(a) }
46913}
46914#[doc = "Vector reinterpret cast operation"]
46915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
46916#[inline]
46917#[cfg(target_endian = "big")]
46918#[target_feature(enable = "neon")]
46919#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46920#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46921#[cfg_attr(
46922 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46923 assert_instr(nop)
46924)]
46925#[cfg_attr(
46926 not(target_arch = "arm"),
46927 stable(feature = "neon_intrinsics", since = "1.59.0")
46928)]
46929#[cfg_attr(
46930 target_arch = "arm",
46931 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46932)]
46933pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
46934 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46935 unsafe {
46936 let ret_val: float32x2_t = transmute(a);
46937 simd_shuffle!(ret_val, ret_val, [1, 0])
46938 }
46939}
46940#[doc = "Vector reinterpret cast operation"]
46941#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
46942#[inline]
46943#[cfg(target_endian = "little")]
46944#[target_feature(enable = "neon")]
46945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46947#[cfg_attr(
46948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46949 assert_instr(nop)
46950)]
46951#[cfg_attr(
46952 not(target_arch = "arm"),
46953 stable(feature = "neon_intrinsics", since = "1.59.0")
46954)]
46955#[cfg_attr(
46956 target_arch = "arm",
46957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46958)]
46959pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
46960 unsafe { transmute(a) }
46961}
46962#[doc = "Vector reinterpret cast operation"]
46963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
46964#[inline]
46965#[cfg(target_endian = "big")]
46966#[target_feature(enable = "neon")]
46967#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46968#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46969#[cfg_attr(
46970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46971 assert_instr(nop)
46972)]
46973#[cfg_attr(
46974 not(target_arch = "arm"),
46975 stable(feature = "neon_intrinsics", since = "1.59.0")
46976)]
46977#[cfg_attr(
46978 target_arch = "arm",
46979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
46980)]
46981pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
46982 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
46983 unsafe {
46984 let ret_val: int8x8_t = transmute(a);
46985 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
46986 }
46987}
46988#[doc = "Vector reinterpret cast operation"]
46989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
46990#[inline]
46991#[cfg(target_endian = "little")]
46992#[target_feature(enable = "neon")]
46993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
46994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
46995#[cfg_attr(
46996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
46997 assert_instr(nop)
46998)]
46999#[cfg_attr(
47000 not(target_arch = "arm"),
47001 stable(feature = "neon_intrinsics", since = "1.59.0")
47002)]
47003#[cfg_attr(
47004 target_arch = "arm",
47005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47006)]
47007pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47008 unsafe { transmute(a) }
47009}
47010#[doc = "Vector reinterpret cast operation"]
47011#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
47012#[inline]
47013#[cfg(target_endian = "big")]
47014#[target_feature(enable = "neon")]
47015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47017#[cfg_attr(
47018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47019 assert_instr(nop)
47020)]
47021#[cfg_attr(
47022 not(target_arch = "arm"),
47023 stable(feature = "neon_intrinsics", since = "1.59.0")
47024)]
47025#[cfg_attr(
47026 target_arch = "arm",
47027 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47028)]
47029pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
47030 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47031 unsafe {
47032 let ret_val: int16x4_t = transmute(a);
47033 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47034 }
47035}
47036#[doc = "Vector reinterpret cast operation"]
47037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47038#[inline]
47039#[cfg(target_endian = "little")]
47040#[target_feature(enable = "neon")]
47041#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47042#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47043#[cfg_attr(
47044 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47045 assert_instr(nop)
47046)]
47047#[cfg_attr(
47048 not(target_arch = "arm"),
47049 stable(feature = "neon_intrinsics", since = "1.59.0")
47050)]
47051#[cfg_attr(
47052 target_arch = "arm",
47053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47054)]
47055pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47056 unsafe { transmute(a) }
47057}
47058#[doc = "Vector reinterpret cast operation"]
47059#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
47060#[inline]
47061#[cfg(target_endian = "big")]
47062#[target_feature(enable = "neon")]
47063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47065#[cfg_attr(
47066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47067 assert_instr(nop)
47068)]
47069#[cfg_attr(
47070 not(target_arch = "arm"),
47071 stable(feature = "neon_intrinsics", since = "1.59.0")
47072)]
47073#[cfg_attr(
47074 target_arch = "arm",
47075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47076)]
47077pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
47078 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47079 unsafe { transmute(a) }
47080}
47081#[doc = "Vector reinterpret cast operation"]
47082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47083#[inline]
47084#[cfg(target_endian = "little")]
47085#[target_feature(enable = "neon")]
47086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47088#[cfg_attr(
47089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47090 assert_instr(nop)
47091)]
47092#[cfg_attr(
47093 not(target_arch = "arm"),
47094 stable(feature = "neon_intrinsics", since = "1.59.0")
47095)]
47096#[cfg_attr(
47097 target_arch = "arm",
47098 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47099)]
47100pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47101 unsafe { transmute(a) }
47102}
47103#[doc = "Vector reinterpret cast operation"]
47104#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
47105#[inline]
47106#[cfg(target_endian = "big")]
47107#[target_feature(enable = "neon")]
47108#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47109#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47110#[cfg_attr(
47111 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47112 assert_instr(nop)
47113)]
47114#[cfg_attr(
47115 not(target_arch = "arm"),
47116 stable(feature = "neon_intrinsics", since = "1.59.0")
47117)]
47118#[cfg_attr(
47119 target_arch = "arm",
47120 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47121)]
47122pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
47123 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47124 unsafe {
47125 let ret_val: uint8x8_t = transmute(a);
47126 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47127 }
47128}
47129#[doc = "Vector reinterpret cast operation"]
47130#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47131#[inline]
47132#[cfg(target_endian = "little")]
47133#[target_feature(enable = "neon")]
47134#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47135#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47136#[cfg_attr(
47137 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47138 assert_instr(nop)
47139)]
47140#[cfg_attr(
47141 not(target_arch = "arm"),
47142 stable(feature = "neon_intrinsics", since = "1.59.0")
47143)]
47144#[cfg_attr(
47145 target_arch = "arm",
47146 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47147)]
47148pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47149 unsafe { transmute(a) }
47150}
47151#[doc = "Vector reinterpret cast operation"]
47152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
47153#[inline]
47154#[cfg(target_endian = "big")]
47155#[target_feature(enable = "neon")]
47156#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47157#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47158#[cfg_attr(
47159 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47160 assert_instr(nop)
47161)]
47162#[cfg_attr(
47163 not(target_arch = "arm"),
47164 stable(feature = "neon_intrinsics", since = "1.59.0")
47165)]
47166#[cfg_attr(
47167 target_arch = "arm",
47168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47169)]
47170pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
47171 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47172 unsafe {
47173 let ret_val: uint16x4_t = transmute(a);
47174 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47175 }
47176}
47177#[doc = "Vector reinterpret cast operation"]
47178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47179#[inline]
47180#[cfg(target_endian = "little")]
47181#[target_feature(enable = "neon")]
47182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47184#[cfg_attr(
47185 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47186 assert_instr(nop)
47187)]
47188#[cfg_attr(
47189 not(target_arch = "arm"),
47190 stable(feature = "neon_intrinsics", since = "1.59.0")
47191)]
47192#[cfg_attr(
47193 target_arch = "arm",
47194 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47195)]
47196pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47197 unsafe { transmute(a) }
47198}
47199#[doc = "Vector reinterpret cast operation"]
47200#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
47201#[inline]
47202#[cfg(target_endian = "big")]
47203#[target_feature(enable = "neon")]
47204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47206#[cfg_attr(
47207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47208 assert_instr(nop)
47209)]
47210#[cfg_attr(
47211 not(target_arch = "arm"),
47212 stable(feature = "neon_intrinsics", since = "1.59.0")
47213)]
47214#[cfg_attr(
47215 target_arch = "arm",
47216 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47217)]
47218pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
47219 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47220 unsafe {
47221 let ret_val: uint32x2_t = transmute(a);
47222 simd_shuffle!(ret_val, ret_val, [1, 0])
47223 }
47224}
47225#[doc = "Vector reinterpret cast operation"]
47226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47227#[inline]
47228#[cfg(target_endian = "little")]
47229#[target_feature(enable = "neon")]
47230#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47231#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47232#[cfg_attr(
47233 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47234 assert_instr(nop)
47235)]
47236#[cfg_attr(
47237 not(target_arch = "arm"),
47238 stable(feature = "neon_intrinsics", since = "1.59.0")
47239)]
47240#[cfg_attr(
47241 target_arch = "arm",
47242 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47243)]
47244pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47245 unsafe { transmute(a) }
47246}
47247#[doc = "Vector reinterpret cast operation"]
47248#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
47249#[inline]
47250#[cfg(target_endian = "big")]
47251#[target_feature(enable = "neon")]
47252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47254#[cfg_attr(
47255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47256 assert_instr(nop)
47257)]
47258#[cfg_attr(
47259 not(target_arch = "arm"),
47260 stable(feature = "neon_intrinsics", since = "1.59.0")
47261)]
47262#[cfg_attr(
47263 target_arch = "arm",
47264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47265)]
47266pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
47267 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47268 unsafe { transmute(a) }
47269}
47270#[doc = "Vector reinterpret cast operation"]
47271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47272#[inline]
47273#[cfg(target_endian = "little")]
47274#[target_feature(enable = "neon")]
47275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47277#[cfg_attr(
47278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47279 assert_instr(nop)
47280)]
47281#[cfg_attr(
47282 not(target_arch = "arm"),
47283 stable(feature = "neon_intrinsics", since = "1.59.0")
47284)]
47285#[cfg_attr(
47286 target_arch = "arm",
47287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47288)]
47289pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47290 unsafe { transmute(a) }
47291}
47292#[doc = "Vector reinterpret cast operation"]
47293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
47294#[inline]
47295#[cfg(target_endian = "big")]
47296#[target_feature(enable = "neon")]
47297#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47298#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47299#[cfg_attr(
47300 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47301 assert_instr(nop)
47302)]
47303#[cfg_attr(
47304 not(target_arch = "arm"),
47305 stable(feature = "neon_intrinsics", since = "1.59.0")
47306)]
47307#[cfg_attr(
47308 target_arch = "arm",
47309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47310)]
47311pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
47312 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47313 unsafe {
47314 let ret_val: poly8x8_t = transmute(a);
47315 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47316 }
47317}
47318#[doc = "Vector reinterpret cast operation"]
47319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47320#[inline]
47321#[cfg(target_endian = "little")]
47322#[target_feature(enable = "neon")]
47323#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47324#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47325#[cfg_attr(
47326 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47327 assert_instr(nop)
47328)]
47329#[cfg_attr(
47330 not(target_arch = "arm"),
47331 stable(feature = "neon_intrinsics", since = "1.59.0")
47332)]
47333#[cfg_attr(
47334 target_arch = "arm",
47335 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47336)]
47337pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47338 unsafe { transmute(a) }
47339}
47340#[doc = "Vector reinterpret cast operation"]
47341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
47342#[inline]
47343#[cfg(target_endian = "big")]
47344#[target_feature(enable = "neon")]
47345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47347#[cfg_attr(
47348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47349 assert_instr(nop)
47350)]
47351#[cfg_attr(
47352 not(target_arch = "arm"),
47353 stable(feature = "neon_intrinsics", since = "1.59.0")
47354)]
47355#[cfg_attr(
47356 target_arch = "arm",
47357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47358)]
47359pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
47360 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
47361 unsafe {
47362 let ret_val: poly16x4_t = transmute(a);
47363 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47364 }
47365}
47366#[doc = "Vector reinterpret cast operation"]
47367#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47368#[inline]
47369#[cfg(target_endian = "little")]
47370#[target_feature(enable = "neon")]
47371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47372#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47373#[cfg_attr(
47374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47375 assert_instr(nop)
47376)]
47377#[cfg_attr(
47378 not(target_arch = "arm"),
47379 stable(feature = "neon_intrinsics", since = "1.59.0")
47380)]
47381#[cfg_attr(
47382 target_arch = "arm",
47383 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47384)]
47385pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47386 unsafe { transmute(a) }
47387}
47388#[doc = "Vector reinterpret cast operation"]
47389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
47390#[inline]
47391#[cfg(target_endian = "big")]
47392#[target_feature(enable = "neon")]
47393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47395#[cfg_attr(
47396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47397 assert_instr(nop)
47398)]
47399#[cfg_attr(
47400 not(target_arch = "arm"),
47401 stable(feature = "neon_intrinsics", since = "1.59.0")
47402)]
47403#[cfg_attr(
47404 target_arch = "arm",
47405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47406)]
47407pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
47408 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47409 unsafe {
47410 let ret_val: float32x4_t = transmute(a);
47411 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47412 }
47413}
47414#[doc = "Vector reinterpret cast operation"]
47415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47416#[inline]
47417#[cfg(target_endian = "little")]
47418#[target_feature(enable = "neon")]
47419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47421#[cfg_attr(
47422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47423 assert_instr(nop)
47424)]
47425#[cfg_attr(
47426 not(target_arch = "arm"),
47427 stable(feature = "neon_intrinsics", since = "1.59.0")
47428)]
47429#[cfg_attr(
47430 target_arch = "arm",
47431 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47432)]
47433pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47434 unsafe { transmute(a) }
47435}
47436#[doc = "Vector reinterpret cast operation"]
47437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
47438#[inline]
47439#[cfg(target_endian = "big")]
47440#[target_feature(enable = "neon")]
47441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47443#[cfg_attr(
47444 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47445 assert_instr(nop)
47446)]
47447#[cfg_attr(
47448 not(target_arch = "arm"),
47449 stable(feature = "neon_intrinsics", since = "1.59.0")
47450)]
47451#[cfg_attr(
47452 target_arch = "arm",
47453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47454)]
47455pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
47456 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47457 unsafe {
47458 let ret_val: int8x16_t = transmute(a);
47459 simd_shuffle!(
47460 ret_val,
47461 ret_val,
47462 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47463 )
47464 }
47465}
47466#[doc = "Vector reinterpret cast operation"]
47467#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47468#[inline]
47469#[cfg(target_endian = "little")]
47470#[target_feature(enable = "neon")]
47471#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47472#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47473#[cfg_attr(
47474 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47475 assert_instr(nop)
47476)]
47477#[cfg_attr(
47478 not(target_arch = "arm"),
47479 stable(feature = "neon_intrinsics", since = "1.59.0")
47480)]
47481#[cfg_attr(
47482 target_arch = "arm",
47483 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47484)]
47485pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47486 unsafe { transmute(a) }
47487}
47488#[doc = "Vector reinterpret cast operation"]
47489#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
47490#[inline]
47491#[cfg(target_endian = "big")]
47492#[target_feature(enable = "neon")]
47493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47495#[cfg_attr(
47496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47497 assert_instr(nop)
47498)]
47499#[cfg_attr(
47500 not(target_arch = "arm"),
47501 stable(feature = "neon_intrinsics", since = "1.59.0")
47502)]
47503#[cfg_attr(
47504 target_arch = "arm",
47505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47506)]
47507pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
47508 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47509 unsafe {
47510 let ret_val: int16x8_t = transmute(a);
47511 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47512 }
47513}
47514#[doc = "Vector reinterpret cast operation"]
47515#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47516#[inline]
47517#[cfg(target_endian = "little")]
47518#[target_feature(enable = "neon")]
47519#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47520#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47521#[cfg_attr(
47522 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47523 assert_instr(nop)
47524)]
47525#[cfg_attr(
47526 not(target_arch = "arm"),
47527 stable(feature = "neon_intrinsics", since = "1.59.0")
47528)]
47529#[cfg_attr(
47530 target_arch = "arm",
47531 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47532)]
47533pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47534 unsafe { transmute(a) }
47535}
47536#[doc = "Vector reinterpret cast operation"]
47537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
47538#[inline]
47539#[cfg(target_endian = "big")]
47540#[target_feature(enable = "neon")]
47541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47543#[cfg_attr(
47544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47545 assert_instr(nop)
47546)]
47547#[cfg_attr(
47548 not(target_arch = "arm"),
47549 stable(feature = "neon_intrinsics", since = "1.59.0")
47550)]
47551#[cfg_attr(
47552 target_arch = "arm",
47553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47554)]
47555pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
47556 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47557 unsafe {
47558 let ret_val: int64x2_t = transmute(a);
47559 simd_shuffle!(ret_val, ret_val, [1, 0])
47560 }
47561}
47562#[doc = "Vector reinterpret cast operation"]
47563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
47564#[inline]
47565#[cfg(target_endian = "little")]
47566#[target_feature(enable = "neon")]
47567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47569#[cfg_attr(
47570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47571 assert_instr(nop)
47572)]
47573#[cfg_attr(
47574 not(target_arch = "arm"),
47575 stable(feature = "neon_intrinsics", since = "1.59.0")
47576)]
47577#[cfg_attr(
47578 target_arch = "arm",
47579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47580)]
47581pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
47582 unsafe { transmute(a) }
47583}
47584#[doc = "Vector reinterpret cast operation"]
47585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
47586#[inline]
47587#[cfg(target_endian = "big")]
47588#[target_feature(enable = "neon")]
47589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47591#[cfg_attr(
47592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47593 assert_instr(nop)
47594)]
47595#[cfg_attr(
47596 not(target_arch = "arm"),
47597 stable(feature = "neon_intrinsics", since = "1.59.0")
47598)]
47599#[cfg_attr(
47600 target_arch = "arm",
47601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47602)]
47603pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
47604 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47605 unsafe {
47606 let ret_val: uint8x16_t = transmute(a);
47607 simd_shuffle!(
47608 ret_val,
47609 ret_val,
47610 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47611 )
47612 }
47613}
47614#[doc = "Vector reinterpret cast operation"]
47615#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
47616#[inline]
47617#[cfg(target_endian = "little")]
47618#[target_feature(enable = "neon")]
47619#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47620#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47621#[cfg_attr(
47622 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47623 assert_instr(nop)
47624)]
47625#[cfg_attr(
47626 not(target_arch = "arm"),
47627 stable(feature = "neon_intrinsics", since = "1.59.0")
47628)]
47629#[cfg_attr(
47630 target_arch = "arm",
47631 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47632)]
47633pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
47634 unsafe { transmute(a) }
47635}
47636#[doc = "Vector reinterpret cast operation"]
47637#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
47638#[inline]
47639#[cfg(target_endian = "big")]
47640#[target_feature(enable = "neon")]
47641#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47642#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47643#[cfg_attr(
47644 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47645 assert_instr(nop)
47646)]
47647#[cfg_attr(
47648 not(target_arch = "arm"),
47649 stable(feature = "neon_intrinsics", since = "1.59.0")
47650)]
47651#[cfg_attr(
47652 target_arch = "arm",
47653 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47654)]
47655pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
47656 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47657 unsafe {
47658 let ret_val: uint16x8_t = transmute(a);
47659 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47660 }
47661}
47662#[doc = "Vector reinterpret cast operation"]
47663#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
47664#[inline]
47665#[cfg(target_endian = "little")]
47666#[target_feature(enable = "neon")]
47667#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47668#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47669#[cfg_attr(
47670 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47671 assert_instr(nop)
47672)]
47673#[cfg_attr(
47674 not(target_arch = "arm"),
47675 stable(feature = "neon_intrinsics", since = "1.59.0")
47676)]
47677#[cfg_attr(
47678 target_arch = "arm",
47679 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47680)]
47681pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
47682 unsafe { transmute(a) }
47683}
47684#[doc = "Vector reinterpret cast operation"]
47685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
47686#[inline]
47687#[cfg(target_endian = "big")]
47688#[target_feature(enable = "neon")]
47689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47691#[cfg_attr(
47692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47693 assert_instr(nop)
47694)]
47695#[cfg_attr(
47696 not(target_arch = "arm"),
47697 stable(feature = "neon_intrinsics", since = "1.59.0")
47698)]
47699#[cfg_attr(
47700 target_arch = "arm",
47701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47702)]
47703pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
47704 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47705 unsafe {
47706 let ret_val: uint32x4_t = transmute(a);
47707 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47708 }
47709}
47710#[doc = "Vector reinterpret cast operation"]
47711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
47712#[inline]
47713#[cfg(target_endian = "little")]
47714#[target_feature(enable = "neon")]
47715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47717#[cfg_attr(
47718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47719 assert_instr(nop)
47720)]
47721#[cfg_attr(
47722 not(target_arch = "arm"),
47723 stable(feature = "neon_intrinsics", since = "1.59.0")
47724)]
47725#[cfg_attr(
47726 target_arch = "arm",
47727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47728)]
47729pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
47730 unsafe { transmute(a) }
47731}
47732#[doc = "Vector reinterpret cast operation"]
47733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
47734#[inline]
47735#[cfg(target_endian = "big")]
47736#[target_feature(enable = "neon")]
47737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47739#[cfg_attr(
47740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47741 assert_instr(nop)
47742)]
47743#[cfg_attr(
47744 not(target_arch = "arm"),
47745 stable(feature = "neon_intrinsics", since = "1.59.0")
47746)]
47747#[cfg_attr(
47748 target_arch = "arm",
47749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47750)]
47751pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
47752 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47753 unsafe {
47754 let ret_val: uint64x2_t = transmute(a);
47755 simd_shuffle!(ret_val, ret_val, [1, 0])
47756 }
47757}
47758#[doc = "Vector reinterpret cast operation"]
47759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
47760#[inline]
47761#[cfg(target_endian = "little")]
47762#[target_feature(enable = "neon")]
47763#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47764#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47765#[cfg_attr(
47766 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47767 assert_instr(nop)
47768)]
47769#[cfg_attr(
47770 not(target_arch = "arm"),
47771 stable(feature = "neon_intrinsics", since = "1.59.0")
47772)]
47773#[cfg_attr(
47774 target_arch = "arm",
47775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47776)]
47777pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
47778 unsafe { transmute(a) }
47779}
47780#[doc = "Vector reinterpret cast operation"]
47781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
47782#[inline]
47783#[cfg(target_endian = "big")]
47784#[target_feature(enable = "neon")]
47785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47787#[cfg_attr(
47788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47789 assert_instr(nop)
47790)]
47791#[cfg_attr(
47792 not(target_arch = "arm"),
47793 stable(feature = "neon_intrinsics", since = "1.59.0")
47794)]
47795#[cfg_attr(
47796 target_arch = "arm",
47797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47798)]
47799pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
47800 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47801 unsafe {
47802 let ret_val: poly8x16_t = transmute(a);
47803 simd_shuffle!(
47804 ret_val,
47805 ret_val,
47806 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
47807 )
47808 }
47809}
47810#[doc = "Vector reinterpret cast operation"]
47811#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
47812#[inline]
47813#[cfg(target_endian = "little")]
47814#[target_feature(enable = "neon")]
47815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47817#[cfg_attr(
47818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47819 assert_instr(nop)
47820)]
47821#[cfg_attr(
47822 not(target_arch = "arm"),
47823 stable(feature = "neon_intrinsics", since = "1.59.0")
47824)]
47825#[cfg_attr(
47826 target_arch = "arm",
47827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47828)]
47829pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
47830 unsafe { transmute(a) }
47831}
47832#[doc = "Vector reinterpret cast operation"]
47833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
47834#[inline]
47835#[cfg(target_endian = "big")]
47836#[target_feature(enable = "neon")]
47837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47839#[cfg_attr(
47840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47841 assert_instr(nop)
47842)]
47843#[cfg_attr(
47844 not(target_arch = "arm"),
47845 stable(feature = "neon_intrinsics", since = "1.59.0")
47846)]
47847#[cfg_attr(
47848 target_arch = "arm",
47849 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47850)]
47851pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
47852 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
47853 unsafe {
47854 let ret_val: poly16x8_t = transmute(a);
47855 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47856 }
47857}
47858#[doc = "Vector reinterpret cast operation"]
47859#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
47860#[inline]
47861#[cfg(target_endian = "little")]
47862#[target_feature(enable = "neon")]
47863#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47864#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47865#[cfg_attr(
47866 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47867 assert_instr(nop)
47868)]
47869#[cfg_attr(
47870 not(target_arch = "arm"),
47871 stable(feature = "neon_intrinsics", since = "1.59.0")
47872)]
47873#[cfg_attr(
47874 target_arch = "arm",
47875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47876)]
47877pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
47878 unsafe { transmute(a) }
47879}
47880#[doc = "Vector reinterpret cast operation"]
47881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
47882#[inline]
47883#[cfg(target_endian = "big")]
47884#[target_feature(enable = "neon")]
47885#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47886#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47887#[cfg_attr(
47888 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47889 assert_instr(nop)
47890)]
47891#[cfg_attr(
47892 not(target_arch = "arm"),
47893 stable(feature = "neon_intrinsics", since = "1.59.0")
47894)]
47895#[cfg_attr(
47896 target_arch = "arm",
47897 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47898)]
47899pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
47900 unsafe {
47901 let ret_val: float32x2_t = transmute(a);
47902 simd_shuffle!(ret_val, ret_val, [1, 0])
47903 }
47904}
47905#[doc = "Vector reinterpret cast operation"]
47906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
47907#[inline]
47908#[cfg(target_endian = "little")]
47909#[target_feature(enable = "neon")]
47910#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47911#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47912#[cfg_attr(
47913 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47914 assert_instr(nop)
47915)]
47916#[cfg_attr(
47917 not(target_arch = "arm"),
47918 stable(feature = "neon_intrinsics", since = "1.59.0")
47919)]
47920#[cfg_attr(
47921 target_arch = "arm",
47922 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47923)]
47924pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
47925 unsafe { transmute(a) }
47926}
47927#[doc = "Vector reinterpret cast operation"]
47928#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
47929#[inline]
47930#[cfg(target_endian = "big")]
47931#[target_feature(enable = "neon")]
47932#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47933#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47934#[cfg_attr(
47935 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47936 assert_instr(nop)
47937)]
47938#[cfg_attr(
47939 not(target_arch = "arm"),
47940 stable(feature = "neon_intrinsics", since = "1.59.0")
47941)]
47942#[cfg_attr(
47943 target_arch = "arm",
47944 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47945)]
47946pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
47947 unsafe {
47948 let ret_val: int8x8_t = transmute(a);
47949 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
47950 }
47951}
47952#[doc = "Vector reinterpret cast operation"]
47953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
47954#[inline]
47955#[cfg(target_endian = "little")]
47956#[target_feature(enable = "neon")]
47957#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47959#[cfg_attr(
47960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47961 assert_instr(nop)
47962)]
47963#[cfg_attr(
47964 not(target_arch = "arm"),
47965 stable(feature = "neon_intrinsics", since = "1.59.0")
47966)]
47967#[cfg_attr(
47968 target_arch = "arm",
47969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47970)]
47971pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
47972 unsafe { transmute(a) }
47973}
47974#[doc = "Vector reinterpret cast operation"]
47975#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
47976#[inline]
47977#[cfg(target_endian = "big")]
47978#[target_feature(enable = "neon")]
47979#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
47980#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
47981#[cfg_attr(
47982 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
47983 assert_instr(nop)
47984)]
47985#[cfg_attr(
47986 not(target_arch = "arm"),
47987 stable(feature = "neon_intrinsics", since = "1.59.0")
47988)]
47989#[cfg_attr(
47990 target_arch = "arm",
47991 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
47992)]
47993pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
47994 unsafe {
47995 let ret_val: int16x4_t = transmute(a);
47996 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
47997 }
47998}
47999#[doc = "Vector reinterpret cast operation"]
48000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48001#[inline]
48002#[cfg(target_endian = "little")]
48003#[target_feature(enable = "neon")]
48004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48006#[cfg_attr(
48007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48008 assert_instr(nop)
48009)]
48010#[cfg_attr(
48011 not(target_arch = "arm"),
48012 stable(feature = "neon_intrinsics", since = "1.59.0")
48013)]
48014#[cfg_attr(
48015 target_arch = "arm",
48016 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48017)]
48018pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48019 unsafe { transmute(a) }
48020}
48021#[doc = "Vector reinterpret cast operation"]
48022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
48023#[inline]
48024#[cfg(target_endian = "big")]
48025#[target_feature(enable = "neon")]
48026#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48027#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48028#[cfg_attr(
48029 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48030 assert_instr(nop)
48031)]
48032#[cfg_attr(
48033 not(target_arch = "arm"),
48034 stable(feature = "neon_intrinsics", since = "1.59.0")
48035)]
48036#[cfg_attr(
48037 target_arch = "arm",
48038 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48039)]
48040pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
48041 unsafe {
48042 let ret_val: int32x2_t = transmute(a);
48043 simd_shuffle!(ret_val, ret_val, [1, 0])
48044 }
48045}
48046#[doc = "Vector reinterpret cast operation"]
48047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48048#[inline]
48049#[cfg(target_endian = "little")]
48050#[target_feature(enable = "neon")]
48051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48052#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48053#[cfg_attr(
48054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48055 assert_instr(nop)
48056)]
48057#[cfg_attr(
48058 not(target_arch = "arm"),
48059 stable(feature = "neon_intrinsics", since = "1.59.0")
48060)]
48061#[cfg_attr(
48062 target_arch = "arm",
48063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48064)]
48065pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48066 unsafe { transmute(a) }
48067}
48068#[doc = "Vector reinterpret cast operation"]
48069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
48070#[inline]
48071#[cfg(target_endian = "big")]
48072#[target_feature(enable = "neon")]
48073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48075#[cfg_attr(
48076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48077 assert_instr(nop)
48078)]
48079#[cfg_attr(
48080 not(target_arch = "arm"),
48081 stable(feature = "neon_intrinsics", since = "1.59.0")
48082)]
48083#[cfg_attr(
48084 target_arch = "arm",
48085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48086)]
48087pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
48088 unsafe {
48089 let ret_val: uint8x8_t = transmute(a);
48090 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48091 }
48092}
48093#[doc = "Vector reinterpret cast operation"]
48094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48095#[inline]
48096#[cfg(target_endian = "little")]
48097#[target_feature(enable = "neon")]
48098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48099#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48100#[cfg_attr(
48101 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48102 assert_instr(nop)
48103)]
48104#[cfg_attr(
48105 not(target_arch = "arm"),
48106 stable(feature = "neon_intrinsics", since = "1.59.0")
48107)]
48108#[cfg_attr(
48109 target_arch = "arm",
48110 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48111)]
48112pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48113 unsafe { transmute(a) }
48114}
48115#[doc = "Vector reinterpret cast operation"]
48116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
48117#[inline]
48118#[cfg(target_endian = "big")]
48119#[target_feature(enable = "neon")]
48120#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48121#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48122#[cfg_attr(
48123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48124 assert_instr(nop)
48125)]
48126#[cfg_attr(
48127 not(target_arch = "arm"),
48128 stable(feature = "neon_intrinsics", since = "1.59.0")
48129)]
48130#[cfg_attr(
48131 target_arch = "arm",
48132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48133)]
48134pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
48135 unsafe {
48136 let ret_val: uint16x4_t = transmute(a);
48137 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48138 }
48139}
48140#[doc = "Vector reinterpret cast operation"]
48141#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48142#[inline]
48143#[cfg(target_endian = "little")]
48144#[target_feature(enable = "neon")]
48145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48147#[cfg_attr(
48148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48149 assert_instr(nop)
48150)]
48151#[cfg_attr(
48152 not(target_arch = "arm"),
48153 stable(feature = "neon_intrinsics", since = "1.59.0")
48154)]
48155#[cfg_attr(
48156 target_arch = "arm",
48157 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48158)]
48159pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48160 unsafe { transmute(a) }
48161}
48162#[doc = "Vector reinterpret cast operation"]
48163#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
48164#[inline]
48165#[cfg(target_endian = "big")]
48166#[target_feature(enable = "neon")]
48167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48168#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48169#[cfg_attr(
48170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48171 assert_instr(nop)
48172)]
48173#[cfg_attr(
48174 not(target_arch = "arm"),
48175 stable(feature = "neon_intrinsics", since = "1.59.0")
48176)]
48177#[cfg_attr(
48178 target_arch = "arm",
48179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48180)]
48181pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
48182 unsafe {
48183 let ret_val: uint32x2_t = transmute(a);
48184 simd_shuffle!(ret_val, ret_val, [1, 0])
48185 }
48186}
48187#[doc = "Vector reinterpret cast operation"]
48188#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
48189#[inline]
48190#[target_feature(enable = "neon")]
48191#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48192#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48193#[cfg_attr(
48194 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48195 assert_instr(nop)
48196)]
48197#[cfg_attr(
48198 not(target_arch = "arm"),
48199 stable(feature = "neon_intrinsics", since = "1.59.0")
48200)]
48201#[cfg_attr(
48202 target_arch = "arm",
48203 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48204)]
48205pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
48206 unsafe { transmute(a) }
48207}
48208#[doc = "Vector reinterpret cast operation"]
48209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48210#[inline]
48211#[cfg(target_endian = "little")]
48212#[target_feature(enable = "neon")]
48213#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48215#[cfg_attr(
48216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48217 assert_instr(nop)
48218)]
48219#[cfg_attr(
48220 not(target_arch = "arm"),
48221 stable(feature = "neon_intrinsics", since = "1.59.0")
48222)]
48223#[cfg_attr(
48224 target_arch = "arm",
48225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48226)]
48227pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48228 unsafe { transmute(a) }
48229}
48230#[doc = "Vector reinterpret cast operation"]
48231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
48232#[inline]
48233#[cfg(target_endian = "big")]
48234#[target_feature(enable = "neon")]
48235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48237#[cfg_attr(
48238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48239 assert_instr(nop)
48240)]
48241#[cfg_attr(
48242 not(target_arch = "arm"),
48243 stable(feature = "neon_intrinsics", since = "1.59.0")
48244)]
48245#[cfg_attr(
48246 target_arch = "arm",
48247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48248)]
48249pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
48250 unsafe {
48251 let ret_val: poly8x8_t = transmute(a);
48252 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48253 }
48254}
48255#[doc = "Vector reinterpret cast operation"]
48256#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48257#[inline]
48258#[cfg(target_endian = "little")]
48259#[target_feature(enable = "neon")]
48260#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48261#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48262#[cfg_attr(
48263 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48264 assert_instr(nop)
48265)]
48266#[cfg_attr(
48267 not(target_arch = "arm"),
48268 stable(feature = "neon_intrinsics", since = "1.59.0")
48269)]
48270#[cfg_attr(
48271 target_arch = "arm",
48272 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48273)]
48274pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48275 unsafe { transmute(a) }
48276}
48277#[doc = "Vector reinterpret cast operation"]
48278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
48279#[inline]
48280#[cfg(target_endian = "big")]
48281#[target_feature(enable = "neon")]
48282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48283#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48284#[cfg_attr(
48285 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48286 assert_instr(nop)
48287)]
48288#[cfg_attr(
48289 not(target_arch = "arm"),
48290 stable(feature = "neon_intrinsics", since = "1.59.0")
48291)]
48292#[cfg_attr(
48293 target_arch = "arm",
48294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48295)]
48296pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
48297 unsafe {
48298 let ret_val: poly16x4_t = transmute(a);
48299 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48300 }
48301}
48302#[doc = "Vector reinterpret cast operation"]
48303#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48304#[inline]
48305#[cfg(target_endian = "little")]
48306#[target_feature(enable = "neon")]
48307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48309#[cfg_attr(
48310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48311 assert_instr(nop)
48312)]
48313#[cfg_attr(
48314 not(target_arch = "arm"),
48315 stable(feature = "neon_intrinsics", since = "1.59.0")
48316)]
48317#[cfg_attr(
48318 target_arch = "arm",
48319 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48320)]
48321pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48322 unsafe { transmute(a) }
48323}
48324#[doc = "Vector reinterpret cast operation"]
48325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
48326#[inline]
48327#[cfg(target_endian = "big")]
48328#[target_feature(enable = "neon")]
48329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48331#[cfg_attr(
48332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48333 assert_instr(nop)
48334)]
48335#[cfg_attr(
48336 not(target_arch = "arm"),
48337 stable(feature = "neon_intrinsics", since = "1.59.0")
48338)]
48339#[cfg_attr(
48340 target_arch = "arm",
48341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48342)]
48343pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
48344 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48345 unsafe {
48346 let ret_val: float32x4_t = transmute(a);
48347 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48348 }
48349}
48350#[doc = "Vector reinterpret cast operation"]
48351#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48352#[inline]
48353#[cfg(target_endian = "little")]
48354#[target_feature(enable = "neon")]
48355#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48356#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48357#[cfg_attr(
48358 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48359 assert_instr(nop)
48360)]
48361#[cfg_attr(
48362 not(target_arch = "arm"),
48363 stable(feature = "neon_intrinsics", since = "1.59.0")
48364)]
48365#[cfg_attr(
48366 target_arch = "arm",
48367 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48368)]
48369pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48370 unsafe { transmute(a) }
48371}
48372#[doc = "Vector reinterpret cast operation"]
48373#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
48374#[inline]
48375#[cfg(target_endian = "big")]
48376#[target_feature(enable = "neon")]
48377#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48378#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48379#[cfg_attr(
48380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48381 assert_instr(nop)
48382)]
48383#[cfg_attr(
48384 not(target_arch = "arm"),
48385 stable(feature = "neon_intrinsics", since = "1.59.0")
48386)]
48387#[cfg_attr(
48388 target_arch = "arm",
48389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48390)]
48391pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
48392 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48393 unsafe {
48394 let ret_val: int8x16_t = transmute(a);
48395 simd_shuffle!(
48396 ret_val,
48397 ret_val,
48398 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48399 )
48400 }
48401}
48402#[doc = "Vector reinterpret cast operation"]
48403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48404#[inline]
48405#[cfg(target_endian = "little")]
48406#[target_feature(enable = "neon")]
48407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48409#[cfg_attr(
48410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48411 assert_instr(nop)
48412)]
48413#[cfg_attr(
48414 not(target_arch = "arm"),
48415 stable(feature = "neon_intrinsics", since = "1.59.0")
48416)]
48417#[cfg_attr(
48418 target_arch = "arm",
48419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48420)]
48421pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48422 unsafe { transmute(a) }
48423}
48424#[doc = "Vector reinterpret cast operation"]
48425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
48426#[inline]
48427#[cfg(target_endian = "big")]
48428#[target_feature(enable = "neon")]
48429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48431#[cfg_attr(
48432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48433 assert_instr(nop)
48434)]
48435#[cfg_attr(
48436 not(target_arch = "arm"),
48437 stable(feature = "neon_intrinsics", since = "1.59.0")
48438)]
48439#[cfg_attr(
48440 target_arch = "arm",
48441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48442)]
48443pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
48444 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48445 unsafe {
48446 let ret_val: int16x8_t = transmute(a);
48447 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48448 }
48449}
48450#[doc = "Vector reinterpret cast operation"]
48451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48452#[inline]
48453#[cfg(target_endian = "little")]
48454#[target_feature(enable = "neon")]
48455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48457#[cfg_attr(
48458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48459 assert_instr(nop)
48460)]
48461#[cfg_attr(
48462 not(target_arch = "arm"),
48463 stable(feature = "neon_intrinsics", since = "1.59.0")
48464)]
48465#[cfg_attr(
48466 target_arch = "arm",
48467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48468)]
48469pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48470 unsafe { transmute(a) }
48471}
48472#[doc = "Vector reinterpret cast operation"]
48473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
48474#[inline]
48475#[cfg(target_endian = "big")]
48476#[target_feature(enable = "neon")]
48477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48479#[cfg_attr(
48480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48481 assert_instr(nop)
48482)]
48483#[cfg_attr(
48484 not(target_arch = "arm"),
48485 stable(feature = "neon_intrinsics", since = "1.59.0")
48486)]
48487#[cfg_attr(
48488 target_arch = "arm",
48489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48490)]
48491pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
48492 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48493 unsafe {
48494 let ret_val: int32x4_t = transmute(a);
48495 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48496 }
48497}
48498#[doc = "Vector reinterpret cast operation"]
48499#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48500#[inline]
48501#[cfg(target_endian = "little")]
48502#[target_feature(enable = "neon")]
48503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48505#[cfg_attr(
48506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48507 assert_instr(nop)
48508)]
48509#[cfg_attr(
48510 not(target_arch = "arm"),
48511 stable(feature = "neon_intrinsics", since = "1.59.0")
48512)]
48513#[cfg_attr(
48514 target_arch = "arm",
48515 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48516)]
48517pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48518 unsafe { transmute(a) }
48519}
48520#[doc = "Vector reinterpret cast operation"]
48521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
48522#[inline]
48523#[cfg(target_endian = "big")]
48524#[target_feature(enable = "neon")]
48525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48527#[cfg_attr(
48528 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48529 assert_instr(nop)
48530)]
48531#[cfg_attr(
48532 not(target_arch = "arm"),
48533 stable(feature = "neon_intrinsics", since = "1.59.0")
48534)]
48535#[cfg_attr(
48536 target_arch = "arm",
48537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48538)]
48539pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
48540 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48541 unsafe {
48542 let ret_val: uint8x16_t = transmute(a);
48543 simd_shuffle!(
48544 ret_val,
48545 ret_val,
48546 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48547 )
48548 }
48549}
48550#[doc = "Vector reinterpret cast operation"]
48551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
48552#[inline]
48553#[cfg(target_endian = "little")]
48554#[target_feature(enable = "neon")]
48555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48557#[cfg_attr(
48558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48559 assert_instr(nop)
48560)]
48561#[cfg_attr(
48562 not(target_arch = "arm"),
48563 stable(feature = "neon_intrinsics", since = "1.59.0")
48564)]
48565#[cfg_attr(
48566 target_arch = "arm",
48567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48568)]
48569pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
48570 unsafe { transmute(a) }
48571}
48572#[doc = "Vector reinterpret cast operation"]
48573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
48574#[inline]
48575#[cfg(target_endian = "big")]
48576#[target_feature(enable = "neon")]
48577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48579#[cfg_attr(
48580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48581 assert_instr(nop)
48582)]
48583#[cfg_attr(
48584 not(target_arch = "arm"),
48585 stable(feature = "neon_intrinsics", since = "1.59.0")
48586)]
48587#[cfg_attr(
48588 target_arch = "arm",
48589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48590)]
48591pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
48592 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48593 unsafe {
48594 let ret_val: uint16x8_t = transmute(a);
48595 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48596 }
48597}
48598#[doc = "Vector reinterpret cast operation"]
48599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
48600#[inline]
48601#[cfg(target_endian = "little")]
48602#[target_feature(enable = "neon")]
48603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48605#[cfg_attr(
48606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48607 assert_instr(nop)
48608)]
48609#[cfg_attr(
48610 not(target_arch = "arm"),
48611 stable(feature = "neon_intrinsics", since = "1.59.0")
48612)]
48613#[cfg_attr(
48614 target_arch = "arm",
48615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48616)]
48617pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
48618 unsafe { transmute(a) }
48619}
48620#[doc = "Vector reinterpret cast operation"]
48621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
48622#[inline]
48623#[cfg(target_endian = "big")]
48624#[target_feature(enable = "neon")]
48625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48627#[cfg_attr(
48628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48629 assert_instr(nop)
48630)]
48631#[cfg_attr(
48632 not(target_arch = "arm"),
48633 stable(feature = "neon_intrinsics", since = "1.59.0")
48634)]
48635#[cfg_attr(
48636 target_arch = "arm",
48637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48638)]
48639pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
48640 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48641 unsafe {
48642 let ret_val: uint32x4_t = transmute(a);
48643 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48644 }
48645}
48646#[doc = "Vector reinterpret cast operation"]
48647#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
48648#[inline]
48649#[cfg(target_endian = "little")]
48650#[target_feature(enable = "neon")]
48651#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48652#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48653#[cfg_attr(
48654 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48655 assert_instr(nop)
48656)]
48657#[cfg_attr(
48658 not(target_arch = "arm"),
48659 stable(feature = "neon_intrinsics", since = "1.59.0")
48660)]
48661#[cfg_attr(
48662 target_arch = "arm",
48663 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48664)]
48665pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
48666 unsafe { transmute(a) }
48667}
48668#[doc = "Vector reinterpret cast operation"]
48669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
48670#[inline]
48671#[cfg(target_endian = "big")]
48672#[target_feature(enable = "neon")]
48673#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48674#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48675#[cfg_attr(
48676 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48677 assert_instr(nop)
48678)]
48679#[cfg_attr(
48680 not(target_arch = "arm"),
48681 stable(feature = "neon_intrinsics", since = "1.59.0")
48682)]
48683#[cfg_attr(
48684 target_arch = "arm",
48685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48686)]
48687pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
48688 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48689 unsafe {
48690 let ret_val: uint64x2_t = transmute(a);
48691 simd_shuffle!(ret_val, ret_val, [1, 0])
48692 }
48693}
48694#[doc = "Vector reinterpret cast operation"]
48695#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
48696#[inline]
48697#[cfg(target_endian = "little")]
48698#[target_feature(enable = "neon")]
48699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48700#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48701#[cfg_attr(
48702 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48703 assert_instr(nop)
48704)]
48705#[cfg_attr(
48706 not(target_arch = "arm"),
48707 stable(feature = "neon_intrinsics", since = "1.59.0")
48708)]
48709#[cfg_attr(
48710 target_arch = "arm",
48711 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48712)]
48713pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
48714 unsafe { transmute(a) }
48715}
48716#[doc = "Vector reinterpret cast operation"]
48717#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
48718#[inline]
48719#[cfg(target_endian = "big")]
48720#[target_feature(enable = "neon")]
48721#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48722#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48723#[cfg_attr(
48724 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48725 assert_instr(nop)
48726)]
48727#[cfg_attr(
48728 not(target_arch = "arm"),
48729 stable(feature = "neon_intrinsics", since = "1.59.0")
48730)]
48731#[cfg_attr(
48732 target_arch = "arm",
48733 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48734)]
48735pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
48736 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48737 unsafe {
48738 let ret_val: poly8x16_t = transmute(a);
48739 simd_shuffle!(
48740 ret_val,
48741 ret_val,
48742 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
48743 )
48744 }
48745}
48746#[doc = "Vector reinterpret cast operation"]
48747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
48748#[inline]
48749#[cfg(target_endian = "little")]
48750#[target_feature(enable = "neon")]
48751#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48752#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48753#[cfg_attr(
48754 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48755 assert_instr(nop)
48756)]
48757#[cfg_attr(
48758 not(target_arch = "arm"),
48759 stable(feature = "neon_intrinsics", since = "1.59.0")
48760)]
48761#[cfg_attr(
48762 target_arch = "arm",
48763 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48764)]
48765pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
48766 unsafe { transmute(a) }
48767}
48768#[doc = "Vector reinterpret cast operation"]
48769#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
48770#[inline]
48771#[cfg(target_endian = "big")]
48772#[target_feature(enable = "neon")]
48773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48774#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48775#[cfg_attr(
48776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48777 assert_instr(nop)
48778)]
48779#[cfg_attr(
48780 not(target_arch = "arm"),
48781 stable(feature = "neon_intrinsics", since = "1.59.0")
48782)]
48783#[cfg_attr(
48784 target_arch = "arm",
48785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48786)]
48787pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
48788 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
48789 unsafe {
48790 let ret_val: poly16x8_t = transmute(a);
48791 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48792 }
48793}
48794#[doc = "Vector reinterpret cast operation"]
48795#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
48796#[inline]
48797#[cfg(target_endian = "little")]
48798#[target_feature(enable = "neon")]
48799#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48800#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48801#[cfg_attr(
48802 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48803 assert_instr(nop)
48804)]
48805#[cfg_attr(
48806 not(target_arch = "arm"),
48807 stable(feature = "neon_intrinsics", since = "1.59.0")
48808)]
48809#[cfg_attr(
48810 target_arch = "arm",
48811 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48812)]
48813pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
48814 unsafe { transmute(a) }
48815}
48816#[doc = "Vector reinterpret cast operation"]
48817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
48818#[inline]
48819#[cfg(target_endian = "big")]
48820#[target_feature(enable = "neon")]
48821#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48822#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48823#[cfg_attr(
48824 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48825 assert_instr(nop)
48826)]
48827#[cfg_attr(
48828 not(target_arch = "arm"),
48829 stable(feature = "neon_intrinsics", since = "1.59.0")
48830)]
48831#[cfg_attr(
48832 target_arch = "arm",
48833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48834)]
48835pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
48836 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48837 unsafe {
48838 let ret_val: float32x2_t = transmute(a);
48839 simd_shuffle!(ret_val, ret_val, [1, 0])
48840 }
48841}
48842#[doc = "Vector reinterpret cast operation"]
48843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
48844#[inline]
48845#[cfg(target_endian = "little")]
48846#[target_feature(enable = "neon")]
48847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48849#[cfg_attr(
48850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48851 assert_instr(nop)
48852)]
48853#[cfg_attr(
48854 not(target_arch = "arm"),
48855 stable(feature = "neon_intrinsics", since = "1.59.0")
48856)]
48857#[cfg_attr(
48858 target_arch = "arm",
48859 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48860)]
48861pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
48862 unsafe { transmute(a) }
48863}
48864#[doc = "Vector reinterpret cast operation"]
48865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
48866#[inline]
48867#[cfg(target_endian = "big")]
48868#[target_feature(enable = "neon")]
48869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48871#[cfg_attr(
48872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48873 assert_instr(nop)
48874)]
48875#[cfg_attr(
48876 not(target_arch = "arm"),
48877 stable(feature = "neon_intrinsics", since = "1.59.0")
48878)]
48879#[cfg_attr(
48880 target_arch = "arm",
48881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48882)]
48883pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
48884 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48885 unsafe {
48886 let ret_val: int8x8_t = transmute(a);
48887 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
48888 }
48889}
48890#[doc = "Vector reinterpret cast operation"]
48891#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
48892#[inline]
48893#[cfg(target_endian = "little")]
48894#[target_feature(enable = "neon")]
48895#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48896#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48897#[cfg_attr(
48898 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48899 assert_instr(nop)
48900)]
48901#[cfg_attr(
48902 not(target_arch = "arm"),
48903 stable(feature = "neon_intrinsics", since = "1.59.0")
48904)]
48905#[cfg_attr(
48906 target_arch = "arm",
48907 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48908)]
48909pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
48910 unsafe { transmute(a) }
48911}
48912#[doc = "Vector reinterpret cast operation"]
48913#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
48914#[inline]
48915#[cfg(target_endian = "big")]
48916#[target_feature(enable = "neon")]
48917#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48918#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48919#[cfg_attr(
48920 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48921 assert_instr(nop)
48922)]
48923#[cfg_attr(
48924 not(target_arch = "arm"),
48925 stable(feature = "neon_intrinsics", since = "1.59.0")
48926)]
48927#[cfg_attr(
48928 target_arch = "arm",
48929 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48930)]
48931pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
48932 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48933 unsafe {
48934 let ret_val: int16x4_t = transmute(a);
48935 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
48936 }
48937}
48938#[doc = "Vector reinterpret cast operation"]
48939#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
48940#[inline]
48941#[cfg(target_endian = "little")]
48942#[target_feature(enable = "neon")]
48943#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48944#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48945#[cfg_attr(
48946 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48947 assert_instr(nop)
48948)]
48949#[cfg_attr(
48950 not(target_arch = "arm"),
48951 stable(feature = "neon_intrinsics", since = "1.59.0")
48952)]
48953#[cfg_attr(
48954 target_arch = "arm",
48955 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48956)]
48957pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
48958 unsafe { transmute(a) }
48959}
48960#[doc = "Vector reinterpret cast operation"]
48961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
48962#[inline]
48963#[cfg(target_endian = "big")]
48964#[target_feature(enable = "neon")]
48965#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48966#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48967#[cfg_attr(
48968 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48969 assert_instr(nop)
48970)]
48971#[cfg_attr(
48972 not(target_arch = "arm"),
48973 stable(feature = "neon_intrinsics", since = "1.59.0")
48974)]
48975#[cfg_attr(
48976 target_arch = "arm",
48977 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
48978)]
48979pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
48980 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
48981 unsafe {
48982 let ret_val: int32x2_t = transmute(a);
48983 simd_shuffle!(ret_val, ret_val, [1, 0])
48984 }
48985}
48986#[doc = "Vector reinterpret cast operation"]
48987#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
48988#[inline]
48989#[cfg(target_endian = "little")]
48990#[target_feature(enable = "neon")]
48991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
48992#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
48993#[cfg_attr(
48994 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
48995 assert_instr(nop)
48996)]
48997#[cfg_attr(
48998 not(target_arch = "arm"),
48999 stable(feature = "neon_intrinsics", since = "1.59.0")
49000)]
49001#[cfg_attr(
49002 target_arch = "arm",
49003 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49004)]
49005pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49006 unsafe { transmute(a) }
49007}
49008#[doc = "Vector reinterpret cast operation"]
49009#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
49010#[inline]
49011#[cfg(target_endian = "big")]
49012#[target_feature(enable = "neon")]
49013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49014#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49015#[cfg_attr(
49016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49017 assert_instr(nop)
49018)]
49019#[cfg_attr(
49020 not(target_arch = "arm"),
49021 stable(feature = "neon_intrinsics", since = "1.59.0")
49022)]
49023#[cfg_attr(
49024 target_arch = "arm",
49025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49026)]
49027pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
49028 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49029 unsafe { transmute(a) }
49030}
49031#[doc = "Vector reinterpret cast operation"]
49032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49033#[inline]
49034#[cfg(target_endian = "little")]
49035#[target_feature(enable = "neon")]
49036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49037#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49038#[cfg_attr(
49039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49040 assert_instr(nop)
49041)]
49042#[cfg_attr(
49043 not(target_arch = "arm"),
49044 stable(feature = "neon_intrinsics", since = "1.59.0")
49045)]
49046#[cfg_attr(
49047 target_arch = "arm",
49048 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49049)]
49050pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49051 unsafe { transmute(a) }
49052}
49053#[doc = "Vector reinterpret cast operation"]
49054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
49055#[inline]
49056#[cfg(target_endian = "big")]
49057#[target_feature(enable = "neon")]
49058#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49059#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49060#[cfg_attr(
49061 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49062 assert_instr(nop)
49063)]
49064#[cfg_attr(
49065 not(target_arch = "arm"),
49066 stable(feature = "neon_intrinsics", since = "1.59.0")
49067)]
49068#[cfg_attr(
49069 target_arch = "arm",
49070 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49071)]
49072pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
49073 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49074 unsafe {
49075 let ret_val: uint16x4_t = transmute(a);
49076 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49077 }
49078}
49079#[doc = "Vector reinterpret cast operation"]
49080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49081#[inline]
49082#[cfg(target_endian = "little")]
49083#[target_feature(enable = "neon")]
49084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49085#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49086#[cfg_attr(
49087 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49088 assert_instr(nop)
49089)]
49090#[cfg_attr(
49091 not(target_arch = "arm"),
49092 stable(feature = "neon_intrinsics", since = "1.59.0")
49093)]
49094#[cfg_attr(
49095 target_arch = "arm",
49096 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49097)]
49098pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49099 unsafe { transmute(a) }
49100}
49101#[doc = "Vector reinterpret cast operation"]
49102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
49103#[inline]
49104#[cfg(target_endian = "big")]
49105#[target_feature(enable = "neon")]
49106#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49108#[cfg_attr(
49109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49110 assert_instr(nop)
49111)]
49112#[cfg_attr(
49113 not(target_arch = "arm"),
49114 stable(feature = "neon_intrinsics", since = "1.59.0")
49115)]
49116#[cfg_attr(
49117 target_arch = "arm",
49118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49119)]
49120pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
49121 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49122 unsafe {
49123 let ret_val: uint32x2_t = transmute(a);
49124 simd_shuffle!(ret_val, ret_val, [1, 0])
49125 }
49126}
49127#[doc = "Vector reinterpret cast operation"]
49128#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49129#[inline]
49130#[cfg(target_endian = "little")]
49131#[target_feature(enable = "neon")]
49132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49134#[cfg_attr(
49135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49136 assert_instr(nop)
49137)]
49138#[cfg_attr(
49139 not(target_arch = "arm"),
49140 stable(feature = "neon_intrinsics", since = "1.59.0")
49141)]
49142#[cfg_attr(
49143 target_arch = "arm",
49144 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49145)]
49146pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49147 unsafe { transmute(a) }
49148}
49149#[doc = "Vector reinterpret cast operation"]
49150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
49151#[inline]
49152#[cfg(target_endian = "big")]
49153#[target_feature(enable = "neon")]
49154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49156#[cfg_attr(
49157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49158 assert_instr(nop)
49159)]
49160#[cfg_attr(
49161 not(target_arch = "arm"),
49162 stable(feature = "neon_intrinsics", since = "1.59.0")
49163)]
49164#[cfg_attr(
49165 target_arch = "arm",
49166 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49167)]
49168pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
49169 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49170 unsafe { transmute(a) }
49171}
49172#[doc = "Vector reinterpret cast operation"]
49173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49174#[inline]
49175#[cfg(target_endian = "little")]
49176#[target_feature(enable = "neon")]
49177#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49178#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49179#[cfg_attr(
49180 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49181 assert_instr(nop)
49182)]
49183#[cfg_attr(
49184 not(target_arch = "arm"),
49185 stable(feature = "neon_intrinsics", since = "1.59.0")
49186)]
49187#[cfg_attr(
49188 target_arch = "arm",
49189 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49190)]
49191pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49192 unsafe { transmute(a) }
49193}
49194#[doc = "Vector reinterpret cast operation"]
49195#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
49196#[inline]
49197#[cfg(target_endian = "big")]
49198#[target_feature(enable = "neon")]
49199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49201#[cfg_attr(
49202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49203 assert_instr(nop)
49204)]
49205#[cfg_attr(
49206 not(target_arch = "arm"),
49207 stable(feature = "neon_intrinsics", since = "1.59.0")
49208)]
49209#[cfg_attr(
49210 target_arch = "arm",
49211 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49212)]
49213pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
49214 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49215 unsafe {
49216 let ret_val: poly8x8_t = transmute(a);
49217 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49218 }
49219}
49220#[doc = "Vector reinterpret cast operation"]
49221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49222#[inline]
49223#[cfg(target_endian = "little")]
49224#[target_feature(enable = "neon")]
49225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49227#[cfg_attr(
49228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49229 assert_instr(nop)
49230)]
49231#[cfg_attr(
49232 not(target_arch = "arm"),
49233 stable(feature = "neon_intrinsics", since = "1.59.0")
49234)]
49235#[cfg_attr(
49236 target_arch = "arm",
49237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49238)]
49239pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49240 unsafe { transmute(a) }
49241}
49242#[doc = "Vector reinterpret cast operation"]
49243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
49244#[inline]
49245#[cfg(target_endian = "big")]
49246#[target_feature(enable = "neon")]
49247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49249#[cfg_attr(
49250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49251 assert_instr(nop)
49252)]
49253#[cfg_attr(
49254 not(target_arch = "arm"),
49255 stable(feature = "neon_intrinsics", since = "1.59.0")
49256)]
49257#[cfg_attr(
49258 target_arch = "arm",
49259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49260)]
49261pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
49262 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
49263 unsafe {
49264 let ret_val: poly16x4_t = transmute(a);
49265 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49266 }
49267}
49268#[doc = "Vector reinterpret cast operation"]
49269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49270#[inline]
49271#[cfg(target_endian = "little")]
49272#[target_feature(enable = "neon")]
49273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49275#[cfg_attr(
49276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49277 assert_instr(nop)
49278)]
49279#[cfg_attr(
49280 not(target_arch = "arm"),
49281 stable(feature = "neon_intrinsics", since = "1.59.0")
49282)]
49283#[cfg_attr(
49284 target_arch = "arm",
49285 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49286)]
49287pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49288 unsafe { transmute(a) }
49289}
49290#[doc = "Vector reinterpret cast operation"]
49291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
49292#[inline]
49293#[cfg(target_endian = "big")]
49294#[target_feature(enable = "neon")]
49295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49297#[cfg_attr(
49298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49299 assert_instr(nop)
49300)]
49301#[cfg_attr(
49302 not(target_arch = "arm"),
49303 stable(feature = "neon_intrinsics", since = "1.59.0")
49304)]
49305#[cfg_attr(
49306 target_arch = "arm",
49307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49308)]
49309pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
49310 let a: uint8x16_t =
49311 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49312 unsafe {
49313 let ret_val: float32x4_t = transmute(a);
49314 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49315 }
49316}
49317#[doc = "Vector reinterpret cast operation"]
49318#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49319#[inline]
49320#[cfg(target_endian = "little")]
49321#[target_feature(enable = "neon")]
49322#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49323#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49324#[cfg_attr(
49325 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49326 assert_instr(nop)
49327)]
49328#[cfg_attr(
49329 not(target_arch = "arm"),
49330 stable(feature = "neon_intrinsics", since = "1.59.0")
49331)]
49332#[cfg_attr(
49333 target_arch = "arm",
49334 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49335)]
49336pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49337 unsafe { transmute(a) }
49338}
49339#[doc = "Vector reinterpret cast operation"]
49340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
49341#[inline]
49342#[cfg(target_endian = "big")]
49343#[target_feature(enable = "neon")]
49344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49346#[cfg_attr(
49347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49348 assert_instr(nop)
49349)]
49350#[cfg_attr(
49351 not(target_arch = "arm"),
49352 stable(feature = "neon_intrinsics", since = "1.59.0")
49353)]
49354#[cfg_attr(
49355 target_arch = "arm",
49356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49357)]
49358pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
49359 let a: uint8x16_t =
49360 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49361 unsafe {
49362 let ret_val: int8x16_t = transmute(a);
49363 simd_shuffle!(
49364 ret_val,
49365 ret_val,
49366 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49367 )
49368 }
49369}
49370#[doc = "Vector reinterpret cast operation"]
49371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49372#[inline]
49373#[cfg(target_endian = "little")]
49374#[target_feature(enable = "neon")]
49375#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49377#[cfg_attr(
49378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49379 assert_instr(nop)
49380)]
49381#[cfg_attr(
49382 not(target_arch = "arm"),
49383 stable(feature = "neon_intrinsics", since = "1.59.0")
49384)]
49385#[cfg_attr(
49386 target_arch = "arm",
49387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49388)]
49389pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49390 unsafe { transmute(a) }
49391}
49392#[doc = "Vector reinterpret cast operation"]
49393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
49394#[inline]
49395#[cfg(target_endian = "big")]
49396#[target_feature(enable = "neon")]
49397#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49398#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49399#[cfg_attr(
49400 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49401 assert_instr(nop)
49402)]
49403#[cfg_attr(
49404 not(target_arch = "arm"),
49405 stable(feature = "neon_intrinsics", since = "1.59.0")
49406)]
49407#[cfg_attr(
49408 target_arch = "arm",
49409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49410)]
49411pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
49412 let a: uint8x16_t =
49413 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49414 unsafe {
49415 let ret_val: int16x8_t = transmute(a);
49416 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49417 }
49418}
49419#[doc = "Vector reinterpret cast operation"]
49420#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49421#[inline]
49422#[cfg(target_endian = "little")]
49423#[target_feature(enable = "neon")]
49424#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49425#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49426#[cfg_attr(
49427 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49428 assert_instr(nop)
49429)]
49430#[cfg_attr(
49431 not(target_arch = "arm"),
49432 stable(feature = "neon_intrinsics", since = "1.59.0")
49433)]
49434#[cfg_attr(
49435 target_arch = "arm",
49436 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49437)]
49438pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49439 unsafe { transmute(a) }
49440}
49441#[doc = "Vector reinterpret cast operation"]
49442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
49443#[inline]
49444#[cfg(target_endian = "big")]
49445#[target_feature(enable = "neon")]
49446#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49447#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49448#[cfg_attr(
49449 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49450 assert_instr(nop)
49451)]
49452#[cfg_attr(
49453 not(target_arch = "arm"),
49454 stable(feature = "neon_intrinsics", since = "1.59.0")
49455)]
49456#[cfg_attr(
49457 target_arch = "arm",
49458 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49459)]
49460pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
49461 let a: uint8x16_t =
49462 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49463 unsafe {
49464 let ret_val: int32x4_t = transmute(a);
49465 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49466 }
49467}
49468#[doc = "Vector reinterpret cast operation"]
49469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49470#[inline]
49471#[cfg(target_endian = "little")]
49472#[target_feature(enable = "neon")]
49473#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49474#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49475#[cfg_attr(
49476 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49477 assert_instr(nop)
49478)]
49479#[cfg_attr(
49480 not(target_arch = "arm"),
49481 stable(feature = "neon_intrinsics", since = "1.59.0")
49482)]
49483#[cfg_attr(
49484 target_arch = "arm",
49485 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49486)]
49487pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49488 unsafe { transmute(a) }
49489}
49490#[doc = "Vector reinterpret cast operation"]
49491#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
49492#[inline]
49493#[cfg(target_endian = "big")]
49494#[target_feature(enable = "neon")]
49495#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49496#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49497#[cfg_attr(
49498 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49499 assert_instr(nop)
49500)]
49501#[cfg_attr(
49502 not(target_arch = "arm"),
49503 stable(feature = "neon_intrinsics", since = "1.59.0")
49504)]
49505#[cfg_attr(
49506 target_arch = "arm",
49507 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49508)]
49509pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
49510 let a: uint8x16_t =
49511 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49512 unsafe {
49513 let ret_val: int64x2_t = transmute(a);
49514 simd_shuffle!(ret_val, ret_val, [1, 0])
49515 }
49516}
49517#[doc = "Vector reinterpret cast operation"]
49518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49519#[inline]
49520#[cfg(target_endian = "little")]
49521#[target_feature(enable = "neon")]
49522#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49524#[cfg_attr(
49525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49526 assert_instr(nop)
49527)]
49528#[cfg_attr(
49529 not(target_arch = "arm"),
49530 stable(feature = "neon_intrinsics", since = "1.59.0")
49531)]
49532#[cfg_attr(
49533 target_arch = "arm",
49534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49535)]
49536pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49537 unsafe { transmute(a) }
49538}
49539#[doc = "Vector reinterpret cast operation"]
49540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
49541#[inline]
49542#[cfg(target_endian = "big")]
49543#[target_feature(enable = "neon")]
49544#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49546#[cfg_attr(
49547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49548 assert_instr(nop)
49549)]
49550#[cfg_attr(
49551 not(target_arch = "arm"),
49552 stable(feature = "neon_intrinsics", since = "1.59.0")
49553)]
49554#[cfg_attr(
49555 target_arch = "arm",
49556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49557)]
49558pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
49559 let a: uint8x16_t =
49560 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49561 unsafe {
49562 let ret_val: uint16x8_t = transmute(a);
49563 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49564 }
49565}
49566#[doc = "Vector reinterpret cast operation"]
49567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
49568#[inline]
49569#[cfg(target_endian = "little")]
49570#[target_feature(enable = "neon")]
49571#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49572#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49573#[cfg_attr(
49574 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49575 assert_instr(nop)
49576)]
49577#[cfg_attr(
49578 not(target_arch = "arm"),
49579 stable(feature = "neon_intrinsics", since = "1.59.0")
49580)]
49581#[cfg_attr(
49582 target_arch = "arm",
49583 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49584)]
49585pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
49586 unsafe { transmute(a) }
49587}
49588#[doc = "Vector reinterpret cast operation"]
49589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
49590#[inline]
49591#[cfg(target_endian = "big")]
49592#[target_feature(enable = "neon")]
49593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49594#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49595#[cfg_attr(
49596 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49597 assert_instr(nop)
49598)]
49599#[cfg_attr(
49600 not(target_arch = "arm"),
49601 stable(feature = "neon_intrinsics", since = "1.59.0")
49602)]
49603#[cfg_attr(
49604 target_arch = "arm",
49605 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49606)]
49607pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
49608 let a: uint8x16_t =
49609 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49610 unsafe {
49611 let ret_val: uint32x4_t = transmute(a);
49612 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49613 }
49614}
49615#[doc = "Vector reinterpret cast operation"]
49616#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
49617#[inline]
49618#[cfg(target_endian = "little")]
49619#[target_feature(enable = "neon")]
49620#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49621#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49622#[cfg_attr(
49623 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49624 assert_instr(nop)
49625)]
49626#[cfg_attr(
49627 not(target_arch = "arm"),
49628 stable(feature = "neon_intrinsics", since = "1.59.0")
49629)]
49630#[cfg_attr(
49631 target_arch = "arm",
49632 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49633)]
49634pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
49635 unsafe { transmute(a) }
49636}
49637#[doc = "Vector reinterpret cast operation"]
49638#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
49639#[inline]
49640#[cfg(target_endian = "big")]
49641#[target_feature(enable = "neon")]
49642#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49643#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49644#[cfg_attr(
49645 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49646 assert_instr(nop)
49647)]
49648#[cfg_attr(
49649 not(target_arch = "arm"),
49650 stable(feature = "neon_intrinsics", since = "1.59.0")
49651)]
49652#[cfg_attr(
49653 target_arch = "arm",
49654 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49655)]
49656pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
49657 let a: uint8x16_t =
49658 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49659 unsafe {
49660 let ret_val: uint64x2_t = transmute(a);
49661 simd_shuffle!(ret_val, ret_val, [1, 0])
49662 }
49663}
49664#[doc = "Vector reinterpret cast operation"]
49665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
49666#[inline]
49667#[cfg(target_endian = "little")]
49668#[target_feature(enable = "neon")]
49669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49671#[cfg_attr(
49672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49673 assert_instr(nop)
49674)]
49675#[cfg_attr(
49676 not(target_arch = "arm"),
49677 stable(feature = "neon_intrinsics", since = "1.59.0")
49678)]
49679#[cfg_attr(
49680 target_arch = "arm",
49681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49682)]
49683pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
49684 unsafe { transmute(a) }
49685}
49686#[doc = "Vector reinterpret cast operation"]
49687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
49688#[inline]
49689#[cfg(target_endian = "big")]
49690#[target_feature(enable = "neon")]
49691#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49692#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49693#[cfg_attr(
49694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49695 assert_instr(nop)
49696)]
49697#[cfg_attr(
49698 not(target_arch = "arm"),
49699 stable(feature = "neon_intrinsics", since = "1.59.0")
49700)]
49701#[cfg_attr(
49702 target_arch = "arm",
49703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49704)]
49705pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
49706 let a: uint8x16_t =
49707 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49708 unsafe {
49709 let ret_val: poly8x16_t = transmute(a);
49710 simd_shuffle!(
49711 ret_val,
49712 ret_val,
49713 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
49714 )
49715 }
49716}
49717#[doc = "Vector reinterpret cast operation"]
49718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
49719#[inline]
49720#[cfg(target_endian = "little")]
49721#[target_feature(enable = "neon")]
49722#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49724#[cfg_attr(
49725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49726 assert_instr(nop)
49727)]
49728#[cfg_attr(
49729 not(target_arch = "arm"),
49730 stable(feature = "neon_intrinsics", since = "1.59.0")
49731)]
49732#[cfg_attr(
49733 target_arch = "arm",
49734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49735)]
49736pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
49737 unsafe { transmute(a) }
49738}
49739#[doc = "Vector reinterpret cast operation"]
49740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
49741#[inline]
49742#[cfg(target_endian = "big")]
49743#[target_feature(enable = "neon")]
49744#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49746#[cfg_attr(
49747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49748 assert_instr(nop)
49749)]
49750#[cfg_attr(
49751 not(target_arch = "arm"),
49752 stable(feature = "neon_intrinsics", since = "1.59.0")
49753)]
49754#[cfg_attr(
49755 target_arch = "arm",
49756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49757)]
49758pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
49759 let a: uint8x16_t =
49760 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
49761 unsafe {
49762 let ret_val: poly16x8_t = transmute(a);
49763 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49764 }
49765}
49766#[doc = "Vector reinterpret cast operation"]
49767#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
49768#[inline]
49769#[cfg(target_endian = "little")]
49770#[target_feature(enable = "neon")]
49771#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49772#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49773#[cfg_attr(
49774 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49775 assert_instr(nop)
49776)]
49777#[cfg_attr(
49778 not(target_arch = "arm"),
49779 stable(feature = "neon_intrinsics", since = "1.59.0")
49780)]
49781#[cfg_attr(
49782 target_arch = "arm",
49783 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49784)]
49785pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
49786 unsafe { transmute(a) }
49787}
49788#[doc = "Vector reinterpret cast operation"]
49789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
49790#[inline]
49791#[cfg(target_endian = "big")]
49792#[target_feature(enable = "neon")]
49793#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49794#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49795#[cfg_attr(
49796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49797 assert_instr(nop)
49798)]
49799#[cfg_attr(
49800 not(target_arch = "arm"),
49801 stable(feature = "neon_intrinsics", since = "1.59.0")
49802)]
49803#[cfg_attr(
49804 target_arch = "arm",
49805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49806)]
49807pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
49808 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49809 unsafe {
49810 let ret_val: float32x2_t = transmute(a);
49811 simd_shuffle!(ret_val, ret_val, [1, 0])
49812 }
49813}
49814#[doc = "Vector reinterpret cast operation"]
49815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
49816#[inline]
49817#[cfg(target_endian = "little")]
49818#[target_feature(enable = "neon")]
49819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49821#[cfg_attr(
49822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49823 assert_instr(nop)
49824)]
49825#[cfg_attr(
49826 not(target_arch = "arm"),
49827 stable(feature = "neon_intrinsics", since = "1.59.0")
49828)]
49829#[cfg_attr(
49830 target_arch = "arm",
49831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49832)]
49833pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
49834 unsafe { transmute(a) }
49835}
49836#[doc = "Vector reinterpret cast operation"]
49837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
49838#[inline]
49839#[cfg(target_endian = "big")]
49840#[target_feature(enable = "neon")]
49841#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49842#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49843#[cfg_attr(
49844 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49845 assert_instr(nop)
49846)]
49847#[cfg_attr(
49848 not(target_arch = "arm"),
49849 stable(feature = "neon_intrinsics", since = "1.59.0")
49850)]
49851#[cfg_attr(
49852 target_arch = "arm",
49853 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49854)]
49855pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
49856 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49857 unsafe {
49858 let ret_val: int8x8_t = transmute(a);
49859 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
49860 }
49861}
49862#[doc = "Vector reinterpret cast operation"]
49863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
49864#[inline]
49865#[cfg(target_endian = "little")]
49866#[target_feature(enable = "neon")]
49867#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49869#[cfg_attr(
49870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49871 assert_instr(nop)
49872)]
49873#[cfg_attr(
49874 not(target_arch = "arm"),
49875 stable(feature = "neon_intrinsics", since = "1.59.0")
49876)]
49877#[cfg_attr(
49878 target_arch = "arm",
49879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49880)]
49881pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
49882 unsafe { transmute(a) }
49883}
49884#[doc = "Vector reinterpret cast operation"]
49885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
49886#[inline]
49887#[cfg(target_endian = "big")]
49888#[target_feature(enable = "neon")]
49889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49891#[cfg_attr(
49892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49893 assert_instr(nop)
49894)]
49895#[cfg_attr(
49896 not(target_arch = "arm"),
49897 stable(feature = "neon_intrinsics", since = "1.59.0")
49898)]
49899#[cfg_attr(
49900 target_arch = "arm",
49901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49902)]
49903pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
49904 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49905 unsafe {
49906 let ret_val: int16x4_t = transmute(a);
49907 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
49908 }
49909}
49910#[doc = "Vector reinterpret cast operation"]
49911#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
49912#[inline]
49913#[cfg(target_endian = "little")]
49914#[target_feature(enable = "neon")]
49915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49917#[cfg_attr(
49918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49919 assert_instr(nop)
49920)]
49921#[cfg_attr(
49922 not(target_arch = "arm"),
49923 stable(feature = "neon_intrinsics", since = "1.59.0")
49924)]
49925#[cfg_attr(
49926 target_arch = "arm",
49927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49928)]
49929pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
49930 unsafe { transmute(a) }
49931}
49932#[doc = "Vector reinterpret cast operation"]
49933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
49934#[inline]
49935#[cfg(target_endian = "big")]
49936#[target_feature(enable = "neon")]
49937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49939#[cfg_attr(
49940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49941 assert_instr(nop)
49942)]
49943#[cfg_attr(
49944 not(target_arch = "arm"),
49945 stable(feature = "neon_intrinsics", since = "1.59.0")
49946)]
49947#[cfg_attr(
49948 target_arch = "arm",
49949 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49950)]
49951pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
49952 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
49953 unsafe {
49954 let ret_val: int32x2_t = transmute(a);
49955 simd_shuffle!(ret_val, ret_val, [1, 0])
49956 }
49957}
49958#[doc = "Vector reinterpret cast operation"]
49959#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
49960#[inline]
49961#[cfg(target_endian = "little")]
49962#[target_feature(enable = "neon")]
49963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49965#[cfg_attr(
49966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49967 assert_instr(nop)
49968)]
49969#[cfg_attr(
49970 not(target_arch = "arm"),
49971 stable(feature = "neon_intrinsics", since = "1.59.0")
49972)]
49973#[cfg_attr(
49974 target_arch = "arm",
49975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49976)]
49977pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
49978 unsafe { transmute(a) }
49979}
49980#[doc = "Vector reinterpret cast operation"]
49981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
49982#[inline]
49983#[cfg(target_endian = "big")]
49984#[target_feature(enable = "neon")]
49985#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
49986#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
49987#[cfg_attr(
49988 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
49989 assert_instr(nop)
49990)]
49991#[cfg_attr(
49992 not(target_arch = "arm"),
49993 stable(feature = "neon_intrinsics", since = "1.59.0")
49994)]
49995#[cfg_attr(
49996 target_arch = "arm",
49997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
49998)]
49999pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
50000 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50001 unsafe { transmute(a) }
50002}
50003#[doc = "Vector reinterpret cast operation"]
50004#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50005#[inline]
50006#[cfg(target_endian = "little")]
50007#[target_feature(enable = "neon")]
50008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50009#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50010#[cfg_attr(
50011 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50012 assert_instr(nop)
50013)]
50014#[cfg_attr(
50015 not(target_arch = "arm"),
50016 stable(feature = "neon_intrinsics", since = "1.59.0")
50017)]
50018#[cfg_attr(
50019 target_arch = "arm",
50020 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50021)]
50022pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50023 unsafe { transmute(a) }
50024}
50025#[doc = "Vector reinterpret cast operation"]
50026#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
50027#[inline]
50028#[cfg(target_endian = "big")]
50029#[target_feature(enable = "neon")]
50030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50031#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50032#[cfg_attr(
50033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50034 assert_instr(nop)
50035)]
50036#[cfg_attr(
50037 not(target_arch = "arm"),
50038 stable(feature = "neon_intrinsics", since = "1.59.0")
50039)]
50040#[cfg_attr(
50041 target_arch = "arm",
50042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50043)]
50044pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
50045 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50046 unsafe {
50047 let ret_val: uint8x8_t = transmute(a);
50048 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50049 }
50050}
50051#[doc = "Vector reinterpret cast operation"]
50052#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50053#[inline]
50054#[cfg(target_endian = "little")]
50055#[target_feature(enable = "neon")]
50056#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50057#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50058#[cfg_attr(
50059 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50060 assert_instr(nop)
50061)]
50062#[cfg_attr(
50063 not(target_arch = "arm"),
50064 stable(feature = "neon_intrinsics", since = "1.59.0")
50065)]
50066#[cfg_attr(
50067 target_arch = "arm",
50068 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50069)]
50070pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50071 unsafe { transmute(a) }
50072}
50073#[doc = "Vector reinterpret cast operation"]
50074#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
50075#[inline]
50076#[cfg(target_endian = "big")]
50077#[target_feature(enable = "neon")]
50078#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50079#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50080#[cfg_attr(
50081 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50082 assert_instr(nop)
50083)]
50084#[cfg_attr(
50085 not(target_arch = "arm"),
50086 stable(feature = "neon_intrinsics", since = "1.59.0")
50087)]
50088#[cfg_attr(
50089 target_arch = "arm",
50090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50091)]
50092pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
50093 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50094 unsafe {
50095 let ret_val: uint32x2_t = transmute(a);
50096 simd_shuffle!(ret_val, ret_val, [1, 0])
50097 }
50098}
50099#[doc = "Vector reinterpret cast operation"]
50100#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50101#[inline]
50102#[cfg(target_endian = "little")]
50103#[target_feature(enable = "neon")]
50104#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50105#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50106#[cfg_attr(
50107 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50108 assert_instr(nop)
50109)]
50110#[cfg_attr(
50111 not(target_arch = "arm"),
50112 stable(feature = "neon_intrinsics", since = "1.59.0")
50113)]
50114#[cfg_attr(
50115 target_arch = "arm",
50116 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50117)]
50118pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50119 unsafe { transmute(a) }
50120}
50121#[doc = "Vector reinterpret cast operation"]
50122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
50123#[inline]
50124#[cfg(target_endian = "big")]
50125#[target_feature(enable = "neon")]
50126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50127#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50128#[cfg_attr(
50129 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50130 assert_instr(nop)
50131)]
50132#[cfg_attr(
50133 not(target_arch = "arm"),
50134 stable(feature = "neon_intrinsics", since = "1.59.0")
50135)]
50136#[cfg_attr(
50137 target_arch = "arm",
50138 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50139)]
50140pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
50141 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50142 unsafe { transmute(a) }
50143}
50144#[doc = "Vector reinterpret cast operation"]
50145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50146#[inline]
50147#[cfg(target_endian = "little")]
50148#[target_feature(enable = "neon")]
50149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50150#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50151#[cfg_attr(
50152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50153 assert_instr(nop)
50154)]
50155#[cfg_attr(
50156 not(target_arch = "arm"),
50157 stable(feature = "neon_intrinsics", since = "1.59.0")
50158)]
50159#[cfg_attr(
50160 target_arch = "arm",
50161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50162)]
50163pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50164 unsafe { transmute(a) }
50165}
50166#[doc = "Vector reinterpret cast operation"]
50167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
50168#[inline]
50169#[cfg(target_endian = "big")]
50170#[target_feature(enable = "neon")]
50171#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50172#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50173#[cfg_attr(
50174 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50175 assert_instr(nop)
50176)]
50177#[cfg_attr(
50178 not(target_arch = "arm"),
50179 stable(feature = "neon_intrinsics", since = "1.59.0")
50180)]
50181#[cfg_attr(
50182 target_arch = "arm",
50183 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50184)]
50185pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
50186 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50187 unsafe {
50188 let ret_val: poly8x8_t = transmute(a);
50189 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50190 }
50191}
50192#[doc = "Vector reinterpret cast operation"]
50193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50194#[inline]
50195#[cfg(target_endian = "little")]
50196#[target_feature(enable = "neon")]
50197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50199#[cfg_attr(
50200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50201 assert_instr(nop)
50202)]
50203#[cfg_attr(
50204 not(target_arch = "arm"),
50205 stable(feature = "neon_intrinsics", since = "1.59.0")
50206)]
50207#[cfg_attr(
50208 target_arch = "arm",
50209 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50210)]
50211pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50212 unsafe { transmute(a) }
50213}
50214#[doc = "Vector reinterpret cast operation"]
50215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
50216#[inline]
50217#[cfg(target_endian = "big")]
50218#[target_feature(enable = "neon")]
50219#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50221#[cfg_attr(
50222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50223 assert_instr(nop)
50224)]
50225#[cfg_attr(
50226 not(target_arch = "arm"),
50227 stable(feature = "neon_intrinsics", since = "1.59.0")
50228)]
50229#[cfg_attr(
50230 target_arch = "arm",
50231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50232)]
50233pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
50234 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
50235 unsafe {
50236 let ret_val: poly16x4_t = transmute(a);
50237 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50238 }
50239}
50240#[doc = "Vector reinterpret cast operation"]
50241#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50242#[inline]
50243#[cfg(target_endian = "little")]
50244#[target_feature(enable = "neon")]
50245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50246#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50247#[cfg_attr(
50248 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50249 assert_instr(nop)
50250)]
50251#[cfg_attr(
50252 not(target_arch = "arm"),
50253 stable(feature = "neon_intrinsics", since = "1.59.0")
50254)]
50255#[cfg_attr(
50256 target_arch = "arm",
50257 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50258)]
50259pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50260 unsafe { transmute(a) }
50261}
50262#[doc = "Vector reinterpret cast operation"]
50263#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
50264#[inline]
50265#[cfg(target_endian = "big")]
50266#[target_feature(enable = "neon")]
50267#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50268#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50269#[cfg_attr(
50270 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50271 assert_instr(nop)
50272)]
50273#[cfg_attr(
50274 not(target_arch = "arm"),
50275 stable(feature = "neon_intrinsics", since = "1.59.0")
50276)]
50277#[cfg_attr(
50278 target_arch = "arm",
50279 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50280)]
50281pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
50282 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50283 unsafe {
50284 let ret_val: float32x4_t = transmute(a);
50285 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50286 }
50287}
50288#[doc = "Vector reinterpret cast operation"]
50289#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50290#[inline]
50291#[cfg(target_endian = "little")]
50292#[target_feature(enable = "neon")]
50293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50295#[cfg_attr(
50296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50297 assert_instr(nop)
50298)]
50299#[cfg_attr(
50300 not(target_arch = "arm"),
50301 stable(feature = "neon_intrinsics", since = "1.59.0")
50302)]
50303#[cfg_attr(
50304 target_arch = "arm",
50305 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50306)]
50307pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50308 unsafe { transmute(a) }
50309}
50310#[doc = "Vector reinterpret cast operation"]
50311#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
50312#[inline]
50313#[cfg(target_endian = "big")]
50314#[target_feature(enable = "neon")]
50315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50317#[cfg_attr(
50318 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50319 assert_instr(nop)
50320)]
50321#[cfg_attr(
50322 not(target_arch = "arm"),
50323 stable(feature = "neon_intrinsics", since = "1.59.0")
50324)]
50325#[cfg_attr(
50326 target_arch = "arm",
50327 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50328)]
50329pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
50330 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50331 unsafe {
50332 let ret_val: int8x16_t = transmute(a);
50333 simd_shuffle!(
50334 ret_val,
50335 ret_val,
50336 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50337 )
50338 }
50339}
50340#[doc = "Vector reinterpret cast operation"]
50341#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50342#[inline]
50343#[cfg(target_endian = "little")]
50344#[target_feature(enable = "neon")]
50345#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50346#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50347#[cfg_attr(
50348 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50349 assert_instr(nop)
50350)]
50351#[cfg_attr(
50352 not(target_arch = "arm"),
50353 stable(feature = "neon_intrinsics", since = "1.59.0")
50354)]
50355#[cfg_attr(
50356 target_arch = "arm",
50357 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50358)]
50359pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50360 unsafe { transmute(a) }
50361}
50362#[doc = "Vector reinterpret cast operation"]
50363#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
50364#[inline]
50365#[cfg(target_endian = "big")]
50366#[target_feature(enable = "neon")]
50367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50369#[cfg_attr(
50370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50371 assert_instr(nop)
50372)]
50373#[cfg_attr(
50374 not(target_arch = "arm"),
50375 stable(feature = "neon_intrinsics", since = "1.59.0")
50376)]
50377#[cfg_attr(
50378 target_arch = "arm",
50379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50380)]
50381pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
50382 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50383 unsafe {
50384 let ret_val: int16x8_t = transmute(a);
50385 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50386 }
50387}
50388#[doc = "Vector reinterpret cast operation"]
50389#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50390#[inline]
50391#[cfg(target_endian = "little")]
50392#[target_feature(enable = "neon")]
50393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50395#[cfg_attr(
50396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50397 assert_instr(nop)
50398)]
50399#[cfg_attr(
50400 not(target_arch = "arm"),
50401 stable(feature = "neon_intrinsics", since = "1.59.0")
50402)]
50403#[cfg_attr(
50404 target_arch = "arm",
50405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50406)]
50407pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50408 unsafe { transmute(a) }
50409}
50410#[doc = "Vector reinterpret cast operation"]
50411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
50412#[inline]
50413#[cfg(target_endian = "big")]
50414#[target_feature(enable = "neon")]
50415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50417#[cfg_attr(
50418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50419 assert_instr(nop)
50420)]
50421#[cfg_attr(
50422 not(target_arch = "arm"),
50423 stable(feature = "neon_intrinsics", since = "1.59.0")
50424)]
50425#[cfg_attr(
50426 target_arch = "arm",
50427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50428)]
50429pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
50430 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50431 unsafe {
50432 let ret_val: int32x4_t = transmute(a);
50433 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50434 }
50435}
50436#[doc = "Vector reinterpret cast operation"]
50437#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50438#[inline]
50439#[cfg(target_endian = "little")]
50440#[target_feature(enable = "neon")]
50441#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50442#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50443#[cfg_attr(
50444 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50445 assert_instr(nop)
50446)]
50447#[cfg_attr(
50448 not(target_arch = "arm"),
50449 stable(feature = "neon_intrinsics", since = "1.59.0")
50450)]
50451#[cfg_attr(
50452 target_arch = "arm",
50453 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50454)]
50455pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50456 unsafe { transmute(a) }
50457}
50458#[doc = "Vector reinterpret cast operation"]
50459#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
50460#[inline]
50461#[cfg(target_endian = "big")]
50462#[target_feature(enable = "neon")]
50463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50464#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50465#[cfg_attr(
50466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50467 assert_instr(nop)
50468)]
50469#[cfg_attr(
50470 not(target_arch = "arm"),
50471 stable(feature = "neon_intrinsics", since = "1.59.0")
50472)]
50473#[cfg_attr(
50474 target_arch = "arm",
50475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50476)]
50477pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
50478 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50479 unsafe {
50480 let ret_val: int64x2_t = transmute(a);
50481 simd_shuffle!(ret_val, ret_val, [1, 0])
50482 }
50483}
50484#[doc = "Vector reinterpret cast operation"]
50485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50486#[inline]
50487#[cfg(target_endian = "little")]
50488#[target_feature(enable = "neon")]
50489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50491#[cfg_attr(
50492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50493 assert_instr(nop)
50494)]
50495#[cfg_attr(
50496 not(target_arch = "arm"),
50497 stable(feature = "neon_intrinsics", since = "1.59.0")
50498)]
50499#[cfg_attr(
50500 target_arch = "arm",
50501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50502)]
50503pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50504 unsafe { transmute(a) }
50505}
50506#[doc = "Vector reinterpret cast operation"]
50507#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
50508#[inline]
50509#[cfg(target_endian = "big")]
50510#[target_feature(enable = "neon")]
50511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50513#[cfg_attr(
50514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50515 assert_instr(nop)
50516)]
50517#[cfg_attr(
50518 not(target_arch = "arm"),
50519 stable(feature = "neon_intrinsics", since = "1.59.0")
50520)]
50521#[cfg_attr(
50522 target_arch = "arm",
50523 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50524)]
50525pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
50526 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50527 unsafe {
50528 let ret_val: uint8x16_t = transmute(a);
50529 simd_shuffle!(
50530 ret_val,
50531 ret_val,
50532 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50533 )
50534 }
50535}
50536#[doc = "Vector reinterpret cast operation"]
50537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50538#[inline]
50539#[cfg(target_endian = "little")]
50540#[target_feature(enable = "neon")]
50541#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50543#[cfg_attr(
50544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50545 assert_instr(nop)
50546)]
50547#[cfg_attr(
50548 not(target_arch = "arm"),
50549 stable(feature = "neon_intrinsics", since = "1.59.0")
50550)]
50551#[cfg_attr(
50552 target_arch = "arm",
50553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50554)]
50555pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
50556 unsafe { transmute(a) }
50557}
50558#[doc = "Vector reinterpret cast operation"]
50559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
50560#[inline]
50561#[cfg(target_endian = "big")]
50562#[target_feature(enable = "neon")]
50563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50565#[cfg_attr(
50566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50567 assert_instr(nop)
50568)]
50569#[cfg_attr(
50570 not(target_arch = "arm"),
50571 stable(feature = "neon_intrinsics", since = "1.59.0")
50572)]
50573#[cfg_attr(
50574 target_arch = "arm",
50575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50576)]
50577pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
50578 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50579 unsafe {
50580 let ret_val: uint32x4_t = transmute(a);
50581 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50582 }
50583}
50584#[doc = "Vector reinterpret cast operation"]
50585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
50586#[inline]
50587#[cfg(target_endian = "little")]
50588#[target_feature(enable = "neon")]
50589#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50591#[cfg_attr(
50592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50593 assert_instr(nop)
50594)]
50595#[cfg_attr(
50596 not(target_arch = "arm"),
50597 stable(feature = "neon_intrinsics", since = "1.59.0")
50598)]
50599#[cfg_attr(
50600 target_arch = "arm",
50601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50602)]
50603pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
50604 unsafe { transmute(a) }
50605}
50606#[doc = "Vector reinterpret cast operation"]
50607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
50608#[inline]
50609#[cfg(target_endian = "big")]
50610#[target_feature(enable = "neon")]
50611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50613#[cfg_attr(
50614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50615 assert_instr(nop)
50616)]
50617#[cfg_attr(
50618 not(target_arch = "arm"),
50619 stable(feature = "neon_intrinsics", since = "1.59.0")
50620)]
50621#[cfg_attr(
50622 target_arch = "arm",
50623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50624)]
50625pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
50626 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50627 unsafe {
50628 let ret_val: uint64x2_t = transmute(a);
50629 simd_shuffle!(ret_val, ret_val, [1, 0])
50630 }
50631}
50632#[doc = "Vector reinterpret cast operation"]
50633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
50634#[inline]
50635#[cfg(target_endian = "little")]
50636#[target_feature(enable = "neon")]
50637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50639#[cfg_attr(
50640 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50641 assert_instr(nop)
50642)]
50643#[cfg_attr(
50644 not(target_arch = "arm"),
50645 stable(feature = "neon_intrinsics", since = "1.59.0")
50646)]
50647#[cfg_attr(
50648 target_arch = "arm",
50649 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50650)]
50651pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
50652 unsafe { transmute(a) }
50653}
50654#[doc = "Vector reinterpret cast operation"]
50655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
50656#[inline]
50657#[cfg(target_endian = "big")]
50658#[target_feature(enable = "neon")]
50659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50661#[cfg_attr(
50662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50663 assert_instr(nop)
50664)]
50665#[cfg_attr(
50666 not(target_arch = "arm"),
50667 stable(feature = "neon_intrinsics", since = "1.59.0")
50668)]
50669#[cfg_attr(
50670 target_arch = "arm",
50671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50672)]
50673pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
50674 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50675 unsafe {
50676 let ret_val: poly8x16_t = transmute(a);
50677 simd_shuffle!(
50678 ret_val,
50679 ret_val,
50680 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
50681 )
50682 }
50683}
50684#[doc = "Vector reinterpret cast operation"]
50685#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
50686#[inline]
50687#[cfg(target_endian = "little")]
50688#[target_feature(enable = "neon")]
50689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50690#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50691#[cfg_attr(
50692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50693 assert_instr(nop)
50694)]
50695#[cfg_attr(
50696 not(target_arch = "arm"),
50697 stable(feature = "neon_intrinsics", since = "1.59.0")
50698)]
50699#[cfg_attr(
50700 target_arch = "arm",
50701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50702)]
50703pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
50704 unsafe { transmute(a) }
50705}
50706#[doc = "Vector reinterpret cast operation"]
50707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
50708#[inline]
50709#[cfg(target_endian = "big")]
50710#[target_feature(enable = "neon")]
50711#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50712#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50713#[cfg_attr(
50714 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50715 assert_instr(nop)
50716)]
50717#[cfg_attr(
50718 not(target_arch = "arm"),
50719 stable(feature = "neon_intrinsics", since = "1.59.0")
50720)]
50721#[cfg_attr(
50722 target_arch = "arm",
50723 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50724)]
50725pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
50726 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
50727 unsafe {
50728 let ret_val: poly16x8_t = transmute(a);
50729 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50730 }
50731}
50732#[doc = "Vector reinterpret cast operation"]
50733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
50734#[inline]
50735#[cfg(target_endian = "little")]
50736#[target_feature(enable = "neon")]
50737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50739#[cfg_attr(
50740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50741 assert_instr(nop)
50742)]
50743#[cfg_attr(
50744 not(target_arch = "arm"),
50745 stable(feature = "neon_intrinsics", since = "1.59.0")
50746)]
50747#[cfg_attr(
50748 target_arch = "arm",
50749 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50750)]
50751pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
50752 unsafe { transmute(a) }
50753}
50754#[doc = "Vector reinterpret cast operation"]
50755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
50756#[inline]
50757#[cfg(target_endian = "big")]
50758#[target_feature(enable = "neon")]
50759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50761#[cfg_attr(
50762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50763 assert_instr(nop)
50764)]
50765#[cfg_attr(
50766 not(target_arch = "arm"),
50767 stable(feature = "neon_intrinsics", since = "1.59.0")
50768)]
50769#[cfg_attr(
50770 target_arch = "arm",
50771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50772)]
50773pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
50774 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50775 unsafe {
50776 let ret_val: float32x2_t = transmute(a);
50777 simd_shuffle!(ret_val, ret_val, [1, 0])
50778 }
50779}
50780#[doc = "Vector reinterpret cast operation"]
50781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
50782#[inline]
50783#[cfg(target_endian = "little")]
50784#[target_feature(enable = "neon")]
50785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50787#[cfg_attr(
50788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50789 assert_instr(nop)
50790)]
50791#[cfg_attr(
50792 not(target_arch = "arm"),
50793 stable(feature = "neon_intrinsics", since = "1.59.0")
50794)]
50795#[cfg_attr(
50796 target_arch = "arm",
50797 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50798)]
50799pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
50800 unsafe { transmute(a) }
50801}
50802#[doc = "Vector reinterpret cast operation"]
50803#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
50804#[inline]
50805#[cfg(target_endian = "big")]
50806#[target_feature(enable = "neon")]
50807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50809#[cfg_attr(
50810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50811 assert_instr(nop)
50812)]
50813#[cfg_attr(
50814 not(target_arch = "arm"),
50815 stable(feature = "neon_intrinsics", since = "1.59.0")
50816)]
50817#[cfg_attr(
50818 target_arch = "arm",
50819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50820)]
50821pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
50822 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50823 unsafe {
50824 let ret_val: int8x8_t = transmute(a);
50825 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
50826 }
50827}
50828#[doc = "Vector reinterpret cast operation"]
50829#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
50830#[inline]
50831#[cfg(target_endian = "little")]
50832#[target_feature(enable = "neon")]
50833#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50834#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50835#[cfg_attr(
50836 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50837 assert_instr(nop)
50838)]
50839#[cfg_attr(
50840 not(target_arch = "arm"),
50841 stable(feature = "neon_intrinsics", since = "1.59.0")
50842)]
50843#[cfg_attr(
50844 target_arch = "arm",
50845 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50846)]
50847pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
50848 unsafe { transmute(a) }
50849}
50850#[doc = "Vector reinterpret cast operation"]
50851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
50852#[inline]
50853#[cfg(target_endian = "big")]
50854#[target_feature(enable = "neon")]
50855#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50856#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50857#[cfg_attr(
50858 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50859 assert_instr(nop)
50860)]
50861#[cfg_attr(
50862 not(target_arch = "arm"),
50863 stable(feature = "neon_intrinsics", since = "1.59.0")
50864)]
50865#[cfg_attr(
50866 target_arch = "arm",
50867 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50868)]
50869pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
50870 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50871 unsafe {
50872 let ret_val: int16x4_t = transmute(a);
50873 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
50874 }
50875}
50876#[doc = "Vector reinterpret cast operation"]
50877#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
50878#[inline]
50879#[cfg(target_endian = "little")]
50880#[target_feature(enable = "neon")]
50881#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50882#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50883#[cfg_attr(
50884 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50885 assert_instr(nop)
50886)]
50887#[cfg_attr(
50888 not(target_arch = "arm"),
50889 stable(feature = "neon_intrinsics", since = "1.59.0")
50890)]
50891#[cfg_attr(
50892 target_arch = "arm",
50893 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50894)]
50895pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
50896 unsafe { transmute(a) }
50897}
50898#[doc = "Vector reinterpret cast operation"]
50899#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
50900#[inline]
50901#[cfg(target_endian = "big")]
50902#[target_feature(enable = "neon")]
50903#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50904#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50905#[cfg_attr(
50906 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50907 assert_instr(nop)
50908)]
50909#[cfg_attr(
50910 not(target_arch = "arm"),
50911 stable(feature = "neon_intrinsics", since = "1.59.0")
50912)]
50913#[cfg_attr(
50914 target_arch = "arm",
50915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50916)]
50917pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
50918 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50919 unsafe {
50920 let ret_val: int32x2_t = transmute(a);
50921 simd_shuffle!(ret_val, ret_val, [1, 0])
50922 }
50923}
50924#[doc = "Vector reinterpret cast operation"]
50925#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
50926#[inline]
50927#[cfg(target_endian = "little")]
50928#[target_feature(enable = "neon")]
50929#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50930#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50931#[cfg_attr(
50932 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50933 assert_instr(nop)
50934)]
50935#[cfg_attr(
50936 not(target_arch = "arm"),
50937 stable(feature = "neon_intrinsics", since = "1.59.0")
50938)]
50939#[cfg_attr(
50940 target_arch = "arm",
50941 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50942)]
50943pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
50944 unsafe { transmute(a) }
50945}
50946#[doc = "Vector reinterpret cast operation"]
50947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
50948#[inline]
50949#[cfg(target_endian = "big")]
50950#[target_feature(enable = "neon")]
50951#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50952#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50953#[cfg_attr(
50954 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50955 assert_instr(nop)
50956)]
50957#[cfg_attr(
50958 not(target_arch = "arm"),
50959 stable(feature = "neon_intrinsics", since = "1.59.0")
50960)]
50961#[cfg_attr(
50962 target_arch = "arm",
50963 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50964)]
50965pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
50966 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
50967 unsafe { transmute(a) }
50968}
50969#[doc = "Vector reinterpret cast operation"]
50970#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
50971#[inline]
50972#[cfg(target_endian = "little")]
50973#[target_feature(enable = "neon")]
50974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50975#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50976#[cfg_attr(
50977 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
50978 assert_instr(nop)
50979)]
50980#[cfg_attr(
50981 not(target_arch = "arm"),
50982 stable(feature = "neon_intrinsics", since = "1.59.0")
50983)]
50984#[cfg_attr(
50985 target_arch = "arm",
50986 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
50987)]
50988pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
50989 unsafe { transmute(a) }
50990}
50991#[doc = "Vector reinterpret cast operation"]
50992#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
50993#[inline]
50994#[cfg(target_endian = "big")]
50995#[target_feature(enable = "neon")]
50996#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
50997#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
50998#[cfg_attr(
50999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51000 assert_instr(nop)
51001)]
51002#[cfg_attr(
51003 not(target_arch = "arm"),
51004 stable(feature = "neon_intrinsics", since = "1.59.0")
51005)]
51006#[cfg_attr(
51007 target_arch = "arm",
51008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51009)]
51010pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
51011 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51012 unsafe {
51013 let ret_val: uint8x8_t = transmute(a);
51014 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51015 }
51016}
51017#[doc = "Vector reinterpret cast operation"]
51018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51019#[inline]
51020#[cfg(target_endian = "little")]
51021#[target_feature(enable = "neon")]
51022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51023#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51024#[cfg_attr(
51025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51026 assert_instr(nop)
51027)]
51028#[cfg_attr(
51029 not(target_arch = "arm"),
51030 stable(feature = "neon_intrinsics", since = "1.59.0")
51031)]
51032#[cfg_attr(
51033 target_arch = "arm",
51034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51035)]
51036pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51037 unsafe { transmute(a) }
51038}
51039#[doc = "Vector reinterpret cast operation"]
51040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
51041#[inline]
51042#[cfg(target_endian = "big")]
51043#[target_feature(enable = "neon")]
51044#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51045#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51046#[cfg_attr(
51047 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51048 assert_instr(nop)
51049)]
51050#[cfg_attr(
51051 not(target_arch = "arm"),
51052 stable(feature = "neon_intrinsics", since = "1.59.0")
51053)]
51054#[cfg_attr(
51055 target_arch = "arm",
51056 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51057)]
51058pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
51059 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51060 unsafe {
51061 let ret_val: uint16x4_t = transmute(a);
51062 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51063 }
51064}
51065#[doc = "Vector reinterpret cast operation"]
51066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51067#[inline]
51068#[cfg(target_endian = "little")]
51069#[target_feature(enable = "neon")]
51070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51071#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51072#[cfg_attr(
51073 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51074 assert_instr(nop)
51075)]
51076#[cfg_attr(
51077 not(target_arch = "arm"),
51078 stable(feature = "neon_intrinsics", since = "1.59.0")
51079)]
51080#[cfg_attr(
51081 target_arch = "arm",
51082 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51083)]
51084pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51085 unsafe { transmute(a) }
51086}
51087#[doc = "Vector reinterpret cast operation"]
51088#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
51089#[inline]
51090#[cfg(target_endian = "big")]
51091#[target_feature(enable = "neon")]
51092#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51093#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51094#[cfg_attr(
51095 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51096 assert_instr(nop)
51097)]
51098#[cfg_attr(
51099 not(target_arch = "arm"),
51100 stable(feature = "neon_intrinsics", since = "1.59.0")
51101)]
51102#[cfg_attr(
51103 target_arch = "arm",
51104 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51105)]
51106pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
51107 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51108 unsafe { transmute(a) }
51109}
51110#[doc = "Vector reinterpret cast operation"]
51111#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51112#[inline]
51113#[cfg(target_endian = "little")]
51114#[target_feature(enable = "neon")]
51115#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51116#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51117#[cfg_attr(
51118 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51119 assert_instr(nop)
51120)]
51121#[cfg_attr(
51122 not(target_arch = "arm"),
51123 stable(feature = "neon_intrinsics", since = "1.59.0")
51124)]
51125#[cfg_attr(
51126 target_arch = "arm",
51127 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51128)]
51129pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51130 unsafe { transmute(a) }
51131}
51132#[doc = "Vector reinterpret cast operation"]
51133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
51134#[inline]
51135#[cfg(target_endian = "big")]
51136#[target_feature(enable = "neon")]
51137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51139#[cfg_attr(
51140 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51141 assert_instr(nop)
51142)]
51143#[cfg_attr(
51144 not(target_arch = "arm"),
51145 stable(feature = "neon_intrinsics", since = "1.59.0")
51146)]
51147#[cfg_attr(
51148 target_arch = "arm",
51149 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51150)]
51151pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
51152 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51153 unsafe {
51154 let ret_val: poly8x8_t = transmute(a);
51155 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51156 }
51157}
51158#[doc = "Vector reinterpret cast operation"]
51159#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51160#[inline]
51161#[cfg(target_endian = "little")]
51162#[target_feature(enable = "neon")]
51163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51165#[cfg_attr(
51166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51167 assert_instr(nop)
51168)]
51169#[cfg_attr(
51170 not(target_arch = "arm"),
51171 stable(feature = "neon_intrinsics", since = "1.59.0")
51172)]
51173#[cfg_attr(
51174 target_arch = "arm",
51175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51176)]
51177pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51178 unsafe { transmute(a) }
51179}
51180#[doc = "Vector reinterpret cast operation"]
51181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
51182#[inline]
51183#[cfg(target_endian = "big")]
51184#[target_feature(enable = "neon")]
51185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51187#[cfg_attr(
51188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51189 assert_instr(nop)
51190)]
51191#[cfg_attr(
51192 not(target_arch = "arm"),
51193 stable(feature = "neon_intrinsics", since = "1.59.0")
51194)]
51195#[cfg_attr(
51196 target_arch = "arm",
51197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51198)]
51199pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
51200 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
51201 unsafe {
51202 let ret_val: poly16x4_t = transmute(a);
51203 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51204 }
51205}
51206#[doc = "Vector reinterpret cast operation"]
51207#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51208#[inline]
51209#[cfg(target_endian = "little")]
51210#[target_feature(enable = "neon")]
51211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51213#[cfg_attr(
51214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51215 assert_instr(nop)
51216)]
51217#[cfg_attr(
51218 not(target_arch = "arm"),
51219 stable(feature = "neon_intrinsics", since = "1.59.0")
51220)]
51221#[cfg_attr(
51222 target_arch = "arm",
51223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51224)]
51225pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51226 unsafe { transmute(a) }
51227}
51228#[doc = "Vector reinterpret cast operation"]
51229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
51230#[inline]
51231#[cfg(target_endian = "big")]
51232#[target_feature(enable = "neon")]
51233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51235#[cfg_attr(
51236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51237 assert_instr(nop)
51238)]
51239#[cfg_attr(
51240 not(target_arch = "arm"),
51241 stable(feature = "neon_intrinsics", since = "1.59.0")
51242)]
51243#[cfg_attr(
51244 target_arch = "arm",
51245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51246)]
51247pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
51248 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51249 unsafe {
51250 let ret_val: float32x4_t = transmute(a);
51251 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51252 }
51253}
51254#[doc = "Vector reinterpret cast operation"]
51255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51256#[inline]
51257#[cfg(target_endian = "little")]
51258#[target_feature(enable = "neon")]
51259#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51260#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51261#[cfg_attr(
51262 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51263 assert_instr(nop)
51264)]
51265#[cfg_attr(
51266 not(target_arch = "arm"),
51267 stable(feature = "neon_intrinsics", since = "1.59.0")
51268)]
51269#[cfg_attr(
51270 target_arch = "arm",
51271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51272)]
51273pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51274 unsafe { transmute(a) }
51275}
51276#[doc = "Vector reinterpret cast operation"]
51277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
51278#[inline]
51279#[cfg(target_endian = "big")]
51280#[target_feature(enable = "neon")]
51281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51283#[cfg_attr(
51284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51285 assert_instr(nop)
51286)]
51287#[cfg_attr(
51288 not(target_arch = "arm"),
51289 stable(feature = "neon_intrinsics", since = "1.59.0")
51290)]
51291#[cfg_attr(
51292 target_arch = "arm",
51293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51294)]
51295pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
51296 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51297 unsafe {
51298 let ret_val: int8x16_t = transmute(a);
51299 simd_shuffle!(
51300 ret_val,
51301 ret_val,
51302 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51303 )
51304 }
51305}
51306#[doc = "Vector reinterpret cast operation"]
51307#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51308#[inline]
51309#[cfg(target_endian = "little")]
51310#[target_feature(enable = "neon")]
51311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51312#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51313#[cfg_attr(
51314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51315 assert_instr(nop)
51316)]
51317#[cfg_attr(
51318 not(target_arch = "arm"),
51319 stable(feature = "neon_intrinsics", since = "1.59.0")
51320)]
51321#[cfg_attr(
51322 target_arch = "arm",
51323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51324)]
51325pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51326 unsafe { transmute(a) }
51327}
51328#[doc = "Vector reinterpret cast operation"]
51329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
51330#[inline]
51331#[cfg(target_endian = "big")]
51332#[target_feature(enable = "neon")]
51333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51334#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51335#[cfg_attr(
51336 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51337 assert_instr(nop)
51338)]
51339#[cfg_attr(
51340 not(target_arch = "arm"),
51341 stable(feature = "neon_intrinsics", since = "1.59.0")
51342)]
51343#[cfg_attr(
51344 target_arch = "arm",
51345 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51346)]
51347pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
51348 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51349 unsafe {
51350 let ret_val: int16x8_t = transmute(a);
51351 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51352 }
51353}
51354#[doc = "Vector reinterpret cast operation"]
51355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51356#[inline]
51357#[cfg(target_endian = "little")]
51358#[target_feature(enable = "neon")]
51359#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51360#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51361#[cfg_attr(
51362 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51363 assert_instr(nop)
51364)]
51365#[cfg_attr(
51366 not(target_arch = "arm"),
51367 stable(feature = "neon_intrinsics", since = "1.59.0")
51368)]
51369#[cfg_attr(
51370 target_arch = "arm",
51371 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51372)]
51373pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51374 unsafe { transmute(a) }
51375}
51376#[doc = "Vector reinterpret cast operation"]
51377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
51378#[inline]
51379#[cfg(target_endian = "big")]
51380#[target_feature(enable = "neon")]
51381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51383#[cfg_attr(
51384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51385 assert_instr(nop)
51386)]
51387#[cfg_attr(
51388 not(target_arch = "arm"),
51389 stable(feature = "neon_intrinsics", since = "1.59.0")
51390)]
51391#[cfg_attr(
51392 target_arch = "arm",
51393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51394)]
51395pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
51396 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51397 unsafe {
51398 let ret_val: int32x4_t = transmute(a);
51399 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51400 }
51401}
51402#[doc = "Vector reinterpret cast operation"]
51403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51404#[inline]
51405#[cfg(target_endian = "little")]
51406#[target_feature(enable = "neon")]
51407#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51408#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51409#[cfg_attr(
51410 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51411 assert_instr(nop)
51412)]
51413#[cfg_attr(
51414 not(target_arch = "arm"),
51415 stable(feature = "neon_intrinsics", since = "1.59.0")
51416)]
51417#[cfg_attr(
51418 target_arch = "arm",
51419 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51420)]
51421pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51422 unsafe { transmute(a) }
51423}
51424#[doc = "Vector reinterpret cast operation"]
51425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
51426#[inline]
51427#[cfg(target_endian = "big")]
51428#[target_feature(enable = "neon")]
51429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51431#[cfg_attr(
51432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51433 assert_instr(nop)
51434)]
51435#[cfg_attr(
51436 not(target_arch = "arm"),
51437 stable(feature = "neon_intrinsics", since = "1.59.0")
51438)]
51439#[cfg_attr(
51440 target_arch = "arm",
51441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51442)]
51443pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
51444 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51445 unsafe {
51446 let ret_val: int64x2_t = transmute(a);
51447 simd_shuffle!(ret_val, ret_val, [1, 0])
51448 }
51449}
51450#[doc = "Vector reinterpret cast operation"]
51451#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51452#[inline]
51453#[cfg(target_endian = "little")]
51454#[target_feature(enable = "neon")]
51455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51457#[cfg_attr(
51458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51459 assert_instr(nop)
51460)]
51461#[cfg_attr(
51462 not(target_arch = "arm"),
51463 stable(feature = "neon_intrinsics", since = "1.59.0")
51464)]
51465#[cfg_attr(
51466 target_arch = "arm",
51467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51468)]
51469pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51470 unsafe { transmute(a) }
51471}
51472#[doc = "Vector reinterpret cast operation"]
51473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
51474#[inline]
51475#[cfg(target_endian = "big")]
51476#[target_feature(enable = "neon")]
51477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51479#[cfg_attr(
51480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51481 assert_instr(nop)
51482)]
51483#[cfg_attr(
51484 not(target_arch = "arm"),
51485 stable(feature = "neon_intrinsics", since = "1.59.0")
51486)]
51487#[cfg_attr(
51488 target_arch = "arm",
51489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51490)]
51491pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
51492 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51493 unsafe {
51494 let ret_val: uint8x16_t = transmute(a);
51495 simd_shuffle!(
51496 ret_val,
51497 ret_val,
51498 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51499 )
51500 }
51501}
51502#[doc = "Vector reinterpret cast operation"]
51503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51504#[inline]
51505#[cfg(target_endian = "little")]
51506#[target_feature(enable = "neon")]
51507#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51508#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51509#[cfg_attr(
51510 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51511 assert_instr(nop)
51512)]
51513#[cfg_attr(
51514 not(target_arch = "arm"),
51515 stable(feature = "neon_intrinsics", since = "1.59.0")
51516)]
51517#[cfg_attr(
51518 target_arch = "arm",
51519 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51520)]
51521pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51522 unsafe { transmute(a) }
51523}
51524#[doc = "Vector reinterpret cast operation"]
51525#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
51526#[inline]
51527#[cfg(target_endian = "big")]
51528#[target_feature(enable = "neon")]
51529#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51530#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51531#[cfg_attr(
51532 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51533 assert_instr(nop)
51534)]
51535#[cfg_attr(
51536 not(target_arch = "arm"),
51537 stable(feature = "neon_intrinsics", since = "1.59.0")
51538)]
51539#[cfg_attr(
51540 target_arch = "arm",
51541 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51542)]
51543pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
51544 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51545 unsafe {
51546 let ret_val: uint16x8_t = transmute(a);
51547 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51548 }
51549}
51550#[doc = "Vector reinterpret cast operation"]
51551#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
51552#[inline]
51553#[cfg(target_endian = "little")]
51554#[target_feature(enable = "neon")]
51555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51557#[cfg_attr(
51558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51559 assert_instr(nop)
51560)]
51561#[cfg_attr(
51562 not(target_arch = "arm"),
51563 stable(feature = "neon_intrinsics", since = "1.59.0")
51564)]
51565#[cfg_attr(
51566 target_arch = "arm",
51567 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51568)]
51569pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
51570 unsafe { transmute(a) }
51571}
51572#[doc = "Vector reinterpret cast operation"]
51573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
51574#[inline]
51575#[cfg(target_endian = "big")]
51576#[target_feature(enable = "neon")]
51577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51579#[cfg_attr(
51580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51581 assert_instr(nop)
51582)]
51583#[cfg_attr(
51584 not(target_arch = "arm"),
51585 stable(feature = "neon_intrinsics", since = "1.59.0")
51586)]
51587#[cfg_attr(
51588 target_arch = "arm",
51589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51590)]
51591pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
51592 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51593 unsafe {
51594 let ret_val: uint64x2_t = transmute(a);
51595 simd_shuffle!(ret_val, ret_val, [1, 0])
51596 }
51597}
51598#[doc = "Vector reinterpret cast operation"]
51599#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
51600#[inline]
51601#[cfg(target_endian = "little")]
51602#[target_feature(enable = "neon")]
51603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51605#[cfg_attr(
51606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51607 assert_instr(nop)
51608)]
51609#[cfg_attr(
51610 not(target_arch = "arm"),
51611 stable(feature = "neon_intrinsics", since = "1.59.0")
51612)]
51613#[cfg_attr(
51614 target_arch = "arm",
51615 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51616)]
51617pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
51618 unsafe { transmute(a) }
51619}
51620#[doc = "Vector reinterpret cast operation"]
51621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
51622#[inline]
51623#[cfg(target_endian = "big")]
51624#[target_feature(enable = "neon")]
51625#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51626#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51627#[cfg_attr(
51628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51629 assert_instr(nop)
51630)]
51631#[cfg_attr(
51632 not(target_arch = "arm"),
51633 stable(feature = "neon_intrinsics", since = "1.59.0")
51634)]
51635#[cfg_attr(
51636 target_arch = "arm",
51637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51638)]
51639pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
51640 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51641 unsafe {
51642 let ret_val: poly8x16_t = transmute(a);
51643 simd_shuffle!(
51644 ret_val,
51645 ret_val,
51646 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
51647 )
51648 }
51649}
51650#[doc = "Vector reinterpret cast operation"]
51651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
51652#[inline]
51653#[cfg(target_endian = "little")]
51654#[target_feature(enable = "neon")]
51655#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51656#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51657#[cfg_attr(
51658 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51659 assert_instr(nop)
51660)]
51661#[cfg_attr(
51662 not(target_arch = "arm"),
51663 stable(feature = "neon_intrinsics", since = "1.59.0")
51664)]
51665#[cfg_attr(
51666 target_arch = "arm",
51667 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51668)]
51669pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
51670 unsafe { transmute(a) }
51671}
51672#[doc = "Vector reinterpret cast operation"]
51673#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
51674#[inline]
51675#[cfg(target_endian = "big")]
51676#[target_feature(enable = "neon")]
51677#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51678#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51679#[cfg_attr(
51680 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51681 assert_instr(nop)
51682)]
51683#[cfg_attr(
51684 not(target_arch = "arm"),
51685 stable(feature = "neon_intrinsics", since = "1.59.0")
51686)]
51687#[cfg_attr(
51688 target_arch = "arm",
51689 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51690)]
51691pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
51692 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
51693 unsafe {
51694 let ret_val: poly16x8_t = transmute(a);
51695 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51696 }
51697}
51698#[doc = "Vector reinterpret cast operation"]
51699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
51700#[inline]
51701#[cfg(target_endian = "little")]
51702#[target_feature(enable = "neon")]
51703#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51704#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51705#[cfg_attr(
51706 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51707 assert_instr(nop)
51708)]
51709#[cfg_attr(
51710 not(target_arch = "arm"),
51711 stable(feature = "neon_intrinsics", since = "1.59.0")
51712)]
51713#[cfg_attr(
51714 target_arch = "arm",
51715 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51716)]
51717pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
51718 unsafe { transmute(a) }
51719}
51720#[doc = "Vector reinterpret cast operation"]
51721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
51722#[inline]
51723#[cfg(target_endian = "big")]
51724#[target_feature(enable = "neon")]
51725#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51726#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51727#[cfg_attr(
51728 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51729 assert_instr(nop)
51730)]
51731#[cfg_attr(
51732 not(target_arch = "arm"),
51733 stable(feature = "neon_intrinsics", since = "1.59.0")
51734)]
51735#[cfg_attr(
51736 target_arch = "arm",
51737 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51738)]
51739pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
51740 unsafe {
51741 let ret_val: float32x2_t = transmute(a);
51742 simd_shuffle!(ret_val, ret_val, [1, 0])
51743 }
51744}
51745#[doc = "Vector reinterpret cast operation"]
51746#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
51747#[inline]
51748#[cfg(target_endian = "little")]
51749#[target_feature(enable = "neon")]
51750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51751#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51752#[cfg_attr(
51753 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51754 assert_instr(nop)
51755)]
51756#[cfg_attr(
51757 not(target_arch = "arm"),
51758 stable(feature = "neon_intrinsics", since = "1.59.0")
51759)]
51760#[cfg_attr(
51761 target_arch = "arm",
51762 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51763)]
51764pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
51765 unsafe { transmute(a) }
51766}
51767#[doc = "Vector reinterpret cast operation"]
51768#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
51769#[inline]
51770#[cfg(target_endian = "big")]
51771#[target_feature(enable = "neon")]
51772#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51773#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51774#[cfg_attr(
51775 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51776 assert_instr(nop)
51777)]
51778#[cfg_attr(
51779 not(target_arch = "arm"),
51780 stable(feature = "neon_intrinsics", since = "1.59.0")
51781)]
51782#[cfg_attr(
51783 target_arch = "arm",
51784 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51785)]
51786pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
51787 unsafe {
51788 let ret_val: int8x8_t = transmute(a);
51789 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51790 }
51791}
51792#[doc = "Vector reinterpret cast operation"]
51793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
51794#[inline]
51795#[cfg(target_endian = "little")]
51796#[target_feature(enable = "neon")]
51797#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51799#[cfg_attr(
51800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51801 assert_instr(nop)
51802)]
51803#[cfg_attr(
51804 not(target_arch = "arm"),
51805 stable(feature = "neon_intrinsics", since = "1.59.0")
51806)]
51807#[cfg_attr(
51808 target_arch = "arm",
51809 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51810)]
51811pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
51812 unsafe { transmute(a) }
51813}
51814#[doc = "Vector reinterpret cast operation"]
51815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
51816#[inline]
51817#[cfg(target_endian = "big")]
51818#[target_feature(enable = "neon")]
51819#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51821#[cfg_attr(
51822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51823 assert_instr(nop)
51824)]
51825#[cfg_attr(
51826 not(target_arch = "arm"),
51827 stable(feature = "neon_intrinsics", since = "1.59.0")
51828)]
51829#[cfg_attr(
51830 target_arch = "arm",
51831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51832)]
51833pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
51834 unsafe {
51835 let ret_val: int16x4_t = transmute(a);
51836 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51837 }
51838}
51839#[doc = "Vector reinterpret cast operation"]
51840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
51841#[inline]
51842#[cfg(target_endian = "little")]
51843#[target_feature(enable = "neon")]
51844#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51845#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51846#[cfg_attr(
51847 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51848 assert_instr(nop)
51849)]
51850#[cfg_attr(
51851 not(target_arch = "arm"),
51852 stable(feature = "neon_intrinsics", since = "1.59.0")
51853)]
51854#[cfg_attr(
51855 target_arch = "arm",
51856 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51857)]
51858pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
51859 unsafe { transmute(a) }
51860}
51861#[doc = "Vector reinterpret cast operation"]
51862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
51863#[inline]
51864#[cfg(target_endian = "big")]
51865#[target_feature(enable = "neon")]
51866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51868#[cfg_attr(
51869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51870 assert_instr(nop)
51871)]
51872#[cfg_attr(
51873 not(target_arch = "arm"),
51874 stable(feature = "neon_intrinsics", since = "1.59.0")
51875)]
51876#[cfg_attr(
51877 target_arch = "arm",
51878 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51879)]
51880pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
51881 unsafe {
51882 let ret_val: int32x2_t = transmute(a);
51883 simd_shuffle!(ret_val, ret_val, [1, 0])
51884 }
51885}
51886#[doc = "Vector reinterpret cast operation"]
51887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
51888#[inline]
51889#[target_feature(enable = "neon")]
51890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51892#[cfg_attr(
51893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51894 assert_instr(nop)
51895)]
51896#[cfg_attr(
51897 not(target_arch = "arm"),
51898 stable(feature = "neon_intrinsics", since = "1.59.0")
51899)]
51900#[cfg_attr(
51901 target_arch = "arm",
51902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51903)]
51904pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
51905 unsafe { transmute(a) }
51906}
51907#[doc = "Vector reinterpret cast operation"]
51908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
51909#[inline]
51910#[cfg(target_endian = "little")]
51911#[target_feature(enable = "neon")]
51912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51914#[cfg_attr(
51915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51916 assert_instr(nop)
51917)]
51918#[cfg_attr(
51919 not(target_arch = "arm"),
51920 stable(feature = "neon_intrinsics", since = "1.59.0")
51921)]
51922#[cfg_attr(
51923 target_arch = "arm",
51924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51925)]
51926pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
51927 unsafe { transmute(a) }
51928}
51929#[doc = "Vector reinterpret cast operation"]
51930#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
51931#[inline]
51932#[cfg(target_endian = "big")]
51933#[target_feature(enable = "neon")]
51934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51936#[cfg_attr(
51937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51938 assert_instr(nop)
51939)]
51940#[cfg_attr(
51941 not(target_arch = "arm"),
51942 stable(feature = "neon_intrinsics", since = "1.59.0")
51943)]
51944#[cfg_attr(
51945 target_arch = "arm",
51946 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51947)]
51948pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
51949 unsafe {
51950 let ret_val: uint8x8_t = transmute(a);
51951 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
51952 }
51953}
51954#[doc = "Vector reinterpret cast operation"]
51955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
51956#[inline]
51957#[cfg(target_endian = "little")]
51958#[target_feature(enable = "neon")]
51959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51961#[cfg_attr(
51962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51963 assert_instr(nop)
51964)]
51965#[cfg_attr(
51966 not(target_arch = "arm"),
51967 stable(feature = "neon_intrinsics", since = "1.59.0")
51968)]
51969#[cfg_attr(
51970 target_arch = "arm",
51971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51972)]
51973pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
51974 unsafe { transmute(a) }
51975}
51976#[doc = "Vector reinterpret cast operation"]
51977#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
51978#[inline]
51979#[cfg(target_endian = "big")]
51980#[target_feature(enable = "neon")]
51981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
51982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
51983#[cfg_attr(
51984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
51985 assert_instr(nop)
51986)]
51987#[cfg_attr(
51988 not(target_arch = "arm"),
51989 stable(feature = "neon_intrinsics", since = "1.59.0")
51990)]
51991#[cfg_attr(
51992 target_arch = "arm",
51993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
51994)]
51995pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
51996 unsafe {
51997 let ret_val: uint16x4_t = transmute(a);
51998 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
51999 }
52000}
52001#[doc = "Vector reinterpret cast operation"]
52002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52003#[inline]
52004#[cfg(target_endian = "little")]
52005#[target_feature(enable = "neon")]
52006#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52007#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52008#[cfg_attr(
52009 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52010 assert_instr(nop)
52011)]
52012#[cfg_attr(
52013 not(target_arch = "arm"),
52014 stable(feature = "neon_intrinsics", since = "1.59.0")
52015)]
52016#[cfg_attr(
52017 target_arch = "arm",
52018 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52019)]
52020pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52021 unsafe { transmute(a) }
52022}
52023#[doc = "Vector reinterpret cast operation"]
52024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
52025#[inline]
52026#[cfg(target_endian = "big")]
52027#[target_feature(enable = "neon")]
52028#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52030#[cfg_attr(
52031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52032 assert_instr(nop)
52033)]
52034#[cfg_attr(
52035 not(target_arch = "arm"),
52036 stable(feature = "neon_intrinsics", since = "1.59.0")
52037)]
52038#[cfg_attr(
52039 target_arch = "arm",
52040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52041)]
52042pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
52043 unsafe {
52044 let ret_val: uint32x2_t = transmute(a);
52045 simd_shuffle!(ret_val, ret_val, [1, 0])
52046 }
52047}
52048#[doc = "Vector reinterpret cast operation"]
52049#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52050#[inline]
52051#[cfg(target_endian = "little")]
52052#[target_feature(enable = "neon")]
52053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52055#[cfg_attr(
52056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52057 assert_instr(nop)
52058)]
52059#[cfg_attr(
52060 not(target_arch = "arm"),
52061 stable(feature = "neon_intrinsics", since = "1.59.0")
52062)]
52063#[cfg_attr(
52064 target_arch = "arm",
52065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52066)]
52067pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52068 unsafe { transmute(a) }
52069}
52070#[doc = "Vector reinterpret cast operation"]
52071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
52072#[inline]
52073#[cfg(target_endian = "big")]
52074#[target_feature(enable = "neon")]
52075#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52077#[cfg_attr(
52078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52079 assert_instr(nop)
52080)]
52081#[cfg_attr(
52082 not(target_arch = "arm"),
52083 stable(feature = "neon_intrinsics", since = "1.59.0")
52084)]
52085#[cfg_attr(
52086 target_arch = "arm",
52087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52088)]
52089pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
52090 unsafe {
52091 let ret_val: poly8x8_t = transmute(a);
52092 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52093 }
52094}
52095#[doc = "Vector reinterpret cast operation"]
52096#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52097#[inline]
52098#[cfg(target_endian = "little")]
52099#[target_feature(enable = "neon")]
52100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52101#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52102#[cfg_attr(
52103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52104 assert_instr(nop)
52105)]
52106#[cfg_attr(
52107 not(target_arch = "arm"),
52108 stable(feature = "neon_intrinsics", since = "1.59.0")
52109)]
52110#[cfg_attr(
52111 target_arch = "arm",
52112 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52113)]
52114pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52115 unsafe { transmute(a) }
52116}
52117#[doc = "Vector reinterpret cast operation"]
52118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
52119#[inline]
52120#[cfg(target_endian = "big")]
52121#[target_feature(enable = "neon")]
52122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52123#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52124#[cfg_attr(
52125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52126 assert_instr(nop)
52127)]
52128#[cfg_attr(
52129 not(target_arch = "arm"),
52130 stable(feature = "neon_intrinsics", since = "1.59.0")
52131)]
52132#[cfg_attr(
52133 target_arch = "arm",
52134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52135)]
52136pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
52137 unsafe {
52138 let ret_val: poly16x4_t = transmute(a);
52139 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52140 }
52141}
52142#[doc = "Vector reinterpret cast operation"]
52143#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52144#[inline]
52145#[cfg(target_endian = "little")]
52146#[target_feature(enable = "neon")]
52147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52149#[cfg_attr(
52150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52151 assert_instr(nop)
52152)]
52153#[cfg_attr(
52154 not(target_arch = "arm"),
52155 stable(feature = "neon_intrinsics", since = "1.59.0")
52156)]
52157#[cfg_attr(
52158 target_arch = "arm",
52159 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52160)]
52161pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52162 unsafe { transmute(a) }
52163}
52164#[doc = "Vector reinterpret cast operation"]
52165#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
52166#[inline]
52167#[cfg(target_endian = "big")]
52168#[target_feature(enable = "neon")]
52169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52170#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52171#[cfg_attr(
52172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52173 assert_instr(nop)
52174)]
52175#[cfg_attr(
52176 not(target_arch = "arm"),
52177 stable(feature = "neon_intrinsics", since = "1.59.0")
52178)]
52179#[cfg_attr(
52180 target_arch = "arm",
52181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52182)]
52183pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
52184 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52185 unsafe {
52186 let ret_val: float32x4_t = transmute(a);
52187 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52188 }
52189}
52190#[doc = "Vector reinterpret cast operation"]
52191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52192#[inline]
52193#[cfg(target_endian = "little")]
52194#[target_feature(enable = "neon")]
52195#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52196#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52197#[cfg_attr(
52198 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52199 assert_instr(nop)
52200)]
52201#[cfg_attr(
52202 not(target_arch = "arm"),
52203 stable(feature = "neon_intrinsics", since = "1.59.0")
52204)]
52205#[cfg_attr(
52206 target_arch = "arm",
52207 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52208)]
52209pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52210 unsafe { transmute(a) }
52211}
52212#[doc = "Vector reinterpret cast operation"]
52213#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
52214#[inline]
52215#[cfg(target_endian = "big")]
52216#[target_feature(enable = "neon")]
52217#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52218#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52219#[cfg_attr(
52220 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52221 assert_instr(nop)
52222)]
52223#[cfg_attr(
52224 not(target_arch = "arm"),
52225 stable(feature = "neon_intrinsics", since = "1.59.0")
52226)]
52227#[cfg_attr(
52228 target_arch = "arm",
52229 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52230)]
52231pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
52232 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52233 unsafe {
52234 let ret_val: int8x16_t = transmute(a);
52235 simd_shuffle!(
52236 ret_val,
52237 ret_val,
52238 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52239 )
52240 }
52241}
52242#[doc = "Vector reinterpret cast operation"]
52243#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52244#[inline]
52245#[cfg(target_endian = "little")]
52246#[target_feature(enable = "neon")]
52247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52249#[cfg_attr(
52250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52251 assert_instr(nop)
52252)]
52253#[cfg_attr(
52254 not(target_arch = "arm"),
52255 stable(feature = "neon_intrinsics", since = "1.59.0")
52256)]
52257#[cfg_attr(
52258 target_arch = "arm",
52259 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52260)]
52261pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52262 unsafe { transmute(a) }
52263}
52264#[doc = "Vector reinterpret cast operation"]
52265#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
52266#[inline]
52267#[cfg(target_endian = "big")]
52268#[target_feature(enable = "neon")]
52269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52270#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52271#[cfg_attr(
52272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52273 assert_instr(nop)
52274)]
52275#[cfg_attr(
52276 not(target_arch = "arm"),
52277 stable(feature = "neon_intrinsics", since = "1.59.0")
52278)]
52279#[cfg_attr(
52280 target_arch = "arm",
52281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52282)]
52283pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
52284 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52285 unsafe {
52286 let ret_val: int16x8_t = transmute(a);
52287 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52288 }
52289}
52290#[doc = "Vector reinterpret cast operation"]
52291#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52292#[inline]
52293#[cfg(target_endian = "little")]
52294#[target_feature(enable = "neon")]
52295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52296#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52297#[cfg_attr(
52298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52299 assert_instr(nop)
52300)]
52301#[cfg_attr(
52302 not(target_arch = "arm"),
52303 stable(feature = "neon_intrinsics", since = "1.59.0")
52304)]
52305#[cfg_attr(
52306 target_arch = "arm",
52307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52308)]
52309pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52310 unsafe { transmute(a) }
52311}
52312#[doc = "Vector reinterpret cast operation"]
52313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
52314#[inline]
52315#[cfg(target_endian = "big")]
52316#[target_feature(enable = "neon")]
52317#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52318#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52319#[cfg_attr(
52320 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52321 assert_instr(nop)
52322)]
52323#[cfg_attr(
52324 not(target_arch = "arm"),
52325 stable(feature = "neon_intrinsics", since = "1.59.0")
52326)]
52327#[cfg_attr(
52328 target_arch = "arm",
52329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52330)]
52331pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
52332 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52333 unsafe {
52334 let ret_val: int32x4_t = transmute(a);
52335 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52336 }
52337}
52338#[doc = "Vector reinterpret cast operation"]
52339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52340#[inline]
52341#[cfg(target_endian = "little")]
52342#[target_feature(enable = "neon")]
52343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52344#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52345#[cfg_attr(
52346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52347 assert_instr(nop)
52348)]
52349#[cfg_attr(
52350 not(target_arch = "arm"),
52351 stable(feature = "neon_intrinsics", since = "1.59.0")
52352)]
52353#[cfg_attr(
52354 target_arch = "arm",
52355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52356)]
52357pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52358 unsafe { transmute(a) }
52359}
52360#[doc = "Vector reinterpret cast operation"]
52361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
52362#[inline]
52363#[cfg(target_endian = "big")]
52364#[target_feature(enable = "neon")]
52365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52367#[cfg_attr(
52368 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52369 assert_instr(nop)
52370)]
52371#[cfg_attr(
52372 not(target_arch = "arm"),
52373 stable(feature = "neon_intrinsics", since = "1.59.0")
52374)]
52375#[cfg_attr(
52376 target_arch = "arm",
52377 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52378)]
52379pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
52380 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52381 unsafe {
52382 let ret_val: int64x2_t = transmute(a);
52383 simd_shuffle!(ret_val, ret_val, [1, 0])
52384 }
52385}
52386#[doc = "Vector reinterpret cast operation"]
52387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52388#[inline]
52389#[cfg(target_endian = "little")]
52390#[target_feature(enable = "neon")]
52391#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52392#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52393#[cfg_attr(
52394 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52395 assert_instr(nop)
52396)]
52397#[cfg_attr(
52398 not(target_arch = "arm"),
52399 stable(feature = "neon_intrinsics", since = "1.59.0")
52400)]
52401#[cfg_attr(
52402 target_arch = "arm",
52403 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52404)]
52405pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52406 unsafe { transmute(a) }
52407}
52408#[doc = "Vector reinterpret cast operation"]
52409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
52410#[inline]
52411#[cfg(target_endian = "big")]
52412#[target_feature(enable = "neon")]
52413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52414#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52415#[cfg_attr(
52416 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52417 assert_instr(nop)
52418)]
52419#[cfg_attr(
52420 not(target_arch = "arm"),
52421 stable(feature = "neon_intrinsics", since = "1.59.0")
52422)]
52423#[cfg_attr(
52424 target_arch = "arm",
52425 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52426)]
52427pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
52428 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52429 unsafe {
52430 let ret_val: uint8x16_t = transmute(a);
52431 simd_shuffle!(
52432 ret_val,
52433 ret_val,
52434 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52435 )
52436 }
52437}
52438#[doc = "Vector reinterpret cast operation"]
52439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52440#[inline]
52441#[cfg(target_endian = "little")]
52442#[target_feature(enable = "neon")]
52443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52445#[cfg_attr(
52446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52447 assert_instr(nop)
52448)]
52449#[cfg_attr(
52450 not(target_arch = "arm"),
52451 stable(feature = "neon_intrinsics", since = "1.59.0")
52452)]
52453#[cfg_attr(
52454 target_arch = "arm",
52455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52456)]
52457pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52458 unsafe { transmute(a) }
52459}
52460#[doc = "Vector reinterpret cast operation"]
52461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
52462#[inline]
52463#[cfg(target_endian = "big")]
52464#[target_feature(enable = "neon")]
52465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52467#[cfg_attr(
52468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52469 assert_instr(nop)
52470)]
52471#[cfg_attr(
52472 not(target_arch = "arm"),
52473 stable(feature = "neon_intrinsics", since = "1.59.0")
52474)]
52475#[cfg_attr(
52476 target_arch = "arm",
52477 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52478)]
52479pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
52480 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52481 unsafe {
52482 let ret_val: uint16x8_t = transmute(a);
52483 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52484 }
52485}
52486#[doc = "Vector reinterpret cast operation"]
52487#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52488#[inline]
52489#[cfg(target_endian = "little")]
52490#[target_feature(enable = "neon")]
52491#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52492#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52493#[cfg_attr(
52494 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52495 assert_instr(nop)
52496)]
52497#[cfg_attr(
52498 not(target_arch = "arm"),
52499 stable(feature = "neon_intrinsics", since = "1.59.0")
52500)]
52501#[cfg_attr(
52502 target_arch = "arm",
52503 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52504)]
52505pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52506 unsafe { transmute(a) }
52507}
52508#[doc = "Vector reinterpret cast operation"]
52509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
52510#[inline]
52511#[cfg(target_endian = "big")]
52512#[target_feature(enable = "neon")]
52513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52515#[cfg_attr(
52516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52517 assert_instr(nop)
52518)]
52519#[cfg_attr(
52520 not(target_arch = "arm"),
52521 stable(feature = "neon_intrinsics", since = "1.59.0")
52522)]
52523#[cfg_attr(
52524 target_arch = "arm",
52525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52526)]
52527pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
52528 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52529 unsafe {
52530 let ret_val: uint32x4_t = transmute(a);
52531 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52532 }
52533}
52534#[doc = "Vector reinterpret cast operation"]
52535#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52536#[inline]
52537#[cfg(target_endian = "little")]
52538#[target_feature(enable = "neon")]
52539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52540#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52541#[cfg_attr(
52542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52543 assert_instr(nop)
52544)]
52545#[cfg_attr(
52546 not(target_arch = "arm"),
52547 stable(feature = "neon_intrinsics", since = "1.59.0")
52548)]
52549#[cfg_attr(
52550 target_arch = "arm",
52551 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52552)]
52553pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
52554 unsafe { transmute(a) }
52555}
52556#[doc = "Vector reinterpret cast operation"]
52557#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
52558#[inline]
52559#[cfg(target_endian = "big")]
52560#[target_feature(enable = "neon")]
52561#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52562#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52563#[cfg_attr(
52564 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52565 assert_instr(nop)
52566)]
52567#[cfg_attr(
52568 not(target_arch = "arm"),
52569 stable(feature = "neon_intrinsics", since = "1.59.0")
52570)]
52571#[cfg_attr(
52572 target_arch = "arm",
52573 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52574)]
52575pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
52576 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52577 unsafe {
52578 let ret_val: poly8x16_t = transmute(a);
52579 simd_shuffle!(
52580 ret_val,
52581 ret_val,
52582 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
52583 )
52584 }
52585}
52586#[doc = "Vector reinterpret cast operation"]
52587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
52588#[inline]
52589#[cfg(target_endian = "little")]
52590#[target_feature(enable = "neon")]
52591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52592#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52593#[cfg_attr(
52594 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52595 assert_instr(nop)
52596)]
52597#[cfg_attr(
52598 not(target_arch = "arm"),
52599 stable(feature = "neon_intrinsics", since = "1.59.0")
52600)]
52601#[cfg_attr(
52602 target_arch = "arm",
52603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52604)]
52605pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
52606 unsafe { transmute(a) }
52607}
52608#[doc = "Vector reinterpret cast operation"]
52609#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
52610#[inline]
52611#[cfg(target_endian = "big")]
52612#[target_feature(enable = "neon")]
52613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52614#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52615#[cfg_attr(
52616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52617 assert_instr(nop)
52618)]
52619#[cfg_attr(
52620 not(target_arch = "arm"),
52621 stable(feature = "neon_intrinsics", since = "1.59.0")
52622)]
52623#[cfg_attr(
52624 target_arch = "arm",
52625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52626)]
52627pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
52628 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
52629 unsafe {
52630 let ret_val: poly16x8_t = transmute(a);
52631 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52632 }
52633}
52634#[doc = "Vector reinterpret cast operation"]
52635#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
52636#[inline]
52637#[cfg(target_endian = "little")]
52638#[target_feature(enable = "neon")]
52639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52641#[cfg_attr(
52642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52643 assert_instr(nop)
52644)]
52645#[cfg_attr(
52646 not(target_arch = "arm"),
52647 stable(feature = "neon_intrinsics", since = "1.59.0")
52648)]
52649#[cfg_attr(
52650 target_arch = "arm",
52651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52652)]
52653pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
52654 unsafe { transmute(a) }
52655}
52656#[doc = "Vector reinterpret cast operation"]
52657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
52658#[inline]
52659#[cfg(target_endian = "big")]
52660#[target_feature(enable = "neon")]
52661#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52662#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52663#[cfg_attr(
52664 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52665 assert_instr(nop)
52666)]
52667#[cfg_attr(
52668 not(target_arch = "arm"),
52669 stable(feature = "neon_intrinsics", since = "1.59.0")
52670)]
52671#[cfg_attr(
52672 target_arch = "arm",
52673 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52674)]
52675pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
52676 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52677 unsafe {
52678 let ret_val: float32x2_t = transmute(a);
52679 simd_shuffle!(ret_val, ret_val, [1, 0])
52680 }
52681}
52682#[doc = "Vector reinterpret cast operation"]
52683#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
52684#[inline]
52685#[cfg(target_endian = "little")]
52686#[target_feature(enable = "neon")]
52687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52689#[cfg_attr(
52690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52691 assert_instr(nop)
52692)]
52693#[cfg_attr(
52694 not(target_arch = "arm"),
52695 stable(feature = "neon_intrinsics", since = "1.59.0")
52696)]
52697#[cfg_attr(
52698 target_arch = "arm",
52699 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52700)]
52701pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
52702 unsafe { transmute(a) }
52703}
52704#[doc = "Vector reinterpret cast operation"]
52705#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
52706#[inline]
52707#[cfg(target_endian = "big")]
52708#[target_feature(enable = "neon")]
52709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52711#[cfg_attr(
52712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52713 assert_instr(nop)
52714)]
52715#[cfg_attr(
52716 not(target_arch = "arm"),
52717 stable(feature = "neon_intrinsics", since = "1.59.0")
52718)]
52719#[cfg_attr(
52720 target_arch = "arm",
52721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52722)]
52723pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
52724 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52725 unsafe {
52726 let ret_val: int8x8_t = transmute(a);
52727 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52728 }
52729}
52730#[doc = "Vector reinterpret cast operation"]
52731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
52732#[inline]
52733#[cfg(target_endian = "little")]
52734#[target_feature(enable = "neon")]
52735#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52736#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52737#[cfg_attr(
52738 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52739 assert_instr(nop)
52740)]
52741#[cfg_attr(
52742 not(target_arch = "arm"),
52743 stable(feature = "neon_intrinsics", since = "1.59.0")
52744)]
52745#[cfg_attr(
52746 target_arch = "arm",
52747 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52748)]
52749pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
52750 unsafe { transmute(a) }
52751}
52752#[doc = "Vector reinterpret cast operation"]
52753#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
52754#[inline]
52755#[cfg(target_endian = "big")]
52756#[target_feature(enable = "neon")]
52757#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52758#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52759#[cfg_attr(
52760 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52761 assert_instr(nop)
52762)]
52763#[cfg_attr(
52764 not(target_arch = "arm"),
52765 stable(feature = "neon_intrinsics", since = "1.59.0")
52766)]
52767#[cfg_attr(
52768 target_arch = "arm",
52769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52770)]
52771pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
52772 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52773 unsafe {
52774 let ret_val: int16x4_t = transmute(a);
52775 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52776 }
52777}
52778#[doc = "Vector reinterpret cast operation"]
52779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
52780#[inline]
52781#[cfg(target_endian = "little")]
52782#[target_feature(enable = "neon")]
52783#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52784#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52785#[cfg_attr(
52786 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52787 assert_instr(nop)
52788)]
52789#[cfg_attr(
52790 not(target_arch = "arm"),
52791 stable(feature = "neon_intrinsics", since = "1.59.0")
52792)]
52793#[cfg_attr(
52794 target_arch = "arm",
52795 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52796)]
52797pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
52798 unsafe { transmute(a) }
52799}
52800#[doc = "Vector reinterpret cast operation"]
52801#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
52802#[inline]
52803#[cfg(target_endian = "big")]
52804#[target_feature(enable = "neon")]
52805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52806#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52807#[cfg_attr(
52808 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52809 assert_instr(nop)
52810)]
52811#[cfg_attr(
52812 not(target_arch = "arm"),
52813 stable(feature = "neon_intrinsics", since = "1.59.0")
52814)]
52815#[cfg_attr(
52816 target_arch = "arm",
52817 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52818)]
52819pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
52820 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52821 unsafe {
52822 let ret_val: int32x2_t = transmute(a);
52823 simd_shuffle!(ret_val, ret_val, [1, 0])
52824 }
52825}
52826#[doc = "Vector reinterpret cast operation"]
52827#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
52828#[inline]
52829#[cfg(target_endian = "little")]
52830#[target_feature(enable = "neon")]
52831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52833#[cfg_attr(
52834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52835 assert_instr(nop)
52836)]
52837#[cfg_attr(
52838 not(target_arch = "arm"),
52839 stable(feature = "neon_intrinsics", since = "1.59.0")
52840)]
52841#[cfg_attr(
52842 target_arch = "arm",
52843 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52844)]
52845pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
52846 unsafe { transmute(a) }
52847}
52848#[doc = "Vector reinterpret cast operation"]
52849#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
52850#[inline]
52851#[cfg(target_endian = "big")]
52852#[target_feature(enable = "neon")]
52853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52855#[cfg_attr(
52856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52857 assert_instr(nop)
52858)]
52859#[cfg_attr(
52860 not(target_arch = "arm"),
52861 stable(feature = "neon_intrinsics", since = "1.59.0")
52862)]
52863#[cfg_attr(
52864 target_arch = "arm",
52865 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52866)]
52867pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
52868 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52869 unsafe { transmute(a) }
52870}
52871#[doc = "Vector reinterpret cast operation"]
52872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
52873#[inline]
52874#[cfg(target_endian = "little")]
52875#[target_feature(enable = "neon")]
52876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52878#[cfg_attr(
52879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52880 assert_instr(nop)
52881)]
52882#[cfg_attr(
52883 not(target_arch = "arm"),
52884 stable(feature = "neon_intrinsics", since = "1.59.0")
52885)]
52886#[cfg_attr(
52887 target_arch = "arm",
52888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52889)]
52890pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
52891 unsafe { transmute(a) }
52892}
52893#[doc = "Vector reinterpret cast operation"]
52894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
52895#[inline]
52896#[cfg(target_endian = "big")]
52897#[target_feature(enable = "neon")]
52898#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52899#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52900#[cfg_attr(
52901 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52902 assert_instr(nop)
52903)]
52904#[cfg_attr(
52905 not(target_arch = "arm"),
52906 stable(feature = "neon_intrinsics", since = "1.59.0")
52907)]
52908#[cfg_attr(
52909 target_arch = "arm",
52910 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52911)]
52912pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
52913 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52914 unsafe {
52915 let ret_val: uint8x8_t = transmute(a);
52916 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
52917 }
52918}
52919#[doc = "Vector reinterpret cast operation"]
52920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
52921#[inline]
52922#[cfg(target_endian = "little")]
52923#[target_feature(enable = "neon")]
52924#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52925#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52926#[cfg_attr(
52927 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52928 assert_instr(nop)
52929)]
52930#[cfg_attr(
52931 not(target_arch = "arm"),
52932 stable(feature = "neon_intrinsics", since = "1.59.0")
52933)]
52934#[cfg_attr(
52935 target_arch = "arm",
52936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52937)]
52938pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
52939 unsafe { transmute(a) }
52940}
52941#[doc = "Vector reinterpret cast operation"]
52942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
52943#[inline]
52944#[cfg(target_endian = "big")]
52945#[target_feature(enable = "neon")]
52946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52948#[cfg_attr(
52949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52950 assert_instr(nop)
52951)]
52952#[cfg_attr(
52953 not(target_arch = "arm"),
52954 stable(feature = "neon_intrinsics", since = "1.59.0")
52955)]
52956#[cfg_attr(
52957 target_arch = "arm",
52958 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52959)]
52960pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
52961 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
52962 unsafe {
52963 let ret_val: uint16x4_t = transmute(a);
52964 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
52965 }
52966}
52967#[doc = "Vector reinterpret cast operation"]
52968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
52969#[inline]
52970#[cfg(target_endian = "little")]
52971#[target_feature(enable = "neon")]
52972#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52973#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52974#[cfg_attr(
52975 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52976 assert_instr(nop)
52977)]
52978#[cfg_attr(
52979 not(target_arch = "arm"),
52980 stable(feature = "neon_intrinsics", since = "1.59.0")
52981)]
52982#[cfg_attr(
52983 target_arch = "arm",
52984 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
52985)]
52986pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
52987 unsafe { transmute(a) }
52988}
52989#[doc = "Vector reinterpret cast operation"]
52990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
52991#[inline]
52992#[cfg(target_endian = "big")]
52993#[target_feature(enable = "neon")]
52994#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
52995#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
52996#[cfg_attr(
52997 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
52998 assert_instr(nop)
52999)]
53000#[cfg_attr(
53001 not(target_arch = "arm"),
53002 stable(feature = "neon_intrinsics", since = "1.59.0")
53003)]
53004#[cfg_attr(
53005 target_arch = "arm",
53006 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53007)]
53008pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
53009 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53010 unsafe {
53011 let ret_val: uint32x2_t = transmute(a);
53012 simd_shuffle!(ret_val, ret_val, [1, 0])
53013 }
53014}
53015#[doc = "Vector reinterpret cast operation"]
53016#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53017#[inline]
53018#[cfg(target_endian = "little")]
53019#[target_feature(enable = "neon")]
53020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53021#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53022#[cfg_attr(
53023 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53024 assert_instr(nop)
53025)]
53026#[cfg_attr(
53027 not(target_arch = "arm"),
53028 stable(feature = "neon_intrinsics", since = "1.59.0")
53029)]
53030#[cfg_attr(
53031 target_arch = "arm",
53032 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53033)]
53034pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53035 unsafe { transmute(a) }
53036}
53037#[doc = "Vector reinterpret cast operation"]
53038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
53039#[inline]
53040#[cfg(target_endian = "big")]
53041#[target_feature(enable = "neon")]
53042#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53043#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53044#[cfg_attr(
53045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53046 assert_instr(nop)
53047)]
53048#[cfg_attr(
53049 not(target_arch = "arm"),
53050 stable(feature = "neon_intrinsics", since = "1.59.0")
53051)]
53052#[cfg_attr(
53053 target_arch = "arm",
53054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53055)]
53056pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
53057 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53058 unsafe { transmute(a) }
53059}
53060#[doc = "Vector reinterpret cast operation"]
53061#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53062#[inline]
53063#[cfg(target_endian = "little")]
53064#[target_feature(enable = "neon")]
53065#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53066#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53067#[cfg_attr(
53068 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53069 assert_instr(nop)
53070)]
53071#[cfg_attr(
53072 not(target_arch = "arm"),
53073 stable(feature = "neon_intrinsics", since = "1.59.0")
53074)]
53075#[cfg_attr(
53076 target_arch = "arm",
53077 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53078)]
53079pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53080 unsafe { transmute(a) }
53081}
53082#[doc = "Vector reinterpret cast operation"]
53083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
53084#[inline]
53085#[cfg(target_endian = "big")]
53086#[target_feature(enable = "neon")]
53087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53089#[cfg_attr(
53090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53091 assert_instr(nop)
53092)]
53093#[cfg_attr(
53094 not(target_arch = "arm"),
53095 stable(feature = "neon_intrinsics", since = "1.59.0")
53096)]
53097#[cfg_attr(
53098 target_arch = "arm",
53099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53100)]
53101pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
53102 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
53103 unsafe {
53104 let ret_val: poly16x4_t = transmute(a);
53105 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53106 }
53107}
53108#[doc = "Vector reinterpret cast operation"]
53109#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53110#[inline]
53111#[cfg(target_endian = "little")]
53112#[target_feature(enable = "neon")]
53113#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53114#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53115#[cfg_attr(
53116 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53117 assert_instr(nop)
53118)]
53119#[cfg_attr(
53120 not(target_arch = "arm"),
53121 stable(feature = "neon_intrinsics", since = "1.59.0")
53122)]
53123#[cfg_attr(
53124 target_arch = "arm",
53125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53126)]
53127pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53128 unsafe { transmute(a) }
53129}
53130#[doc = "Vector reinterpret cast operation"]
53131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
53132#[inline]
53133#[cfg(target_endian = "big")]
53134#[target_feature(enable = "neon")]
53135#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53136#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53137#[cfg_attr(
53138 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53139 assert_instr(nop)
53140)]
53141#[cfg_attr(
53142 not(target_arch = "arm"),
53143 stable(feature = "neon_intrinsics", since = "1.59.0")
53144)]
53145#[cfg_attr(
53146 target_arch = "arm",
53147 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53148)]
53149pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
53150 let a: poly8x16_t =
53151 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53152 unsafe {
53153 let ret_val: float32x4_t = transmute(a);
53154 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53155 }
53156}
53157#[doc = "Vector reinterpret cast operation"]
53158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53159#[inline]
53160#[cfg(target_endian = "little")]
53161#[target_feature(enable = "neon")]
53162#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53164#[cfg_attr(
53165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53166 assert_instr(nop)
53167)]
53168#[cfg_attr(
53169 not(target_arch = "arm"),
53170 stable(feature = "neon_intrinsics", since = "1.59.0")
53171)]
53172#[cfg_attr(
53173 target_arch = "arm",
53174 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53175)]
53176pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53177 unsafe { transmute(a) }
53178}
53179#[doc = "Vector reinterpret cast operation"]
53180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
53181#[inline]
53182#[cfg(target_endian = "big")]
53183#[target_feature(enable = "neon")]
53184#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53185#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53186#[cfg_attr(
53187 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53188 assert_instr(nop)
53189)]
53190#[cfg_attr(
53191 not(target_arch = "arm"),
53192 stable(feature = "neon_intrinsics", since = "1.59.0")
53193)]
53194#[cfg_attr(
53195 target_arch = "arm",
53196 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53197)]
53198pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
53199 let a: poly8x16_t =
53200 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53201 unsafe {
53202 let ret_val: int8x16_t = transmute(a);
53203 simd_shuffle!(
53204 ret_val,
53205 ret_val,
53206 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53207 )
53208 }
53209}
53210#[doc = "Vector reinterpret cast operation"]
53211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53212#[inline]
53213#[cfg(target_endian = "little")]
53214#[target_feature(enable = "neon")]
53215#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53216#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53217#[cfg_attr(
53218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53219 assert_instr(nop)
53220)]
53221#[cfg_attr(
53222 not(target_arch = "arm"),
53223 stable(feature = "neon_intrinsics", since = "1.59.0")
53224)]
53225#[cfg_attr(
53226 target_arch = "arm",
53227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53228)]
53229pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53230 unsafe { transmute(a) }
53231}
53232#[doc = "Vector reinterpret cast operation"]
53233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
53234#[inline]
53235#[cfg(target_endian = "big")]
53236#[target_feature(enable = "neon")]
53237#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53238#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53239#[cfg_attr(
53240 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53241 assert_instr(nop)
53242)]
53243#[cfg_attr(
53244 not(target_arch = "arm"),
53245 stable(feature = "neon_intrinsics", since = "1.59.0")
53246)]
53247#[cfg_attr(
53248 target_arch = "arm",
53249 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53250)]
53251pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
53252 let a: poly8x16_t =
53253 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53254 unsafe {
53255 let ret_val: int16x8_t = transmute(a);
53256 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53257 }
53258}
53259#[doc = "Vector reinterpret cast operation"]
53260#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53261#[inline]
53262#[cfg(target_endian = "little")]
53263#[target_feature(enable = "neon")]
53264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53265#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53266#[cfg_attr(
53267 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53268 assert_instr(nop)
53269)]
53270#[cfg_attr(
53271 not(target_arch = "arm"),
53272 stable(feature = "neon_intrinsics", since = "1.59.0")
53273)]
53274#[cfg_attr(
53275 target_arch = "arm",
53276 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53277)]
53278pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53279 unsafe { transmute(a) }
53280}
53281#[doc = "Vector reinterpret cast operation"]
53282#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
53283#[inline]
53284#[cfg(target_endian = "big")]
53285#[target_feature(enable = "neon")]
53286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53288#[cfg_attr(
53289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53290 assert_instr(nop)
53291)]
53292#[cfg_attr(
53293 not(target_arch = "arm"),
53294 stable(feature = "neon_intrinsics", since = "1.59.0")
53295)]
53296#[cfg_attr(
53297 target_arch = "arm",
53298 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53299)]
53300pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
53301 let a: poly8x16_t =
53302 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53303 unsafe {
53304 let ret_val: int32x4_t = transmute(a);
53305 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53306 }
53307}
53308#[doc = "Vector reinterpret cast operation"]
53309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53310#[inline]
53311#[cfg(target_endian = "little")]
53312#[target_feature(enable = "neon")]
53313#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53315#[cfg_attr(
53316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53317 assert_instr(nop)
53318)]
53319#[cfg_attr(
53320 not(target_arch = "arm"),
53321 stable(feature = "neon_intrinsics", since = "1.59.0")
53322)]
53323#[cfg_attr(
53324 target_arch = "arm",
53325 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53326)]
53327pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53328 unsafe { transmute(a) }
53329}
53330#[doc = "Vector reinterpret cast operation"]
53331#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
53332#[inline]
53333#[cfg(target_endian = "big")]
53334#[target_feature(enable = "neon")]
53335#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53336#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53337#[cfg_attr(
53338 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53339 assert_instr(nop)
53340)]
53341#[cfg_attr(
53342 not(target_arch = "arm"),
53343 stable(feature = "neon_intrinsics", since = "1.59.0")
53344)]
53345#[cfg_attr(
53346 target_arch = "arm",
53347 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53348)]
53349pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
53350 let a: poly8x16_t =
53351 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53352 unsafe {
53353 let ret_val: int64x2_t = transmute(a);
53354 simd_shuffle!(ret_val, ret_val, [1, 0])
53355 }
53356}
53357#[doc = "Vector reinterpret cast operation"]
53358#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53359#[inline]
53360#[cfg(target_endian = "little")]
53361#[target_feature(enable = "neon")]
53362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53364#[cfg_attr(
53365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53366 assert_instr(nop)
53367)]
53368#[cfg_attr(
53369 not(target_arch = "arm"),
53370 stable(feature = "neon_intrinsics", since = "1.59.0")
53371)]
53372#[cfg_attr(
53373 target_arch = "arm",
53374 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53375)]
53376pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53377 unsafe { transmute(a) }
53378}
53379#[doc = "Vector reinterpret cast operation"]
53380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
53381#[inline]
53382#[cfg(target_endian = "big")]
53383#[target_feature(enable = "neon")]
53384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53386#[cfg_attr(
53387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53388 assert_instr(nop)
53389)]
53390#[cfg_attr(
53391 not(target_arch = "arm"),
53392 stable(feature = "neon_intrinsics", since = "1.59.0")
53393)]
53394#[cfg_attr(
53395 target_arch = "arm",
53396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53397)]
53398pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
53399 let a: poly8x16_t =
53400 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53401 unsafe {
53402 let ret_val: uint8x16_t = transmute(a);
53403 simd_shuffle!(
53404 ret_val,
53405 ret_val,
53406 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
53407 )
53408 }
53409}
53410#[doc = "Vector reinterpret cast operation"]
53411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53412#[inline]
53413#[cfg(target_endian = "little")]
53414#[target_feature(enable = "neon")]
53415#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53416#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53417#[cfg_attr(
53418 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53419 assert_instr(nop)
53420)]
53421#[cfg_attr(
53422 not(target_arch = "arm"),
53423 stable(feature = "neon_intrinsics", since = "1.59.0")
53424)]
53425#[cfg_attr(
53426 target_arch = "arm",
53427 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53428)]
53429pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53430 unsafe { transmute(a) }
53431}
53432#[doc = "Vector reinterpret cast operation"]
53433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
53434#[inline]
53435#[cfg(target_endian = "big")]
53436#[target_feature(enable = "neon")]
53437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53438#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53439#[cfg_attr(
53440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53441 assert_instr(nop)
53442)]
53443#[cfg_attr(
53444 not(target_arch = "arm"),
53445 stable(feature = "neon_intrinsics", since = "1.59.0")
53446)]
53447#[cfg_attr(
53448 target_arch = "arm",
53449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53450)]
53451pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
53452 let a: poly8x16_t =
53453 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53454 unsafe {
53455 let ret_val: uint16x8_t = transmute(a);
53456 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53457 }
53458}
53459#[doc = "Vector reinterpret cast operation"]
53460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53461#[inline]
53462#[cfg(target_endian = "little")]
53463#[target_feature(enable = "neon")]
53464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53466#[cfg_attr(
53467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53468 assert_instr(nop)
53469)]
53470#[cfg_attr(
53471 not(target_arch = "arm"),
53472 stable(feature = "neon_intrinsics", since = "1.59.0")
53473)]
53474#[cfg_attr(
53475 target_arch = "arm",
53476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53477)]
53478pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53479 unsafe { transmute(a) }
53480}
53481#[doc = "Vector reinterpret cast operation"]
53482#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
53483#[inline]
53484#[cfg(target_endian = "big")]
53485#[target_feature(enable = "neon")]
53486#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53487#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53488#[cfg_attr(
53489 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53490 assert_instr(nop)
53491)]
53492#[cfg_attr(
53493 not(target_arch = "arm"),
53494 stable(feature = "neon_intrinsics", since = "1.59.0")
53495)]
53496#[cfg_attr(
53497 target_arch = "arm",
53498 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53499)]
53500pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
53501 let a: poly8x16_t =
53502 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53503 unsafe {
53504 let ret_val: uint32x4_t = transmute(a);
53505 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53506 }
53507}
53508#[doc = "Vector reinterpret cast operation"]
53509#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53510#[inline]
53511#[cfg(target_endian = "little")]
53512#[target_feature(enable = "neon")]
53513#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53514#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53515#[cfg_attr(
53516 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53517 assert_instr(nop)
53518)]
53519#[cfg_attr(
53520 not(target_arch = "arm"),
53521 stable(feature = "neon_intrinsics", since = "1.59.0")
53522)]
53523#[cfg_attr(
53524 target_arch = "arm",
53525 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53526)]
53527pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53528 unsafe { transmute(a) }
53529}
53530#[doc = "Vector reinterpret cast operation"]
53531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
53532#[inline]
53533#[cfg(target_endian = "big")]
53534#[target_feature(enable = "neon")]
53535#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53536#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53537#[cfg_attr(
53538 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53539 assert_instr(nop)
53540)]
53541#[cfg_attr(
53542 not(target_arch = "arm"),
53543 stable(feature = "neon_intrinsics", since = "1.59.0")
53544)]
53545#[cfg_attr(
53546 target_arch = "arm",
53547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53548)]
53549pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
53550 let a: poly8x16_t =
53551 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53552 unsafe {
53553 let ret_val: uint64x2_t = transmute(a);
53554 simd_shuffle!(ret_val, ret_val, [1, 0])
53555 }
53556}
53557#[doc = "Vector reinterpret cast operation"]
53558#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
53559#[inline]
53560#[cfg(target_endian = "little")]
53561#[target_feature(enable = "neon")]
53562#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53563#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53564#[cfg_attr(
53565 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53566 assert_instr(nop)
53567)]
53568#[cfg_attr(
53569 not(target_arch = "arm"),
53570 stable(feature = "neon_intrinsics", since = "1.59.0")
53571)]
53572#[cfg_attr(
53573 target_arch = "arm",
53574 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53575)]
53576pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
53577 unsafe { transmute(a) }
53578}
53579#[doc = "Vector reinterpret cast operation"]
53580#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
53581#[inline]
53582#[cfg(target_endian = "big")]
53583#[target_feature(enable = "neon")]
53584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53586#[cfg_attr(
53587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53588 assert_instr(nop)
53589)]
53590#[cfg_attr(
53591 not(target_arch = "arm"),
53592 stable(feature = "neon_intrinsics", since = "1.59.0")
53593)]
53594#[cfg_attr(
53595 target_arch = "arm",
53596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53597)]
53598pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
53599 let a: poly8x16_t =
53600 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
53601 unsafe {
53602 let ret_val: poly16x8_t = transmute(a);
53603 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53604 }
53605}
53606#[doc = "Vector reinterpret cast operation"]
53607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
53608#[inline]
53609#[cfg(target_endian = "little")]
53610#[target_feature(enable = "neon")]
53611#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53612#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53613#[cfg_attr(
53614 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53615 assert_instr(nop)
53616)]
53617#[cfg_attr(
53618 not(target_arch = "arm"),
53619 stable(feature = "neon_intrinsics", since = "1.59.0")
53620)]
53621#[cfg_attr(
53622 target_arch = "arm",
53623 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53624)]
53625pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
53626 unsafe { transmute(a) }
53627}
53628#[doc = "Vector reinterpret cast operation"]
53629#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
53630#[inline]
53631#[cfg(target_endian = "big")]
53632#[target_feature(enable = "neon")]
53633#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53634#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53635#[cfg_attr(
53636 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53637 assert_instr(nop)
53638)]
53639#[cfg_attr(
53640 not(target_arch = "arm"),
53641 stable(feature = "neon_intrinsics", since = "1.59.0")
53642)]
53643#[cfg_attr(
53644 target_arch = "arm",
53645 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53646)]
53647pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
53648 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53649 unsafe {
53650 let ret_val: float32x2_t = transmute(a);
53651 simd_shuffle!(ret_val, ret_val, [1, 0])
53652 }
53653}
53654#[doc = "Vector reinterpret cast operation"]
53655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
53656#[inline]
53657#[cfg(target_endian = "little")]
53658#[target_feature(enable = "neon")]
53659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53661#[cfg_attr(
53662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53663 assert_instr(nop)
53664)]
53665#[cfg_attr(
53666 not(target_arch = "arm"),
53667 stable(feature = "neon_intrinsics", since = "1.59.0")
53668)]
53669#[cfg_attr(
53670 target_arch = "arm",
53671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53672)]
53673pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
53674 unsafe { transmute(a) }
53675}
53676#[doc = "Vector reinterpret cast operation"]
53677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
53678#[inline]
53679#[cfg(target_endian = "big")]
53680#[target_feature(enable = "neon")]
53681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53683#[cfg_attr(
53684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53685 assert_instr(nop)
53686)]
53687#[cfg_attr(
53688 not(target_arch = "arm"),
53689 stable(feature = "neon_intrinsics", since = "1.59.0")
53690)]
53691#[cfg_attr(
53692 target_arch = "arm",
53693 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53694)]
53695pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
53696 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53697 unsafe {
53698 let ret_val: int8x8_t = transmute(a);
53699 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53700 }
53701}
53702#[doc = "Vector reinterpret cast operation"]
53703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
53704#[inline]
53705#[cfg(target_endian = "little")]
53706#[target_feature(enable = "neon")]
53707#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53709#[cfg_attr(
53710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53711 assert_instr(nop)
53712)]
53713#[cfg_attr(
53714 not(target_arch = "arm"),
53715 stable(feature = "neon_intrinsics", since = "1.59.0")
53716)]
53717#[cfg_attr(
53718 target_arch = "arm",
53719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53720)]
53721pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
53722 unsafe { transmute(a) }
53723}
53724#[doc = "Vector reinterpret cast operation"]
53725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
53726#[inline]
53727#[cfg(target_endian = "big")]
53728#[target_feature(enable = "neon")]
53729#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53731#[cfg_attr(
53732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53733 assert_instr(nop)
53734)]
53735#[cfg_attr(
53736 not(target_arch = "arm"),
53737 stable(feature = "neon_intrinsics", since = "1.59.0")
53738)]
53739#[cfg_attr(
53740 target_arch = "arm",
53741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53742)]
53743pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
53744 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53745 unsafe {
53746 let ret_val: int16x4_t = transmute(a);
53747 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53748 }
53749}
53750#[doc = "Vector reinterpret cast operation"]
53751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
53752#[inline]
53753#[cfg(target_endian = "little")]
53754#[target_feature(enable = "neon")]
53755#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53756#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53757#[cfg_attr(
53758 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53759 assert_instr(nop)
53760)]
53761#[cfg_attr(
53762 not(target_arch = "arm"),
53763 stable(feature = "neon_intrinsics", since = "1.59.0")
53764)]
53765#[cfg_attr(
53766 target_arch = "arm",
53767 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53768)]
53769pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
53770 unsafe { transmute(a) }
53771}
53772#[doc = "Vector reinterpret cast operation"]
53773#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
53774#[inline]
53775#[cfg(target_endian = "big")]
53776#[target_feature(enable = "neon")]
53777#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53778#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53779#[cfg_attr(
53780 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53781 assert_instr(nop)
53782)]
53783#[cfg_attr(
53784 not(target_arch = "arm"),
53785 stable(feature = "neon_intrinsics", since = "1.59.0")
53786)]
53787#[cfg_attr(
53788 target_arch = "arm",
53789 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53790)]
53791pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
53792 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53793 unsafe {
53794 let ret_val: int32x2_t = transmute(a);
53795 simd_shuffle!(ret_val, ret_val, [1, 0])
53796 }
53797}
53798#[doc = "Vector reinterpret cast operation"]
53799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
53800#[inline]
53801#[cfg(target_endian = "little")]
53802#[target_feature(enable = "neon")]
53803#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53804#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53805#[cfg_attr(
53806 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53807 assert_instr(nop)
53808)]
53809#[cfg_attr(
53810 not(target_arch = "arm"),
53811 stable(feature = "neon_intrinsics", since = "1.59.0")
53812)]
53813#[cfg_attr(
53814 target_arch = "arm",
53815 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53816)]
53817pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
53818 unsafe { transmute(a) }
53819}
53820#[doc = "Vector reinterpret cast operation"]
53821#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
53822#[inline]
53823#[cfg(target_endian = "big")]
53824#[target_feature(enable = "neon")]
53825#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53826#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53827#[cfg_attr(
53828 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53829 assert_instr(nop)
53830)]
53831#[cfg_attr(
53832 not(target_arch = "arm"),
53833 stable(feature = "neon_intrinsics", since = "1.59.0")
53834)]
53835#[cfg_attr(
53836 target_arch = "arm",
53837 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53838)]
53839pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
53840 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53841 unsafe { transmute(a) }
53842}
53843#[doc = "Vector reinterpret cast operation"]
53844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
53845#[inline]
53846#[cfg(target_endian = "little")]
53847#[target_feature(enable = "neon")]
53848#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53849#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53850#[cfg_attr(
53851 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53852 assert_instr(nop)
53853)]
53854#[cfg_attr(
53855 not(target_arch = "arm"),
53856 stable(feature = "neon_intrinsics", since = "1.59.0")
53857)]
53858#[cfg_attr(
53859 target_arch = "arm",
53860 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53861)]
53862pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
53863 unsafe { transmute(a) }
53864}
53865#[doc = "Vector reinterpret cast operation"]
53866#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
53867#[inline]
53868#[cfg(target_endian = "big")]
53869#[target_feature(enable = "neon")]
53870#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53871#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53872#[cfg_attr(
53873 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53874 assert_instr(nop)
53875)]
53876#[cfg_attr(
53877 not(target_arch = "arm"),
53878 stable(feature = "neon_intrinsics", since = "1.59.0")
53879)]
53880#[cfg_attr(
53881 target_arch = "arm",
53882 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53883)]
53884pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
53885 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53886 unsafe {
53887 let ret_val: uint8x8_t = transmute(a);
53888 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
53889 }
53890}
53891#[doc = "Vector reinterpret cast operation"]
53892#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
53893#[inline]
53894#[cfg(target_endian = "little")]
53895#[target_feature(enable = "neon")]
53896#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53897#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53898#[cfg_attr(
53899 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53900 assert_instr(nop)
53901)]
53902#[cfg_attr(
53903 not(target_arch = "arm"),
53904 stable(feature = "neon_intrinsics", since = "1.59.0")
53905)]
53906#[cfg_attr(
53907 target_arch = "arm",
53908 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53909)]
53910pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
53911 unsafe { transmute(a) }
53912}
53913#[doc = "Vector reinterpret cast operation"]
53914#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
53915#[inline]
53916#[cfg(target_endian = "big")]
53917#[target_feature(enable = "neon")]
53918#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53919#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53920#[cfg_attr(
53921 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53922 assert_instr(nop)
53923)]
53924#[cfg_attr(
53925 not(target_arch = "arm"),
53926 stable(feature = "neon_intrinsics", since = "1.59.0")
53927)]
53928#[cfg_attr(
53929 target_arch = "arm",
53930 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53931)]
53932pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
53933 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53934 unsafe {
53935 let ret_val: uint16x4_t = transmute(a);
53936 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
53937 }
53938}
53939#[doc = "Vector reinterpret cast operation"]
53940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
53941#[inline]
53942#[cfg(target_endian = "little")]
53943#[target_feature(enable = "neon")]
53944#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53945#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53946#[cfg_attr(
53947 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53948 assert_instr(nop)
53949)]
53950#[cfg_attr(
53951 not(target_arch = "arm"),
53952 stable(feature = "neon_intrinsics", since = "1.59.0")
53953)]
53954#[cfg_attr(
53955 target_arch = "arm",
53956 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53957)]
53958pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
53959 unsafe { transmute(a) }
53960}
53961#[doc = "Vector reinterpret cast operation"]
53962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
53963#[inline]
53964#[cfg(target_endian = "big")]
53965#[target_feature(enable = "neon")]
53966#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53967#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53968#[cfg_attr(
53969 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53970 assert_instr(nop)
53971)]
53972#[cfg_attr(
53973 not(target_arch = "arm"),
53974 stable(feature = "neon_intrinsics", since = "1.59.0")
53975)]
53976#[cfg_attr(
53977 target_arch = "arm",
53978 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
53979)]
53980pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
53981 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
53982 unsafe {
53983 let ret_val: uint32x2_t = transmute(a);
53984 simd_shuffle!(ret_val, ret_val, [1, 0])
53985 }
53986}
53987#[doc = "Vector reinterpret cast operation"]
53988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
53989#[inline]
53990#[cfg(target_endian = "little")]
53991#[target_feature(enable = "neon")]
53992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
53993#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
53994#[cfg_attr(
53995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
53996 assert_instr(nop)
53997)]
53998#[cfg_attr(
53999 not(target_arch = "arm"),
54000 stable(feature = "neon_intrinsics", since = "1.59.0")
54001)]
54002#[cfg_attr(
54003 target_arch = "arm",
54004 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54005)]
54006pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54007 unsafe { transmute(a) }
54008}
54009#[doc = "Vector reinterpret cast operation"]
54010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
54011#[inline]
54012#[cfg(target_endian = "big")]
54013#[target_feature(enable = "neon")]
54014#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54015#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54016#[cfg_attr(
54017 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54018 assert_instr(nop)
54019)]
54020#[cfg_attr(
54021 not(target_arch = "arm"),
54022 stable(feature = "neon_intrinsics", since = "1.59.0")
54023)]
54024#[cfg_attr(
54025 target_arch = "arm",
54026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54027)]
54028pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
54029 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54030 unsafe { transmute(a) }
54031}
54032#[doc = "Vector reinterpret cast operation"]
54033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54034#[inline]
54035#[cfg(target_endian = "little")]
54036#[target_feature(enable = "neon")]
54037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54039#[cfg_attr(
54040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54041 assert_instr(nop)
54042)]
54043#[cfg_attr(
54044 not(target_arch = "arm"),
54045 stable(feature = "neon_intrinsics", since = "1.59.0")
54046)]
54047#[cfg_attr(
54048 target_arch = "arm",
54049 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54050)]
54051pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54052 unsafe { transmute(a) }
54053}
54054#[doc = "Vector reinterpret cast operation"]
54055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
54056#[inline]
54057#[cfg(target_endian = "big")]
54058#[target_feature(enable = "neon")]
54059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54061#[cfg_attr(
54062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54063 assert_instr(nop)
54064)]
54065#[cfg_attr(
54066 not(target_arch = "arm"),
54067 stable(feature = "neon_intrinsics", since = "1.59.0")
54068)]
54069#[cfg_attr(
54070 target_arch = "arm",
54071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54072)]
54073pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
54074 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
54075 unsafe {
54076 let ret_val: poly8x8_t = transmute(a);
54077 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54078 }
54079}
54080#[doc = "Vector reinterpret cast operation"]
54081#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54082#[inline]
54083#[cfg(target_endian = "little")]
54084#[target_feature(enable = "neon")]
54085#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54086#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54087#[cfg_attr(
54088 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54089 assert_instr(nop)
54090)]
54091#[cfg_attr(
54092 not(target_arch = "arm"),
54093 stable(feature = "neon_intrinsics", since = "1.59.0")
54094)]
54095#[cfg_attr(
54096 target_arch = "arm",
54097 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54098)]
54099pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54100 unsafe { transmute(a) }
54101}
54102#[doc = "Vector reinterpret cast operation"]
54103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
54104#[inline]
54105#[cfg(target_endian = "big")]
54106#[target_feature(enable = "neon")]
54107#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54108#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54109#[cfg_attr(
54110 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54111 assert_instr(nop)
54112)]
54113#[cfg_attr(
54114 not(target_arch = "arm"),
54115 stable(feature = "neon_intrinsics", since = "1.59.0")
54116)]
54117#[cfg_attr(
54118 target_arch = "arm",
54119 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54120)]
54121pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
54122 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54123 unsafe {
54124 let ret_val: float32x4_t = transmute(a);
54125 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54126 }
54127}
54128#[doc = "Vector reinterpret cast operation"]
54129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54130#[inline]
54131#[cfg(target_endian = "little")]
54132#[target_feature(enable = "neon")]
54133#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54134#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54135#[cfg_attr(
54136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54137 assert_instr(nop)
54138)]
54139#[cfg_attr(
54140 not(target_arch = "arm"),
54141 stable(feature = "neon_intrinsics", since = "1.59.0")
54142)]
54143#[cfg_attr(
54144 target_arch = "arm",
54145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54146)]
54147pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54148 unsafe { transmute(a) }
54149}
54150#[doc = "Vector reinterpret cast operation"]
54151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
54152#[inline]
54153#[cfg(target_endian = "big")]
54154#[target_feature(enable = "neon")]
54155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54157#[cfg_attr(
54158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54159 assert_instr(nop)
54160)]
54161#[cfg_attr(
54162 not(target_arch = "arm"),
54163 stable(feature = "neon_intrinsics", since = "1.59.0")
54164)]
54165#[cfg_attr(
54166 target_arch = "arm",
54167 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54168)]
54169pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
54170 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54171 unsafe {
54172 let ret_val: int8x16_t = transmute(a);
54173 simd_shuffle!(
54174 ret_val,
54175 ret_val,
54176 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54177 )
54178 }
54179}
54180#[doc = "Vector reinterpret cast operation"]
54181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54182#[inline]
54183#[cfg(target_endian = "little")]
54184#[target_feature(enable = "neon")]
54185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54187#[cfg_attr(
54188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54189 assert_instr(nop)
54190)]
54191#[cfg_attr(
54192 not(target_arch = "arm"),
54193 stable(feature = "neon_intrinsics", since = "1.59.0")
54194)]
54195#[cfg_attr(
54196 target_arch = "arm",
54197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54198)]
54199pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54200 unsafe { transmute(a) }
54201}
54202#[doc = "Vector reinterpret cast operation"]
54203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
54204#[inline]
54205#[cfg(target_endian = "big")]
54206#[target_feature(enable = "neon")]
54207#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54208#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54209#[cfg_attr(
54210 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54211 assert_instr(nop)
54212)]
54213#[cfg_attr(
54214 not(target_arch = "arm"),
54215 stable(feature = "neon_intrinsics", since = "1.59.0")
54216)]
54217#[cfg_attr(
54218 target_arch = "arm",
54219 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54220)]
54221pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
54222 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54223 unsafe {
54224 let ret_val: int16x8_t = transmute(a);
54225 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54226 }
54227}
54228#[doc = "Vector reinterpret cast operation"]
54229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54230#[inline]
54231#[cfg(target_endian = "little")]
54232#[target_feature(enable = "neon")]
54233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54234#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54235#[cfg_attr(
54236 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54237 assert_instr(nop)
54238)]
54239#[cfg_attr(
54240 not(target_arch = "arm"),
54241 stable(feature = "neon_intrinsics", since = "1.59.0")
54242)]
54243#[cfg_attr(
54244 target_arch = "arm",
54245 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54246)]
54247pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54248 unsafe { transmute(a) }
54249}
54250#[doc = "Vector reinterpret cast operation"]
54251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
54252#[inline]
54253#[cfg(target_endian = "big")]
54254#[target_feature(enable = "neon")]
54255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54257#[cfg_attr(
54258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54259 assert_instr(nop)
54260)]
54261#[cfg_attr(
54262 not(target_arch = "arm"),
54263 stable(feature = "neon_intrinsics", since = "1.59.0")
54264)]
54265#[cfg_attr(
54266 target_arch = "arm",
54267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54268)]
54269pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
54270 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54271 unsafe {
54272 let ret_val: int32x4_t = transmute(a);
54273 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54274 }
54275}
54276#[doc = "Vector reinterpret cast operation"]
54277#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54278#[inline]
54279#[cfg(target_endian = "little")]
54280#[target_feature(enable = "neon")]
54281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54283#[cfg_attr(
54284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54285 assert_instr(nop)
54286)]
54287#[cfg_attr(
54288 not(target_arch = "arm"),
54289 stable(feature = "neon_intrinsics", since = "1.59.0")
54290)]
54291#[cfg_attr(
54292 target_arch = "arm",
54293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54294)]
54295pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54296 unsafe { transmute(a) }
54297}
54298#[doc = "Vector reinterpret cast operation"]
54299#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
54300#[inline]
54301#[cfg(target_endian = "big")]
54302#[target_feature(enable = "neon")]
54303#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54304#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54305#[cfg_attr(
54306 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54307 assert_instr(nop)
54308)]
54309#[cfg_attr(
54310 not(target_arch = "arm"),
54311 stable(feature = "neon_intrinsics", since = "1.59.0")
54312)]
54313#[cfg_attr(
54314 target_arch = "arm",
54315 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54316)]
54317pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
54318 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54319 unsafe {
54320 let ret_val: int64x2_t = transmute(a);
54321 simd_shuffle!(ret_val, ret_val, [1, 0])
54322 }
54323}
54324#[doc = "Vector reinterpret cast operation"]
54325#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54326#[inline]
54327#[cfg(target_endian = "little")]
54328#[target_feature(enable = "neon")]
54329#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54330#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54331#[cfg_attr(
54332 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54333 assert_instr(nop)
54334)]
54335#[cfg_attr(
54336 not(target_arch = "arm"),
54337 stable(feature = "neon_intrinsics", since = "1.59.0")
54338)]
54339#[cfg_attr(
54340 target_arch = "arm",
54341 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54342)]
54343pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54344 unsafe { transmute(a) }
54345}
54346#[doc = "Vector reinterpret cast operation"]
54347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
54348#[inline]
54349#[cfg(target_endian = "big")]
54350#[target_feature(enable = "neon")]
54351#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54352#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54353#[cfg_attr(
54354 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54355 assert_instr(nop)
54356)]
54357#[cfg_attr(
54358 not(target_arch = "arm"),
54359 stable(feature = "neon_intrinsics", since = "1.59.0")
54360)]
54361#[cfg_attr(
54362 target_arch = "arm",
54363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54364)]
54365pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
54366 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54367 unsafe {
54368 let ret_val: uint8x16_t = transmute(a);
54369 simd_shuffle!(
54370 ret_val,
54371 ret_val,
54372 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54373 )
54374 }
54375}
54376#[doc = "Vector reinterpret cast operation"]
54377#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54378#[inline]
54379#[cfg(target_endian = "little")]
54380#[target_feature(enable = "neon")]
54381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54383#[cfg_attr(
54384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54385 assert_instr(nop)
54386)]
54387#[cfg_attr(
54388 not(target_arch = "arm"),
54389 stable(feature = "neon_intrinsics", since = "1.59.0")
54390)]
54391#[cfg_attr(
54392 target_arch = "arm",
54393 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54394)]
54395pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54396 unsafe { transmute(a) }
54397}
54398#[doc = "Vector reinterpret cast operation"]
54399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
54400#[inline]
54401#[cfg(target_endian = "big")]
54402#[target_feature(enable = "neon")]
54403#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54404#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54405#[cfg_attr(
54406 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54407 assert_instr(nop)
54408)]
54409#[cfg_attr(
54410 not(target_arch = "arm"),
54411 stable(feature = "neon_intrinsics", since = "1.59.0")
54412)]
54413#[cfg_attr(
54414 target_arch = "arm",
54415 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54416)]
54417pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
54418 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54419 unsafe {
54420 let ret_val: uint16x8_t = transmute(a);
54421 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54422 }
54423}
54424#[doc = "Vector reinterpret cast operation"]
54425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54426#[inline]
54427#[cfg(target_endian = "little")]
54428#[target_feature(enable = "neon")]
54429#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54431#[cfg_attr(
54432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54433 assert_instr(nop)
54434)]
54435#[cfg_attr(
54436 not(target_arch = "arm"),
54437 stable(feature = "neon_intrinsics", since = "1.59.0")
54438)]
54439#[cfg_attr(
54440 target_arch = "arm",
54441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54442)]
54443pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54444 unsafe { transmute(a) }
54445}
54446#[doc = "Vector reinterpret cast operation"]
54447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
54448#[inline]
54449#[cfg(target_endian = "big")]
54450#[target_feature(enable = "neon")]
54451#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54453#[cfg_attr(
54454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54455 assert_instr(nop)
54456)]
54457#[cfg_attr(
54458 not(target_arch = "arm"),
54459 stable(feature = "neon_intrinsics", since = "1.59.0")
54460)]
54461#[cfg_attr(
54462 target_arch = "arm",
54463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54464)]
54465pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
54466 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54467 unsafe {
54468 let ret_val: uint32x4_t = transmute(a);
54469 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54470 }
54471}
54472#[doc = "Vector reinterpret cast operation"]
54473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54474#[inline]
54475#[cfg(target_endian = "little")]
54476#[target_feature(enable = "neon")]
54477#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54478#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54479#[cfg_attr(
54480 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54481 assert_instr(nop)
54482)]
54483#[cfg_attr(
54484 not(target_arch = "arm"),
54485 stable(feature = "neon_intrinsics", since = "1.59.0")
54486)]
54487#[cfg_attr(
54488 target_arch = "arm",
54489 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54490)]
54491pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54492 unsafe { transmute(a) }
54493}
54494#[doc = "Vector reinterpret cast operation"]
54495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
54496#[inline]
54497#[cfg(target_endian = "big")]
54498#[target_feature(enable = "neon")]
54499#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54500#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54501#[cfg_attr(
54502 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54503 assert_instr(nop)
54504)]
54505#[cfg_attr(
54506 not(target_arch = "arm"),
54507 stable(feature = "neon_intrinsics", since = "1.59.0")
54508)]
54509#[cfg_attr(
54510 target_arch = "arm",
54511 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54512)]
54513pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
54514 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54515 unsafe {
54516 let ret_val: uint64x2_t = transmute(a);
54517 simd_shuffle!(ret_val, ret_val, [1, 0])
54518 }
54519}
54520#[doc = "Vector reinterpret cast operation"]
54521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54522#[inline]
54523#[cfg(target_endian = "little")]
54524#[target_feature(enable = "neon")]
54525#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54526#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54527#[cfg_attr(
54528 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54529 assert_instr(nop)
54530)]
54531#[cfg_attr(
54532 not(target_arch = "arm"),
54533 stable(feature = "neon_intrinsics", since = "1.59.0")
54534)]
54535#[cfg_attr(
54536 target_arch = "arm",
54537 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54538)]
54539pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54540 unsafe { transmute(a) }
54541}
54542#[doc = "Vector reinterpret cast operation"]
54543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
54544#[inline]
54545#[cfg(target_endian = "big")]
54546#[target_feature(enable = "neon")]
54547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
54548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54549#[cfg_attr(
54550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54551 assert_instr(nop)
54552)]
54553#[cfg_attr(
54554 not(target_arch = "arm"),
54555 stable(feature = "neon_intrinsics", since = "1.59.0")
54556)]
54557#[cfg_attr(
54558 target_arch = "arm",
54559 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54560)]
54561pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
54562 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
54563 unsafe {
54564 let ret_val: poly8x16_t = transmute(a);
54565 simd_shuffle!(
54566 ret_val,
54567 ret_val,
54568 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54569 )
54570 }
54571}
54572#[doc = "Vector reinterpret cast operation"]
54573#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
54574#[inline]
54575#[cfg(target_endian = "little")]
54576#[target_feature(enable = "neon,aes")]
54577#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54579#[cfg_attr(
54580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54581 assert_instr(nop)
54582)]
54583#[cfg_attr(
54584 not(target_arch = "arm"),
54585 stable(feature = "neon_intrinsics", since = "1.59.0")
54586)]
54587#[cfg_attr(
54588 target_arch = "arm",
54589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54590)]
54591pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
54592 unsafe { transmute(a) }
54593}
54594#[doc = "Vector reinterpret cast operation"]
54595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
54596#[inline]
54597#[cfg(target_endian = "big")]
54598#[target_feature(enable = "neon,aes")]
54599#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54600#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54601#[cfg_attr(
54602 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54603 assert_instr(nop)
54604)]
54605#[cfg_attr(
54606 not(target_arch = "arm"),
54607 stable(feature = "neon_intrinsics", since = "1.59.0")
54608)]
54609#[cfg_attr(
54610 target_arch = "arm",
54611 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54612)]
54613pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
54614 unsafe {
54615 let ret_val: int8x16_t = transmute(a);
54616 simd_shuffle!(
54617 ret_val,
54618 ret_val,
54619 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54620 )
54621 }
54622}
54623#[doc = "Vector reinterpret cast operation"]
54624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
54625#[inline]
54626#[cfg(target_endian = "little")]
54627#[target_feature(enable = "neon,aes")]
54628#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54629#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54630#[cfg_attr(
54631 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54632 assert_instr(nop)
54633)]
54634#[cfg_attr(
54635 not(target_arch = "arm"),
54636 stable(feature = "neon_intrinsics", since = "1.59.0")
54637)]
54638#[cfg_attr(
54639 target_arch = "arm",
54640 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54641)]
54642pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
54643 unsafe { transmute(a) }
54644}
54645#[doc = "Vector reinterpret cast operation"]
54646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
54647#[inline]
54648#[cfg(target_endian = "big")]
54649#[target_feature(enable = "neon,aes")]
54650#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54651#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54652#[cfg_attr(
54653 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54654 assert_instr(nop)
54655)]
54656#[cfg_attr(
54657 not(target_arch = "arm"),
54658 stable(feature = "neon_intrinsics", since = "1.59.0")
54659)]
54660#[cfg_attr(
54661 target_arch = "arm",
54662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54663)]
54664pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
54665 unsafe {
54666 let ret_val: int16x8_t = transmute(a);
54667 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54668 }
54669}
54670#[doc = "Vector reinterpret cast operation"]
54671#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
54672#[inline]
54673#[cfg(target_endian = "little")]
54674#[target_feature(enable = "neon,aes")]
54675#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54677#[cfg_attr(
54678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54679 assert_instr(nop)
54680)]
54681#[cfg_attr(
54682 not(target_arch = "arm"),
54683 stable(feature = "neon_intrinsics", since = "1.59.0")
54684)]
54685#[cfg_attr(
54686 target_arch = "arm",
54687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54688)]
54689pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
54690 unsafe { transmute(a) }
54691}
54692#[doc = "Vector reinterpret cast operation"]
54693#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
54694#[inline]
54695#[cfg(target_endian = "big")]
54696#[target_feature(enable = "neon,aes")]
54697#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54698#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54699#[cfg_attr(
54700 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54701 assert_instr(nop)
54702)]
54703#[cfg_attr(
54704 not(target_arch = "arm"),
54705 stable(feature = "neon_intrinsics", since = "1.59.0")
54706)]
54707#[cfg_attr(
54708 target_arch = "arm",
54709 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54710)]
54711pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
54712 unsafe {
54713 let ret_val: int32x4_t = transmute(a);
54714 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54715 }
54716}
54717#[doc = "Vector reinterpret cast operation"]
54718#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
54719#[inline]
54720#[cfg(target_endian = "little")]
54721#[target_feature(enable = "neon,aes")]
54722#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54723#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54724#[cfg_attr(
54725 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54726 assert_instr(nop)
54727)]
54728#[cfg_attr(
54729 not(target_arch = "arm"),
54730 stable(feature = "neon_intrinsics", since = "1.59.0")
54731)]
54732#[cfg_attr(
54733 target_arch = "arm",
54734 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54735)]
54736pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
54737 unsafe { transmute(a) }
54738}
54739#[doc = "Vector reinterpret cast operation"]
54740#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
54741#[inline]
54742#[cfg(target_endian = "big")]
54743#[target_feature(enable = "neon,aes")]
54744#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54745#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54746#[cfg_attr(
54747 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54748 assert_instr(nop)
54749)]
54750#[cfg_attr(
54751 not(target_arch = "arm"),
54752 stable(feature = "neon_intrinsics", since = "1.59.0")
54753)]
54754#[cfg_attr(
54755 target_arch = "arm",
54756 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54757)]
54758pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
54759 unsafe {
54760 let ret_val: int64x2_t = transmute(a);
54761 simd_shuffle!(ret_val, ret_val, [1, 0])
54762 }
54763}
54764#[doc = "Vector reinterpret cast operation"]
54765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
54766#[inline]
54767#[cfg(target_endian = "little")]
54768#[target_feature(enable = "neon,aes")]
54769#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54770#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54771#[cfg_attr(
54772 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54773 assert_instr(nop)
54774)]
54775#[cfg_attr(
54776 not(target_arch = "arm"),
54777 stable(feature = "neon_intrinsics", since = "1.59.0")
54778)]
54779#[cfg_attr(
54780 target_arch = "arm",
54781 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54782)]
54783pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
54784 unsafe { transmute(a) }
54785}
54786#[doc = "Vector reinterpret cast operation"]
54787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
54788#[inline]
54789#[cfg(target_endian = "big")]
54790#[target_feature(enable = "neon,aes")]
54791#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54793#[cfg_attr(
54794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54795 assert_instr(nop)
54796)]
54797#[cfg_attr(
54798 not(target_arch = "arm"),
54799 stable(feature = "neon_intrinsics", since = "1.59.0")
54800)]
54801#[cfg_attr(
54802 target_arch = "arm",
54803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54804)]
54805pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
54806 unsafe {
54807 let ret_val: uint8x16_t = transmute(a);
54808 simd_shuffle!(
54809 ret_val,
54810 ret_val,
54811 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
54812 )
54813 }
54814}
54815#[doc = "Vector reinterpret cast operation"]
54816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
54817#[inline]
54818#[cfg(target_endian = "little")]
54819#[target_feature(enable = "neon,aes")]
54820#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54822#[cfg_attr(
54823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54824 assert_instr(nop)
54825)]
54826#[cfg_attr(
54827 not(target_arch = "arm"),
54828 stable(feature = "neon_intrinsics", since = "1.59.0")
54829)]
54830#[cfg_attr(
54831 target_arch = "arm",
54832 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54833)]
54834pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
54835 unsafe { transmute(a) }
54836}
54837#[doc = "Vector reinterpret cast operation"]
54838#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
54839#[inline]
54840#[cfg(target_endian = "big")]
54841#[target_feature(enable = "neon,aes")]
54842#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54843#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54844#[cfg_attr(
54845 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54846 assert_instr(nop)
54847)]
54848#[cfg_attr(
54849 not(target_arch = "arm"),
54850 stable(feature = "neon_intrinsics", since = "1.59.0")
54851)]
54852#[cfg_attr(
54853 target_arch = "arm",
54854 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54855)]
54856pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
54857 unsafe {
54858 let ret_val: uint16x8_t = transmute(a);
54859 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
54860 }
54861}
54862#[doc = "Vector reinterpret cast operation"]
54863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
54864#[inline]
54865#[cfg(target_endian = "little")]
54866#[target_feature(enable = "neon,aes")]
54867#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54869#[cfg_attr(
54870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54871 assert_instr(nop)
54872)]
54873#[cfg_attr(
54874 not(target_arch = "arm"),
54875 stable(feature = "neon_intrinsics", since = "1.59.0")
54876)]
54877#[cfg_attr(
54878 target_arch = "arm",
54879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54880)]
54881pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
54882 unsafe { transmute(a) }
54883}
54884#[doc = "Vector reinterpret cast operation"]
54885#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
54886#[inline]
54887#[cfg(target_endian = "big")]
54888#[target_feature(enable = "neon,aes")]
54889#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54891#[cfg_attr(
54892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54893 assert_instr(nop)
54894)]
54895#[cfg_attr(
54896 not(target_arch = "arm"),
54897 stable(feature = "neon_intrinsics", since = "1.59.0")
54898)]
54899#[cfg_attr(
54900 target_arch = "arm",
54901 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54902)]
54903pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
54904 unsafe {
54905 let ret_val: uint32x4_t = transmute(a);
54906 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
54907 }
54908}
54909#[doc = "Vector reinterpret cast operation"]
54910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
54911#[inline]
54912#[cfg(target_endian = "little")]
54913#[target_feature(enable = "neon,aes")]
54914#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54915#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54916#[cfg_attr(
54917 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54918 assert_instr(nop)
54919)]
54920#[cfg_attr(
54921 not(target_arch = "arm"),
54922 stable(feature = "neon_intrinsics", since = "1.59.0")
54923)]
54924#[cfg_attr(
54925 target_arch = "arm",
54926 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54927)]
54928pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
54929 unsafe { transmute(a) }
54930}
54931#[doc = "Vector reinterpret cast operation"]
54932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
54933#[inline]
54934#[cfg(target_endian = "big")]
54935#[target_feature(enable = "neon,aes")]
54936#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54937#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54938#[cfg_attr(
54939 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54940 assert_instr(nop)
54941)]
54942#[cfg_attr(
54943 not(target_arch = "arm"),
54944 stable(feature = "neon_intrinsics", since = "1.59.0")
54945)]
54946#[cfg_attr(
54947 target_arch = "arm",
54948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54949)]
54950pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
54951 unsafe {
54952 let ret_val: uint64x2_t = transmute(a);
54953 simd_shuffle!(ret_val, ret_val, [1, 0])
54954 }
54955}
54956#[doc = "Vector reinterpret cast operation"]
54957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
54958#[inline]
54959#[cfg(target_endian = "little")]
54960#[target_feature(enable = "neon,aes")]
54961#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54963#[cfg_attr(
54964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54965 assert_instr(nop)
54966)]
54967#[cfg_attr(
54968 not(target_arch = "arm"),
54969 stable(feature = "neon_intrinsics", since = "1.59.0")
54970)]
54971#[cfg_attr(
54972 target_arch = "arm",
54973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54974)]
54975pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
54976 unsafe { transmute(a) }
54977}
54978#[doc = "Vector reinterpret cast operation"]
54979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
54980#[inline]
54981#[cfg(target_endian = "big")]
54982#[target_feature(enable = "neon,aes")]
54983#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
54984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
54985#[cfg_attr(
54986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
54987 assert_instr(nop)
54988)]
54989#[cfg_attr(
54990 not(target_arch = "arm"),
54991 stable(feature = "neon_intrinsics", since = "1.59.0")
54992)]
54993#[cfg_attr(
54994 target_arch = "arm",
54995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
54996)]
54997pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
54998 unsafe {
54999 let ret_val: poly8x16_t = transmute(a);
55000 simd_shuffle!(
55001 ret_val,
55002 ret_val,
55003 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
55004 )
55005 }
55006}
55007#[doc = "Vector reinterpret cast operation"]
55008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55009#[inline]
55010#[cfg(target_endian = "little")]
55011#[target_feature(enable = "neon,aes")]
55012#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55014#[cfg_attr(
55015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55016 assert_instr(nop)
55017)]
55018#[cfg_attr(
55019 not(target_arch = "arm"),
55020 stable(feature = "neon_intrinsics", since = "1.59.0")
55021)]
55022#[cfg_attr(
55023 target_arch = "arm",
55024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55025)]
55026pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55027 unsafe { transmute(a) }
55028}
55029#[doc = "Vector reinterpret cast operation"]
55030#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
55031#[inline]
55032#[cfg(target_endian = "big")]
55033#[target_feature(enable = "neon,aes")]
55034#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55035#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55036#[cfg_attr(
55037 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55038 assert_instr(nop)
55039)]
55040#[cfg_attr(
55041 not(target_arch = "arm"),
55042 stable(feature = "neon_intrinsics", since = "1.59.0")
55043)]
55044#[cfg_attr(
55045 target_arch = "arm",
55046 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55047)]
55048pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
55049 unsafe {
55050 let ret_val: poly16x8_t = transmute(a);
55051 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
55052 }
55053}
55054#[doc = "Vector reinterpret cast operation"]
55055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55056#[inline]
55057#[cfg(target_endian = "little")]
55058#[target_feature(enable = "neon,aes")]
55059#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55060#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55061#[cfg_attr(
55062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55063 assert_instr(nop)
55064)]
55065#[cfg_attr(
55066 not(target_arch = "arm"),
55067 stable(feature = "neon_intrinsics", since = "1.59.0")
55068)]
55069#[cfg_attr(
55070 target_arch = "arm",
55071 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55072)]
55073pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55074 unsafe { transmute(a) }
55075}
55076#[doc = "Vector reinterpret cast operation"]
55077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
55078#[inline]
55079#[cfg(target_endian = "big")]
55080#[target_feature(enable = "neon,aes")]
55081#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55082#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55083#[cfg_attr(
55084 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55085 assert_instr(nop)
55086)]
55087#[cfg_attr(
55088 not(target_arch = "arm"),
55089 stable(feature = "neon_intrinsics", since = "1.59.0")
55090)]
55091#[cfg_attr(
55092 target_arch = "arm",
55093 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55094)]
55095pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
55096 unsafe {
55097 let ret_val: poly64x2_t = transmute(a);
55098 simd_shuffle!(ret_val, ret_val, [1, 0])
55099 }
55100}
55101#[doc = "Vector reinterpret cast operation"]
55102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55103#[inline]
55104#[cfg(target_endian = "little")]
55105#[target_feature(enable = "neon,aes")]
55106#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55107#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55108#[cfg_attr(
55109 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55110 assert_instr(nop)
55111)]
55112#[cfg_attr(
55113 not(target_arch = "arm"),
55114 stable(feature = "neon_intrinsics", since = "1.59.0")
55115)]
55116#[cfg_attr(
55117 target_arch = "arm",
55118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55119)]
55120pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55121 unsafe { transmute(a) }
55122}
55123#[doc = "Vector reinterpret cast operation"]
55124#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
55125#[inline]
55126#[cfg(target_endian = "big")]
55127#[target_feature(enable = "neon,aes")]
55128#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55129#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55130#[cfg_attr(
55131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55132 assert_instr(nop)
55133)]
55134#[cfg_attr(
55135 not(target_arch = "arm"),
55136 stable(feature = "neon_intrinsics", since = "1.59.0")
55137)]
55138#[cfg_attr(
55139 target_arch = "arm",
55140 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55141)]
55142pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
55143 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55144 unsafe { transmute(a) }
55145}
55146#[doc = "Vector reinterpret cast operation"]
55147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55148#[inline]
55149#[cfg(target_endian = "little")]
55150#[target_feature(enable = "neon,aes")]
55151#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55153#[cfg_attr(
55154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55155 assert_instr(nop)
55156)]
55157#[cfg_attr(
55158 not(target_arch = "arm"),
55159 stable(feature = "neon_intrinsics", since = "1.59.0")
55160)]
55161#[cfg_attr(
55162 target_arch = "arm",
55163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55164)]
55165pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55166 unsafe { transmute(a) }
55167}
55168#[doc = "Vector reinterpret cast operation"]
55169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
55170#[inline]
55171#[cfg(target_endian = "big")]
55172#[target_feature(enable = "neon,aes")]
55173#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55174#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55175#[cfg_attr(
55176 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55177 assert_instr(nop)
55178)]
55179#[cfg_attr(
55180 not(target_arch = "arm"),
55181 stable(feature = "neon_intrinsics", since = "1.59.0")
55182)]
55183#[cfg_attr(
55184 target_arch = "arm",
55185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55186)]
55187pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
55188 let a: int8x16_t =
55189 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55190 unsafe { transmute(a) }
55191}
55192#[doc = "Vector reinterpret cast operation"]
55193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55194#[inline]
55195#[cfg(target_endian = "little")]
55196#[target_feature(enable = "neon,aes")]
55197#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55198#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55199#[cfg_attr(
55200 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55201 assert_instr(nop)
55202)]
55203#[cfg_attr(
55204 not(target_arch = "arm"),
55205 stable(feature = "neon_intrinsics", since = "1.59.0")
55206)]
55207#[cfg_attr(
55208 target_arch = "arm",
55209 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55210)]
55211pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55212 unsafe { transmute(a) }
55213}
55214#[doc = "Vector reinterpret cast operation"]
55215#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
55216#[inline]
55217#[cfg(target_endian = "big")]
55218#[target_feature(enable = "neon,aes")]
55219#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55220#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55221#[cfg_attr(
55222 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55223 assert_instr(nop)
55224)]
55225#[cfg_attr(
55226 not(target_arch = "arm"),
55227 stable(feature = "neon_intrinsics", since = "1.59.0")
55228)]
55229#[cfg_attr(
55230 target_arch = "arm",
55231 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55232)]
55233pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
55234 let a: int8x16_t =
55235 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55236 unsafe {
55237 let ret_val: poly64x2_t = transmute(a);
55238 simd_shuffle!(ret_val, ret_val, [1, 0])
55239 }
55240}
55241#[doc = "Vector reinterpret cast operation"]
55242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55243#[inline]
55244#[cfg(target_endian = "little")]
55245#[target_feature(enable = "neon,aes")]
55246#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55247#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55248#[cfg_attr(
55249 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55250 assert_instr(nop)
55251)]
55252#[cfg_attr(
55253 not(target_arch = "arm"),
55254 stable(feature = "neon_intrinsics", since = "1.59.0")
55255)]
55256#[cfg_attr(
55257 target_arch = "arm",
55258 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55259)]
55260pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55261 unsafe { transmute(a) }
55262}
55263#[doc = "Vector reinterpret cast operation"]
55264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
55265#[inline]
55266#[cfg(target_endian = "big")]
55267#[target_feature(enable = "neon,aes")]
55268#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55269#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55270#[cfg_attr(
55271 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55272 assert_instr(nop)
55273)]
55274#[cfg_attr(
55275 not(target_arch = "arm"),
55276 stable(feature = "neon_intrinsics", since = "1.59.0")
55277)]
55278#[cfg_attr(
55279 target_arch = "arm",
55280 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55281)]
55282pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
55283 let a: int16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55284 unsafe { transmute(a) }
55285}
55286#[doc = "Vector reinterpret cast operation"]
55287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55288#[inline]
55289#[cfg(target_endian = "little")]
55290#[target_feature(enable = "neon,aes")]
55291#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55292#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55293#[cfg_attr(
55294 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55295 assert_instr(nop)
55296)]
55297#[cfg_attr(
55298 not(target_arch = "arm"),
55299 stable(feature = "neon_intrinsics", since = "1.59.0")
55300)]
55301#[cfg_attr(
55302 target_arch = "arm",
55303 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55304)]
55305pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55306 unsafe { transmute(a) }
55307}
55308#[doc = "Vector reinterpret cast operation"]
55309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
55310#[inline]
55311#[cfg(target_endian = "big")]
55312#[target_feature(enable = "neon,aes")]
55313#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55314#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55315#[cfg_attr(
55316 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55317 assert_instr(nop)
55318)]
55319#[cfg_attr(
55320 not(target_arch = "arm"),
55321 stable(feature = "neon_intrinsics", since = "1.59.0")
55322)]
55323#[cfg_attr(
55324 target_arch = "arm",
55325 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55326)]
55327pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
55328 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55329 unsafe { transmute(a) }
55330}
55331#[doc = "Vector reinterpret cast operation"]
55332#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55333#[inline]
55334#[cfg(target_endian = "little")]
55335#[target_feature(enable = "neon,aes")]
55336#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55338#[cfg_attr(
55339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55340 assert_instr(nop)
55341)]
55342#[cfg_attr(
55343 not(target_arch = "arm"),
55344 stable(feature = "neon_intrinsics", since = "1.59.0")
55345)]
55346#[cfg_attr(
55347 target_arch = "arm",
55348 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55349)]
55350pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55351 unsafe { transmute(a) }
55352}
55353#[doc = "Vector reinterpret cast operation"]
55354#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
55355#[inline]
55356#[cfg(target_endian = "big")]
55357#[target_feature(enable = "neon,aes")]
55358#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55359#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55360#[cfg_attr(
55361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55362 assert_instr(nop)
55363)]
55364#[cfg_attr(
55365 not(target_arch = "arm"),
55366 stable(feature = "neon_intrinsics", since = "1.59.0")
55367)]
55368#[cfg_attr(
55369 target_arch = "arm",
55370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55371)]
55372pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
55373 let a: int16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55374 unsafe {
55375 let ret_val: poly64x2_t = transmute(a);
55376 simd_shuffle!(ret_val, ret_val, [1, 0])
55377 }
55378}
55379#[doc = "Vector reinterpret cast operation"]
55380#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55381#[inline]
55382#[cfg(target_endian = "little")]
55383#[target_feature(enable = "neon,aes")]
55384#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55386#[cfg_attr(
55387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55388 assert_instr(nop)
55389)]
55390#[cfg_attr(
55391 not(target_arch = "arm"),
55392 stable(feature = "neon_intrinsics", since = "1.59.0")
55393)]
55394#[cfg_attr(
55395 target_arch = "arm",
55396 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55397)]
55398pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55399 unsafe { transmute(a) }
55400}
55401#[doc = "Vector reinterpret cast operation"]
55402#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
55403#[inline]
55404#[cfg(target_endian = "big")]
55405#[target_feature(enable = "neon,aes")]
55406#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55408#[cfg_attr(
55409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55410 assert_instr(nop)
55411)]
55412#[cfg_attr(
55413 not(target_arch = "arm"),
55414 stable(feature = "neon_intrinsics", since = "1.59.0")
55415)]
55416#[cfg_attr(
55417 target_arch = "arm",
55418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55419)]
55420pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
55421 let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55422 unsafe { transmute(a) }
55423}
55424#[doc = "Vector reinterpret cast operation"]
55425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55426#[inline]
55427#[cfg(target_endian = "little")]
55428#[target_feature(enable = "neon,aes")]
55429#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55430#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55431#[cfg_attr(
55432 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55433 assert_instr(nop)
55434)]
55435#[cfg_attr(
55436 not(target_arch = "arm"),
55437 stable(feature = "neon_intrinsics", since = "1.59.0")
55438)]
55439#[cfg_attr(
55440 target_arch = "arm",
55441 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55442)]
55443pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55444 unsafe { transmute(a) }
55445}
55446#[doc = "Vector reinterpret cast operation"]
55447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
55448#[inline]
55449#[cfg(target_endian = "big")]
55450#[target_feature(enable = "neon,aes")]
55451#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55452#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55453#[cfg_attr(
55454 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55455 assert_instr(nop)
55456)]
55457#[cfg_attr(
55458 not(target_arch = "arm"),
55459 stable(feature = "neon_intrinsics", since = "1.59.0")
55460)]
55461#[cfg_attr(
55462 target_arch = "arm",
55463 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55464)]
55465pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
55466 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55467 unsafe { transmute(a) }
55468}
55469#[doc = "Vector reinterpret cast operation"]
55470#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55471#[inline]
55472#[cfg(target_endian = "little")]
55473#[target_feature(enable = "neon,aes")]
55474#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55475#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55476#[cfg_attr(
55477 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55478 assert_instr(nop)
55479)]
55480#[cfg_attr(
55481 not(target_arch = "arm"),
55482 stable(feature = "neon_intrinsics", since = "1.59.0")
55483)]
55484#[cfg_attr(
55485 target_arch = "arm",
55486 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55487)]
55488pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55489 unsafe { transmute(a) }
55490}
55491#[doc = "Vector reinterpret cast operation"]
55492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
55493#[inline]
55494#[cfg(target_endian = "big")]
55495#[target_feature(enable = "neon,aes")]
55496#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55497#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55498#[cfg_attr(
55499 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55500 assert_instr(nop)
55501)]
55502#[cfg_attr(
55503 not(target_arch = "arm"),
55504 stable(feature = "neon_intrinsics", since = "1.59.0")
55505)]
55506#[cfg_attr(
55507 target_arch = "arm",
55508 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55509)]
55510pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
55511 let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55512 unsafe {
55513 let ret_val: poly64x2_t = transmute(a);
55514 simd_shuffle!(ret_val, ret_val, [1, 0])
55515 }
55516}
55517#[doc = "Vector reinterpret cast operation"]
55518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55519#[inline]
55520#[cfg(target_endian = "little")]
55521#[target_feature(enable = "neon,aes")]
55522#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55524#[cfg_attr(
55525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55526 assert_instr(nop)
55527)]
55528#[cfg_attr(
55529 not(target_arch = "arm"),
55530 stable(feature = "neon_intrinsics", since = "1.59.0")
55531)]
55532#[cfg_attr(
55533 target_arch = "arm",
55534 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55535)]
55536pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55537 unsafe { transmute(a) }
55538}
55539#[doc = "Vector reinterpret cast operation"]
55540#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
55541#[inline]
55542#[cfg(target_endian = "big")]
55543#[target_feature(enable = "neon,aes")]
55544#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55546#[cfg_attr(
55547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55548 assert_instr(nop)
55549)]
55550#[cfg_attr(
55551 not(target_arch = "arm"),
55552 stable(feature = "neon_intrinsics", since = "1.59.0")
55553)]
55554#[cfg_attr(
55555 target_arch = "arm",
55556 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55557)]
55558pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
55559 let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55560 unsafe { transmute(a) }
55561}
55562#[doc = "Vector reinterpret cast operation"]
55563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
55564#[inline]
55565#[cfg(target_endian = "little")]
55566#[target_feature(enable = "neon,aes")]
55567#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55568#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55569#[cfg_attr(
55570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55571 assert_instr(nop)
55572)]
55573#[cfg_attr(
55574 not(target_arch = "arm"),
55575 stable(feature = "neon_intrinsics", since = "1.59.0")
55576)]
55577#[cfg_attr(
55578 target_arch = "arm",
55579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55580)]
55581pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
55582 unsafe { transmute(a) }
55583}
55584#[doc = "Vector reinterpret cast operation"]
55585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
55586#[inline]
55587#[cfg(target_endian = "big")]
55588#[target_feature(enable = "neon,aes")]
55589#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55590#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55591#[cfg_attr(
55592 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55593 assert_instr(nop)
55594)]
55595#[cfg_attr(
55596 not(target_arch = "arm"),
55597 stable(feature = "neon_intrinsics", since = "1.59.0")
55598)]
55599#[cfg_attr(
55600 target_arch = "arm",
55601 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55602)]
55603pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
55604 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55605 unsafe { transmute(a) }
55606}
55607#[doc = "Vector reinterpret cast operation"]
55608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
55609#[inline]
55610#[cfg(target_endian = "little")]
55611#[target_feature(enable = "neon,aes")]
55612#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55614#[cfg_attr(
55615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55616 assert_instr(nop)
55617)]
55618#[cfg_attr(
55619 not(target_arch = "arm"),
55620 stable(feature = "neon_intrinsics", since = "1.59.0")
55621)]
55622#[cfg_attr(
55623 target_arch = "arm",
55624 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55625)]
55626pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
55627 unsafe { transmute(a) }
55628}
55629#[doc = "Vector reinterpret cast operation"]
55630#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
55631#[inline]
55632#[cfg(target_endian = "big")]
55633#[target_feature(enable = "neon,aes")]
55634#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55636#[cfg_attr(
55637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55638 assert_instr(nop)
55639)]
55640#[cfg_attr(
55641 not(target_arch = "arm"),
55642 stable(feature = "neon_intrinsics", since = "1.59.0")
55643)]
55644#[cfg_attr(
55645 target_arch = "arm",
55646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55647)]
55648pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
55649 let a: uint8x16_t =
55650 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55651 unsafe { transmute(a) }
55652}
55653#[doc = "Vector reinterpret cast operation"]
55654#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
55655#[inline]
55656#[cfg(target_endian = "little")]
55657#[target_feature(enable = "neon,aes")]
55658#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55660#[cfg_attr(
55661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55662 assert_instr(nop)
55663)]
55664#[cfg_attr(
55665 not(target_arch = "arm"),
55666 stable(feature = "neon_intrinsics", since = "1.59.0")
55667)]
55668#[cfg_attr(
55669 target_arch = "arm",
55670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55671)]
55672pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
55673 unsafe { transmute(a) }
55674}
55675#[doc = "Vector reinterpret cast operation"]
55676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
55677#[inline]
55678#[cfg(target_endian = "big")]
55679#[target_feature(enable = "neon,aes")]
55680#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55682#[cfg_attr(
55683 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55684 assert_instr(nop)
55685)]
55686#[cfg_attr(
55687 not(target_arch = "arm"),
55688 stable(feature = "neon_intrinsics", since = "1.59.0")
55689)]
55690#[cfg_attr(
55691 target_arch = "arm",
55692 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55693)]
55694pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
55695 let a: uint8x16_t =
55696 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
55697 unsafe {
55698 let ret_val: poly64x2_t = transmute(a);
55699 simd_shuffle!(ret_val, ret_val, [1, 0])
55700 }
55701}
55702#[doc = "Vector reinterpret cast operation"]
55703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
55704#[inline]
55705#[cfg(target_endian = "little")]
55706#[target_feature(enable = "neon,aes")]
55707#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55708#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55709#[cfg_attr(
55710 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55711 assert_instr(nop)
55712)]
55713#[cfg_attr(
55714 not(target_arch = "arm"),
55715 stable(feature = "neon_intrinsics", since = "1.59.0")
55716)]
55717#[cfg_attr(
55718 target_arch = "arm",
55719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55720)]
55721pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
55722 unsafe { transmute(a) }
55723}
55724#[doc = "Vector reinterpret cast operation"]
55725#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
55726#[inline]
55727#[cfg(target_endian = "big")]
55728#[target_feature(enable = "neon,aes")]
55729#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55730#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55731#[cfg_attr(
55732 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55733 assert_instr(nop)
55734)]
55735#[cfg_attr(
55736 not(target_arch = "arm"),
55737 stable(feature = "neon_intrinsics", since = "1.59.0")
55738)]
55739#[cfg_attr(
55740 target_arch = "arm",
55741 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55742)]
55743pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
55744 let a: uint16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55745 unsafe { transmute(a) }
55746}
55747#[doc = "Vector reinterpret cast operation"]
55748#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
55749#[inline]
55750#[cfg(target_endian = "little")]
55751#[target_feature(enable = "neon,aes")]
55752#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55754#[cfg_attr(
55755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55756 assert_instr(nop)
55757)]
55758#[cfg_attr(
55759 not(target_arch = "arm"),
55760 stable(feature = "neon_intrinsics", since = "1.59.0")
55761)]
55762#[cfg_attr(
55763 target_arch = "arm",
55764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55765)]
55766pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
55767 unsafe { transmute(a) }
55768}
55769#[doc = "Vector reinterpret cast operation"]
55770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
55771#[inline]
55772#[cfg(target_endian = "big")]
55773#[target_feature(enable = "neon,aes")]
55774#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55775#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55776#[cfg_attr(
55777 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55778 assert_instr(nop)
55779)]
55780#[cfg_attr(
55781 not(target_arch = "arm"),
55782 stable(feature = "neon_intrinsics", since = "1.59.0")
55783)]
55784#[cfg_attr(
55785 target_arch = "arm",
55786 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55787)]
55788pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
55789 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55790 unsafe { transmute(a) }
55791}
55792#[doc = "Vector reinterpret cast operation"]
55793#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
55794#[inline]
55795#[cfg(target_endian = "little")]
55796#[target_feature(enable = "neon,aes")]
55797#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55798#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55799#[cfg_attr(
55800 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55801 assert_instr(nop)
55802)]
55803#[cfg_attr(
55804 not(target_arch = "arm"),
55805 stable(feature = "neon_intrinsics", since = "1.59.0")
55806)]
55807#[cfg_attr(
55808 target_arch = "arm",
55809 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55810)]
55811pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
55812 unsafe { transmute(a) }
55813}
55814#[doc = "Vector reinterpret cast operation"]
55815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
55816#[inline]
55817#[cfg(target_endian = "big")]
55818#[target_feature(enable = "neon,aes")]
55819#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55820#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55821#[cfg_attr(
55822 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55823 assert_instr(nop)
55824)]
55825#[cfg_attr(
55826 not(target_arch = "arm"),
55827 stable(feature = "neon_intrinsics", since = "1.59.0")
55828)]
55829#[cfg_attr(
55830 target_arch = "arm",
55831 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55832)]
55833pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
55834 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
55835 unsafe {
55836 let ret_val: poly64x2_t = transmute(a);
55837 simd_shuffle!(ret_val, ret_val, [1, 0])
55838 }
55839}
55840#[doc = "Vector reinterpret cast operation"]
55841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
55842#[inline]
55843#[cfg(target_endian = "little")]
55844#[target_feature(enable = "neon,aes")]
55845#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55846#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55847#[cfg_attr(
55848 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55849 assert_instr(nop)
55850)]
55851#[cfg_attr(
55852 not(target_arch = "arm"),
55853 stable(feature = "neon_intrinsics", since = "1.59.0")
55854)]
55855#[cfg_attr(
55856 target_arch = "arm",
55857 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55858)]
55859pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
55860 unsafe { transmute(a) }
55861}
55862#[doc = "Vector reinterpret cast operation"]
55863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
55864#[inline]
55865#[cfg(target_endian = "big")]
55866#[target_feature(enable = "neon,aes")]
55867#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55868#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55869#[cfg_attr(
55870 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55871 assert_instr(nop)
55872)]
55873#[cfg_attr(
55874 not(target_arch = "arm"),
55875 stable(feature = "neon_intrinsics", since = "1.59.0")
55876)]
55877#[cfg_attr(
55878 target_arch = "arm",
55879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55880)]
55881pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
55882 let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
55883 unsafe { transmute(a) }
55884}
55885#[doc = "Vector reinterpret cast operation"]
55886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
55887#[inline]
55888#[cfg(target_endian = "little")]
55889#[target_feature(enable = "neon,aes")]
55890#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55892#[cfg_attr(
55893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55894 assert_instr(nop)
55895)]
55896#[cfg_attr(
55897 not(target_arch = "arm"),
55898 stable(feature = "neon_intrinsics", since = "1.59.0")
55899)]
55900#[cfg_attr(
55901 target_arch = "arm",
55902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55903)]
55904pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
55905 unsafe { transmute(a) }
55906}
55907#[doc = "Vector reinterpret cast operation"]
55908#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
55909#[inline]
55910#[cfg(target_endian = "big")]
55911#[target_feature(enable = "neon,aes")]
55912#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55914#[cfg_attr(
55915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55916 assert_instr(nop)
55917)]
55918#[cfg_attr(
55919 not(target_arch = "arm"),
55920 stable(feature = "neon_intrinsics", since = "1.59.0")
55921)]
55922#[cfg_attr(
55923 target_arch = "arm",
55924 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55925)]
55926pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
55927 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55928 unsafe { transmute(a) }
55929}
55930#[doc = "Vector reinterpret cast operation"]
55931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
55932#[inline]
55933#[cfg(target_endian = "little")]
55934#[target_feature(enable = "neon,aes")]
55935#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55937#[cfg_attr(
55938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55939 assert_instr(nop)
55940)]
55941#[cfg_attr(
55942 not(target_arch = "arm"),
55943 stable(feature = "neon_intrinsics", since = "1.59.0")
55944)]
55945#[cfg_attr(
55946 target_arch = "arm",
55947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55948)]
55949pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
55950 unsafe { transmute(a) }
55951}
55952#[doc = "Vector reinterpret cast operation"]
55953#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
55954#[inline]
55955#[cfg(target_endian = "big")]
55956#[target_feature(enable = "neon,aes")]
55957#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55958#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55959#[cfg_attr(
55960 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55961 assert_instr(nop)
55962)]
55963#[cfg_attr(
55964 not(target_arch = "arm"),
55965 stable(feature = "neon_intrinsics", since = "1.59.0")
55966)]
55967#[cfg_attr(
55968 target_arch = "arm",
55969 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55970)]
55971pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
55972 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
55973 unsafe {
55974 let ret_val: poly64x2_t = transmute(a);
55975 simd_shuffle!(ret_val, ret_val, [1, 0])
55976 }
55977}
55978#[doc = "Vector reinterpret cast operation"]
55979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
55980#[inline]
55981#[cfg(target_endian = "little")]
55982#[target_feature(enable = "neon,aes")]
55983#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
55984#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
55985#[cfg_attr(
55986 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
55987 assert_instr(nop)
55988)]
55989#[cfg_attr(
55990 not(target_arch = "arm"),
55991 stable(feature = "neon_intrinsics", since = "1.59.0")
55992)]
55993#[cfg_attr(
55994 target_arch = "arm",
55995 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
55996)]
55997pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
55998 unsafe { transmute(a) }
55999}
56000#[doc = "Vector reinterpret cast operation"]
56001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
56002#[inline]
56003#[cfg(target_endian = "big")]
56004#[target_feature(enable = "neon,aes")]
56005#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56006#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56007#[cfg_attr(
56008 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56009 assert_instr(nop)
56010)]
56011#[cfg_attr(
56012 not(target_arch = "arm"),
56013 stable(feature = "neon_intrinsics", since = "1.59.0")
56014)]
56015#[cfg_attr(
56016 target_arch = "arm",
56017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56018)]
56019pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
56020 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56021 unsafe { transmute(a) }
56022}
56023#[doc = "Vector reinterpret cast operation"]
56024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56025#[inline]
56026#[cfg(target_endian = "little")]
56027#[target_feature(enable = "neon,aes")]
56028#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56029#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56030#[cfg_attr(
56031 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56032 assert_instr(nop)
56033)]
56034#[cfg_attr(
56035 not(target_arch = "arm"),
56036 stable(feature = "neon_intrinsics", since = "1.59.0")
56037)]
56038#[cfg_attr(
56039 target_arch = "arm",
56040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56041)]
56042pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56043 unsafe { transmute(a) }
56044}
56045#[doc = "Vector reinterpret cast operation"]
56046#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
56047#[inline]
56048#[cfg(target_endian = "big")]
56049#[target_feature(enable = "neon,aes")]
56050#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56052#[cfg_attr(
56053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56054 assert_instr(nop)
56055)]
56056#[cfg_attr(
56057 not(target_arch = "arm"),
56058 stable(feature = "neon_intrinsics", since = "1.59.0")
56059)]
56060#[cfg_attr(
56061 target_arch = "arm",
56062 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56063)]
56064pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
56065 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56066 unsafe { transmute(a) }
56067}
56068#[doc = "Vector reinterpret cast operation"]
56069#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56070#[inline]
56071#[cfg(target_endian = "little")]
56072#[target_feature(enable = "neon,aes")]
56073#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56075#[cfg_attr(
56076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56077 assert_instr(nop)
56078)]
56079#[cfg_attr(
56080 not(target_arch = "arm"),
56081 stable(feature = "neon_intrinsics", since = "1.59.0")
56082)]
56083#[cfg_attr(
56084 target_arch = "arm",
56085 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56086)]
56087pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56088 unsafe { transmute(a) }
56089}
56090#[doc = "Vector reinterpret cast operation"]
56091#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
56092#[inline]
56093#[cfg(target_endian = "big")]
56094#[target_feature(enable = "neon,aes")]
56095#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56096#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56097#[cfg_attr(
56098 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56099 assert_instr(nop)
56100)]
56101#[cfg_attr(
56102 not(target_arch = "arm"),
56103 stable(feature = "neon_intrinsics", since = "1.59.0")
56104)]
56105#[cfg_attr(
56106 target_arch = "arm",
56107 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56108)]
56109pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
56110 let a: poly8x16_t =
56111 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56112 unsafe { transmute(a) }
56113}
56114#[doc = "Vector reinterpret cast operation"]
56115#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56116#[inline]
56117#[cfg(target_endian = "little")]
56118#[target_feature(enable = "neon,aes")]
56119#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56121#[cfg_attr(
56122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56123 assert_instr(nop)
56124)]
56125#[cfg_attr(
56126 not(target_arch = "arm"),
56127 stable(feature = "neon_intrinsics", since = "1.59.0")
56128)]
56129#[cfg_attr(
56130 target_arch = "arm",
56131 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56132)]
56133pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56134 unsafe { transmute(a) }
56135}
56136#[doc = "Vector reinterpret cast operation"]
56137#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
56138#[inline]
56139#[cfg(target_endian = "big")]
56140#[target_feature(enable = "neon,aes")]
56141#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56142#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56143#[cfg_attr(
56144 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56145 assert_instr(nop)
56146)]
56147#[cfg_attr(
56148 not(target_arch = "arm"),
56149 stable(feature = "neon_intrinsics", since = "1.59.0")
56150)]
56151#[cfg_attr(
56152 target_arch = "arm",
56153 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56154)]
56155pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
56156 let a: poly8x16_t =
56157 unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
56158 unsafe {
56159 let ret_val: poly64x2_t = transmute(a);
56160 simd_shuffle!(ret_val, ret_val, [1, 0])
56161 }
56162}
56163#[doc = "Vector reinterpret cast operation"]
56164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56165#[inline]
56166#[cfg(target_endian = "little")]
56167#[target_feature(enable = "neon,aes")]
56168#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56169#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56170#[cfg_attr(
56171 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56172 assert_instr(nop)
56173)]
56174#[cfg_attr(
56175 not(target_arch = "arm"),
56176 stable(feature = "neon_intrinsics", since = "1.59.0")
56177)]
56178#[cfg_attr(
56179 target_arch = "arm",
56180 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56181)]
56182pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56183 unsafe { transmute(a) }
56184}
56185#[doc = "Vector reinterpret cast operation"]
56186#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
56187#[inline]
56188#[cfg(target_endian = "big")]
56189#[target_feature(enable = "neon,aes")]
56190#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56191#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56192#[cfg_attr(
56193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56194 assert_instr(nop)
56195)]
56196#[cfg_attr(
56197 not(target_arch = "arm"),
56198 stable(feature = "neon_intrinsics", since = "1.59.0")
56199)]
56200#[cfg_attr(
56201 target_arch = "arm",
56202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56203)]
56204pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
56205 let a: poly16x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
56206 unsafe { transmute(a) }
56207}
56208#[doc = "Vector reinterpret cast operation"]
56209#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56210#[inline]
56211#[cfg(target_endian = "little")]
56212#[target_feature(enable = "neon,aes")]
56213#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56214#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56215#[cfg_attr(
56216 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56217 assert_instr(nop)
56218)]
56219#[cfg_attr(
56220 not(target_arch = "arm"),
56221 stable(feature = "neon_intrinsics", since = "1.59.0")
56222)]
56223#[cfg_attr(
56224 target_arch = "arm",
56225 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56226)]
56227pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56228 unsafe { transmute(a) }
56229}
56230#[doc = "Vector reinterpret cast operation"]
56231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
56232#[inline]
56233#[cfg(target_endian = "big")]
56234#[target_feature(enable = "neon,aes")]
56235#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56236#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56237#[cfg_attr(
56238 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56239 assert_instr(nop)
56240)]
56241#[cfg_attr(
56242 not(target_arch = "arm"),
56243 stable(feature = "neon_intrinsics", since = "1.59.0")
56244)]
56245#[cfg_attr(
56246 target_arch = "arm",
56247 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56248)]
56249pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
56250 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56251 unsafe { transmute(a) }
56252}
56253#[doc = "Vector reinterpret cast operation"]
56254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56255#[inline]
56256#[cfg(target_endian = "little")]
56257#[target_feature(enable = "neon,aes")]
56258#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56260#[cfg_attr(
56261 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56262 assert_instr(nop)
56263)]
56264#[cfg_attr(
56265 not(target_arch = "arm"),
56266 stable(feature = "neon_intrinsics", since = "1.59.0")
56267)]
56268#[cfg_attr(
56269 target_arch = "arm",
56270 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56271)]
56272pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56273 unsafe { transmute(a) }
56274}
56275#[doc = "Vector reinterpret cast operation"]
56276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
56277#[inline]
56278#[cfg(target_endian = "big")]
56279#[target_feature(enable = "neon,aes")]
56280#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56281#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56282#[cfg_attr(
56283 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56284 assert_instr(nop)
56285)]
56286#[cfg_attr(
56287 not(target_arch = "arm"),
56288 stable(feature = "neon_intrinsics", since = "1.59.0")
56289)]
56290#[cfg_attr(
56291 target_arch = "arm",
56292 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56293)]
56294pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
56295 let a: poly16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
56296 unsafe {
56297 let ret_val: poly64x2_t = transmute(a);
56298 simd_shuffle!(ret_val, ret_val, [1, 0])
56299 }
56300}
56301#[doc = "Vector reinterpret cast operation"]
56302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56303#[inline]
56304#[cfg(target_endian = "little")]
56305#[target_feature(enable = "neon,aes")]
56306#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56307#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56308#[cfg_attr(
56309 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56310 assert_instr(nop)
56311)]
56312#[cfg_attr(
56313 not(target_arch = "arm"),
56314 stable(feature = "neon_intrinsics", since = "1.59.0")
56315)]
56316#[cfg_attr(
56317 target_arch = "arm",
56318 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56319)]
56320pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56321 unsafe { transmute(a) }
56322}
56323#[doc = "Vector reinterpret cast operation"]
56324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
56325#[inline]
56326#[cfg(target_endian = "big")]
56327#[target_feature(enable = "neon,aes")]
56328#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56329#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56330#[cfg_attr(
56331 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56332 assert_instr(nop)
56333)]
56334#[cfg_attr(
56335 not(target_arch = "arm"),
56336 stable(feature = "neon_intrinsics", since = "1.59.0")
56337)]
56338#[cfg_attr(
56339 target_arch = "arm",
56340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56341)]
56342pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
56343 unsafe {
56344 let ret_val: int8x8_t = transmute(a);
56345 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56346 }
56347}
56348#[doc = "Vector reinterpret cast operation"]
56349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56350#[inline]
56351#[cfg(target_endian = "little")]
56352#[target_feature(enable = "neon,aes")]
56353#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56354#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56355#[cfg_attr(
56356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56357 assert_instr(nop)
56358)]
56359#[cfg_attr(
56360 not(target_arch = "arm"),
56361 stable(feature = "neon_intrinsics", since = "1.59.0")
56362)]
56363#[cfg_attr(
56364 target_arch = "arm",
56365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56366)]
56367pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56368 unsafe { transmute(a) }
56369}
56370#[doc = "Vector reinterpret cast operation"]
56371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
56372#[inline]
56373#[cfg(target_endian = "big")]
56374#[target_feature(enable = "neon,aes")]
56375#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56376#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56377#[cfg_attr(
56378 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56379 assert_instr(nop)
56380)]
56381#[cfg_attr(
56382 not(target_arch = "arm"),
56383 stable(feature = "neon_intrinsics", since = "1.59.0")
56384)]
56385#[cfg_attr(
56386 target_arch = "arm",
56387 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56388)]
56389pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
56390 unsafe {
56391 let ret_val: int16x4_t = transmute(a);
56392 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56393 }
56394}
56395#[doc = "Vector reinterpret cast operation"]
56396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56397#[inline]
56398#[cfg(target_endian = "little")]
56399#[target_feature(enable = "neon,aes")]
56400#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56401#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56402#[cfg_attr(
56403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56404 assert_instr(nop)
56405)]
56406#[cfg_attr(
56407 not(target_arch = "arm"),
56408 stable(feature = "neon_intrinsics", since = "1.59.0")
56409)]
56410#[cfg_attr(
56411 target_arch = "arm",
56412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56413)]
56414pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56415 unsafe { transmute(a) }
56416}
56417#[doc = "Vector reinterpret cast operation"]
56418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
56419#[inline]
56420#[cfg(target_endian = "big")]
56421#[target_feature(enable = "neon,aes")]
56422#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56423#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56424#[cfg_attr(
56425 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56426 assert_instr(nop)
56427)]
56428#[cfg_attr(
56429 not(target_arch = "arm"),
56430 stable(feature = "neon_intrinsics", since = "1.59.0")
56431)]
56432#[cfg_attr(
56433 target_arch = "arm",
56434 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56435)]
56436pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
56437 unsafe {
56438 let ret_val: int32x2_t = transmute(a);
56439 simd_shuffle!(ret_val, ret_val, [1, 0])
56440 }
56441}
56442#[doc = "Vector reinterpret cast operation"]
56443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56444#[inline]
56445#[cfg(target_endian = "little")]
56446#[target_feature(enable = "neon,aes")]
56447#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56448#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56449#[cfg_attr(
56450 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56451 assert_instr(nop)
56452)]
56453#[cfg_attr(
56454 not(target_arch = "arm"),
56455 stable(feature = "neon_intrinsics", since = "1.59.0")
56456)]
56457#[cfg_attr(
56458 target_arch = "arm",
56459 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56460)]
56461pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56462 unsafe { transmute(a) }
56463}
56464#[doc = "Vector reinterpret cast operation"]
56465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
56466#[inline]
56467#[cfg(target_endian = "big")]
56468#[target_feature(enable = "neon,aes")]
56469#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56470#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56471#[cfg_attr(
56472 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56473 assert_instr(nop)
56474)]
56475#[cfg_attr(
56476 not(target_arch = "arm"),
56477 stable(feature = "neon_intrinsics", since = "1.59.0")
56478)]
56479#[cfg_attr(
56480 target_arch = "arm",
56481 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56482)]
56483pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
56484 unsafe {
56485 let ret_val: uint8x8_t = transmute(a);
56486 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56487 }
56488}
56489#[doc = "Vector reinterpret cast operation"]
56490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56491#[inline]
56492#[cfg(target_endian = "little")]
56493#[target_feature(enable = "neon,aes")]
56494#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56495#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56496#[cfg_attr(
56497 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56498 assert_instr(nop)
56499)]
56500#[cfg_attr(
56501 not(target_arch = "arm"),
56502 stable(feature = "neon_intrinsics", since = "1.59.0")
56503)]
56504#[cfg_attr(
56505 target_arch = "arm",
56506 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56507)]
56508pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56509 unsafe { transmute(a) }
56510}
56511#[doc = "Vector reinterpret cast operation"]
56512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
56513#[inline]
56514#[cfg(target_endian = "big")]
56515#[target_feature(enable = "neon,aes")]
56516#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56517#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56518#[cfg_attr(
56519 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56520 assert_instr(nop)
56521)]
56522#[cfg_attr(
56523 not(target_arch = "arm"),
56524 stable(feature = "neon_intrinsics", since = "1.59.0")
56525)]
56526#[cfg_attr(
56527 target_arch = "arm",
56528 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56529)]
56530pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
56531 unsafe {
56532 let ret_val: uint16x4_t = transmute(a);
56533 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56534 }
56535}
56536#[doc = "Vector reinterpret cast operation"]
56537#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56538#[inline]
56539#[cfg(target_endian = "little")]
56540#[target_feature(enable = "neon,aes")]
56541#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56542#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56543#[cfg_attr(
56544 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56545 assert_instr(nop)
56546)]
56547#[cfg_attr(
56548 not(target_arch = "arm"),
56549 stable(feature = "neon_intrinsics", since = "1.59.0")
56550)]
56551#[cfg_attr(
56552 target_arch = "arm",
56553 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56554)]
56555pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
56556 unsafe { transmute(a) }
56557}
56558#[doc = "Vector reinterpret cast operation"]
56559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
56560#[inline]
56561#[cfg(target_endian = "big")]
56562#[target_feature(enable = "neon,aes")]
56563#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56565#[cfg_attr(
56566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56567 assert_instr(nop)
56568)]
56569#[cfg_attr(
56570 not(target_arch = "arm"),
56571 stable(feature = "neon_intrinsics", since = "1.59.0")
56572)]
56573#[cfg_attr(
56574 target_arch = "arm",
56575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56576)]
56577pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
56578 unsafe {
56579 let ret_val: uint32x2_t = transmute(a);
56580 simd_shuffle!(ret_val, ret_val, [1, 0])
56581 }
56582}
56583#[doc = "Vector reinterpret cast operation"]
56584#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
56585#[inline]
56586#[cfg(target_endian = "little")]
56587#[target_feature(enable = "neon,aes")]
56588#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56590#[cfg_attr(
56591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56592 assert_instr(nop)
56593)]
56594#[cfg_attr(
56595 not(target_arch = "arm"),
56596 stable(feature = "neon_intrinsics", since = "1.59.0")
56597)]
56598#[cfg_attr(
56599 target_arch = "arm",
56600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56601)]
56602pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
56603 unsafe { transmute(a) }
56604}
56605#[doc = "Vector reinterpret cast operation"]
56606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
56607#[inline]
56608#[cfg(target_endian = "big")]
56609#[target_feature(enable = "neon,aes")]
56610#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56611#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56612#[cfg_attr(
56613 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56614 assert_instr(nop)
56615)]
56616#[cfg_attr(
56617 not(target_arch = "arm"),
56618 stable(feature = "neon_intrinsics", since = "1.59.0")
56619)]
56620#[cfg_attr(
56621 target_arch = "arm",
56622 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56623)]
56624pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
56625 unsafe {
56626 let ret_val: poly8x8_t = transmute(a);
56627 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56628 }
56629}
56630#[doc = "Vector reinterpret cast operation"]
56631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
56632#[inline]
56633#[cfg(target_endian = "little")]
56634#[target_feature(enable = "neon,aes")]
56635#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56636#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56637#[cfg_attr(
56638 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56639 assert_instr(nop)
56640)]
56641#[cfg_attr(
56642 not(target_arch = "arm"),
56643 stable(feature = "neon_intrinsics", since = "1.59.0")
56644)]
56645#[cfg_attr(
56646 target_arch = "arm",
56647 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56648)]
56649pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
56650 unsafe { transmute(a) }
56651}
56652#[doc = "Vector reinterpret cast operation"]
56653#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
56654#[inline]
56655#[cfg(target_endian = "big")]
56656#[target_feature(enable = "neon,aes")]
56657#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56658#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56659#[cfg_attr(
56660 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56661 assert_instr(nop)
56662)]
56663#[cfg_attr(
56664 not(target_arch = "arm"),
56665 stable(feature = "neon_intrinsics", since = "1.59.0")
56666)]
56667#[cfg_attr(
56668 target_arch = "arm",
56669 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56670)]
56671pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
56672 unsafe {
56673 let ret_val: poly16x4_t = transmute(a);
56674 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56675 }
56676}
56677#[doc = "Vector reinterpret cast operation"]
56678#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
56679#[inline]
56680#[cfg(target_endian = "little")]
56681#[target_feature(enable = "neon,aes")]
56682#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56683#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56684#[cfg_attr(
56685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56686 assert_instr(nop)
56687)]
56688#[cfg_attr(
56689 not(target_arch = "arm"),
56690 stable(feature = "neon_intrinsics", since = "1.59.0")
56691)]
56692#[cfg_attr(
56693 target_arch = "arm",
56694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56695)]
56696pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
56697 unsafe { transmute(a) }
56698}
56699#[doc = "Vector reinterpret cast operation"]
56700#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
56701#[inline]
56702#[cfg(target_endian = "big")]
56703#[target_feature(enable = "neon,aes")]
56704#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56706#[cfg_attr(
56707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56708 assert_instr(nop)
56709)]
56710#[cfg_attr(
56711 not(target_arch = "arm"),
56712 stable(feature = "neon_intrinsics", since = "1.59.0")
56713)]
56714#[cfg_attr(
56715 target_arch = "arm",
56716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56717)]
56718pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
56719 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56720 unsafe { transmute(a) }
56721}
56722#[doc = "Vector reinterpret cast operation"]
56723#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
56724#[inline]
56725#[cfg(target_endian = "little")]
56726#[target_feature(enable = "neon,aes")]
56727#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56728#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56729#[cfg_attr(
56730 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56731 assert_instr(nop)
56732)]
56733#[cfg_attr(
56734 not(target_arch = "arm"),
56735 stable(feature = "neon_intrinsics", since = "1.59.0")
56736)]
56737#[cfg_attr(
56738 target_arch = "arm",
56739 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56740)]
56741pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
56742 unsafe { transmute(a) }
56743}
56744#[doc = "Vector reinterpret cast operation"]
56745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
56746#[inline]
56747#[cfg(target_endian = "big")]
56748#[target_feature(enable = "neon,aes")]
56749#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56750#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56751#[cfg_attr(
56752 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56753 assert_instr(nop)
56754)]
56755#[cfg_attr(
56756 not(target_arch = "arm"),
56757 stable(feature = "neon_intrinsics", since = "1.59.0")
56758)]
56759#[cfg_attr(
56760 target_arch = "arm",
56761 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56762)]
56763pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
56764 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56765 unsafe {
56766 let ret_val: int8x16_t = transmute(a);
56767 simd_shuffle!(
56768 ret_val,
56769 ret_val,
56770 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
56771 )
56772 }
56773}
56774#[doc = "Vector reinterpret cast operation"]
56775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
56776#[inline]
56777#[cfg(target_endian = "little")]
56778#[target_feature(enable = "neon,aes")]
56779#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56780#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56781#[cfg_attr(
56782 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56783 assert_instr(nop)
56784)]
56785#[cfg_attr(
56786 not(target_arch = "arm"),
56787 stable(feature = "neon_intrinsics", since = "1.59.0")
56788)]
56789#[cfg_attr(
56790 target_arch = "arm",
56791 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56792)]
56793pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
56794 unsafe { transmute(a) }
56795}
56796#[doc = "Vector reinterpret cast operation"]
56797#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
56798#[inline]
56799#[cfg(target_endian = "big")]
56800#[target_feature(enable = "neon,aes")]
56801#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56802#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56803#[cfg_attr(
56804 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56805 assert_instr(nop)
56806)]
56807#[cfg_attr(
56808 not(target_arch = "arm"),
56809 stable(feature = "neon_intrinsics", since = "1.59.0")
56810)]
56811#[cfg_attr(
56812 target_arch = "arm",
56813 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56814)]
56815pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
56816 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56817 unsafe {
56818 let ret_val: int16x8_t = transmute(a);
56819 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56820 }
56821}
56822#[doc = "Vector reinterpret cast operation"]
56823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
56824#[inline]
56825#[cfg(target_endian = "little")]
56826#[target_feature(enable = "neon,aes")]
56827#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56828#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56829#[cfg_attr(
56830 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56831 assert_instr(nop)
56832)]
56833#[cfg_attr(
56834 not(target_arch = "arm"),
56835 stable(feature = "neon_intrinsics", since = "1.59.0")
56836)]
56837#[cfg_attr(
56838 target_arch = "arm",
56839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56840)]
56841pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
56842 unsafe { transmute(a) }
56843}
56844#[doc = "Vector reinterpret cast operation"]
56845#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
56846#[inline]
56847#[cfg(target_endian = "big")]
56848#[target_feature(enable = "neon,aes")]
56849#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56850#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56851#[cfg_attr(
56852 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56853 assert_instr(nop)
56854)]
56855#[cfg_attr(
56856 not(target_arch = "arm"),
56857 stable(feature = "neon_intrinsics", since = "1.59.0")
56858)]
56859#[cfg_attr(
56860 target_arch = "arm",
56861 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56862)]
56863pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
56864 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56865 unsafe {
56866 let ret_val: int32x4_t = transmute(a);
56867 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
56868 }
56869}
56870#[doc = "Vector reinterpret cast operation"]
56871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
56872#[inline]
56873#[cfg(target_endian = "little")]
56874#[target_feature(enable = "neon,aes")]
56875#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56876#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56877#[cfg_attr(
56878 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56879 assert_instr(nop)
56880)]
56881#[cfg_attr(
56882 not(target_arch = "arm"),
56883 stable(feature = "neon_intrinsics", since = "1.59.0")
56884)]
56885#[cfg_attr(
56886 target_arch = "arm",
56887 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56888)]
56889pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
56890 unsafe { transmute(a) }
56891}
56892#[doc = "Vector reinterpret cast operation"]
56893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
56894#[inline]
56895#[cfg(target_endian = "big")]
56896#[target_feature(enable = "neon,aes")]
56897#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56899#[cfg_attr(
56900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56901 assert_instr(nop)
56902)]
56903#[cfg_attr(
56904 not(target_arch = "arm"),
56905 stable(feature = "neon_intrinsics", since = "1.59.0")
56906)]
56907#[cfg_attr(
56908 target_arch = "arm",
56909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56910)]
56911pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
56912 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56913 unsafe {
56914 let ret_val: uint8x16_t = transmute(a);
56915 simd_shuffle!(
56916 ret_val,
56917 ret_val,
56918 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
56919 )
56920 }
56921}
56922#[doc = "Vector reinterpret cast operation"]
56923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
56924#[inline]
56925#[cfg(target_endian = "little")]
56926#[target_feature(enable = "neon,aes")]
56927#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56929#[cfg_attr(
56930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56931 assert_instr(nop)
56932)]
56933#[cfg_attr(
56934 not(target_arch = "arm"),
56935 stable(feature = "neon_intrinsics", since = "1.59.0")
56936)]
56937#[cfg_attr(
56938 target_arch = "arm",
56939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56940)]
56941pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
56942 unsafe { transmute(a) }
56943}
56944#[doc = "Vector reinterpret cast operation"]
56945#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
56946#[inline]
56947#[cfg(target_endian = "big")]
56948#[target_feature(enable = "neon,aes")]
56949#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56950#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56951#[cfg_attr(
56952 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56953 assert_instr(nop)
56954)]
56955#[cfg_attr(
56956 not(target_arch = "arm"),
56957 stable(feature = "neon_intrinsics", since = "1.59.0")
56958)]
56959#[cfg_attr(
56960 target_arch = "arm",
56961 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56962)]
56963pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
56964 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
56965 unsafe {
56966 let ret_val: uint16x8_t = transmute(a);
56967 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
56968 }
56969}
56970#[doc = "Vector reinterpret cast operation"]
56971#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
56972#[inline]
56973#[cfg(target_endian = "little")]
56974#[target_feature(enable = "neon,aes")]
56975#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56976#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56977#[cfg_attr(
56978 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
56979 assert_instr(nop)
56980)]
56981#[cfg_attr(
56982 not(target_arch = "arm"),
56983 stable(feature = "neon_intrinsics", since = "1.59.0")
56984)]
56985#[cfg_attr(
56986 target_arch = "arm",
56987 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
56988)]
56989pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
56990 unsafe { transmute(a) }
56991}
56992#[doc = "Vector reinterpret cast operation"]
56993#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
56994#[inline]
56995#[cfg(target_endian = "big")]
56996#[target_feature(enable = "neon,aes")]
56997#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
56998#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
56999#[cfg_attr(
57000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57001 assert_instr(nop)
57002)]
57003#[cfg_attr(
57004 not(target_arch = "arm"),
57005 stable(feature = "neon_intrinsics", since = "1.59.0")
57006)]
57007#[cfg_attr(
57008 target_arch = "arm",
57009 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57010)]
57011pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
57012 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57013 unsafe {
57014 let ret_val: uint32x4_t = transmute(a);
57015 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
57016 }
57017}
57018#[doc = "Vector reinterpret cast operation"]
57019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57020#[inline]
57021#[cfg(target_endian = "little")]
57022#[target_feature(enable = "neon,aes")]
57023#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57024#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57025#[cfg_attr(
57026 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57027 assert_instr(nop)
57028)]
57029#[cfg_attr(
57030 not(target_arch = "arm"),
57031 stable(feature = "neon_intrinsics", since = "1.59.0")
57032)]
57033#[cfg_attr(
57034 target_arch = "arm",
57035 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57036)]
57037pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57038 unsafe { transmute(a) }
57039}
57040#[doc = "Vector reinterpret cast operation"]
57041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
57042#[inline]
57043#[cfg(target_endian = "big")]
57044#[target_feature(enable = "neon,aes")]
57045#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57047#[cfg_attr(
57048 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57049 assert_instr(nop)
57050)]
57051#[cfg_attr(
57052 not(target_arch = "arm"),
57053 stable(feature = "neon_intrinsics", since = "1.59.0")
57054)]
57055#[cfg_attr(
57056 target_arch = "arm",
57057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57058)]
57059pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
57060 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57061 unsafe {
57062 let ret_val: poly8x16_t = transmute(a);
57063 simd_shuffle!(
57064 ret_val,
57065 ret_val,
57066 [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]
57067 )
57068 }
57069}
57070#[doc = "Vector reinterpret cast operation"]
57071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57072#[inline]
57073#[cfg(target_endian = "little")]
57074#[target_feature(enable = "neon,aes")]
57075#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57076#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57077#[cfg_attr(
57078 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57079 assert_instr(nop)
57080)]
57081#[cfg_attr(
57082 not(target_arch = "arm"),
57083 stable(feature = "neon_intrinsics", since = "1.59.0")
57084)]
57085#[cfg_attr(
57086 target_arch = "arm",
57087 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57088)]
57089pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57090 unsafe { transmute(a) }
57091}
57092#[doc = "Vector reinterpret cast operation"]
57093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
57094#[inline]
57095#[cfg(target_endian = "big")]
57096#[target_feature(enable = "neon,aes")]
57097#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
57098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
57099#[cfg_attr(
57100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57101 assert_instr(nop)
57102)]
57103#[cfg_attr(
57104 not(target_arch = "arm"),
57105 stable(feature = "neon_intrinsics", since = "1.59.0")
57106)]
57107#[cfg_attr(
57108 target_arch = "arm",
57109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57110)]
57111pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
57112 let a: poly64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
57113 unsafe {
57114 let ret_val: poly16x8_t = transmute(a);
57115 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
57116 }
57117}
57118#[doc = "Reversing vector elements (swap endianness)"]
57119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
57120#[inline]
57121#[target_feature(enable = "neon")]
57122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57123#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57124#[cfg_attr(
57125 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57126 assert_instr(rev16)
57127)]
57128#[cfg_attr(
57129 not(target_arch = "arm"),
57130 stable(feature = "neon_intrinsics", since = "1.59.0")
57131)]
57132#[cfg_attr(
57133 target_arch = "arm",
57134 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57135)]
57136pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
57137 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57138}
57139#[doc = "Reversing vector elements (swap endianness)"]
57140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
57141#[inline]
57142#[target_feature(enable = "neon")]
57143#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57144#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57145#[cfg_attr(
57146 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57147 assert_instr(rev16)
57148)]
57149#[cfg_attr(
57150 not(target_arch = "arm"),
57151 stable(feature = "neon_intrinsics", since = "1.59.0")
57152)]
57153#[cfg_attr(
57154 target_arch = "arm",
57155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57156)]
57157pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
57158 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57159}
57160#[doc = "Reversing vector elements (swap endianness)"]
57161#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
57162#[inline]
57163#[target_feature(enable = "neon")]
57164#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57165#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57166#[cfg_attr(
57167 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57168 assert_instr(rev16)
57169)]
57170#[cfg_attr(
57171 not(target_arch = "arm"),
57172 stable(feature = "neon_intrinsics", since = "1.59.0")
57173)]
57174#[cfg_attr(
57175 target_arch = "arm",
57176 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57177)]
57178pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
57179 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57180}
57181#[doc = "Reversing vector elements (swap endianness)"]
57182#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
57183#[inline]
57184#[target_feature(enable = "neon")]
57185#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57186#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57187#[cfg_attr(
57188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57189 assert_instr(rev16)
57190)]
57191#[cfg_attr(
57192 not(target_arch = "arm"),
57193 stable(feature = "neon_intrinsics", since = "1.59.0")
57194)]
57195#[cfg_attr(
57196 target_arch = "arm",
57197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57198)]
57199pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
57200 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57201}
57202#[doc = "Reversing vector elements (swap endianness)"]
57203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
57204#[inline]
57205#[target_feature(enable = "neon")]
57206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57207#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57208#[cfg_attr(
57209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57210 assert_instr(rev16)
57211)]
57212#[cfg_attr(
57213 not(target_arch = "arm"),
57214 stable(feature = "neon_intrinsics", since = "1.59.0")
57215)]
57216#[cfg_attr(
57217 target_arch = "arm",
57218 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57219)]
57220pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
57221 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57222}
57223#[doc = "Reversing vector elements (swap endianness)"]
57224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
57225#[inline]
57226#[target_feature(enable = "neon")]
57227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57228#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
57229#[cfg_attr(
57230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57231 assert_instr(rev16)
57232)]
57233#[cfg_attr(
57234 not(target_arch = "arm"),
57235 stable(feature = "neon_intrinsics", since = "1.59.0")
57236)]
57237#[cfg_attr(
57238 target_arch = "arm",
57239 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57240)]
57241pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
57242 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14]) }
57243}
57244#[doc = "Reversing vector elements (swap endianness)"]
57245#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
57246#[inline]
57247#[target_feature(enable = "neon")]
57248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57249#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57250#[cfg_attr(
57251 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57252 assert_instr(rev32)
57253)]
57254#[cfg_attr(
57255 not(target_arch = "arm"),
57256 stable(feature = "neon_intrinsics", since = "1.59.0")
57257)]
57258#[cfg_attr(
57259 target_arch = "arm",
57260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57261)]
57262pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
57263 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57264}
57265#[doc = "Reversing vector elements (swap endianness)"]
57266#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
57267#[inline]
57268#[target_feature(enable = "neon")]
57269#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57270#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57271#[cfg_attr(
57272 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57273 assert_instr(rev32)
57274)]
57275#[cfg_attr(
57276 not(target_arch = "arm"),
57277 stable(feature = "neon_intrinsics", since = "1.59.0")
57278)]
57279#[cfg_attr(
57280 target_arch = "arm",
57281 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57282)]
57283pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
57284 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57285}
57286#[doc = "Reversing vector elements (swap endianness)"]
57287#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
57288#[inline]
57289#[target_feature(enable = "neon")]
57290#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57291#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57292#[cfg_attr(
57293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57294 assert_instr(rev32)
57295)]
57296#[cfg_attr(
57297 not(target_arch = "arm"),
57298 stable(feature = "neon_intrinsics", since = "1.59.0")
57299)]
57300#[cfg_attr(
57301 target_arch = "arm",
57302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57303)]
57304pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
57305 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57306}
57307#[doc = "Reversing vector elements (swap endianness)"]
57308#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
57309#[inline]
57310#[target_feature(enable = "neon")]
57311#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57312#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57313#[cfg_attr(
57314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57315 assert_instr(rev32)
57316)]
57317#[cfg_attr(
57318 not(target_arch = "arm"),
57319 stable(feature = "neon_intrinsics", since = "1.59.0")
57320)]
57321#[cfg_attr(
57322 target_arch = "arm",
57323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57324)]
57325pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
57326 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57327}
57328#[doc = "Reversing vector elements (swap endianness)"]
57329#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
57330#[inline]
57331#[target_feature(enable = "neon")]
57332#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57333#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57334#[cfg_attr(
57335 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57336 assert_instr(rev32)
57337)]
57338#[cfg_attr(
57339 not(target_arch = "arm"),
57340 stable(feature = "neon_intrinsics", since = "1.59.0")
57341)]
57342#[cfg_attr(
57343 target_arch = "arm",
57344 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57345)]
57346pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
57347 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57348}
57349#[doc = "Reversing vector elements (swap endianness)"]
57350#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
57351#[inline]
57352#[target_feature(enable = "neon")]
57353#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57354#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57355#[cfg_attr(
57356 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57357 assert_instr(rev32)
57358)]
57359#[cfg_attr(
57360 not(target_arch = "arm"),
57361 stable(feature = "neon_intrinsics", since = "1.59.0")
57362)]
57363#[cfg_attr(
57364 target_arch = "arm",
57365 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57366)]
57367pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
57368 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57369}
57370#[doc = "Reversing vector elements (swap endianness)"]
57371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
57372#[inline]
57373#[target_feature(enable = "neon")]
57374#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57375#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57376#[cfg_attr(
57377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57378 assert_instr(rev32)
57379)]
57380#[cfg_attr(
57381 not(target_arch = "arm"),
57382 stable(feature = "neon_intrinsics", since = "1.59.0")
57383)]
57384#[cfg_attr(
57385 target_arch = "arm",
57386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57387)]
57388pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
57389 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57390}
57391#[doc = "Reversing vector elements (swap endianness)"]
57392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
57393#[inline]
57394#[target_feature(enable = "neon")]
57395#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57396#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57397#[cfg_attr(
57398 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57399 assert_instr(rev32)
57400)]
57401#[cfg_attr(
57402 not(target_arch = "arm"),
57403 stable(feature = "neon_intrinsics", since = "1.59.0")
57404)]
57405#[cfg_attr(
57406 target_arch = "arm",
57407 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57408)]
57409pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
57410 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57411}
57412#[doc = "Reversing vector elements (swap endianness)"]
57413#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
57414#[inline]
57415#[target_feature(enable = "neon")]
57416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57417#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57418#[cfg_attr(
57419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57420 assert_instr(rev32)
57421)]
57422#[cfg_attr(
57423 not(target_arch = "arm"),
57424 stable(feature = "neon_intrinsics", since = "1.59.0")
57425)]
57426#[cfg_attr(
57427 target_arch = "arm",
57428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57429)]
57430pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
57431 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57432}
57433#[doc = "Reversing vector elements (swap endianness)"]
57434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
57435#[inline]
57436#[target_feature(enable = "neon")]
57437#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57438#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57439#[cfg_attr(
57440 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57441 assert_instr(rev32)
57442)]
57443#[cfg_attr(
57444 not(target_arch = "arm"),
57445 stable(feature = "neon_intrinsics", since = "1.59.0")
57446)]
57447#[cfg_attr(
57448 target_arch = "arm",
57449 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57450)]
57451pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
57452 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57453}
57454#[doc = "Reversing vector elements (swap endianness)"]
57455#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
57456#[inline]
57457#[target_feature(enable = "neon")]
57458#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
57460#[cfg_attr(
57461 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57462 assert_instr(rev32)
57463)]
57464#[cfg_attr(
57465 not(target_arch = "arm"),
57466 stable(feature = "neon_intrinsics", since = "1.59.0")
57467)]
57468#[cfg_attr(
57469 target_arch = "arm",
57470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57471)]
57472pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
57473 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2, 5, 4, 7, 6]) }
57474}
57475#[doc = "Reversing vector elements (swap endianness)"]
57476#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
57477#[inline]
57478#[target_feature(enable = "neon")]
57479#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57480#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
57481#[cfg_attr(
57482 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57483 assert_instr(rev32)
57484)]
57485#[cfg_attr(
57486 not(target_arch = "arm"),
57487 stable(feature = "neon_intrinsics", since = "1.59.0")
57488)]
57489#[cfg_attr(
57490 target_arch = "arm",
57491 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57492)]
57493pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
57494 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12]) }
57495}
57496#[doc = "Reversing vector elements (swap endianness)"]
57497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
57498#[inline]
57499#[target_feature(enable = "neon")]
57500#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57501#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57502#[cfg_attr(
57503 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57504 assert_instr(rev64)
57505)]
57506#[cfg_attr(
57507 not(target_arch = "arm"),
57508 stable(feature = "neon_intrinsics", since = "1.59.0")
57509)]
57510#[cfg_attr(
57511 target_arch = "arm",
57512 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57513)]
57514pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
57515 unsafe { simd_shuffle!(a, a, [1, 0]) }
57516}
57517#[doc = "Reversing vector elements (swap endianness)"]
57518#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
57519#[inline]
57520#[target_feature(enable = "neon")]
57521#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57522#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57523#[cfg_attr(
57524 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57525 assert_instr(rev64)
57526)]
57527#[cfg_attr(
57528 not(target_arch = "arm"),
57529 stable(feature = "neon_intrinsics", since = "1.59.0")
57530)]
57531#[cfg_attr(
57532 target_arch = "arm",
57533 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57534)]
57535pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
57536 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57537}
57538#[doc = "Reversing vector elements (swap endianness)"]
57539#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
57540#[inline]
57541#[target_feature(enable = "neon")]
57542#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57543#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57544#[cfg_attr(
57545 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57546 assert_instr(rev64)
57547)]
57548#[cfg_attr(
57549 not(target_arch = "arm"),
57550 stable(feature = "neon_intrinsics", since = "1.59.0")
57551)]
57552#[cfg_attr(
57553 target_arch = "arm",
57554 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57555)]
57556pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
57557 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57558}
57559#[doc = "Reversing vector elements (swap endianness)"]
57560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
57561#[inline]
57562#[target_feature(enable = "neon")]
57563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57564#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57565#[cfg_attr(
57566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57567 assert_instr(rev64)
57568)]
57569#[cfg_attr(
57570 not(target_arch = "arm"),
57571 stable(feature = "neon_intrinsics", since = "1.59.0")
57572)]
57573#[cfg_attr(
57574 target_arch = "arm",
57575 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57576)]
57577pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
57578 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57579}
57580#[doc = "Reversing vector elements (swap endianness)"]
57581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
57582#[inline]
57583#[target_feature(enable = "neon")]
57584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57585#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57586#[cfg_attr(
57587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57588 assert_instr(rev64)
57589)]
57590#[cfg_attr(
57591 not(target_arch = "arm"),
57592 stable(feature = "neon_intrinsics", since = "1.59.0")
57593)]
57594#[cfg_attr(
57595 target_arch = "arm",
57596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57597)]
57598pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
57599 unsafe { simd_shuffle!(a, a, [1, 0]) }
57600}
57601#[doc = "Reversing vector elements (swap endianness)"]
57602#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
57603#[inline]
57604#[target_feature(enable = "neon")]
57605#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57606#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57607#[cfg_attr(
57608 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57609 assert_instr(rev64)
57610)]
57611#[cfg_attr(
57612 not(target_arch = "arm"),
57613 stable(feature = "neon_intrinsics", since = "1.59.0")
57614)]
57615#[cfg_attr(
57616 target_arch = "arm",
57617 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57618)]
57619pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
57620 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57621}
57622#[doc = "Reversing vector elements (swap endianness)"]
57623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
57624#[inline]
57625#[target_feature(enable = "neon")]
57626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57628#[cfg_attr(
57629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57630 assert_instr(rev64)
57631)]
57632#[cfg_attr(
57633 not(target_arch = "arm"),
57634 stable(feature = "neon_intrinsics", since = "1.59.0")
57635)]
57636#[cfg_attr(
57637 target_arch = "arm",
57638 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57639)]
57640pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
57641 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57642}
57643#[doc = "Reversing vector elements (swap endianness)"]
57644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
57645#[inline]
57646#[target_feature(enable = "neon")]
57647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57648#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57649#[cfg_attr(
57650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57651 assert_instr(rev64)
57652)]
57653#[cfg_attr(
57654 not(target_arch = "arm"),
57655 stable(feature = "neon_intrinsics", since = "1.59.0")
57656)]
57657#[cfg_attr(
57658 target_arch = "arm",
57659 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57660)]
57661pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
57662 unsafe { simd_shuffle!(a, a, [1, 0]) }
57663}
57664#[doc = "Reversing vector elements (swap endianness)"]
57665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
57666#[inline]
57667#[target_feature(enable = "neon")]
57668#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57669#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57670#[cfg_attr(
57671 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57672 assert_instr(rev64)
57673)]
57674#[cfg_attr(
57675 not(target_arch = "arm"),
57676 stable(feature = "neon_intrinsics", since = "1.59.0")
57677)]
57678#[cfg_attr(
57679 target_arch = "arm",
57680 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57681)]
57682pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
57683 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }
57684}
57685#[doc = "Reversing vector elements (swap endianness)"]
57686#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
57687#[inline]
57688#[target_feature(enable = "neon")]
57689#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57690#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57691#[cfg_attr(
57692 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57693 assert_instr(rev64)
57694)]
57695#[cfg_attr(
57696 not(target_arch = "arm"),
57697 stable(feature = "neon_intrinsics", since = "1.59.0")
57698)]
57699#[cfg_attr(
57700 target_arch = "arm",
57701 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57702)]
57703pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
57704 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57705}
57706#[doc = "Reversing vector elements (swap endianness)"]
57707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
57708#[inline]
57709#[target_feature(enable = "neon")]
57710#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57711#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57712#[cfg_attr(
57713 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57714 assert_instr(rev64)
57715)]
57716#[cfg_attr(
57717 not(target_arch = "arm"),
57718 stable(feature = "neon_intrinsics", since = "1.59.0")
57719)]
57720#[cfg_attr(
57721 target_arch = "arm",
57722 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57723)]
57724pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
57725 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57726}
57727#[doc = "Reversing vector elements (swap endianness)"]
57728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
57729#[inline]
57730#[target_feature(enable = "neon")]
57731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57732#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57733#[cfg_attr(
57734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57735 assert_instr(rev64)
57736)]
57737#[cfg_attr(
57738 not(target_arch = "arm"),
57739 stable(feature = "neon_intrinsics", since = "1.59.0")
57740)]
57741#[cfg_attr(
57742 target_arch = "arm",
57743 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57744)]
57745pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
57746 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
57747}
57748#[doc = "Reversing vector elements (swap endianness)"]
57749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
57750#[inline]
57751#[target_feature(enable = "neon")]
57752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57753#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57754#[cfg_attr(
57755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57756 assert_instr(rev64)
57757)]
57758#[cfg_attr(
57759 not(target_arch = "arm"),
57760 stable(feature = "neon_intrinsics", since = "1.59.0")
57761)]
57762#[cfg_attr(
57763 target_arch = "arm",
57764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57765)]
57766pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
57767 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57768}
57769#[doc = "Reversing vector elements (swap endianness)"]
57770#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
57771#[inline]
57772#[target_feature(enable = "neon")]
57773#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57774#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57775#[cfg_attr(
57776 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57777 assert_instr(rev64)
57778)]
57779#[cfg_attr(
57780 not(target_arch = "arm"),
57781 stable(feature = "neon_intrinsics", since = "1.59.0")
57782)]
57783#[cfg_attr(
57784 target_arch = "arm",
57785 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57786)]
57787pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
57788 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57789}
57790#[doc = "Reversing vector elements (swap endianness)"]
57791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
57792#[inline]
57793#[target_feature(enable = "neon")]
57794#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57795#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57796#[cfg_attr(
57797 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57798 assert_instr(rev64)
57799)]
57800#[cfg_attr(
57801 not(target_arch = "arm"),
57802 stable(feature = "neon_intrinsics", since = "1.59.0")
57803)]
57804#[cfg_attr(
57805 target_arch = "arm",
57806 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57807)]
57808pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
57809 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
57810}
57811#[doc = "Reversing vector elements (swap endianness)"]
57812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
57813#[inline]
57814#[target_feature(enable = "neon")]
57815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57816#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
57817#[cfg_attr(
57818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57819 assert_instr(rev64)
57820)]
57821#[cfg_attr(
57822 not(target_arch = "arm"),
57823 stable(feature = "neon_intrinsics", since = "1.59.0")
57824)]
57825#[cfg_attr(
57826 target_arch = "arm",
57827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57828)]
57829pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
57830 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57831}
57832#[doc = "Reversing vector elements (swap endianness)"]
57833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
57834#[inline]
57835#[target_feature(enable = "neon")]
57836#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57837#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
57838#[cfg_attr(
57839 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57840 assert_instr(rev64)
57841)]
57842#[cfg_attr(
57843 not(target_arch = "arm"),
57844 stable(feature = "neon_intrinsics", since = "1.59.0")
57845)]
57846#[cfg_attr(
57847 target_arch = "arm",
57848 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57849)]
57850pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
57851 unsafe { simd_shuffle!(a, a, [1, 0, 3, 2]) }
57852}
57853#[doc = "Reversing vector elements (swap endianness)"]
57854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
57855#[inline]
57856#[target_feature(enable = "neon")]
57857#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57858#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
57859#[cfg_attr(
57860 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57861 assert_instr(rev64)
57862)]
57863#[cfg_attr(
57864 not(target_arch = "arm"),
57865 stable(feature = "neon_intrinsics", since = "1.59.0")
57866)]
57867#[cfg_attr(
57868 target_arch = "arm",
57869 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57870)]
57871pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
57872 unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8]) }
57873}
57874#[doc = "Reverse elements in 64-bit doublewords"]
57875#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
57876#[inline]
57877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
57879#[cfg_attr(
57880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57881 assert_instr(rev64)
57882)]
57883#[target_feature(enable = "neon,fp16")]
57884#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57885pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
57886 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }
57887}
57888#[doc = "Reverse elements in 64-bit doublewords"]
57889#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
57890#[inline]
57891#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57892#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
57893#[cfg_attr(
57894 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57895 assert_instr(rev64)
57896)]
57897#[target_feature(enable = "neon,fp16")]
57898#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
57899pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
57900 unsafe { simd_shuffle!(a, a, [3, 2, 1, 0, 7, 6, 5, 4]) }
57901}
57902#[doc = "Rounding halving add"]
57903#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
57904#[inline]
57905#[target_feature(enable = "neon")]
57906#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57907#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
57908#[cfg_attr(
57909 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57910 assert_instr(srhadd)
57911)]
57912#[cfg_attr(
57913 not(target_arch = "arm"),
57914 stable(feature = "neon_intrinsics", since = "1.59.0")
57915)]
57916#[cfg_attr(
57917 target_arch = "arm",
57918 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57919)]
57920pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
57921 unsafe extern "unadjusted" {
57922 #[cfg_attr(
57923 any(target_arch = "aarch64", target_arch = "arm64ec"),
57924 link_name = "llvm.aarch64.neon.srhadd.v8i8"
57925 )]
57926 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")]
57927 fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
57928 }
57929 unsafe { _vrhadd_s8(a, b) }
57930}
57931#[doc = "Rounding halving add"]
57932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
57933#[inline]
57934#[target_feature(enable = "neon")]
57935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57936#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
57937#[cfg_attr(
57938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57939 assert_instr(srhadd)
57940)]
57941#[cfg_attr(
57942 not(target_arch = "arm"),
57943 stable(feature = "neon_intrinsics", since = "1.59.0")
57944)]
57945#[cfg_attr(
57946 target_arch = "arm",
57947 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57948)]
57949pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
57950 unsafe extern "unadjusted" {
57951 #[cfg_attr(
57952 any(target_arch = "aarch64", target_arch = "arm64ec"),
57953 link_name = "llvm.aarch64.neon.srhadd.v16i8"
57954 )]
57955 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")]
57956 fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
57957 }
57958 unsafe { _vrhaddq_s8(a, b) }
57959}
57960#[doc = "Rounding halving add"]
57961#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
57962#[inline]
57963#[target_feature(enable = "neon")]
57964#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
57966#[cfg_attr(
57967 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57968 assert_instr(srhadd)
57969)]
57970#[cfg_attr(
57971 not(target_arch = "arm"),
57972 stable(feature = "neon_intrinsics", since = "1.59.0")
57973)]
57974#[cfg_attr(
57975 target_arch = "arm",
57976 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
57977)]
57978pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
57979 unsafe extern "unadjusted" {
57980 #[cfg_attr(
57981 any(target_arch = "aarch64", target_arch = "arm64ec"),
57982 link_name = "llvm.aarch64.neon.srhadd.v4i16"
57983 )]
57984 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")]
57985 fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
57986 }
57987 unsafe { _vrhadd_s16(a, b) }
57988}
57989#[doc = "Rounding halving add"]
57990#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
57991#[inline]
57992#[target_feature(enable = "neon")]
57993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
57994#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
57995#[cfg_attr(
57996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
57997 assert_instr(srhadd)
57998)]
57999#[cfg_attr(
58000 not(target_arch = "arm"),
58001 stable(feature = "neon_intrinsics", since = "1.59.0")
58002)]
58003#[cfg_attr(
58004 target_arch = "arm",
58005 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58006)]
58007pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58008 unsafe extern "unadjusted" {
58009 #[cfg_attr(
58010 any(target_arch = "aarch64", target_arch = "arm64ec"),
58011 link_name = "llvm.aarch64.neon.srhadd.v8i16"
58012 )]
58013 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")]
58014 fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58015 }
58016 unsafe { _vrhaddq_s16(a, b) }
58017}
58018#[doc = "Rounding halving add"]
58019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
58020#[inline]
58021#[target_feature(enable = "neon")]
58022#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58024#[cfg_attr(
58025 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58026 assert_instr(srhadd)
58027)]
58028#[cfg_attr(
58029 not(target_arch = "arm"),
58030 stable(feature = "neon_intrinsics", since = "1.59.0")
58031)]
58032#[cfg_attr(
58033 target_arch = "arm",
58034 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58035)]
58036pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58037 unsafe extern "unadjusted" {
58038 #[cfg_attr(
58039 any(target_arch = "aarch64", target_arch = "arm64ec"),
58040 link_name = "llvm.aarch64.neon.srhadd.v2i32"
58041 )]
58042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")]
58043 fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58044 }
58045 unsafe { _vrhadd_s32(a, b) }
58046}
58047#[doc = "Rounding halving add"]
58048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
58049#[inline]
58050#[target_feature(enable = "neon")]
58051#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58052#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
58053#[cfg_attr(
58054 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58055 assert_instr(srhadd)
58056)]
58057#[cfg_attr(
58058 not(target_arch = "arm"),
58059 stable(feature = "neon_intrinsics", since = "1.59.0")
58060)]
58061#[cfg_attr(
58062 target_arch = "arm",
58063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58064)]
58065pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58066 unsafe extern "unadjusted" {
58067 #[cfg_attr(
58068 any(target_arch = "aarch64", target_arch = "arm64ec"),
58069 link_name = "llvm.aarch64.neon.srhadd.v4i32"
58070 )]
58071 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")]
58072 fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58073 }
58074 unsafe { _vrhaddq_s32(a, b) }
58075}
58076#[doc = "Rounding halving add"]
58077#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
58078#[inline]
58079#[target_feature(enable = "neon")]
58080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58081#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58082#[cfg_attr(
58083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58084 assert_instr(urhadd)
58085)]
58086#[cfg_attr(
58087 not(target_arch = "arm"),
58088 stable(feature = "neon_intrinsics", since = "1.59.0")
58089)]
58090#[cfg_attr(
58091 target_arch = "arm",
58092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58093)]
58094pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
58095 unsafe extern "unadjusted" {
58096 #[cfg_attr(
58097 any(target_arch = "aarch64", target_arch = "arm64ec"),
58098 link_name = "llvm.aarch64.neon.urhadd.v8i8"
58099 )]
58100 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")]
58101 fn _vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
58102 }
58103 unsafe { _vrhadd_u8(a, b) }
58104}
58105#[doc = "Rounding halving add"]
58106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
58107#[inline]
58108#[target_feature(enable = "neon")]
58109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58110#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
58111#[cfg_attr(
58112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58113 assert_instr(urhadd)
58114)]
58115#[cfg_attr(
58116 not(target_arch = "arm"),
58117 stable(feature = "neon_intrinsics", since = "1.59.0")
58118)]
58119#[cfg_attr(
58120 target_arch = "arm",
58121 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58122)]
58123pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
58124 unsafe extern "unadjusted" {
58125 #[cfg_attr(
58126 any(target_arch = "aarch64", target_arch = "arm64ec"),
58127 link_name = "llvm.aarch64.neon.urhadd.v16i8"
58128 )]
58129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")]
58130 fn _vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
58131 }
58132 unsafe { _vrhaddq_u8(a, b) }
58133}
58134#[doc = "Rounding halving add"]
58135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
58136#[inline]
58137#[target_feature(enable = "neon")]
58138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58139#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58140#[cfg_attr(
58141 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58142 assert_instr(urhadd)
58143)]
58144#[cfg_attr(
58145 not(target_arch = "arm"),
58146 stable(feature = "neon_intrinsics", since = "1.59.0")
58147)]
58148#[cfg_attr(
58149 target_arch = "arm",
58150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58151)]
58152pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
58153 unsafe extern "unadjusted" {
58154 #[cfg_attr(
58155 any(target_arch = "aarch64", target_arch = "arm64ec"),
58156 link_name = "llvm.aarch64.neon.urhadd.v4i16"
58157 )]
58158 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")]
58159 fn _vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
58160 }
58161 unsafe { _vrhadd_u16(a, b) }
58162}
58163#[doc = "Rounding halving add"]
58164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
58165#[inline]
58166#[target_feature(enable = "neon")]
58167#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58168#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
58169#[cfg_attr(
58170 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58171 assert_instr(urhadd)
58172)]
58173#[cfg_attr(
58174 not(target_arch = "arm"),
58175 stable(feature = "neon_intrinsics", since = "1.59.0")
58176)]
58177#[cfg_attr(
58178 target_arch = "arm",
58179 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58180)]
58181pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
58182 unsafe extern "unadjusted" {
58183 #[cfg_attr(
58184 any(target_arch = "aarch64", target_arch = "arm64ec"),
58185 link_name = "llvm.aarch64.neon.urhadd.v8i16"
58186 )]
58187 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")]
58188 fn _vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
58189 }
58190 unsafe { _vrhaddq_u16(a, b) }
58191}
58192#[doc = "Rounding halving add"]
58193#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
58194#[inline]
58195#[target_feature(enable = "neon")]
58196#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58197#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58198#[cfg_attr(
58199 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58200 assert_instr(urhadd)
58201)]
58202#[cfg_attr(
58203 not(target_arch = "arm"),
58204 stable(feature = "neon_intrinsics", since = "1.59.0")
58205)]
58206#[cfg_attr(
58207 target_arch = "arm",
58208 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58209)]
58210pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
58211 unsafe extern "unadjusted" {
58212 #[cfg_attr(
58213 any(target_arch = "aarch64", target_arch = "arm64ec"),
58214 link_name = "llvm.aarch64.neon.urhadd.v2i32"
58215 )]
58216 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")]
58217 fn _vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
58218 }
58219 unsafe { _vrhadd_u32(a, b) }
58220}
58221#[doc = "Rounding halving add"]
58222#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
58223#[inline]
58224#[target_feature(enable = "neon")]
58225#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58226#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
58227#[cfg_attr(
58228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58229 assert_instr(urhadd)
58230)]
58231#[cfg_attr(
58232 not(target_arch = "arm"),
58233 stable(feature = "neon_intrinsics", since = "1.59.0")
58234)]
58235#[cfg_attr(
58236 target_arch = "arm",
58237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58238)]
58239pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
58240 unsafe extern "unadjusted" {
58241 #[cfg_attr(
58242 any(target_arch = "aarch64", target_arch = "arm64ec"),
58243 link_name = "llvm.aarch64.neon.urhadd.v4i32"
58244 )]
58245 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")]
58246 fn _vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
58247 }
58248 unsafe { _vrhaddq_u32(a, b) }
58249}
58250#[doc = "Floating-point round to integral, to nearest with ties to even"]
58251#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
58252#[inline]
58253#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58254#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58255#[cfg_attr(
58256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58257 assert_instr(frintn)
58258)]
58259#[target_feature(enable = "neon,fp16")]
58260#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58261pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
58262 unsafe extern "unadjusted" {
58263 #[cfg_attr(
58264 any(target_arch = "aarch64", target_arch = "arm64ec"),
58265 link_name = "llvm.roundeven.v4f16"
58266 )]
58267 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f16")]
58268 fn _vrndn_f16(a: float16x4_t) -> float16x4_t;
58269 }
58270 unsafe { _vrndn_f16(a) }
58271}
58272#[doc = "Floating-point round to integral, to nearest with ties to even"]
58273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
58274#[inline]
58275#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58277#[cfg_attr(
58278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58279 assert_instr(frintn)
58280)]
58281#[target_feature(enable = "neon,fp16")]
58282#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
58283pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
58284 unsafe extern "unadjusted" {
58285 #[cfg_attr(
58286 any(target_arch = "aarch64", target_arch = "arm64ec"),
58287 link_name = "llvm.roundeven.v8f16"
58288 )]
58289 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v8f16")]
58290 fn _vrndnq_f16(a: float16x8_t) -> float16x8_t;
58291 }
58292 unsafe { _vrndnq_f16(a) }
58293}
58294#[doc = "Floating-point round to integral, to nearest with ties to even"]
58295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
58296#[inline]
58297#[target_feature(enable = "neon")]
58298#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58300#[cfg_attr(
58301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58302 assert_instr(frintn)
58303)]
58304#[cfg_attr(
58305 not(target_arch = "arm"),
58306 stable(feature = "neon_intrinsics", since = "1.59.0")
58307)]
58308#[cfg_attr(
58309 target_arch = "arm",
58310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58311)]
58312pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
58313 unsafe extern "unadjusted" {
58314 #[cfg_attr(
58315 any(target_arch = "aarch64", target_arch = "arm64ec"),
58316 link_name = "llvm.roundeven.v2f32"
58317 )]
58318 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")]
58319 fn _vrndn_f32(a: float32x2_t) -> float32x2_t;
58320 }
58321 unsafe { _vrndn_f32(a) }
58322}
58323#[doc = "Floating-point round to integral, to nearest with ties to even"]
58324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
58325#[inline]
58326#[target_feature(enable = "neon")]
58327#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
58328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
58329#[cfg_attr(
58330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58331 assert_instr(frintn)
58332)]
58333#[cfg_attr(
58334 not(target_arch = "arm"),
58335 stable(feature = "neon_intrinsics", since = "1.59.0")
58336)]
58337#[cfg_attr(
58338 target_arch = "arm",
58339 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58340)]
58341pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
58342 unsafe extern "unadjusted" {
58343 #[cfg_attr(
58344 any(target_arch = "aarch64", target_arch = "arm64ec"),
58345 link_name = "llvm.roundeven.v4f32"
58346 )]
58347 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")]
58348 fn _vrndnq_f32(a: float32x4_t) -> float32x4_t;
58349 }
58350 unsafe { _vrndnq_f32(a) }
58351}
58352#[doc = "Signed rounding shift left"]
58353#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
58354#[inline]
58355#[target_feature(enable = "neon")]
58356#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58357#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58358#[cfg_attr(
58359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58360 assert_instr(srshl)
58361)]
58362#[cfg_attr(
58363 not(target_arch = "arm"),
58364 stable(feature = "neon_intrinsics", since = "1.59.0")
58365)]
58366#[cfg_attr(
58367 target_arch = "arm",
58368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58369)]
58370pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
58371 unsafe extern "unadjusted" {
58372 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")]
58373 #[cfg_attr(
58374 any(target_arch = "aarch64", target_arch = "arm64ec"),
58375 link_name = "llvm.aarch64.neon.srshl.v8i8"
58376 )]
58377 fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
58378 }
58379 unsafe { _vrshl_s8(a, b) }
58380}
58381#[doc = "Signed rounding shift left"]
58382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
58383#[inline]
58384#[target_feature(enable = "neon")]
58385#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58386#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58387#[cfg_attr(
58388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58389 assert_instr(srshl)
58390)]
58391#[cfg_attr(
58392 not(target_arch = "arm"),
58393 stable(feature = "neon_intrinsics", since = "1.59.0")
58394)]
58395#[cfg_attr(
58396 target_arch = "arm",
58397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58398)]
58399pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
58400 unsafe extern "unadjusted" {
58401 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")]
58402 #[cfg_attr(
58403 any(target_arch = "aarch64", target_arch = "arm64ec"),
58404 link_name = "llvm.aarch64.neon.srshl.v16i8"
58405 )]
58406 fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
58407 }
58408 unsafe { _vrshlq_s8(a, b) }
58409}
58410#[doc = "Signed rounding shift left"]
58411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
58412#[inline]
58413#[target_feature(enable = "neon")]
58414#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58415#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58416#[cfg_attr(
58417 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58418 assert_instr(srshl)
58419)]
58420#[cfg_attr(
58421 not(target_arch = "arm"),
58422 stable(feature = "neon_intrinsics", since = "1.59.0")
58423)]
58424#[cfg_attr(
58425 target_arch = "arm",
58426 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58427)]
58428pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
58429 unsafe extern "unadjusted" {
58430 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")]
58431 #[cfg_attr(
58432 any(target_arch = "aarch64", target_arch = "arm64ec"),
58433 link_name = "llvm.aarch64.neon.srshl.v4i16"
58434 )]
58435 fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
58436 }
58437 unsafe { _vrshl_s16(a, b) }
58438}
58439#[doc = "Signed rounding shift left"]
58440#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
58441#[inline]
58442#[target_feature(enable = "neon")]
58443#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58444#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58445#[cfg_attr(
58446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58447 assert_instr(srshl)
58448)]
58449#[cfg_attr(
58450 not(target_arch = "arm"),
58451 stable(feature = "neon_intrinsics", since = "1.59.0")
58452)]
58453#[cfg_attr(
58454 target_arch = "arm",
58455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58456)]
58457pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
58458 unsafe extern "unadjusted" {
58459 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")]
58460 #[cfg_attr(
58461 any(target_arch = "aarch64", target_arch = "arm64ec"),
58462 link_name = "llvm.aarch64.neon.srshl.v8i16"
58463 )]
58464 fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
58465 }
58466 unsafe { _vrshlq_s16(a, b) }
58467}
58468#[doc = "Signed rounding shift left"]
58469#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
58470#[inline]
58471#[target_feature(enable = "neon")]
58472#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58473#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58474#[cfg_attr(
58475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58476 assert_instr(srshl)
58477)]
58478#[cfg_attr(
58479 not(target_arch = "arm"),
58480 stable(feature = "neon_intrinsics", since = "1.59.0")
58481)]
58482#[cfg_attr(
58483 target_arch = "arm",
58484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58485)]
58486pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
58487 unsafe extern "unadjusted" {
58488 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")]
58489 #[cfg_attr(
58490 any(target_arch = "aarch64", target_arch = "arm64ec"),
58491 link_name = "llvm.aarch64.neon.srshl.v2i32"
58492 )]
58493 fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
58494 }
58495 unsafe { _vrshl_s32(a, b) }
58496}
58497#[doc = "Signed rounding shift left"]
58498#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
58499#[inline]
58500#[target_feature(enable = "neon")]
58501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58503#[cfg_attr(
58504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58505 assert_instr(srshl)
58506)]
58507#[cfg_attr(
58508 not(target_arch = "arm"),
58509 stable(feature = "neon_intrinsics", since = "1.59.0")
58510)]
58511#[cfg_attr(
58512 target_arch = "arm",
58513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58514)]
58515pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
58516 unsafe extern "unadjusted" {
58517 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")]
58518 #[cfg_attr(
58519 any(target_arch = "aarch64", target_arch = "arm64ec"),
58520 link_name = "llvm.aarch64.neon.srshl.v4i32"
58521 )]
58522 fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
58523 }
58524 unsafe { _vrshlq_s32(a, b) }
58525}
58526#[doc = "Signed rounding shift left"]
58527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
58528#[inline]
58529#[target_feature(enable = "neon")]
58530#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58531#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58532#[cfg_attr(
58533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58534 assert_instr(srshl)
58535)]
58536#[cfg_attr(
58537 not(target_arch = "arm"),
58538 stable(feature = "neon_intrinsics", since = "1.59.0")
58539)]
58540#[cfg_attr(
58541 target_arch = "arm",
58542 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58543)]
58544pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
58545 unsafe extern "unadjusted" {
58546 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")]
58547 #[cfg_attr(
58548 any(target_arch = "aarch64", target_arch = "arm64ec"),
58549 link_name = "llvm.aarch64.neon.srshl.v1i64"
58550 )]
58551 fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
58552 }
58553 unsafe { _vrshl_s64(a, b) }
58554}
58555#[doc = "Signed rounding shift left"]
58556#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
58557#[inline]
58558#[target_feature(enable = "neon")]
58559#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58560#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58561#[cfg_attr(
58562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58563 assert_instr(srshl)
58564)]
58565#[cfg_attr(
58566 not(target_arch = "arm"),
58567 stable(feature = "neon_intrinsics", since = "1.59.0")
58568)]
58569#[cfg_attr(
58570 target_arch = "arm",
58571 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58572)]
58573pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
58574 unsafe extern "unadjusted" {
58575 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")]
58576 #[cfg_attr(
58577 any(target_arch = "aarch64", target_arch = "arm64ec"),
58578 link_name = "llvm.aarch64.neon.srshl.v2i64"
58579 )]
58580 fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
58581 }
58582 unsafe { _vrshlq_s64(a, b) }
58583}
58584#[doc = "Unsigned rounding shift left"]
58585#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
58586#[inline]
58587#[target_feature(enable = "neon")]
58588#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58589#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58590#[cfg_attr(
58591 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58592 assert_instr(urshl)
58593)]
58594#[cfg_attr(
58595 not(target_arch = "arm"),
58596 stable(feature = "neon_intrinsics", since = "1.59.0")
58597)]
58598#[cfg_attr(
58599 target_arch = "arm",
58600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58601)]
58602pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
58603 unsafe extern "unadjusted" {
58604 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")]
58605 #[cfg_attr(
58606 any(target_arch = "aarch64", target_arch = "arm64ec"),
58607 link_name = "llvm.aarch64.neon.urshl.v8i8"
58608 )]
58609 fn _vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
58610 }
58611 unsafe { _vrshl_u8(a, b) }
58612}
58613#[doc = "Unsigned rounding shift left"]
58614#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
58615#[inline]
58616#[target_feature(enable = "neon")]
58617#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58618#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58619#[cfg_attr(
58620 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58621 assert_instr(urshl)
58622)]
58623#[cfg_attr(
58624 not(target_arch = "arm"),
58625 stable(feature = "neon_intrinsics", since = "1.59.0")
58626)]
58627#[cfg_attr(
58628 target_arch = "arm",
58629 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58630)]
58631pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
58632 unsafe extern "unadjusted" {
58633 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")]
58634 #[cfg_attr(
58635 any(target_arch = "aarch64", target_arch = "arm64ec"),
58636 link_name = "llvm.aarch64.neon.urshl.v16i8"
58637 )]
58638 fn _vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
58639 }
58640 unsafe { _vrshlq_u8(a, b) }
58641}
58642#[doc = "Unsigned rounding shift left"]
58643#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
58644#[inline]
58645#[target_feature(enable = "neon")]
58646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58648#[cfg_attr(
58649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58650 assert_instr(urshl)
58651)]
58652#[cfg_attr(
58653 not(target_arch = "arm"),
58654 stable(feature = "neon_intrinsics", since = "1.59.0")
58655)]
58656#[cfg_attr(
58657 target_arch = "arm",
58658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58659)]
58660pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
58661 unsafe extern "unadjusted" {
58662 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")]
58663 #[cfg_attr(
58664 any(target_arch = "aarch64", target_arch = "arm64ec"),
58665 link_name = "llvm.aarch64.neon.urshl.v4i16"
58666 )]
58667 fn _vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
58668 }
58669 unsafe { _vrshl_u16(a, b) }
58670}
58671#[doc = "Unsigned rounding shift left"]
58672#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
58673#[inline]
58674#[target_feature(enable = "neon")]
58675#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58676#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58677#[cfg_attr(
58678 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58679 assert_instr(urshl)
58680)]
58681#[cfg_attr(
58682 not(target_arch = "arm"),
58683 stable(feature = "neon_intrinsics", since = "1.59.0")
58684)]
58685#[cfg_attr(
58686 target_arch = "arm",
58687 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58688)]
58689pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
58690 unsafe extern "unadjusted" {
58691 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")]
58692 #[cfg_attr(
58693 any(target_arch = "aarch64", target_arch = "arm64ec"),
58694 link_name = "llvm.aarch64.neon.urshl.v8i16"
58695 )]
58696 fn _vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
58697 }
58698 unsafe { _vrshlq_u16(a, b) }
58699}
58700#[doc = "Unsigned rounding shift left"]
58701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
58702#[inline]
58703#[target_feature(enable = "neon")]
58704#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58705#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58706#[cfg_attr(
58707 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58708 assert_instr(urshl)
58709)]
58710#[cfg_attr(
58711 not(target_arch = "arm"),
58712 stable(feature = "neon_intrinsics", since = "1.59.0")
58713)]
58714#[cfg_attr(
58715 target_arch = "arm",
58716 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58717)]
58718pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
58719 unsafe extern "unadjusted" {
58720 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")]
58721 #[cfg_attr(
58722 any(target_arch = "aarch64", target_arch = "arm64ec"),
58723 link_name = "llvm.aarch64.neon.urshl.v2i32"
58724 )]
58725 fn _vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
58726 }
58727 unsafe { _vrshl_u32(a, b) }
58728}
58729#[doc = "Unsigned rounding shift left"]
58730#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
58731#[inline]
58732#[target_feature(enable = "neon")]
58733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58734#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58735#[cfg_attr(
58736 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58737 assert_instr(urshl)
58738)]
58739#[cfg_attr(
58740 not(target_arch = "arm"),
58741 stable(feature = "neon_intrinsics", since = "1.59.0")
58742)]
58743#[cfg_attr(
58744 target_arch = "arm",
58745 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58746)]
58747pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
58748 unsafe extern "unadjusted" {
58749 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")]
58750 #[cfg_attr(
58751 any(target_arch = "aarch64", target_arch = "arm64ec"),
58752 link_name = "llvm.aarch64.neon.urshl.v4i32"
58753 )]
58754 fn _vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
58755 }
58756 unsafe { _vrshlq_u32(a, b) }
58757}
58758#[doc = "Unsigned rounding shift left"]
58759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
58760#[inline]
58761#[target_feature(enable = "neon")]
58762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58764#[cfg_attr(
58765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58766 assert_instr(urshl)
58767)]
58768#[cfg_attr(
58769 not(target_arch = "arm"),
58770 stable(feature = "neon_intrinsics", since = "1.59.0")
58771)]
58772#[cfg_attr(
58773 target_arch = "arm",
58774 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58775)]
58776pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
58777 unsafe extern "unadjusted" {
58778 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")]
58779 #[cfg_attr(
58780 any(target_arch = "aarch64", target_arch = "arm64ec"),
58781 link_name = "llvm.aarch64.neon.urshl.v1i64"
58782 )]
58783 fn _vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
58784 }
58785 unsafe { _vrshl_u64(a, b) }
58786}
58787#[doc = "Unsigned rounding shift left"]
58788#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
58789#[inline]
58790#[target_feature(enable = "neon")]
58791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58792#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
58793#[cfg_attr(
58794 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58795 assert_instr(urshl)
58796)]
58797#[cfg_attr(
58798 not(target_arch = "arm"),
58799 stable(feature = "neon_intrinsics", since = "1.59.0")
58800)]
58801#[cfg_attr(
58802 target_arch = "arm",
58803 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58804)]
58805pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
58806 unsafe extern "unadjusted" {
58807 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")]
58808 #[cfg_attr(
58809 any(target_arch = "aarch64", target_arch = "arm64ec"),
58810 link_name = "llvm.aarch64.neon.urshl.v2i64"
58811 )]
58812 fn _vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
58813 }
58814 unsafe { _vrshlq_u64(a, b) }
58815}
58816#[doc = "Signed rounding shift right"]
58817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
58818#[inline]
58819#[target_feature(enable = "neon")]
58820#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58821#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58822#[cfg_attr(
58823 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58824 assert_instr(srshr, N = 2)
58825)]
58826#[rustc_legacy_const_generics(1)]
58827#[cfg_attr(
58828 not(target_arch = "arm"),
58829 stable(feature = "neon_intrinsics", since = "1.59.0")
58830)]
58831#[cfg_attr(
58832 target_arch = "arm",
58833 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58834)]
58835pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
58836 static_assert!(N >= 1 && N <= 8);
58837 vrshl_s8(a, vdup_n_s8(-N as _))
58838}
58839#[doc = "Signed rounding shift right"]
58840#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
58841#[inline]
58842#[target_feature(enable = "neon")]
58843#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58844#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58845#[cfg_attr(
58846 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58847 assert_instr(srshr, N = 2)
58848)]
58849#[rustc_legacy_const_generics(1)]
58850#[cfg_attr(
58851 not(target_arch = "arm"),
58852 stable(feature = "neon_intrinsics", since = "1.59.0")
58853)]
58854#[cfg_attr(
58855 target_arch = "arm",
58856 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58857)]
58858pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
58859 static_assert!(N >= 1 && N <= 8);
58860 vrshlq_s8(a, vdupq_n_s8(-N as _))
58861}
58862#[doc = "Signed rounding shift right"]
58863#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
58864#[inline]
58865#[target_feature(enable = "neon")]
58866#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58867#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58868#[cfg_attr(
58869 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58870 assert_instr(srshr, N = 2)
58871)]
58872#[rustc_legacy_const_generics(1)]
58873#[cfg_attr(
58874 not(target_arch = "arm"),
58875 stable(feature = "neon_intrinsics", since = "1.59.0")
58876)]
58877#[cfg_attr(
58878 target_arch = "arm",
58879 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58880)]
58881pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
58882 static_assert!(N >= 1 && N <= 16);
58883 vrshl_s16(a, vdup_n_s16(-N as _))
58884}
58885#[doc = "Signed rounding shift right"]
58886#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
58887#[inline]
58888#[target_feature(enable = "neon")]
58889#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58890#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58891#[cfg_attr(
58892 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58893 assert_instr(srshr, N = 2)
58894)]
58895#[rustc_legacy_const_generics(1)]
58896#[cfg_attr(
58897 not(target_arch = "arm"),
58898 stable(feature = "neon_intrinsics", since = "1.59.0")
58899)]
58900#[cfg_attr(
58901 target_arch = "arm",
58902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58903)]
58904pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
58905 static_assert!(N >= 1 && N <= 16);
58906 vrshlq_s16(a, vdupq_n_s16(-N as _))
58907}
58908#[doc = "Signed rounding shift right"]
58909#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
58910#[inline]
58911#[target_feature(enable = "neon")]
58912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58914#[cfg_attr(
58915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58916 assert_instr(srshr, N = 2)
58917)]
58918#[rustc_legacy_const_generics(1)]
58919#[cfg_attr(
58920 not(target_arch = "arm"),
58921 stable(feature = "neon_intrinsics", since = "1.59.0")
58922)]
58923#[cfg_attr(
58924 target_arch = "arm",
58925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58926)]
58927pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
58928 static_assert!(N >= 1 && N <= 32);
58929 vrshl_s32(a, vdup_n_s32(-N as _))
58930}
58931#[doc = "Signed rounding shift right"]
58932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
58933#[inline]
58934#[target_feature(enable = "neon")]
58935#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58936#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58937#[cfg_attr(
58938 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58939 assert_instr(srshr, N = 2)
58940)]
58941#[rustc_legacy_const_generics(1)]
58942#[cfg_attr(
58943 not(target_arch = "arm"),
58944 stable(feature = "neon_intrinsics", since = "1.59.0")
58945)]
58946#[cfg_attr(
58947 target_arch = "arm",
58948 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58949)]
58950pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
58951 static_assert!(N >= 1 && N <= 32);
58952 vrshlq_s32(a, vdupq_n_s32(-N as _))
58953}
58954#[doc = "Signed rounding shift right"]
58955#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
58956#[inline]
58957#[target_feature(enable = "neon")]
58958#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58959#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58960#[cfg_attr(
58961 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58962 assert_instr(srshr, N = 2)
58963)]
58964#[rustc_legacy_const_generics(1)]
58965#[cfg_attr(
58966 not(target_arch = "arm"),
58967 stable(feature = "neon_intrinsics", since = "1.59.0")
58968)]
58969#[cfg_attr(
58970 target_arch = "arm",
58971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58972)]
58973pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
58974 static_assert!(N >= 1 && N <= 64);
58975 vrshl_s64(a, vdup_n_s64(-N as _))
58976}
58977#[doc = "Signed rounding shift right"]
58978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
58979#[inline]
58980#[target_feature(enable = "neon")]
58981#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
58982#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
58983#[cfg_attr(
58984 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
58985 assert_instr(srshr, N = 2)
58986)]
58987#[rustc_legacy_const_generics(1)]
58988#[cfg_attr(
58989 not(target_arch = "arm"),
58990 stable(feature = "neon_intrinsics", since = "1.59.0")
58991)]
58992#[cfg_attr(
58993 target_arch = "arm",
58994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
58995)]
58996pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
58997 static_assert!(N >= 1 && N <= 64);
58998 vrshlq_s64(a, vdupq_n_s64(-N as _))
58999}
59000#[doc = "Unsigned rounding shift right"]
59001#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
59002#[inline]
59003#[target_feature(enable = "neon")]
59004#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59005#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59006#[cfg_attr(
59007 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59008 assert_instr(urshr, N = 2)
59009)]
59010#[rustc_legacy_const_generics(1)]
59011#[cfg_attr(
59012 not(target_arch = "arm"),
59013 stable(feature = "neon_intrinsics", since = "1.59.0")
59014)]
59015#[cfg_attr(
59016 target_arch = "arm",
59017 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59018)]
59019pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
59020 static_assert!(N >= 1 && N <= 8);
59021 vrshl_u8(a, vdup_n_s8(-N as _))
59022}
59023#[doc = "Unsigned rounding shift right"]
59024#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
59025#[inline]
59026#[target_feature(enable = "neon")]
59027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59029#[cfg_attr(
59030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59031 assert_instr(urshr, N = 2)
59032)]
59033#[rustc_legacy_const_generics(1)]
59034#[cfg_attr(
59035 not(target_arch = "arm"),
59036 stable(feature = "neon_intrinsics", since = "1.59.0")
59037)]
59038#[cfg_attr(
59039 target_arch = "arm",
59040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59041)]
59042pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
59043 static_assert!(N >= 1 && N <= 8);
59044 vrshlq_u8(a, vdupq_n_s8(-N as _))
59045}
59046#[doc = "Unsigned rounding shift right"]
59047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
59048#[inline]
59049#[target_feature(enable = "neon")]
59050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59052#[cfg_attr(
59053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59054 assert_instr(urshr, N = 2)
59055)]
59056#[rustc_legacy_const_generics(1)]
59057#[cfg_attr(
59058 not(target_arch = "arm"),
59059 stable(feature = "neon_intrinsics", since = "1.59.0")
59060)]
59061#[cfg_attr(
59062 target_arch = "arm",
59063 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59064)]
59065pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
59066 static_assert!(N >= 1 && N <= 16);
59067 vrshl_u16(a, vdup_n_s16(-N as _))
59068}
59069#[doc = "Unsigned rounding shift right"]
59070#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
59071#[inline]
59072#[target_feature(enable = "neon")]
59073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59074#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59075#[cfg_attr(
59076 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59077 assert_instr(urshr, N = 2)
59078)]
59079#[rustc_legacy_const_generics(1)]
59080#[cfg_attr(
59081 not(target_arch = "arm"),
59082 stable(feature = "neon_intrinsics", since = "1.59.0")
59083)]
59084#[cfg_attr(
59085 target_arch = "arm",
59086 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59087)]
59088pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
59089 static_assert!(N >= 1 && N <= 16);
59090 vrshlq_u16(a, vdupq_n_s16(-N as _))
59091}
59092#[doc = "Unsigned rounding shift right"]
59093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
59094#[inline]
59095#[target_feature(enable = "neon")]
59096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59098#[cfg_attr(
59099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59100 assert_instr(urshr, N = 2)
59101)]
59102#[rustc_legacy_const_generics(1)]
59103#[cfg_attr(
59104 not(target_arch = "arm"),
59105 stable(feature = "neon_intrinsics", since = "1.59.0")
59106)]
59107#[cfg_attr(
59108 target_arch = "arm",
59109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59110)]
59111pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
59112 static_assert!(N >= 1 && N <= 32);
59113 vrshl_u32(a, vdup_n_s32(-N as _))
59114}
59115#[doc = "Unsigned rounding shift right"]
59116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
59117#[inline]
59118#[target_feature(enable = "neon")]
59119#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59120#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59121#[cfg_attr(
59122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59123 assert_instr(urshr, N = 2)
59124)]
59125#[rustc_legacy_const_generics(1)]
59126#[cfg_attr(
59127 not(target_arch = "arm"),
59128 stable(feature = "neon_intrinsics", since = "1.59.0")
59129)]
59130#[cfg_attr(
59131 target_arch = "arm",
59132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59133)]
59134pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
59135 static_assert!(N >= 1 && N <= 32);
59136 vrshlq_u32(a, vdupq_n_s32(-N as _))
59137}
59138#[doc = "Unsigned rounding shift right"]
59139#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
59140#[inline]
59141#[target_feature(enable = "neon")]
59142#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59143#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59144#[cfg_attr(
59145 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59146 assert_instr(urshr, N = 2)
59147)]
59148#[rustc_legacy_const_generics(1)]
59149#[cfg_attr(
59150 not(target_arch = "arm"),
59151 stable(feature = "neon_intrinsics", since = "1.59.0")
59152)]
59153#[cfg_attr(
59154 target_arch = "arm",
59155 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59156)]
59157pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
59158 static_assert!(N >= 1 && N <= 64);
59159 vrshl_u64(a, vdup_n_s64(-N as _))
59160}
59161#[doc = "Unsigned rounding shift right"]
59162#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
59163#[inline]
59164#[target_feature(enable = "neon")]
59165#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59166#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
59167#[cfg_attr(
59168 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59169 assert_instr(urshr, N = 2)
59170)]
59171#[rustc_legacy_const_generics(1)]
59172#[cfg_attr(
59173 not(target_arch = "arm"),
59174 stable(feature = "neon_intrinsics", since = "1.59.0")
59175)]
59176#[cfg_attr(
59177 target_arch = "arm",
59178 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59179)]
59180pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
59181 static_assert!(N >= 1 && N <= 64);
59182 vrshlq_u64(a, vdupq_n_s64(-N as _))
59183}
59184#[doc = "Rounding shift right narrow"]
59185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59186#[inline]
59187#[cfg(target_arch = "arm")]
59188#[target_feature(enable = "neon,v7")]
59189#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59190#[rustc_legacy_const_generics(1)]
59191#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59192pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59193 static_assert!(N >= 1 && N <= 8);
59194 unsafe extern "unadjusted" {
59195 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
59196 fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
59197 }
59198 unsafe { _vrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
59199}
59200#[doc = "Rounding shift right narrow"]
59201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59202#[inline]
59203#[cfg(target_arch = "arm")]
59204#[target_feature(enable = "neon,v7")]
59205#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59206#[rustc_legacy_const_generics(1)]
59207#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59208pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59209 static_assert!(N >= 1 && N <= 16);
59210 unsafe extern "unadjusted" {
59211 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
59212 fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
59213 }
59214 unsafe { _vrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
59215}
59216#[doc = "Rounding shift right narrow"]
59217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59218#[inline]
59219#[cfg(target_arch = "arm")]
59220#[target_feature(enable = "neon,v7")]
59221#[cfg_attr(test, assert_instr(vrshrn, N = 2))]
59222#[rustc_legacy_const_generics(1)]
59223#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
59224pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59225 static_assert!(N >= 1 && N <= 32);
59226 unsafe extern "unadjusted" {
59227 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
59228 fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
59229 }
59230 unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
59231}
59232#[doc = "Rounding shift right narrow"]
59233#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
59234#[inline]
59235#[target_feature(enable = "neon")]
59236#[cfg(not(target_arch = "arm"))]
59237#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59238#[rustc_legacy_const_generics(1)]
59239#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59240pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
59241 static_assert!(N >= 1 && N <= 8);
59242 unsafe extern "unadjusted" {
59243 #[cfg_attr(
59244 any(target_arch = "aarch64", target_arch = "arm64ec"),
59245 link_name = "llvm.aarch64.neon.rshrn.v8i8"
59246 )]
59247 fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t;
59248 }
59249 unsafe { _vrshrn_n_s16(a, N) }
59250}
59251#[doc = "Rounding shift right narrow"]
59252#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
59253#[inline]
59254#[target_feature(enable = "neon")]
59255#[cfg(not(target_arch = "arm"))]
59256#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59257#[rustc_legacy_const_generics(1)]
59258#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59259pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
59260 static_assert!(N >= 1 && N <= 16);
59261 unsafe extern "unadjusted" {
59262 #[cfg_attr(
59263 any(target_arch = "aarch64", target_arch = "arm64ec"),
59264 link_name = "llvm.aarch64.neon.rshrn.v4i16"
59265 )]
59266 fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t;
59267 }
59268 unsafe { _vrshrn_n_s32(a, N) }
59269}
59270#[doc = "Rounding shift right narrow"]
59271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
59272#[inline]
59273#[target_feature(enable = "neon")]
59274#[cfg(not(target_arch = "arm"))]
59275#[cfg_attr(test, assert_instr(rshrn, N = 2))]
59276#[rustc_legacy_const_generics(1)]
59277#[stable(feature = "neon_intrinsics", since = "1.59.0")]
59278pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
59279 static_assert!(N >= 1 && N <= 32);
59280 unsafe extern "unadjusted" {
59281 #[cfg_attr(
59282 any(target_arch = "aarch64", target_arch = "arm64ec"),
59283 link_name = "llvm.aarch64.neon.rshrn.v2i32"
59284 )]
59285 fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t;
59286 }
59287 unsafe { _vrshrn_n_s64(a, N) }
59288}
59289#[doc = "Rounding shift right narrow"]
59290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
59291#[inline]
59292#[target_feature(enable = "neon")]
59293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59295#[cfg_attr(
59296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59297 assert_instr(rshrn, N = 2)
59298)]
59299#[rustc_legacy_const_generics(1)]
59300#[cfg_attr(
59301 not(target_arch = "arm"),
59302 stable(feature = "neon_intrinsics", since = "1.59.0")
59303)]
59304#[cfg_attr(
59305 target_arch = "arm",
59306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59307)]
59308pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
59309 static_assert!(N >= 1 && N <= 8);
59310 unsafe { transmute(vrshrn_n_s16::<N>(transmute(a))) }
59311}
59312#[doc = "Rounding shift right narrow"]
59313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
59314#[inline]
59315#[target_feature(enable = "neon")]
59316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59318#[cfg_attr(
59319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59320 assert_instr(rshrn, N = 2)
59321)]
59322#[rustc_legacy_const_generics(1)]
59323#[cfg_attr(
59324 not(target_arch = "arm"),
59325 stable(feature = "neon_intrinsics", since = "1.59.0")
59326)]
59327#[cfg_attr(
59328 target_arch = "arm",
59329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59330)]
59331pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
59332 static_assert!(N >= 1 && N <= 16);
59333 unsafe { transmute(vrshrn_n_s32::<N>(transmute(a))) }
59334}
59335#[doc = "Rounding shift right narrow"]
59336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
59337#[inline]
59338#[target_feature(enable = "neon")]
59339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
59341#[cfg_attr(
59342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59343 assert_instr(rshrn, N = 2)
59344)]
59345#[rustc_legacy_const_generics(1)]
59346#[cfg_attr(
59347 not(target_arch = "arm"),
59348 stable(feature = "neon_intrinsics", since = "1.59.0")
59349)]
59350#[cfg_attr(
59351 target_arch = "arm",
59352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59353)]
59354pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
59355 static_assert!(N >= 1 && N <= 32);
59356 unsafe { transmute(vrshrn_n_s64::<N>(transmute(a))) }
59357}
59358#[doc = "Reciprocal square-root estimate."]
59359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
59360#[inline]
59361#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59362#[target_feature(enable = "neon,fp16")]
59363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59364#[cfg_attr(
59365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59366 assert_instr(frsqrte)
59367)]
59368#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59369pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
59370 unsafe extern "unadjusted" {
59371 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f16")]
59372 #[cfg_attr(
59373 any(target_arch = "aarch64", target_arch = "arm64ec"),
59374 link_name = "llvm.aarch64.neon.frsqrte.v4f16"
59375 )]
59376 fn _vrsqrte_f16(a: float16x4_t) -> float16x4_t;
59377 }
59378 unsafe { _vrsqrte_f16(a) }
59379}
59380#[doc = "Reciprocal square-root estimate."]
59381#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
59382#[inline]
59383#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59384#[target_feature(enable = "neon,fp16")]
59385#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59386#[cfg_attr(
59387 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59388 assert_instr(frsqrte)
59389)]
59390#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59391pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
59392 unsafe extern "unadjusted" {
59393 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v8f16")]
59394 #[cfg_attr(
59395 any(target_arch = "aarch64", target_arch = "arm64ec"),
59396 link_name = "llvm.aarch64.neon.frsqrte.v8f16"
59397 )]
59398 fn _vrsqrteq_f16(a: float16x8_t) -> float16x8_t;
59399 }
59400 unsafe { _vrsqrteq_f16(a) }
59401}
59402#[doc = "Reciprocal square-root estimate."]
59403#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
59404#[inline]
59405#[target_feature(enable = "neon")]
59406#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59407#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59408#[cfg_attr(
59409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59410 assert_instr(frsqrte)
59411)]
59412#[cfg_attr(
59413 not(target_arch = "arm"),
59414 stable(feature = "neon_intrinsics", since = "1.59.0")
59415)]
59416#[cfg_attr(
59417 target_arch = "arm",
59418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59419)]
59420pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
59421 unsafe extern "unadjusted" {
59422 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
59423 #[cfg_attr(
59424 any(target_arch = "aarch64", target_arch = "arm64ec"),
59425 link_name = "llvm.aarch64.neon.frsqrte.v2f32"
59426 )]
59427 fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t;
59428 }
59429 unsafe { _vrsqrte_f32(a) }
59430}
59431#[doc = "Reciprocal square-root estimate."]
59432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
59433#[inline]
59434#[target_feature(enable = "neon")]
59435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59436#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59437#[cfg_attr(
59438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59439 assert_instr(frsqrte)
59440)]
59441#[cfg_attr(
59442 not(target_arch = "arm"),
59443 stable(feature = "neon_intrinsics", since = "1.59.0")
59444)]
59445#[cfg_attr(
59446 target_arch = "arm",
59447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59448)]
59449pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
59450 unsafe extern "unadjusted" {
59451 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")]
59452 #[cfg_attr(
59453 any(target_arch = "aarch64", target_arch = "arm64ec"),
59454 link_name = "llvm.aarch64.neon.frsqrte.v4f32"
59455 )]
59456 fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t;
59457 }
59458 unsafe { _vrsqrteq_f32(a) }
59459}
59460#[doc = "Unsigned reciprocal square root estimate"]
59461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
59462#[inline]
59463#[target_feature(enable = "neon")]
59464#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59465#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59466#[cfg_attr(
59467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59468 assert_instr(ursqrte)
59469)]
59470#[cfg_attr(
59471 not(target_arch = "arm"),
59472 stable(feature = "neon_intrinsics", since = "1.59.0")
59473)]
59474#[cfg_attr(
59475 target_arch = "arm",
59476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59477)]
59478pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
59479 unsafe extern "unadjusted" {
59480 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")]
59481 #[cfg_attr(
59482 any(target_arch = "aarch64", target_arch = "arm64ec"),
59483 link_name = "llvm.aarch64.neon.ursqrte.v2i32"
59484 )]
59485 fn _vrsqrte_u32(a: uint32x2_t) -> uint32x2_t;
59486 }
59487 unsafe { _vrsqrte_u32(a) }
59488}
59489#[doc = "Unsigned reciprocal square root estimate"]
59490#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
59491#[inline]
59492#[target_feature(enable = "neon")]
59493#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59494#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
59495#[cfg_attr(
59496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59497 assert_instr(ursqrte)
59498)]
59499#[cfg_attr(
59500 not(target_arch = "arm"),
59501 stable(feature = "neon_intrinsics", since = "1.59.0")
59502)]
59503#[cfg_attr(
59504 target_arch = "arm",
59505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59506)]
59507pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
59508 unsafe extern "unadjusted" {
59509 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")]
59510 #[cfg_attr(
59511 any(target_arch = "aarch64", target_arch = "arm64ec"),
59512 link_name = "llvm.aarch64.neon.ursqrte.v4i32"
59513 )]
59514 fn _vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t;
59515 }
59516 unsafe { _vrsqrteq_u32(a) }
59517}
59518#[doc = "Floating-point reciprocal square root step"]
59519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
59520#[inline]
59521#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59522#[target_feature(enable = "neon,fp16")]
59523#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59524#[cfg_attr(
59525 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59526 assert_instr(frsqrts)
59527)]
59528#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59529pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
59530 unsafe extern "unadjusted" {
59531 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f16")]
59532 #[cfg_attr(
59533 any(target_arch = "aarch64", target_arch = "arm64ec"),
59534 link_name = "llvm.aarch64.neon.frsqrts.v4f16"
59535 )]
59536 fn _vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
59537 }
59538 unsafe { _vrsqrts_f16(a, b) }
59539}
59540#[doc = "Floating-point reciprocal square root step"]
59541#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
59542#[inline]
59543#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
59544#[target_feature(enable = "neon,fp16")]
59545#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59546#[cfg_attr(
59547 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59548 assert_instr(frsqrts)
59549)]
59550#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
59551pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
59552 unsafe extern "unadjusted" {
59553 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v8f16")]
59554 #[cfg_attr(
59555 any(target_arch = "aarch64", target_arch = "arm64ec"),
59556 link_name = "llvm.aarch64.neon.frsqrts.v8f16"
59557 )]
59558 fn _vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
59559 }
59560 unsafe { _vrsqrtsq_f16(a, b) }
59561}
59562#[doc = "Floating-point reciprocal square root step"]
59563#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
59564#[inline]
59565#[target_feature(enable = "neon")]
59566#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59567#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59568#[cfg_attr(
59569 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59570 assert_instr(frsqrts)
59571)]
59572#[cfg_attr(
59573 not(target_arch = "arm"),
59574 stable(feature = "neon_intrinsics", since = "1.59.0")
59575)]
59576#[cfg_attr(
59577 target_arch = "arm",
59578 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59579)]
59580pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
59581 unsafe extern "unadjusted" {
59582 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")]
59583 #[cfg_attr(
59584 any(target_arch = "aarch64", target_arch = "arm64ec"),
59585 link_name = "llvm.aarch64.neon.frsqrts.v2f32"
59586 )]
59587 fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
59588 }
59589 unsafe { _vrsqrts_f32(a, b) }
59590}
59591#[doc = "Floating-point reciprocal square root step"]
59592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
59593#[inline]
59594#[target_feature(enable = "neon")]
59595#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59596#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
59597#[cfg_attr(
59598 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59599 assert_instr(frsqrts)
59600)]
59601#[cfg_attr(
59602 not(target_arch = "arm"),
59603 stable(feature = "neon_intrinsics", since = "1.59.0")
59604)]
59605#[cfg_attr(
59606 target_arch = "arm",
59607 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59608)]
59609pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
59610 unsafe extern "unadjusted" {
59611 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")]
59612 #[cfg_attr(
59613 any(target_arch = "aarch64", target_arch = "arm64ec"),
59614 link_name = "llvm.aarch64.neon.frsqrts.v4f32"
59615 )]
59616 fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
59617 }
59618 unsafe { _vrsqrtsq_f32(a, b) }
59619}
59620#[doc = "Signed rounding shift right and accumulate"]
59621#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
59622#[inline]
59623#[target_feature(enable = "neon")]
59624#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59625#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59626#[cfg_attr(
59627 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59628 assert_instr(srsra, N = 2)
59629)]
59630#[rustc_legacy_const_generics(2)]
59631#[cfg_attr(
59632 not(target_arch = "arm"),
59633 stable(feature = "neon_intrinsics", since = "1.59.0")
59634)]
59635#[cfg_attr(
59636 target_arch = "arm",
59637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59638)]
59639pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
59640 static_assert!(N >= 1 && N <= 8);
59641 unsafe { simd_add(a, vrshr_n_s8::<N>(b)) }
59642}
59643#[doc = "Signed rounding shift right and accumulate"]
59644#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
59645#[inline]
59646#[target_feature(enable = "neon")]
59647#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59648#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59649#[cfg_attr(
59650 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59651 assert_instr(srsra, N = 2)
59652)]
59653#[rustc_legacy_const_generics(2)]
59654#[cfg_attr(
59655 not(target_arch = "arm"),
59656 stable(feature = "neon_intrinsics", since = "1.59.0")
59657)]
59658#[cfg_attr(
59659 target_arch = "arm",
59660 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59661)]
59662pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
59663 static_assert!(N >= 1 && N <= 8);
59664 unsafe { simd_add(a, vrshrq_n_s8::<N>(b)) }
59665}
59666#[doc = "Signed rounding shift right and accumulate"]
59667#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
59668#[inline]
59669#[target_feature(enable = "neon")]
59670#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59671#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59672#[cfg_attr(
59673 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59674 assert_instr(srsra, N = 2)
59675)]
59676#[rustc_legacy_const_generics(2)]
59677#[cfg_attr(
59678 not(target_arch = "arm"),
59679 stable(feature = "neon_intrinsics", since = "1.59.0")
59680)]
59681#[cfg_attr(
59682 target_arch = "arm",
59683 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59684)]
59685pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
59686 static_assert!(N >= 1 && N <= 16);
59687 unsafe { simd_add(a, vrshr_n_s16::<N>(b)) }
59688}
59689#[doc = "Signed rounding shift right and accumulate"]
59690#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
59691#[inline]
59692#[target_feature(enable = "neon")]
59693#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59694#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59695#[cfg_attr(
59696 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59697 assert_instr(srsra, N = 2)
59698)]
59699#[rustc_legacy_const_generics(2)]
59700#[cfg_attr(
59701 not(target_arch = "arm"),
59702 stable(feature = "neon_intrinsics", since = "1.59.0")
59703)]
59704#[cfg_attr(
59705 target_arch = "arm",
59706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59707)]
59708pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
59709 static_assert!(N >= 1 && N <= 16);
59710 unsafe { simd_add(a, vrshrq_n_s16::<N>(b)) }
59711}
59712#[doc = "Signed rounding shift right and accumulate"]
59713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
59714#[inline]
59715#[target_feature(enable = "neon")]
59716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59717#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59718#[cfg_attr(
59719 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59720 assert_instr(srsra, N = 2)
59721)]
59722#[rustc_legacy_const_generics(2)]
59723#[cfg_attr(
59724 not(target_arch = "arm"),
59725 stable(feature = "neon_intrinsics", since = "1.59.0")
59726)]
59727#[cfg_attr(
59728 target_arch = "arm",
59729 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59730)]
59731pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
59732 static_assert!(N >= 1 && N <= 32);
59733 unsafe { simd_add(a, vrshr_n_s32::<N>(b)) }
59734}
59735#[doc = "Signed rounding shift right and accumulate"]
59736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
59737#[inline]
59738#[target_feature(enable = "neon")]
59739#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59740#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59741#[cfg_attr(
59742 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59743 assert_instr(srsra, N = 2)
59744)]
59745#[rustc_legacy_const_generics(2)]
59746#[cfg_attr(
59747 not(target_arch = "arm"),
59748 stable(feature = "neon_intrinsics", since = "1.59.0")
59749)]
59750#[cfg_attr(
59751 target_arch = "arm",
59752 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59753)]
59754pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
59755 static_assert!(N >= 1 && N <= 32);
59756 unsafe { simd_add(a, vrshrq_n_s32::<N>(b)) }
59757}
59758#[doc = "Signed rounding shift right and accumulate"]
59759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
59760#[inline]
59761#[target_feature(enable = "neon")]
59762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59764#[cfg_attr(
59765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59766 assert_instr(srsra, N = 2)
59767)]
59768#[rustc_legacy_const_generics(2)]
59769#[cfg_attr(
59770 not(target_arch = "arm"),
59771 stable(feature = "neon_intrinsics", since = "1.59.0")
59772)]
59773#[cfg_attr(
59774 target_arch = "arm",
59775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59776)]
59777pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
59778 static_assert!(N >= 1 && N <= 64);
59779 unsafe { simd_add(a, vrshr_n_s64::<N>(b)) }
59780}
59781#[doc = "Signed rounding shift right and accumulate"]
59782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
59783#[inline]
59784#[target_feature(enable = "neon")]
59785#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59786#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59787#[cfg_attr(
59788 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59789 assert_instr(srsra, N = 2)
59790)]
59791#[rustc_legacy_const_generics(2)]
59792#[cfg_attr(
59793 not(target_arch = "arm"),
59794 stable(feature = "neon_intrinsics", since = "1.59.0")
59795)]
59796#[cfg_attr(
59797 target_arch = "arm",
59798 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59799)]
59800pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
59801 static_assert!(N >= 1 && N <= 64);
59802 unsafe { simd_add(a, vrshrq_n_s64::<N>(b)) }
59803}
59804#[doc = "Unsigned rounding shift right and accumulate"]
59805#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
59806#[inline]
59807#[target_feature(enable = "neon")]
59808#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59809#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59810#[cfg_attr(
59811 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59812 assert_instr(ursra, N = 2)
59813)]
59814#[rustc_legacy_const_generics(2)]
59815#[cfg_attr(
59816 not(target_arch = "arm"),
59817 stable(feature = "neon_intrinsics", since = "1.59.0")
59818)]
59819#[cfg_attr(
59820 target_arch = "arm",
59821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59822)]
59823pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
59824 static_assert!(N >= 1 && N <= 8);
59825 unsafe { simd_add(a, vrshr_n_u8::<N>(b)) }
59826}
59827#[doc = "Unsigned rounding shift right and accumulate"]
59828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
59829#[inline]
59830#[target_feature(enable = "neon")]
59831#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59832#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59833#[cfg_attr(
59834 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59835 assert_instr(ursra, N = 2)
59836)]
59837#[rustc_legacy_const_generics(2)]
59838#[cfg_attr(
59839 not(target_arch = "arm"),
59840 stable(feature = "neon_intrinsics", since = "1.59.0")
59841)]
59842#[cfg_attr(
59843 target_arch = "arm",
59844 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59845)]
59846pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
59847 static_assert!(N >= 1 && N <= 8);
59848 unsafe { simd_add(a, vrshrq_n_u8::<N>(b)) }
59849}
59850#[doc = "Unsigned rounding shift right and accumulate"]
59851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
59852#[inline]
59853#[target_feature(enable = "neon")]
59854#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59855#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59856#[cfg_attr(
59857 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59858 assert_instr(ursra, N = 2)
59859)]
59860#[rustc_legacy_const_generics(2)]
59861#[cfg_attr(
59862 not(target_arch = "arm"),
59863 stable(feature = "neon_intrinsics", since = "1.59.0")
59864)]
59865#[cfg_attr(
59866 target_arch = "arm",
59867 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59868)]
59869pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
59870 static_assert!(N >= 1 && N <= 16);
59871 unsafe { simd_add(a, vrshr_n_u16::<N>(b)) }
59872}
59873#[doc = "Unsigned rounding shift right and accumulate"]
59874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
59875#[inline]
59876#[target_feature(enable = "neon")]
59877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59878#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59879#[cfg_attr(
59880 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59881 assert_instr(ursra, N = 2)
59882)]
59883#[rustc_legacy_const_generics(2)]
59884#[cfg_attr(
59885 not(target_arch = "arm"),
59886 stable(feature = "neon_intrinsics", since = "1.59.0")
59887)]
59888#[cfg_attr(
59889 target_arch = "arm",
59890 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59891)]
59892pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
59893 static_assert!(N >= 1 && N <= 16);
59894 unsafe { simd_add(a, vrshrq_n_u16::<N>(b)) }
59895}
59896#[doc = "Unsigned rounding shift right and accumulate"]
59897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
59898#[inline]
59899#[target_feature(enable = "neon")]
59900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59901#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59902#[cfg_attr(
59903 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59904 assert_instr(ursra, N = 2)
59905)]
59906#[rustc_legacy_const_generics(2)]
59907#[cfg_attr(
59908 not(target_arch = "arm"),
59909 stable(feature = "neon_intrinsics", since = "1.59.0")
59910)]
59911#[cfg_attr(
59912 target_arch = "arm",
59913 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59914)]
59915pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
59916 static_assert!(N >= 1 && N <= 32);
59917 unsafe { simd_add(a, vrshr_n_u32::<N>(b)) }
59918}
59919#[doc = "Unsigned rounding shift right and accumulate"]
59920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
59921#[inline]
59922#[target_feature(enable = "neon")]
59923#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59924#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59925#[cfg_attr(
59926 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59927 assert_instr(ursra, N = 2)
59928)]
59929#[rustc_legacy_const_generics(2)]
59930#[cfg_attr(
59931 not(target_arch = "arm"),
59932 stable(feature = "neon_intrinsics", since = "1.59.0")
59933)]
59934#[cfg_attr(
59935 target_arch = "arm",
59936 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59937)]
59938pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
59939 static_assert!(N >= 1 && N <= 32);
59940 unsafe { simd_add(a, vrshrq_n_u32::<N>(b)) }
59941}
59942#[doc = "Unsigned rounding shift right and accumulate"]
59943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
59944#[inline]
59945#[target_feature(enable = "neon")]
59946#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59947#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59948#[cfg_attr(
59949 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59950 assert_instr(ursra, N = 2)
59951)]
59952#[rustc_legacy_const_generics(2)]
59953#[cfg_attr(
59954 not(target_arch = "arm"),
59955 stable(feature = "neon_intrinsics", since = "1.59.0")
59956)]
59957#[cfg_attr(
59958 target_arch = "arm",
59959 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59960)]
59961pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
59962 static_assert!(N >= 1 && N <= 64);
59963 unsafe { simd_add(a, vrshr_n_u64::<N>(b)) }
59964}
59965#[doc = "Unsigned rounding shift right and accumulate"]
59966#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
59967#[inline]
59968#[target_feature(enable = "neon")]
59969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59970#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
59971#[cfg_attr(
59972 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59973 assert_instr(ursra, N = 2)
59974)]
59975#[rustc_legacy_const_generics(2)]
59976#[cfg_attr(
59977 not(target_arch = "arm"),
59978 stable(feature = "neon_intrinsics", since = "1.59.0")
59979)]
59980#[cfg_attr(
59981 target_arch = "arm",
59982 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
59983)]
59984pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
59985 static_assert!(N >= 1 && N <= 64);
59986 unsafe { simd_add(a, vrshrq_n_u64::<N>(b)) }
59987}
59988#[doc = "Rounding subtract returning high narrow"]
59989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
59990#[inline]
59991#[target_feature(enable = "neon")]
59992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
59993#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
59994#[cfg_attr(
59995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
59996 assert_instr(rsubhn)
59997)]
59998#[cfg_attr(
59999 not(target_arch = "arm"),
60000 stable(feature = "neon_intrinsics", since = "1.59.0")
60001)]
60002#[cfg_attr(
60003 target_arch = "arm",
60004 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60005)]
60006pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
60007 unsafe extern "unadjusted" {
60008 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")]
60009 #[cfg_attr(
60010 any(target_arch = "aarch64", target_arch = "arm64ec"),
60011 link_name = "llvm.aarch64.neon.rsubhn.v8i8"
60012 )]
60013 fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t;
60014 }
60015 unsafe { _vrsubhn_s16(a, b) }
60016}
60017#[doc = "Rounding subtract returning high narrow"]
60018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
60019#[inline]
60020#[target_feature(enable = "neon")]
60021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60023#[cfg_attr(
60024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60025 assert_instr(rsubhn)
60026)]
60027#[cfg_attr(
60028 not(target_arch = "arm"),
60029 stable(feature = "neon_intrinsics", since = "1.59.0")
60030)]
60031#[cfg_attr(
60032 target_arch = "arm",
60033 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60034)]
60035pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
60036 unsafe extern "unadjusted" {
60037 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")]
60038 #[cfg_attr(
60039 any(target_arch = "aarch64", target_arch = "arm64ec"),
60040 link_name = "llvm.aarch64.neon.rsubhn.v4i16"
60041 )]
60042 fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t;
60043 }
60044 unsafe { _vrsubhn_s32(a, b) }
60045}
60046#[doc = "Rounding subtract returning high narrow"]
60047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
60048#[inline]
60049#[target_feature(enable = "neon")]
60050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60052#[cfg_attr(
60053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60054 assert_instr(rsubhn)
60055)]
60056#[cfg_attr(
60057 not(target_arch = "arm"),
60058 stable(feature = "neon_intrinsics", since = "1.59.0")
60059)]
60060#[cfg_attr(
60061 target_arch = "arm",
60062 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60063)]
60064pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
60065 unsafe extern "unadjusted" {
60066 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")]
60067 #[cfg_attr(
60068 any(target_arch = "aarch64", target_arch = "arm64ec"),
60069 link_name = "llvm.aarch64.neon.rsubhn.v2i32"
60070 )]
60071 fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t;
60072 }
60073 unsafe { _vrsubhn_s64(a, b) }
60074}
60075#[doc = "Rounding subtract returning high narrow"]
60076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60077#[inline]
60078#[cfg(target_endian = "little")]
60079#[target_feature(enable = "neon")]
60080#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60081#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60082#[cfg_attr(
60083 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60084 assert_instr(rsubhn)
60085)]
60086#[cfg_attr(
60087 not(target_arch = "arm"),
60088 stable(feature = "neon_intrinsics", since = "1.59.0")
60089)]
60090#[cfg_attr(
60091 target_arch = "arm",
60092 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60093)]
60094pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60095 unsafe { transmute(vrsubhn_s16(transmute(a), transmute(b))) }
60096}
60097#[doc = "Rounding subtract returning high narrow"]
60098#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
60099#[inline]
60100#[cfg(target_endian = "big")]
60101#[target_feature(enable = "neon")]
60102#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60104#[cfg_attr(
60105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60106 assert_instr(rsubhn)
60107)]
60108#[cfg_attr(
60109 not(target_arch = "arm"),
60110 stable(feature = "neon_intrinsics", since = "1.59.0")
60111)]
60112#[cfg_attr(
60113 target_arch = "arm",
60114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60115)]
60116pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
60117 let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
60118 let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
60119 unsafe {
60120 let ret_val: uint8x8_t = transmute(vrsubhn_s16(transmute(a), transmute(b)));
60121 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
60122 }
60123}
60124#[doc = "Rounding subtract returning high narrow"]
60125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60126#[inline]
60127#[cfg(target_endian = "little")]
60128#[target_feature(enable = "neon")]
60129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60130#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60131#[cfg_attr(
60132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60133 assert_instr(rsubhn)
60134)]
60135#[cfg_attr(
60136 not(target_arch = "arm"),
60137 stable(feature = "neon_intrinsics", since = "1.59.0")
60138)]
60139#[cfg_attr(
60140 target_arch = "arm",
60141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60142)]
60143pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60144 unsafe { transmute(vrsubhn_s32(transmute(a), transmute(b))) }
60145}
60146#[doc = "Rounding subtract returning high narrow"]
60147#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
60148#[inline]
60149#[cfg(target_endian = "big")]
60150#[target_feature(enable = "neon")]
60151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60152#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60153#[cfg_attr(
60154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60155 assert_instr(rsubhn)
60156)]
60157#[cfg_attr(
60158 not(target_arch = "arm"),
60159 stable(feature = "neon_intrinsics", since = "1.59.0")
60160)]
60161#[cfg_attr(
60162 target_arch = "arm",
60163 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60164)]
60165pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
60166 let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
60167 let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) };
60168 unsafe {
60169 let ret_val: uint16x4_t = transmute(vrsubhn_s32(transmute(a), transmute(b)));
60170 simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
60171 }
60172}
60173#[doc = "Rounding subtract returning high narrow"]
60174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60175#[inline]
60176#[cfg(target_endian = "little")]
60177#[target_feature(enable = "neon")]
60178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60180#[cfg_attr(
60181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60182 assert_instr(rsubhn)
60183)]
60184#[cfg_attr(
60185 not(target_arch = "arm"),
60186 stable(feature = "neon_intrinsics", since = "1.59.0")
60187)]
60188#[cfg_attr(
60189 target_arch = "arm",
60190 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60191)]
60192pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60193 unsafe { transmute(vrsubhn_s64(transmute(a), transmute(b))) }
60194}
60195#[doc = "Rounding subtract returning high narrow"]
60196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
60197#[inline]
60198#[cfg(target_endian = "big")]
60199#[target_feature(enable = "neon")]
60200#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60201#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
60202#[cfg_attr(
60203 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60204 assert_instr(rsubhn)
60205)]
60206#[cfg_attr(
60207 not(target_arch = "arm"),
60208 stable(feature = "neon_intrinsics", since = "1.59.0")
60209)]
60210#[cfg_attr(
60211 target_arch = "arm",
60212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60213)]
60214pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
60215 let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
60216 let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) };
60217 unsafe {
60218 let ret_val: uint32x2_t = transmute(vrsubhn_s64(transmute(a), transmute(b)));
60219 simd_shuffle!(ret_val, ret_val, [1, 0])
60220 }
60221}
60222#[doc = "Insert vector element from another vector element"]
60223#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
60224#[inline]
60225#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60226#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60227#[cfg_attr(
60228 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60229 assert_instr(nop, LANE = 0)
60230)]
60231#[rustc_legacy_const_generics(2)]
60232#[target_feature(enable = "neon,fp16")]
60233#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60234pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
60235 static_assert_uimm_bits!(LANE, 2);
60236 unsafe { simd_insert!(b, LANE as u32, a) }
60237}
60238#[doc = "Insert vector element from another vector element"]
60239#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
60240#[inline]
60241#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60242#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60243#[cfg_attr(
60244 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60245 assert_instr(nop, LANE = 0)
60246)]
60247#[rustc_legacy_const_generics(2)]
60248#[target_feature(enable = "neon,fp16")]
60249#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
60250pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
60251 static_assert_uimm_bits!(LANE, 3);
60252 unsafe { simd_insert!(b, LANE as u32, a) }
60253}
60254#[doc = "Insert vector element from another vector element"]
60255#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
60256#[inline]
60257#[target_feature(enable = "neon")]
60258#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60259#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60260#[cfg_attr(
60261 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60262 assert_instr(nop, LANE = 0)
60263)]
60264#[rustc_legacy_const_generics(2)]
60265#[cfg_attr(
60266 not(target_arch = "arm"),
60267 stable(feature = "neon_intrinsics", since = "1.59.0")
60268)]
60269#[cfg_attr(
60270 target_arch = "arm",
60271 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60272)]
60273pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
60274 static_assert_uimm_bits!(LANE, 1);
60275 unsafe { simd_insert!(b, LANE as u32, a) }
60276}
60277#[doc = "Insert vector element from another vector element"]
60278#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
60279#[inline]
60280#[target_feature(enable = "neon")]
60281#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60282#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60283#[cfg_attr(
60284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60285 assert_instr(nop, LANE = 0)
60286)]
60287#[rustc_legacy_const_generics(2)]
60288#[cfg_attr(
60289 not(target_arch = "arm"),
60290 stable(feature = "neon_intrinsics", since = "1.59.0")
60291)]
60292#[cfg_attr(
60293 target_arch = "arm",
60294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60295)]
60296pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
60297 static_assert_uimm_bits!(LANE, 2);
60298 unsafe { simd_insert!(b, LANE as u32, a) }
60299}
60300#[doc = "Insert vector element from another vector element"]
60301#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
60302#[inline]
60303#[target_feature(enable = "neon")]
60304#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60305#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60306#[cfg_attr(
60307 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60308 assert_instr(nop, LANE = 0)
60309)]
60310#[rustc_legacy_const_generics(2)]
60311#[cfg_attr(
60312 not(target_arch = "arm"),
60313 stable(feature = "neon_intrinsics", since = "1.59.0")
60314)]
60315#[cfg_attr(
60316 target_arch = "arm",
60317 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60318)]
60319pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
60320 static_assert_uimm_bits!(LANE, 3);
60321 unsafe { simd_insert!(b, LANE as u32, a) }
60322}
60323#[doc = "Insert vector element from another vector element"]
60324#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
60325#[inline]
60326#[target_feature(enable = "neon")]
60327#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60328#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60329#[cfg_attr(
60330 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60331 assert_instr(nop, LANE = 0)
60332)]
60333#[rustc_legacy_const_generics(2)]
60334#[cfg_attr(
60335 not(target_arch = "arm"),
60336 stable(feature = "neon_intrinsics", since = "1.59.0")
60337)]
60338#[cfg_attr(
60339 target_arch = "arm",
60340 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60341)]
60342pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
60343 static_assert_uimm_bits!(LANE, 4);
60344 unsafe { simd_insert!(b, LANE as u32, a) }
60345}
60346#[doc = "Insert vector element from another vector element"]
60347#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
60348#[inline]
60349#[target_feature(enable = "neon")]
60350#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60351#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60352#[cfg_attr(
60353 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60354 assert_instr(nop, LANE = 0)
60355)]
60356#[rustc_legacy_const_generics(2)]
60357#[cfg_attr(
60358 not(target_arch = "arm"),
60359 stable(feature = "neon_intrinsics", since = "1.59.0")
60360)]
60361#[cfg_attr(
60362 target_arch = "arm",
60363 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60364)]
60365pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
60366 static_assert_uimm_bits!(LANE, 2);
60367 unsafe { simd_insert!(b, LANE as u32, a) }
60368}
60369#[doc = "Insert vector element from another vector element"]
60370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
60371#[inline]
60372#[target_feature(enable = "neon")]
60373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60375#[cfg_attr(
60376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60377 assert_instr(nop, LANE = 0)
60378)]
60379#[rustc_legacy_const_generics(2)]
60380#[cfg_attr(
60381 not(target_arch = "arm"),
60382 stable(feature = "neon_intrinsics", since = "1.59.0")
60383)]
60384#[cfg_attr(
60385 target_arch = "arm",
60386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60387)]
60388pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
60389 static_assert_uimm_bits!(LANE, 3);
60390 unsafe { simd_insert!(b, LANE as u32, a) }
60391}
60392#[doc = "Insert vector element from another vector element"]
60393#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
60394#[inline]
60395#[target_feature(enable = "neon")]
60396#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60397#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60398#[cfg_attr(
60399 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60400 assert_instr(nop, LANE = 0)
60401)]
60402#[rustc_legacy_const_generics(2)]
60403#[cfg_attr(
60404 not(target_arch = "arm"),
60405 stable(feature = "neon_intrinsics", since = "1.59.0")
60406)]
60407#[cfg_attr(
60408 target_arch = "arm",
60409 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60410)]
60411pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
60412 static_assert_uimm_bits!(LANE, 1);
60413 unsafe { simd_insert!(b, LANE as u32, a) }
60414}
60415#[doc = "Insert vector element from another vector element"]
60416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
60417#[inline]
60418#[target_feature(enable = "neon")]
60419#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60420#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60421#[cfg_attr(
60422 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60423 assert_instr(nop, LANE = 0)
60424)]
60425#[rustc_legacy_const_generics(2)]
60426#[cfg_attr(
60427 not(target_arch = "arm"),
60428 stable(feature = "neon_intrinsics", since = "1.59.0")
60429)]
60430#[cfg_attr(
60431 target_arch = "arm",
60432 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60433)]
60434pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
60435 static_assert_uimm_bits!(LANE, 2);
60436 unsafe { simd_insert!(b, LANE as u32, a) }
60437}
60438#[doc = "Insert vector element from another vector element"]
60439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
60440#[inline]
60441#[target_feature(enable = "neon")]
60442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60443#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60444#[cfg_attr(
60445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60446 assert_instr(nop, LANE = 0)
60447)]
60448#[rustc_legacy_const_generics(2)]
60449#[cfg_attr(
60450 not(target_arch = "arm"),
60451 stable(feature = "neon_intrinsics", since = "1.59.0")
60452)]
60453#[cfg_attr(
60454 target_arch = "arm",
60455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60456)]
60457pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
60458 static_assert_uimm_bits!(LANE, 1);
60459 unsafe { simd_insert!(b, LANE as u32, a) }
60460}
60461#[doc = "Insert vector element from another vector element"]
60462#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
60463#[inline]
60464#[target_feature(enable = "neon")]
60465#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60466#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60467#[cfg_attr(
60468 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60469 assert_instr(nop, LANE = 0)
60470)]
60471#[rustc_legacy_const_generics(2)]
60472#[cfg_attr(
60473 not(target_arch = "arm"),
60474 stable(feature = "neon_intrinsics", since = "1.59.0")
60475)]
60476#[cfg_attr(
60477 target_arch = "arm",
60478 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60479)]
60480pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
60481 static_assert_uimm_bits!(LANE, 3);
60482 unsafe { simd_insert!(b, LANE as u32, a) }
60483}
60484#[doc = "Insert vector element from another vector element"]
60485#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
60486#[inline]
60487#[target_feature(enable = "neon")]
60488#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60489#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60490#[cfg_attr(
60491 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60492 assert_instr(nop, LANE = 0)
60493)]
60494#[rustc_legacy_const_generics(2)]
60495#[cfg_attr(
60496 not(target_arch = "arm"),
60497 stable(feature = "neon_intrinsics", since = "1.59.0")
60498)]
60499#[cfg_attr(
60500 target_arch = "arm",
60501 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60502)]
60503pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
60504 static_assert_uimm_bits!(LANE, 4);
60505 unsafe { simd_insert!(b, LANE as u32, a) }
60506}
60507#[doc = "Insert vector element from another vector element"]
60508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
60509#[inline]
60510#[target_feature(enable = "neon")]
60511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60512#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60513#[cfg_attr(
60514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60515 assert_instr(nop, LANE = 0)
60516)]
60517#[rustc_legacy_const_generics(2)]
60518#[cfg_attr(
60519 not(target_arch = "arm"),
60520 stable(feature = "neon_intrinsics", since = "1.59.0")
60521)]
60522#[cfg_attr(
60523 target_arch = "arm",
60524 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60525)]
60526pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
60527 static_assert_uimm_bits!(LANE, 2);
60528 unsafe { simd_insert!(b, LANE as u32, a) }
60529}
60530#[doc = "Insert vector element from another vector element"]
60531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
60532#[inline]
60533#[target_feature(enable = "neon")]
60534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60536#[cfg_attr(
60537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60538 assert_instr(nop, LANE = 0)
60539)]
60540#[rustc_legacy_const_generics(2)]
60541#[cfg_attr(
60542 not(target_arch = "arm"),
60543 stable(feature = "neon_intrinsics", since = "1.59.0")
60544)]
60545#[cfg_attr(
60546 target_arch = "arm",
60547 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60548)]
60549pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
60550 static_assert_uimm_bits!(LANE, 3);
60551 unsafe { simd_insert!(b, LANE as u32, a) }
60552}
60553#[doc = "Insert vector element from another vector element"]
60554#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
60555#[inline]
60556#[target_feature(enable = "neon")]
60557#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60558#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60559#[cfg_attr(
60560 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60561 assert_instr(nop, LANE = 0)
60562)]
60563#[rustc_legacy_const_generics(2)]
60564#[cfg_attr(
60565 not(target_arch = "arm"),
60566 stable(feature = "neon_intrinsics", since = "1.59.0")
60567)]
60568#[cfg_attr(
60569 target_arch = "arm",
60570 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60571)]
60572pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
60573 static_assert_uimm_bits!(LANE, 1);
60574 unsafe { simd_insert!(b, LANE as u32, a) }
60575}
60576#[doc = "Insert vector element from another vector element"]
60577#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
60578#[inline]
60579#[target_feature(enable = "neon")]
60580#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60581#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60582#[cfg_attr(
60583 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60584 assert_instr(nop, LANE = 0)
60585)]
60586#[rustc_legacy_const_generics(2)]
60587#[cfg_attr(
60588 not(target_arch = "arm"),
60589 stable(feature = "neon_intrinsics", since = "1.59.0")
60590)]
60591#[cfg_attr(
60592 target_arch = "arm",
60593 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60594)]
60595pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
60596 static_assert_uimm_bits!(LANE, 2);
60597 unsafe { simd_insert!(b, LANE as u32, a) }
60598}
60599#[doc = "Insert vector element from another vector element"]
60600#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
60601#[inline]
60602#[target_feature(enable = "neon")]
60603#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60604#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60605#[cfg_attr(
60606 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60607 assert_instr(nop, LANE = 0)
60608)]
60609#[rustc_legacy_const_generics(2)]
60610#[cfg_attr(
60611 not(target_arch = "arm"),
60612 stable(feature = "neon_intrinsics", since = "1.59.0")
60613)]
60614#[cfg_attr(
60615 target_arch = "arm",
60616 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60617)]
60618pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
60619 static_assert_uimm_bits!(LANE, 1);
60620 unsafe { simd_insert!(b, LANE as u32, a) }
60621}
60622#[doc = "Insert vector element from another vector element"]
60623#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
60624#[inline]
60625#[target_feature(enable = "neon")]
60626#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60627#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60628#[cfg_attr(
60629 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60630 assert_instr(nop, LANE = 0)
60631)]
60632#[rustc_legacy_const_generics(2)]
60633#[cfg_attr(
60634 not(target_arch = "arm"),
60635 stable(feature = "neon_intrinsics", since = "1.59.0")
60636)]
60637#[cfg_attr(
60638 target_arch = "arm",
60639 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60640)]
60641pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
60642 static_assert_uimm_bits!(LANE, 3);
60643 unsafe { simd_insert!(b, LANE as u32, a) }
60644}
60645#[doc = "Insert vector element from another vector element"]
60646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
60647#[inline]
60648#[target_feature(enable = "neon")]
60649#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60650#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60651#[cfg_attr(
60652 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60653 assert_instr(nop, LANE = 0)
60654)]
60655#[rustc_legacy_const_generics(2)]
60656#[cfg_attr(
60657 not(target_arch = "arm"),
60658 stable(feature = "neon_intrinsics", since = "1.59.0")
60659)]
60660#[cfg_attr(
60661 target_arch = "arm",
60662 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60663)]
60664pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
60665 static_assert_uimm_bits!(LANE, 4);
60666 unsafe { simd_insert!(b, LANE as u32, a) }
60667}
60668#[doc = "Insert vector element from another vector element"]
60669#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
60670#[inline]
60671#[target_feature(enable = "neon")]
60672#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60673#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60674#[cfg_attr(
60675 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60676 assert_instr(nop, LANE = 0)
60677)]
60678#[rustc_legacy_const_generics(2)]
60679#[cfg_attr(
60680 not(target_arch = "arm"),
60681 stable(feature = "neon_intrinsics", since = "1.59.0")
60682)]
60683#[cfg_attr(
60684 target_arch = "arm",
60685 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60686)]
60687pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
60688 static_assert_uimm_bits!(LANE, 2);
60689 unsafe { simd_insert!(b, LANE as u32, a) }
60690}
60691#[doc = "Insert vector element from another vector element"]
60692#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
60693#[inline]
60694#[target_feature(enable = "neon")]
60695#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60696#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60697#[cfg_attr(
60698 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60699 assert_instr(nop, LANE = 0)
60700)]
60701#[rustc_legacy_const_generics(2)]
60702#[cfg_attr(
60703 not(target_arch = "arm"),
60704 stable(feature = "neon_intrinsics", since = "1.59.0")
60705)]
60706#[cfg_attr(
60707 target_arch = "arm",
60708 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60709)]
60710pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
60711 static_assert_uimm_bits!(LANE, 3);
60712 unsafe { simd_insert!(b, LANE as u32, a) }
60713}
60714#[doc = "Insert vector element from another vector element"]
60715#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
60716#[inline]
60717#[target_feature(enable = "neon,aes")]
60718#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60719#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60720#[cfg_attr(
60721 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60722 assert_instr(nop, LANE = 0)
60723)]
60724#[rustc_legacy_const_generics(2)]
60725#[cfg_attr(
60726 not(target_arch = "arm"),
60727 stable(feature = "neon_intrinsics", since = "1.59.0")
60728)]
60729#[cfg_attr(
60730 target_arch = "arm",
60731 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60732)]
60733pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
60734 static_assert!(LANE == 0);
60735 unsafe { simd_insert!(b, LANE as u32, a) }
60736}
60737#[doc = "Insert vector element from another vector element"]
60738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
60739#[inline]
60740#[target_feature(enable = "neon")]
60741#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60742#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60743#[cfg_attr(
60744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60745 assert_instr(nop, LANE = 0)
60746)]
60747#[rustc_legacy_const_generics(2)]
60748#[cfg_attr(
60749 not(target_arch = "arm"),
60750 stable(feature = "neon_intrinsics", since = "1.59.0")
60751)]
60752#[cfg_attr(
60753 target_arch = "arm",
60754 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60755)]
60756pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
60757 static_assert!(LANE == 0);
60758 unsafe { simd_insert!(b, LANE as u32, a) }
60759}
60760#[doc = "Insert vector element from another vector element"]
60761#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
60762#[inline]
60763#[target_feature(enable = "neon")]
60764#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
60765#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60766#[cfg_attr(
60767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60768 assert_instr(nop, LANE = 0)
60769)]
60770#[rustc_legacy_const_generics(2)]
60771#[cfg_attr(
60772 not(target_arch = "arm"),
60773 stable(feature = "neon_intrinsics", since = "1.59.0")
60774)]
60775#[cfg_attr(
60776 target_arch = "arm",
60777 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60778)]
60779pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
60780 static_assert!(LANE == 0);
60781 unsafe { simd_insert!(b, LANE as u32, a) }
60782}
60783#[doc = "Insert vector element from another vector element"]
60784#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
60785#[inline]
60786#[target_feature(enable = "neon,aes")]
60787#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
60789#[cfg_attr(
60790 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
60791 assert_instr(nop, LANE = 0)
60792)]
60793#[rustc_legacy_const_generics(2)]
60794#[cfg_attr(
60795 not(target_arch = "arm"),
60796 stable(feature = "neon_intrinsics", since = "1.59.0")
60797)]
60798#[cfg_attr(
60799 target_arch = "arm",
60800 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60801)]
60802pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
60803 static_assert_uimm_bits!(LANE, 1);
60804 unsafe { simd_insert!(b, LANE as u32, a) }
60805}
60806#[doc = "SHA1 hash update accelerator, choose."]
60807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
60808#[inline]
60809#[target_feature(enable = "sha2")]
60810#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60811#[cfg_attr(test, assert_instr(sha1c))]
60812#[cfg_attr(
60813 target_arch = "arm",
60814 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60815)]
60816#[cfg_attr(
60817 not(target_arch = "arm"),
60818 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60819)]
60820pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
60821 unsafe extern "unadjusted" {
60822 #[cfg_attr(
60823 any(target_arch = "aarch64", target_arch = "arm64ec"),
60824 link_name = "llvm.aarch64.crypto.sha1c"
60825 )]
60826 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
60827 fn _vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
60828 }
60829 unsafe { _vsha1cq_u32(hash_abcd, hash_e, wk) }
60830}
60831#[doc = "SHA1 fixed rotate."]
60832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
60833#[inline]
60834#[target_feature(enable = "sha2")]
60835#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60836#[cfg_attr(test, assert_instr(sha1h))]
60837#[cfg_attr(
60838 target_arch = "arm",
60839 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60840)]
60841#[cfg_attr(
60842 not(target_arch = "arm"),
60843 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60844)]
60845pub fn vsha1h_u32(hash_e: u32) -> u32 {
60846 unsafe extern "unadjusted" {
60847 #[cfg_attr(
60848 any(target_arch = "aarch64", target_arch = "arm64ec"),
60849 link_name = "llvm.aarch64.crypto.sha1h"
60850 )]
60851 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
60852 fn _vsha1h_u32(hash_e: u32) -> u32;
60853 }
60854 unsafe { _vsha1h_u32(hash_e) }
60855}
60856#[doc = "SHA1 hash update accelerator, majority"]
60857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
60858#[inline]
60859#[target_feature(enable = "sha2")]
60860#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60861#[cfg_attr(test, assert_instr(sha1m))]
60862#[cfg_attr(
60863 target_arch = "arm",
60864 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60865)]
60866#[cfg_attr(
60867 not(target_arch = "arm"),
60868 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60869)]
60870pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
60871 unsafe extern "unadjusted" {
60872 #[cfg_attr(
60873 any(target_arch = "aarch64", target_arch = "arm64ec"),
60874 link_name = "llvm.aarch64.crypto.sha1m"
60875 )]
60876 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
60877 fn _vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
60878 }
60879 unsafe { _vsha1mq_u32(hash_abcd, hash_e, wk) }
60880}
60881#[doc = "SHA1 hash update accelerator, parity"]
60882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
60883#[inline]
60884#[target_feature(enable = "sha2")]
60885#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60886#[cfg_attr(test, assert_instr(sha1p))]
60887#[cfg_attr(
60888 target_arch = "arm",
60889 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60890)]
60891#[cfg_attr(
60892 not(target_arch = "arm"),
60893 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60894)]
60895pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
60896 unsafe extern "unadjusted" {
60897 #[cfg_attr(
60898 any(target_arch = "aarch64", target_arch = "arm64ec"),
60899 link_name = "llvm.aarch64.crypto.sha1p"
60900 )]
60901 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
60902 fn _vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
60903 }
60904 unsafe { _vsha1pq_u32(hash_abcd, hash_e, wk) }
60905}
60906#[doc = "SHA1 schedule update accelerator, first part."]
60907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
60908#[inline]
60909#[target_feature(enable = "sha2")]
60910#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60911#[cfg_attr(test, assert_instr(sha1su0))]
60912#[cfg_attr(
60913 target_arch = "arm",
60914 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60915)]
60916#[cfg_attr(
60917 not(target_arch = "arm"),
60918 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60919)]
60920pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
60921 unsafe extern "unadjusted" {
60922 #[cfg_attr(
60923 any(target_arch = "aarch64", target_arch = "arm64ec"),
60924 link_name = "llvm.aarch64.crypto.sha1su0"
60925 )]
60926 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
60927 fn _vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
60928 }
60929 unsafe { _vsha1su0q_u32(w0_3, w4_7, w8_11) }
60930}
60931#[doc = "SHA1 schedule update accelerator, second part."]
60932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
60933#[inline]
60934#[target_feature(enable = "sha2")]
60935#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60936#[cfg_attr(test, assert_instr(sha1su1))]
60937#[cfg_attr(
60938 target_arch = "arm",
60939 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60940)]
60941#[cfg_attr(
60942 not(target_arch = "arm"),
60943 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60944)]
60945pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
60946 unsafe extern "unadjusted" {
60947 #[cfg_attr(
60948 any(target_arch = "aarch64", target_arch = "arm64ec"),
60949 link_name = "llvm.aarch64.crypto.sha1su1"
60950 )]
60951 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
60952 fn _vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
60953 }
60954 unsafe { _vsha1su1q_u32(tw0_3, w12_15) }
60955}
60956#[doc = "SHA1 schedule update accelerator, upper part."]
60957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
60958#[inline]
60959#[target_feature(enable = "sha2")]
60960#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60961#[cfg_attr(test, assert_instr(sha256h2))]
60962#[cfg_attr(
60963 target_arch = "arm",
60964 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60965)]
60966#[cfg_attr(
60967 not(target_arch = "arm"),
60968 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60969)]
60970pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
60971 unsafe extern "unadjusted" {
60972 #[cfg_attr(
60973 any(target_arch = "aarch64", target_arch = "arm64ec"),
60974 link_name = "llvm.aarch64.crypto.sha256h2"
60975 )]
60976 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
60977 fn _vsha256h2q_u32(
60978 hash_abcd: uint32x4_t,
60979 hash_efgh: uint32x4_t,
60980 wk: uint32x4_t,
60981 ) -> uint32x4_t;
60982 }
60983 unsafe { _vsha256h2q_u32(hash_abcd, hash_efgh, wk) }
60984}
60985#[doc = "SHA1 schedule update accelerator, first part."]
60986#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
60987#[inline]
60988#[target_feature(enable = "sha2")]
60989#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
60990#[cfg_attr(test, assert_instr(sha256h))]
60991#[cfg_attr(
60992 target_arch = "arm",
60993 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
60994)]
60995#[cfg_attr(
60996 not(target_arch = "arm"),
60997 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
60998)]
60999pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t {
61000 unsafe extern "unadjusted" {
61001 #[cfg_attr(
61002 any(target_arch = "aarch64", target_arch = "arm64ec"),
61003 link_name = "llvm.aarch64.crypto.sha256h"
61004 )]
61005 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
61006 fn _vsha256hq_u32(
61007 hash_abcd: uint32x4_t,
61008 hash_efgh: uint32x4_t,
61009 wk: uint32x4_t,
61010 ) -> uint32x4_t;
61011 }
61012 unsafe { _vsha256hq_u32(hash_abcd, hash_efgh, wk) }
61013}
61014#[doc = "SHA256 schedule update accelerator, first part."]
61015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
61016#[inline]
61017#[target_feature(enable = "sha2")]
61018#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61019#[cfg_attr(test, assert_instr(sha256su0))]
61020#[cfg_attr(
61021 target_arch = "arm",
61022 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61023)]
61024#[cfg_attr(
61025 not(target_arch = "arm"),
61026 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61027)]
61028pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
61029 unsafe extern "unadjusted" {
61030 #[cfg_attr(
61031 any(target_arch = "aarch64", target_arch = "arm64ec"),
61032 link_name = "llvm.aarch64.crypto.sha256su0"
61033 )]
61034 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
61035 fn _vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
61036 }
61037 unsafe { _vsha256su0q_u32(w0_3, w4_7) }
61038}
61039#[doc = "SHA256 schedule update accelerator, second part."]
61040#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
61041#[inline]
61042#[target_feature(enable = "sha2")]
61043#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
61044#[cfg_attr(test, assert_instr(sha256su1))]
61045#[cfg_attr(
61046 target_arch = "arm",
61047 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61048)]
61049#[cfg_attr(
61050 not(target_arch = "arm"),
61051 stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
61052)]
61053pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
61054 unsafe extern "unadjusted" {
61055 #[cfg_attr(
61056 any(target_arch = "aarch64", target_arch = "arm64ec"),
61057 link_name = "llvm.aarch64.crypto.sha256su1"
61058 )]
61059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
61060 fn _vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
61061 -> uint32x4_t;
61062 }
61063 unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
61064}
61065#[doc = "Shift Right and Insert (immediate)"]
61066#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v16i8)"]
61067#[inline]
61068#[target_feature(enable = "neon")]
61069#[cfg(target_arch = "arm")]
61070#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61071#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61072fn vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
61073 unsafe extern "unadjusted" {
61074 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v16i8")]
61075 fn _vshiftins_v16i8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
61076 }
61077 unsafe { _vshiftins_v16i8(a, b, c) }
61078}
61079#[doc = "Shift Right and Insert (immediate)"]
61080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v1i64)"]
61081#[inline]
61082#[target_feature(enable = "neon")]
61083#[cfg(target_arch = "arm")]
61084#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61085#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61086fn vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
61087 unsafe extern "unadjusted" {
61088 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v1i64")]
61089 fn _vshiftins_v1i64(a: int64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t;
61090 }
61091 unsafe { _vshiftins_v1i64(a, b, c) }
61092}
61093#[doc = "Shift Right and Insert (immediate)"]
61094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i32)"]
61095#[inline]
61096#[target_feature(enable = "neon")]
61097#[cfg(target_arch = "arm")]
61098#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61099#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61100fn vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
61101 unsafe extern "unadjusted" {
61102 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i32")]
61103 fn _vshiftins_v2i32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t;
61104 }
61105 unsafe { _vshiftins_v2i32(a, b, c) }
61106}
61107#[doc = "Shift Right and Insert (immediate)"]
61108#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v2i64)"]
61109#[inline]
61110#[target_feature(enable = "neon")]
61111#[cfg(target_arch = "arm")]
61112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61113#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61114fn vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
61115 unsafe extern "unadjusted" {
61116 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v2i64")]
61117 fn _vshiftins_v2i64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t;
61118 }
61119 unsafe { _vshiftins_v2i64(a, b, c) }
61120}
61121#[doc = "Shift Right and Insert (immediate)"]
61122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i16)"]
61123#[inline]
61124#[target_feature(enable = "neon")]
61125#[cfg(target_arch = "arm")]
61126#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61127#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61128fn vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
61129 unsafe extern "unadjusted" {
61130 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i16")]
61131 fn _vshiftins_v4i16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t;
61132 }
61133 unsafe { _vshiftins_v4i16(a, b, c) }
61134}
61135#[doc = "Shift Right and Insert (immediate)"]
61136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v4i32)"]
61137#[inline]
61138#[target_feature(enable = "neon")]
61139#[cfg(target_arch = "arm")]
61140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61141#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61142fn vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
61143 unsafe extern "unadjusted" {
61144 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v4i32")]
61145 fn _vshiftins_v4i32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t;
61146 }
61147 unsafe { _vshiftins_v4i32(a, b, c) }
61148}
61149#[doc = "Shift Right and Insert (immediate)"]
61150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i16)"]
61151#[inline]
61152#[target_feature(enable = "neon")]
61153#[cfg(target_arch = "arm")]
61154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61155#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61156fn vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
61157 unsafe extern "unadjusted" {
61158 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i16")]
61159 fn _vshiftins_v8i16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t;
61160 }
61161 unsafe { _vshiftins_v8i16(a, b, c) }
61162}
61163#[doc = "Shift Right and Insert (immediate)"]
61164#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftins_v8i8)"]
61165#[inline]
61166#[target_feature(enable = "neon")]
61167#[cfg(target_arch = "arm")]
61168#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61169#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
61170fn vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
61171 unsafe extern "unadjusted" {
61172 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftins.v8i8")]
61173 fn _vshiftins_v8i8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
61174 }
61175 unsafe { _vshiftins_v8i8(a, b, c) }
61176}
61177#[doc = "Shift left"]
61178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
61179#[inline]
61180#[target_feature(enable = "neon")]
61181#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61182#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61183#[cfg_attr(
61184 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61185 assert_instr(shl, N = 2)
61186)]
61187#[rustc_legacy_const_generics(1)]
61188#[cfg_attr(
61189 not(target_arch = "arm"),
61190 stable(feature = "neon_intrinsics", since = "1.59.0")
61191)]
61192#[cfg_attr(
61193 target_arch = "arm",
61194 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61195)]
61196pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
61197 static_assert_uimm_bits!(N, 3);
61198 unsafe { simd_shl(a, vdup_n_s8(N as _)) }
61199}
61200#[doc = "Shift left"]
61201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
61202#[inline]
61203#[target_feature(enable = "neon")]
61204#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61205#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61206#[cfg_attr(
61207 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61208 assert_instr(shl, N = 2)
61209)]
61210#[rustc_legacy_const_generics(1)]
61211#[cfg_attr(
61212 not(target_arch = "arm"),
61213 stable(feature = "neon_intrinsics", since = "1.59.0")
61214)]
61215#[cfg_attr(
61216 target_arch = "arm",
61217 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61218)]
61219pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
61220 static_assert_uimm_bits!(N, 3);
61221 unsafe { simd_shl(a, vdupq_n_s8(N as _)) }
61222}
61223#[doc = "Shift left"]
61224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
61225#[inline]
61226#[target_feature(enable = "neon")]
61227#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61228#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61229#[cfg_attr(
61230 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61231 assert_instr(shl, N = 2)
61232)]
61233#[rustc_legacy_const_generics(1)]
61234#[cfg_attr(
61235 not(target_arch = "arm"),
61236 stable(feature = "neon_intrinsics", since = "1.59.0")
61237)]
61238#[cfg_attr(
61239 target_arch = "arm",
61240 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61241)]
61242pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
61243 static_assert_uimm_bits!(N, 4);
61244 unsafe { simd_shl(a, vdup_n_s16(N as _)) }
61245}
61246#[doc = "Shift left"]
61247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
61248#[inline]
61249#[target_feature(enable = "neon")]
61250#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61251#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61252#[cfg_attr(
61253 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61254 assert_instr(shl, N = 2)
61255)]
61256#[rustc_legacy_const_generics(1)]
61257#[cfg_attr(
61258 not(target_arch = "arm"),
61259 stable(feature = "neon_intrinsics", since = "1.59.0")
61260)]
61261#[cfg_attr(
61262 target_arch = "arm",
61263 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61264)]
61265pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
61266 static_assert_uimm_bits!(N, 4);
61267 unsafe { simd_shl(a, vdupq_n_s16(N as _)) }
61268}
61269#[doc = "Shift left"]
61270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
61271#[inline]
61272#[target_feature(enable = "neon")]
61273#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61274#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61275#[cfg_attr(
61276 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61277 assert_instr(shl, N = 2)
61278)]
61279#[rustc_legacy_const_generics(1)]
61280#[cfg_attr(
61281 not(target_arch = "arm"),
61282 stable(feature = "neon_intrinsics", since = "1.59.0")
61283)]
61284#[cfg_attr(
61285 target_arch = "arm",
61286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61287)]
61288pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
61289 static_assert_uimm_bits!(N, 5);
61290 unsafe { simd_shl(a, vdup_n_s32(N as _)) }
61291}
61292#[doc = "Shift left"]
61293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
61294#[inline]
61295#[target_feature(enable = "neon")]
61296#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61297#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61298#[cfg_attr(
61299 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61300 assert_instr(shl, N = 2)
61301)]
61302#[rustc_legacy_const_generics(1)]
61303#[cfg_attr(
61304 not(target_arch = "arm"),
61305 stable(feature = "neon_intrinsics", since = "1.59.0")
61306)]
61307#[cfg_attr(
61308 target_arch = "arm",
61309 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61310)]
61311pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
61312 static_assert_uimm_bits!(N, 5);
61313 unsafe { simd_shl(a, vdupq_n_s32(N as _)) }
61314}
61315#[doc = "Shift left"]
61316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
61317#[inline]
61318#[target_feature(enable = "neon")]
61319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61320#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61321#[cfg_attr(
61322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61323 assert_instr(shl, N = 2)
61324)]
61325#[rustc_legacy_const_generics(1)]
61326#[cfg_attr(
61327 not(target_arch = "arm"),
61328 stable(feature = "neon_intrinsics", since = "1.59.0")
61329)]
61330#[cfg_attr(
61331 target_arch = "arm",
61332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61333)]
61334pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
61335 static_assert_uimm_bits!(N, 6);
61336 unsafe { simd_shl(a, vdup_n_s64(N as _)) }
61337}
61338#[doc = "Shift left"]
61339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
61340#[inline]
61341#[target_feature(enable = "neon")]
61342#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61343#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61344#[cfg_attr(
61345 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61346 assert_instr(shl, N = 2)
61347)]
61348#[rustc_legacy_const_generics(1)]
61349#[cfg_attr(
61350 not(target_arch = "arm"),
61351 stable(feature = "neon_intrinsics", since = "1.59.0")
61352)]
61353#[cfg_attr(
61354 target_arch = "arm",
61355 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61356)]
61357pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
61358 static_assert_uimm_bits!(N, 6);
61359 unsafe { simd_shl(a, vdupq_n_s64(N as _)) }
61360}
61361#[doc = "Shift left"]
61362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
61363#[inline]
61364#[target_feature(enable = "neon")]
61365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61366#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61367#[cfg_attr(
61368 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61369 assert_instr(shl, N = 2)
61370)]
61371#[rustc_legacy_const_generics(1)]
61372#[cfg_attr(
61373 not(target_arch = "arm"),
61374 stable(feature = "neon_intrinsics", since = "1.59.0")
61375)]
61376#[cfg_attr(
61377 target_arch = "arm",
61378 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61379)]
61380pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
61381 static_assert_uimm_bits!(N, 3);
61382 unsafe { simd_shl(a, vdup_n_u8(N as _)) }
61383}
61384#[doc = "Shift left"]
61385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
61386#[inline]
61387#[target_feature(enable = "neon")]
61388#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61389#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61390#[cfg_attr(
61391 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61392 assert_instr(shl, N = 2)
61393)]
61394#[rustc_legacy_const_generics(1)]
61395#[cfg_attr(
61396 not(target_arch = "arm"),
61397 stable(feature = "neon_intrinsics", since = "1.59.0")
61398)]
61399#[cfg_attr(
61400 target_arch = "arm",
61401 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61402)]
61403pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
61404 static_assert_uimm_bits!(N, 3);
61405 unsafe { simd_shl(a, vdupq_n_u8(N as _)) }
61406}
61407#[doc = "Shift left"]
61408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
61409#[inline]
61410#[target_feature(enable = "neon")]
61411#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61412#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61413#[cfg_attr(
61414 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61415 assert_instr(shl, N = 2)
61416)]
61417#[rustc_legacy_const_generics(1)]
61418#[cfg_attr(
61419 not(target_arch = "arm"),
61420 stable(feature = "neon_intrinsics", since = "1.59.0")
61421)]
61422#[cfg_attr(
61423 target_arch = "arm",
61424 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61425)]
61426pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
61427 static_assert_uimm_bits!(N, 4);
61428 unsafe { simd_shl(a, vdup_n_u16(N as _)) }
61429}
61430#[doc = "Shift left"]
61431#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
61432#[inline]
61433#[target_feature(enable = "neon")]
61434#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61435#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61436#[cfg_attr(
61437 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61438 assert_instr(shl, N = 2)
61439)]
61440#[rustc_legacy_const_generics(1)]
61441#[cfg_attr(
61442 not(target_arch = "arm"),
61443 stable(feature = "neon_intrinsics", since = "1.59.0")
61444)]
61445#[cfg_attr(
61446 target_arch = "arm",
61447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61448)]
61449pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
61450 static_assert_uimm_bits!(N, 4);
61451 unsafe { simd_shl(a, vdupq_n_u16(N as _)) }
61452}
61453#[doc = "Shift left"]
61454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
61455#[inline]
61456#[target_feature(enable = "neon")]
61457#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61458#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61459#[cfg_attr(
61460 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61461 assert_instr(shl, N = 2)
61462)]
61463#[rustc_legacy_const_generics(1)]
61464#[cfg_attr(
61465 not(target_arch = "arm"),
61466 stable(feature = "neon_intrinsics", since = "1.59.0")
61467)]
61468#[cfg_attr(
61469 target_arch = "arm",
61470 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61471)]
61472pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
61473 static_assert_uimm_bits!(N, 5);
61474 unsafe { simd_shl(a, vdup_n_u32(N as _)) }
61475}
61476#[doc = "Shift left"]
61477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
61478#[inline]
61479#[target_feature(enable = "neon")]
61480#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61481#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61482#[cfg_attr(
61483 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61484 assert_instr(shl, N = 2)
61485)]
61486#[rustc_legacy_const_generics(1)]
61487#[cfg_attr(
61488 not(target_arch = "arm"),
61489 stable(feature = "neon_intrinsics", since = "1.59.0")
61490)]
61491#[cfg_attr(
61492 target_arch = "arm",
61493 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61494)]
61495pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
61496 static_assert_uimm_bits!(N, 5);
61497 unsafe { simd_shl(a, vdupq_n_u32(N as _)) }
61498}
61499#[doc = "Shift left"]
61500#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
61501#[inline]
61502#[target_feature(enable = "neon")]
61503#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61504#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61505#[cfg_attr(
61506 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61507 assert_instr(shl, N = 2)
61508)]
61509#[rustc_legacy_const_generics(1)]
61510#[cfg_attr(
61511 not(target_arch = "arm"),
61512 stable(feature = "neon_intrinsics", since = "1.59.0")
61513)]
61514#[cfg_attr(
61515 target_arch = "arm",
61516 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61517)]
61518pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
61519 static_assert_uimm_bits!(N, 6);
61520 unsafe { simd_shl(a, vdup_n_u64(N as _)) }
61521}
61522#[doc = "Shift left"]
61523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
61524#[inline]
61525#[target_feature(enable = "neon")]
61526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
61528#[cfg_attr(
61529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61530 assert_instr(shl, N = 2)
61531)]
61532#[rustc_legacy_const_generics(1)]
61533#[cfg_attr(
61534 not(target_arch = "arm"),
61535 stable(feature = "neon_intrinsics", since = "1.59.0")
61536)]
61537#[cfg_attr(
61538 target_arch = "arm",
61539 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61540)]
61541pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
61542 static_assert_uimm_bits!(N, 6);
61543 unsafe { simd_shl(a, vdupq_n_u64(N as _)) }
61544}
61545#[doc = "Signed Shift left"]
61546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
61547#[inline]
61548#[target_feature(enable = "neon")]
61549#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61550#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61551#[cfg_attr(
61552 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61553 assert_instr(sshl)
61554)]
61555#[cfg_attr(
61556 not(target_arch = "arm"),
61557 stable(feature = "neon_intrinsics", since = "1.59.0")
61558)]
61559#[cfg_attr(
61560 target_arch = "arm",
61561 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61562)]
61563pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
61564 unsafe extern "unadjusted" {
61565 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")]
61566 #[cfg_attr(
61567 any(target_arch = "aarch64", target_arch = "arm64ec"),
61568 link_name = "llvm.aarch64.neon.sshl.v8i8"
61569 )]
61570 fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
61571 }
61572 unsafe { _vshl_s8(a, b) }
61573}
61574#[doc = "Signed Shift left"]
61575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
61576#[inline]
61577#[target_feature(enable = "neon")]
61578#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61579#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61580#[cfg_attr(
61581 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61582 assert_instr(sshl)
61583)]
61584#[cfg_attr(
61585 not(target_arch = "arm"),
61586 stable(feature = "neon_intrinsics", since = "1.59.0")
61587)]
61588#[cfg_attr(
61589 target_arch = "arm",
61590 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61591)]
61592pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
61593 unsafe extern "unadjusted" {
61594 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")]
61595 #[cfg_attr(
61596 any(target_arch = "aarch64", target_arch = "arm64ec"),
61597 link_name = "llvm.aarch64.neon.sshl.v16i8"
61598 )]
61599 fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
61600 }
61601 unsafe { _vshlq_s8(a, b) }
61602}
61603#[doc = "Signed Shift left"]
61604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
61605#[inline]
61606#[target_feature(enable = "neon")]
61607#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61608#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61609#[cfg_attr(
61610 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61611 assert_instr(sshl)
61612)]
61613#[cfg_attr(
61614 not(target_arch = "arm"),
61615 stable(feature = "neon_intrinsics", since = "1.59.0")
61616)]
61617#[cfg_attr(
61618 target_arch = "arm",
61619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61620)]
61621pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
61622 unsafe extern "unadjusted" {
61623 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")]
61624 #[cfg_attr(
61625 any(target_arch = "aarch64", target_arch = "arm64ec"),
61626 link_name = "llvm.aarch64.neon.sshl.v4i16"
61627 )]
61628 fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
61629 }
61630 unsafe { _vshl_s16(a, b) }
61631}
61632#[doc = "Signed Shift left"]
61633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
61634#[inline]
61635#[target_feature(enable = "neon")]
61636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61638#[cfg_attr(
61639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61640 assert_instr(sshl)
61641)]
61642#[cfg_attr(
61643 not(target_arch = "arm"),
61644 stable(feature = "neon_intrinsics", since = "1.59.0")
61645)]
61646#[cfg_attr(
61647 target_arch = "arm",
61648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61649)]
61650pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
61651 unsafe extern "unadjusted" {
61652 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")]
61653 #[cfg_attr(
61654 any(target_arch = "aarch64", target_arch = "arm64ec"),
61655 link_name = "llvm.aarch64.neon.sshl.v8i16"
61656 )]
61657 fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
61658 }
61659 unsafe { _vshlq_s16(a, b) }
61660}
61661#[doc = "Signed Shift left"]
61662#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
61663#[inline]
61664#[target_feature(enable = "neon")]
61665#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61666#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61667#[cfg_attr(
61668 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61669 assert_instr(sshl)
61670)]
61671#[cfg_attr(
61672 not(target_arch = "arm"),
61673 stable(feature = "neon_intrinsics", since = "1.59.0")
61674)]
61675#[cfg_attr(
61676 target_arch = "arm",
61677 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61678)]
61679pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
61680 unsafe extern "unadjusted" {
61681 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")]
61682 #[cfg_attr(
61683 any(target_arch = "aarch64", target_arch = "arm64ec"),
61684 link_name = "llvm.aarch64.neon.sshl.v2i32"
61685 )]
61686 fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
61687 }
61688 unsafe { _vshl_s32(a, b) }
61689}
61690#[doc = "Signed Shift left"]
61691#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
61692#[inline]
61693#[target_feature(enable = "neon")]
61694#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61695#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61696#[cfg_attr(
61697 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61698 assert_instr(sshl)
61699)]
61700#[cfg_attr(
61701 not(target_arch = "arm"),
61702 stable(feature = "neon_intrinsics", since = "1.59.0")
61703)]
61704#[cfg_attr(
61705 target_arch = "arm",
61706 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61707)]
61708pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
61709 unsafe extern "unadjusted" {
61710 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")]
61711 #[cfg_attr(
61712 any(target_arch = "aarch64", target_arch = "arm64ec"),
61713 link_name = "llvm.aarch64.neon.sshl.v4i32"
61714 )]
61715 fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
61716 }
61717 unsafe { _vshlq_s32(a, b) }
61718}
61719#[doc = "Signed Shift left"]
61720#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
61721#[inline]
61722#[target_feature(enable = "neon")]
61723#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61724#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61725#[cfg_attr(
61726 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61727 assert_instr(sshl)
61728)]
61729#[cfg_attr(
61730 not(target_arch = "arm"),
61731 stable(feature = "neon_intrinsics", since = "1.59.0")
61732)]
61733#[cfg_attr(
61734 target_arch = "arm",
61735 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61736)]
61737pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
61738 unsafe extern "unadjusted" {
61739 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")]
61740 #[cfg_attr(
61741 any(target_arch = "aarch64", target_arch = "arm64ec"),
61742 link_name = "llvm.aarch64.neon.sshl.v1i64"
61743 )]
61744 fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t;
61745 }
61746 unsafe { _vshl_s64(a, b) }
61747}
61748#[doc = "Signed Shift left"]
61749#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
61750#[inline]
61751#[target_feature(enable = "neon")]
61752#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61753#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61754#[cfg_attr(
61755 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61756 assert_instr(sshl)
61757)]
61758#[cfg_attr(
61759 not(target_arch = "arm"),
61760 stable(feature = "neon_intrinsics", since = "1.59.0")
61761)]
61762#[cfg_attr(
61763 target_arch = "arm",
61764 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61765)]
61766pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
61767 unsafe extern "unadjusted" {
61768 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")]
61769 #[cfg_attr(
61770 any(target_arch = "aarch64", target_arch = "arm64ec"),
61771 link_name = "llvm.aarch64.neon.sshl.v2i64"
61772 )]
61773 fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t;
61774 }
61775 unsafe { _vshlq_s64(a, b) }
61776}
61777#[doc = "Unsigned Shift left"]
61778#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
61779#[inline]
61780#[target_feature(enable = "neon")]
61781#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61783#[cfg_attr(
61784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61785 assert_instr(ushl)
61786)]
61787#[cfg_attr(
61788 not(target_arch = "arm"),
61789 stable(feature = "neon_intrinsics", since = "1.59.0")
61790)]
61791#[cfg_attr(
61792 target_arch = "arm",
61793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61794)]
61795pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
61796 unsafe extern "unadjusted" {
61797 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")]
61798 #[cfg_attr(
61799 any(target_arch = "aarch64", target_arch = "arm64ec"),
61800 link_name = "llvm.aarch64.neon.ushl.v8i8"
61801 )]
61802 fn _vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t;
61803 }
61804 unsafe { _vshl_u8(a, b) }
61805}
61806#[doc = "Unsigned Shift left"]
61807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
61808#[inline]
61809#[target_feature(enable = "neon")]
61810#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61811#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61812#[cfg_attr(
61813 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61814 assert_instr(ushl)
61815)]
61816#[cfg_attr(
61817 not(target_arch = "arm"),
61818 stable(feature = "neon_intrinsics", since = "1.59.0")
61819)]
61820#[cfg_attr(
61821 target_arch = "arm",
61822 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61823)]
61824pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
61825 unsafe extern "unadjusted" {
61826 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")]
61827 #[cfg_attr(
61828 any(target_arch = "aarch64", target_arch = "arm64ec"),
61829 link_name = "llvm.aarch64.neon.ushl.v16i8"
61830 )]
61831 fn _vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t;
61832 }
61833 unsafe { _vshlq_u8(a, b) }
61834}
61835#[doc = "Unsigned Shift left"]
61836#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
61837#[inline]
61838#[target_feature(enable = "neon")]
61839#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61840#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61841#[cfg_attr(
61842 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61843 assert_instr(ushl)
61844)]
61845#[cfg_attr(
61846 not(target_arch = "arm"),
61847 stable(feature = "neon_intrinsics", since = "1.59.0")
61848)]
61849#[cfg_attr(
61850 target_arch = "arm",
61851 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61852)]
61853pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
61854 unsafe extern "unadjusted" {
61855 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")]
61856 #[cfg_attr(
61857 any(target_arch = "aarch64", target_arch = "arm64ec"),
61858 link_name = "llvm.aarch64.neon.ushl.v4i16"
61859 )]
61860 fn _vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t;
61861 }
61862 unsafe { _vshl_u16(a, b) }
61863}
61864#[doc = "Unsigned Shift left"]
61865#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
61866#[inline]
61867#[target_feature(enable = "neon")]
61868#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61869#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61870#[cfg_attr(
61871 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61872 assert_instr(ushl)
61873)]
61874#[cfg_attr(
61875 not(target_arch = "arm"),
61876 stable(feature = "neon_intrinsics", since = "1.59.0")
61877)]
61878#[cfg_attr(
61879 target_arch = "arm",
61880 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61881)]
61882pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
61883 unsafe extern "unadjusted" {
61884 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")]
61885 #[cfg_attr(
61886 any(target_arch = "aarch64", target_arch = "arm64ec"),
61887 link_name = "llvm.aarch64.neon.ushl.v8i16"
61888 )]
61889 fn _vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t;
61890 }
61891 unsafe { _vshlq_u16(a, b) }
61892}
61893#[doc = "Unsigned Shift left"]
61894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
61895#[inline]
61896#[target_feature(enable = "neon")]
61897#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61898#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61899#[cfg_attr(
61900 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61901 assert_instr(ushl)
61902)]
61903#[cfg_attr(
61904 not(target_arch = "arm"),
61905 stable(feature = "neon_intrinsics", since = "1.59.0")
61906)]
61907#[cfg_attr(
61908 target_arch = "arm",
61909 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61910)]
61911pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
61912 unsafe extern "unadjusted" {
61913 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")]
61914 #[cfg_attr(
61915 any(target_arch = "aarch64", target_arch = "arm64ec"),
61916 link_name = "llvm.aarch64.neon.ushl.v2i32"
61917 )]
61918 fn _vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t;
61919 }
61920 unsafe { _vshl_u32(a, b) }
61921}
61922#[doc = "Unsigned Shift left"]
61923#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
61924#[inline]
61925#[target_feature(enable = "neon")]
61926#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61927#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61928#[cfg_attr(
61929 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61930 assert_instr(ushl)
61931)]
61932#[cfg_attr(
61933 not(target_arch = "arm"),
61934 stable(feature = "neon_intrinsics", since = "1.59.0")
61935)]
61936#[cfg_attr(
61937 target_arch = "arm",
61938 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61939)]
61940pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
61941 unsafe extern "unadjusted" {
61942 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")]
61943 #[cfg_attr(
61944 any(target_arch = "aarch64", target_arch = "arm64ec"),
61945 link_name = "llvm.aarch64.neon.ushl.v4i32"
61946 )]
61947 fn _vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t;
61948 }
61949 unsafe { _vshlq_u32(a, b) }
61950}
61951#[doc = "Unsigned Shift left"]
61952#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
61953#[inline]
61954#[target_feature(enable = "neon")]
61955#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61956#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61957#[cfg_attr(
61958 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61959 assert_instr(ushl)
61960)]
61961#[cfg_attr(
61962 not(target_arch = "arm"),
61963 stable(feature = "neon_intrinsics", since = "1.59.0")
61964)]
61965#[cfg_attr(
61966 target_arch = "arm",
61967 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61968)]
61969pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
61970 unsafe extern "unadjusted" {
61971 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")]
61972 #[cfg_attr(
61973 any(target_arch = "aarch64", target_arch = "arm64ec"),
61974 link_name = "llvm.aarch64.neon.ushl.v1i64"
61975 )]
61976 fn _vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t;
61977 }
61978 unsafe { _vshl_u64(a, b) }
61979}
61980#[doc = "Unsigned Shift left"]
61981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
61982#[inline]
61983#[target_feature(enable = "neon")]
61984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
61985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
61986#[cfg_attr(
61987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
61988 assert_instr(ushl)
61989)]
61990#[cfg_attr(
61991 not(target_arch = "arm"),
61992 stable(feature = "neon_intrinsics", since = "1.59.0")
61993)]
61994#[cfg_attr(
61995 target_arch = "arm",
61996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
61997)]
61998pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
61999 unsafe extern "unadjusted" {
62000 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")]
62001 #[cfg_attr(
62002 any(target_arch = "aarch64", target_arch = "arm64ec"),
62003 link_name = "llvm.aarch64.neon.ushl.v2i64"
62004 )]
62005 fn _vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t;
62006 }
62007 unsafe { _vshlq_u64(a, b) }
62008}
62009#[doc = "Signed shift left long"]
62010#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
62011#[inline]
62012#[target_feature(enable = "neon")]
62013#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62014#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
62015#[cfg_attr(
62016 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62017 assert_instr(sshll, N = 2)
62018)]
62019#[rustc_legacy_const_generics(1)]
62020#[cfg_attr(
62021 not(target_arch = "arm"),
62022 stable(feature = "neon_intrinsics", since = "1.59.0")
62023)]
62024#[cfg_attr(
62025 target_arch = "arm",
62026 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62027)]
62028pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
62029 static_assert!(N >= 0 && N <= 16);
62030 unsafe { simd_shl(simd_cast(a), vdupq_n_s32(N as _)) }
62031}
62032#[doc = "Signed shift left long"]
62033#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
62034#[inline]
62035#[target_feature(enable = "neon")]
62036#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62037#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
62038#[cfg_attr(
62039 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62040 assert_instr(sshll, N = 2)
62041)]
62042#[rustc_legacy_const_generics(1)]
62043#[cfg_attr(
62044 not(target_arch = "arm"),
62045 stable(feature = "neon_intrinsics", since = "1.59.0")
62046)]
62047#[cfg_attr(
62048 target_arch = "arm",
62049 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62050)]
62051pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
62052 static_assert!(N >= 0 && N <= 32);
62053 unsafe { simd_shl(simd_cast(a), vdupq_n_s64(N as _)) }
62054}
62055#[doc = "Signed shift left long"]
62056#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
62057#[inline]
62058#[target_feature(enable = "neon")]
62059#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62060#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
62061#[cfg_attr(
62062 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62063 assert_instr(sshll, N = 2)
62064)]
62065#[rustc_legacy_const_generics(1)]
62066#[cfg_attr(
62067 not(target_arch = "arm"),
62068 stable(feature = "neon_intrinsics", since = "1.59.0")
62069)]
62070#[cfg_attr(
62071 target_arch = "arm",
62072 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62073)]
62074pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
62075 static_assert!(N >= 0 && N <= 8);
62076 unsafe { simd_shl(simd_cast(a), vdupq_n_s16(N as _)) }
62077}
62078#[doc = "Signed shift left long"]
62079#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
62080#[inline]
62081#[target_feature(enable = "neon")]
62082#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62083#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
62084#[cfg_attr(
62085 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62086 assert_instr(ushll, N = 2)
62087)]
62088#[rustc_legacy_const_generics(1)]
62089#[cfg_attr(
62090 not(target_arch = "arm"),
62091 stable(feature = "neon_intrinsics", since = "1.59.0")
62092)]
62093#[cfg_attr(
62094 target_arch = "arm",
62095 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62096)]
62097pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
62098 static_assert!(N >= 0 && N <= 16);
62099 unsafe { simd_shl(simd_cast(a), vdupq_n_u32(N as _)) }
62100}
62101#[doc = "Signed shift left long"]
62102#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
62103#[inline]
62104#[target_feature(enable = "neon")]
62105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62106#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
62107#[cfg_attr(
62108 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62109 assert_instr(ushll, N = 2)
62110)]
62111#[rustc_legacy_const_generics(1)]
62112#[cfg_attr(
62113 not(target_arch = "arm"),
62114 stable(feature = "neon_intrinsics", since = "1.59.0")
62115)]
62116#[cfg_attr(
62117 target_arch = "arm",
62118 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62119)]
62120pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
62121 static_assert!(N >= 0 && N <= 32);
62122 unsafe { simd_shl(simd_cast(a), vdupq_n_u64(N as _)) }
62123}
62124#[doc = "Signed shift left long"]
62125#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
62126#[inline]
62127#[target_feature(enable = "neon")]
62128#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62129#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
62130#[cfg_attr(
62131 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62132 assert_instr(ushll, N = 2)
62133)]
62134#[rustc_legacy_const_generics(1)]
62135#[cfg_attr(
62136 not(target_arch = "arm"),
62137 stable(feature = "neon_intrinsics", since = "1.59.0")
62138)]
62139#[cfg_attr(
62140 target_arch = "arm",
62141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62142)]
62143pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
62144 static_assert!(N >= 0 && N <= 8);
62145 unsafe { simd_shl(simd_cast(a), vdupq_n_u16(N as _)) }
62146}
62147#[doc = "Shift right"]
62148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
62149#[inline]
62150#[target_feature(enable = "neon")]
62151#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62152#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62153#[cfg_attr(
62154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62155 assert_instr(sshr, N = 2)
62156)]
62157#[rustc_legacy_const_generics(1)]
62158#[cfg_attr(
62159 not(target_arch = "arm"),
62160 stable(feature = "neon_intrinsics", since = "1.59.0")
62161)]
62162#[cfg_attr(
62163 target_arch = "arm",
62164 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62165)]
62166pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
62167 static_assert!(N >= 1 && N <= 8);
62168 let n: i32 = if N == 8 { 7 } else { N };
62169 unsafe { simd_shr(a, vdup_n_s8(n as _)) }
62170}
62171#[doc = "Shift right"]
62172#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
62173#[inline]
62174#[target_feature(enable = "neon")]
62175#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62176#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
62177#[cfg_attr(
62178 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62179 assert_instr(sshr, N = 2)
62180)]
62181#[rustc_legacy_const_generics(1)]
62182#[cfg_attr(
62183 not(target_arch = "arm"),
62184 stable(feature = "neon_intrinsics", since = "1.59.0")
62185)]
62186#[cfg_attr(
62187 target_arch = "arm",
62188 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62189)]
62190pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
62191 static_assert!(N >= 1 && N <= 8);
62192 let n: i32 = if N == 8 { 7 } else { N };
62193 unsafe { simd_shr(a, vdupq_n_s8(n as _)) }
62194}
62195#[doc = "Shift right"]
62196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
62197#[inline]
62198#[target_feature(enable = "neon")]
62199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62200#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62201#[cfg_attr(
62202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62203 assert_instr(sshr, N = 2)
62204)]
62205#[rustc_legacy_const_generics(1)]
62206#[cfg_attr(
62207 not(target_arch = "arm"),
62208 stable(feature = "neon_intrinsics", since = "1.59.0")
62209)]
62210#[cfg_attr(
62211 target_arch = "arm",
62212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62213)]
62214pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
62215 static_assert!(N >= 1 && N <= 16);
62216 let n: i32 = if N == 16 { 15 } else { N };
62217 unsafe { simd_shr(a, vdup_n_s16(n as _)) }
62218}
62219#[doc = "Shift right"]
62220#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
62221#[inline]
62222#[target_feature(enable = "neon")]
62223#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62224#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
62225#[cfg_attr(
62226 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62227 assert_instr(sshr, N = 2)
62228)]
62229#[rustc_legacy_const_generics(1)]
62230#[cfg_attr(
62231 not(target_arch = "arm"),
62232 stable(feature = "neon_intrinsics", since = "1.59.0")
62233)]
62234#[cfg_attr(
62235 target_arch = "arm",
62236 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62237)]
62238pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
62239 static_assert!(N >= 1 && N <= 16);
62240 let n: i32 = if N == 16 { 15 } else { N };
62241 unsafe { simd_shr(a, vdupq_n_s16(n as _)) }
62242}
62243#[doc = "Shift right"]
62244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
62245#[inline]
62246#[target_feature(enable = "neon")]
62247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62248#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62249#[cfg_attr(
62250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62251 assert_instr(sshr, N = 2)
62252)]
62253#[rustc_legacy_const_generics(1)]
62254#[cfg_attr(
62255 not(target_arch = "arm"),
62256 stable(feature = "neon_intrinsics", since = "1.59.0")
62257)]
62258#[cfg_attr(
62259 target_arch = "arm",
62260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62261)]
62262pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
62263 static_assert!(N >= 1 && N <= 32);
62264 let n: i32 = if N == 32 { 31 } else { N };
62265 unsafe { simd_shr(a, vdup_n_s32(n as _)) }
62266}
62267#[doc = "Shift right"]
62268#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
62269#[inline]
62270#[target_feature(enable = "neon")]
62271#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62272#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
62273#[cfg_attr(
62274 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62275 assert_instr(sshr, N = 2)
62276)]
62277#[rustc_legacy_const_generics(1)]
62278#[cfg_attr(
62279 not(target_arch = "arm"),
62280 stable(feature = "neon_intrinsics", since = "1.59.0")
62281)]
62282#[cfg_attr(
62283 target_arch = "arm",
62284 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62285)]
62286pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
62287 static_assert!(N >= 1 && N <= 32);
62288 let n: i32 = if N == 32 { 31 } else { N };
62289 unsafe { simd_shr(a, vdupq_n_s32(n as _)) }
62290}
62291#[doc = "Shift right"]
62292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
62293#[inline]
62294#[target_feature(enable = "neon")]
62295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62296#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62297#[cfg_attr(
62298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62299 assert_instr(sshr, N = 2)
62300)]
62301#[rustc_legacy_const_generics(1)]
62302#[cfg_attr(
62303 not(target_arch = "arm"),
62304 stable(feature = "neon_intrinsics", since = "1.59.0")
62305)]
62306#[cfg_attr(
62307 target_arch = "arm",
62308 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62309)]
62310pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
62311 static_assert!(N >= 1 && N <= 64);
62312 let n: i32 = if N == 64 { 63 } else { N };
62313 unsafe { simd_shr(a, vdup_n_s64(n as _)) }
62314}
62315#[doc = "Shift right"]
62316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
62317#[inline]
62318#[target_feature(enable = "neon")]
62319#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62320#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
62321#[cfg_attr(
62322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62323 assert_instr(sshr, N = 2)
62324)]
62325#[rustc_legacy_const_generics(1)]
62326#[cfg_attr(
62327 not(target_arch = "arm"),
62328 stable(feature = "neon_intrinsics", since = "1.59.0")
62329)]
62330#[cfg_attr(
62331 target_arch = "arm",
62332 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62333)]
62334pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
62335 static_assert!(N >= 1 && N <= 64);
62336 let n: i32 = if N == 64 { 63 } else { N };
62337 unsafe { simd_shr(a, vdupq_n_s64(n as _)) }
62338}
62339#[doc = "Shift right"]
62340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
62341#[inline]
62342#[target_feature(enable = "neon")]
62343#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62344#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62345#[cfg_attr(
62346 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62347 assert_instr(ushr, N = 2)
62348)]
62349#[rustc_legacy_const_generics(1)]
62350#[cfg_attr(
62351 not(target_arch = "arm"),
62352 stable(feature = "neon_intrinsics", since = "1.59.0")
62353)]
62354#[cfg_attr(
62355 target_arch = "arm",
62356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62357)]
62358pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
62359 static_assert!(N >= 1 && N <= 8);
62360 let n: i32 = if N == 8 {
62361 return vdup_n_u8(0);
62362 } else {
62363 N
62364 };
62365 unsafe { simd_shr(a, vdup_n_u8(n as _)) }
62366}
62367#[doc = "Shift right"]
62368#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
62369#[inline]
62370#[target_feature(enable = "neon")]
62371#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62372#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
62373#[cfg_attr(
62374 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62375 assert_instr(ushr, N = 2)
62376)]
62377#[rustc_legacy_const_generics(1)]
62378#[cfg_attr(
62379 not(target_arch = "arm"),
62380 stable(feature = "neon_intrinsics", since = "1.59.0")
62381)]
62382#[cfg_attr(
62383 target_arch = "arm",
62384 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62385)]
62386pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
62387 static_assert!(N >= 1 && N <= 8);
62388 let n: i32 = if N == 8 {
62389 return vdupq_n_u8(0);
62390 } else {
62391 N
62392 };
62393 unsafe { simd_shr(a, vdupq_n_u8(n as _)) }
62394}
62395#[doc = "Shift right"]
62396#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
62397#[inline]
62398#[target_feature(enable = "neon")]
62399#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62400#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62401#[cfg_attr(
62402 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62403 assert_instr(ushr, N = 2)
62404)]
62405#[rustc_legacy_const_generics(1)]
62406#[cfg_attr(
62407 not(target_arch = "arm"),
62408 stable(feature = "neon_intrinsics", since = "1.59.0")
62409)]
62410#[cfg_attr(
62411 target_arch = "arm",
62412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62413)]
62414pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
62415 static_assert!(N >= 1 && N <= 16);
62416 let n: i32 = if N == 16 {
62417 return vdup_n_u16(0);
62418 } else {
62419 N
62420 };
62421 unsafe { simd_shr(a, vdup_n_u16(n as _)) }
62422}
62423#[doc = "Shift right"]
62424#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
62425#[inline]
62426#[target_feature(enable = "neon")]
62427#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62428#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
62429#[cfg_attr(
62430 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62431 assert_instr(ushr, N = 2)
62432)]
62433#[rustc_legacy_const_generics(1)]
62434#[cfg_attr(
62435 not(target_arch = "arm"),
62436 stable(feature = "neon_intrinsics", since = "1.59.0")
62437)]
62438#[cfg_attr(
62439 target_arch = "arm",
62440 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62441)]
62442pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
62443 static_assert!(N >= 1 && N <= 16);
62444 let n: i32 = if N == 16 {
62445 return vdupq_n_u16(0);
62446 } else {
62447 N
62448 };
62449 unsafe { simd_shr(a, vdupq_n_u16(n as _)) }
62450}
62451#[doc = "Shift right"]
62452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
62453#[inline]
62454#[target_feature(enable = "neon")]
62455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62456#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62457#[cfg_attr(
62458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62459 assert_instr(ushr, N = 2)
62460)]
62461#[rustc_legacy_const_generics(1)]
62462#[cfg_attr(
62463 not(target_arch = "arm"),
62464 stable(feature = "neon_intrinsics", since = "1.59.0")
62465)]
62466#[cfg_attr(
62467 target_arch = "arm",
62468 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62469)]
62470pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
62471 static_assert!(N >= 1 && N <= 32);
62472 let n: i32 = if N == 32 {
62473 return vdup_n_u32(0);
62474 } else {
62475 N
62476 };
62477 unsafe { simd_shr(a, vdup_n_u32(n as _)) }
62478}
62479#[doc = "Shift right"]
62480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
62481#[inline]
62482#[target_feature(enable = "neon")]
62483#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62484#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
62485#[cfg_attr(
62486 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62487 assert_instr(ushr, N = 2)
62488)]
62489#[rustc_legacy_const_generics(1)]
62490#[cfg_attr(
62491 not(target_arch = "arm"),
62492 stable(feature = "neon_intrinsics", since = "1.59.0")
62493)]
62494#[cfg_attr(
62495 target_arch = "arm",
62496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62497)]
62498pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
62499 static_assert!(N >= 1 && N <= 32);
62500 let n: i32 = if N == 32 {
62501 return vdupq_n_u32(0);
62502 } else {
62503 N
62504 };
62505 unsafe { simd_shr(a, vdupq_n_u32(n as _)) }
62506}
62507#[doc = "Shift right"]
62508#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
62509#[inline]
62510#[target_feature(enable = "neon")]
62511#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62512#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62513#[cfg_attr(
62514 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62515 assert_instr(ushr, N = 2)
62516)]
62517#[rustc_legacy_const_generics(1)]
62518#[cfg_attr(
62519 not(target_arch = "arm"),
62520 stable(feature = "neon_intrinsics", since = "1.59.0")
62521)]
62522#[cfg_attr(
62523 target_arch = "arm",
62524 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62525)]
62526pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
62527 static_assert!(N >= 1 && N <= 64);
62528 let n: i32 = if N == 64 {
62529 return vdup_n_u64(0);
62530 } else {
62531 N
62532 };
62533 unsafe { simd_shr(a, vdup_n_u64(n as _)) }
62534}
62535#[doc = "Shift right"]
62536#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
62537#[inline]
62538#[target_feature(enable = "neon")]
62539#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62540#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
62541#[cfg_attr(
62542 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62543 assert_instr(ushr, N = 2)
62544)]
62545#[rustc_legacy_const_generics(1)]
62546#[cfg_attr(
62547 not(target_arch = "arm"),
62548 stable(feature = "neon_intrinsics", since = "1.59.0")
62549)]
62550#[cfg_attr(
62551 target_arch = "arm",
62552 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62553)]
62554pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
62555 static_assert!(N >= 1 && N <= 64);
62556 let n: i32 = if N == 64 {
62557 return vdupq_n_u64(0);
62558 } else {
62559 N
62560 };
62561 unsafe { simd_shr(a, vdupq_n_u64(n as _)) }
62562}
62563#[doc = "Shift right narrow"]
62564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
62565#[inline]
62566#[target_feature(enable = "neon")]
62567#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62568#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
62569#[cfg_attr(
62570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62571 assert_instr(shrn, N = 2)
62572)]
62573#[rustc_legacy_const_generics(1)]
62574#[cfg_attr(
62575 not(target_arch = "arm"),
62576 stable(feature = "neon_intrinsics", since = "1.59.0")
62577)]
62578#[cfg_attr(
62579 target_arch = "arm",
62580 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62581)]
62582pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
62583 static_assert!(N >= 1 && N <= 8);
62584 unsafe { simd_cast(simd_shr(a, vdupq_n_s16(N as _))) }
62585}
62586#[doc = "Shift right narrow"]
62587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
62588#[inline]
62589#[target_feature(enable = "neon")]
62590#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
62592#[cfg_attr(
62593 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62594 assert_instr(shrn, N = 2)
62595)]
62596#[rustc_legacy_const_generics(1)]
62597#[cfg_attr(
62598 not(target_arch = "arm"),
62599 stable(feature = "neon_intrinsics", since = "1.59.0")
62600)]
62601#[cfg_attr(
62602 target_arch = "arm",
62603 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62604)]
62605pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
62606 static_assert!(N >= 1 && N <= 16);
62607 unsafe { simd_cast(simd_shr(a, vdupq_n_s32(N as _))) }
62608}
62609#[doc = "Shift right narrow"]
62610#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
62611#[inline]
62612#[target_feature(enable = "neon")]
62613#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62614#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
62615#[cfg_attr(
62616 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62617 assert_instr(shrn, N = 2)
62618)]
62619#[rustc_legacy_const_generics(1)]
62620#[cfg_attr(
62621 not(target_arch = "arm"),
62622 stable(feature = "neon_intrinsics", since = "1.59.0")
62623)]
62624#[cfg_attr(
62625 target_arch = "arm",
62626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62627)]
62628pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
62629 static_assert!(N >= 1 && N <= 32);
62630 unsafe { simd_cast(simd_shr(a, vdupq_n_s64(N as _))) }
62631}
62632#[doc = "Shift right narrow"]
62633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
62634#[inline]
62635#[target_feature(enable = "neon")]
62636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62637#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
62638#[cfg_attr(
62639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62640 assert_instr(shrn, N = 2)
62641)]
62642#[rustc_legacy_const_generics(1)]
62643#[cfg_attr(
62644 not(target_arch = "arm"),
62645 stable(feature = "neon_intrinsics", since = "1.59.0")
62646)]
62647#[cfg_attr(
62648 target_arch = "arm",
62649 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62650)]
62651pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
62652 static_assert!(N >= 1 && N <= 8);
62653 unsafe { simd_cast(simd_shr(a, vdupq_n_u16(N as _))) }
62654}
62655#[doc = "Shift right narrow"]
62656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
62657#[inline]
62658#[target_feature(enable = "neon")]
62659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62660#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
62661#[cfg_attr(
62662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62663 assert_instr(shrn, N = 2)
62664)]
62665#[rustc_legacy_const_generics(1)]
62666#[cfg_attr(
62667 not(target_arch = "arm"),
62668 stable(feature = "neon_intrinsics", since = "1.59.0")
62669)]
62670#[cfg_attr(
62671 target_arch = "arm",
62672 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62673)]
62674pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
62675 static_assert!(N >= 1 && N <= 16);
62676 unsafe { simd_cast(simd_shr(a, vdupq_n_u32(N as _))) }
62677}
62678#[doc = "Shift right narrow"]
62679#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
62680#[inline]
62681#[target_feature(enable = "neon")]
62682#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
62683#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
62684#[cfg_attr(
62685 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
62686 assert_instr(shrn, N = 2)
62687)]
62688#[rustc_legacy_const_generics(1)]
62689#[cfg_attr(
62690 not(target_arch = "arm"),
62691 stable(feature = "neon_intrinsics", since = "1.59.0")
62692)]
62693#[cfg_attr(
62694 target_arch = "arm",
62695 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
62696)]
62697pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
62698 static_assert!(N >= 1 && N <= 32);
62699 unsafe { simd_cast(simd_shr(a, vdupq_n_u64(N as _))) }
62700}
62701#[doc = "Shift Left and Insert (immediate)"]
62702#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
62703#[inline]
62704#[cfg(target_arch = "arm")]
62705#[target_feature(enable = "neon,v7")]
62706#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62707#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62708#[rustc_legacy_const_generics(2)]
62709pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
62710 static_assert_uimm_bits!(N, 3);
62711 vshiftins_v8i8(a, b, int8x8_t::splat(N as i8))
62712}
62713#[doc = "Shift Left and Insert (immediate)"]
62714#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
62715#[inline]
62716#[cfg(target_arch = "arm")]
62717#[target_feature(enable = "neon,v7")]
62718#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62720#[rustc_legacy_const_generics(2)]
62721pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
62722 static_assert_uimm_bits!(N, 3);
62723 vshiftins_v16i8(a, b, int8x16_t::splat(N as i8))
62724}
62725#[doc = "Shift Left and Insert (immediate)"]
62726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
62727#[inline]
62728#[cfg(target_arch = "arm")]
62729#[target_feature(enable = "neon,v7")]
62730#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62731#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
62732#[rustc_legacy_const_generics(2)]
62733pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
62734 static_assert_uimm_bits!(N, 4);
62735 vshiftins_v4i16(a, b, int16x4_t::splat(N as i16))
62736}
62737#[doc = "Shift Left and Insert (immediate)"]
62738#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
62739#[inline]
62740#[cfg(target_arch = "arm")]
62741#[target_feature(enable = "neon,v7")]
62742#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62743#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
62744#[rustc_legacy_const_generics(2)]
62745pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
62746 static_assert_uimm_bits!(N, 4);
62747 vshiftins_v8i16(a, b, int16x8_t::splat(N as i16))
62748}
62749#[doc = "Shift Left and Insert (immediate)"]
62750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
62751#[inline]
62752#[cfg(target_arch = "arm")]
62753#[target_feature(enable = "neon,v7")]
62754#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62755#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
62756#[rustc_legacy_const_generics(2)]
62757pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
62758 static_assert!(N >= 0 && N <= 31);
62759 vshiftins_v2i32(a, b, int32x2_t::splat(N))
62760}
62761#[doc = "Shift Left and Insert (immediate)"]
62762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
62763#[inline]
62764#[cfg(target_arch = "arm")]
62765#[target_feature(enable = "neon,v7")]
62766#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62767#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
62768#[rustc_legacy_const_generics(2)]
62769pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
62770 static_assert!(N >= 0 && N <= 31);
62771 vshiftins_v4i32(a, b, int32x4_t::splat(N))
62772}
62773#[doc = "Shift Left and Insert (immediate)"]
62774#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
62775#[inline]
62776#[cfg(target_arch = "arm")]
62777#[target_feature(enable = "neon,v7")]
62778#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62779#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
62780#[rustc_legacy_const_generics(2)]
62781pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
62782 static_assert!(N >= 0 && N <= 63);
62783 vshiftins_v1i64(a, b, int64x1_t::splat(N as i64))
62784}
62785#[doc = "Shift Left and Insert (immediate)"]
62786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
62787#[inline]
62788#[cfg(target_arch = "arm")]
62789#[target_feature(enable = "neon,v7")]
62790#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62791#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
62792#[rustc_legacy_const_generics(2)]
62793pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
62794 static_assert!(N >= 0 && N <= 63);
62795 vshiftins_v2i64(a, b, int64x2_t::splat(N as i64))
62796}
62797#[doc = "Shift Left and Insert (immediate)"]
62798#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
62799#[inline]
62800#[cfg(target_arch = "arm")]
62801#[target_feature(enable = "neon,v7")]
62802#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62803#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62804#[rustc_legacy_const_generics(2)]
62805pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
62806 static_assert_uimm_bits!(N, 3);
62807 unsafe {
62808 transmute(vshiftins_v8i8(
62809 transmute(a),
62810 transmute(b),
62811 int8x8_t::splat(N as i8),
62812 ))
62813 }
62814}
62815#[doc = "Shift Left and Insert (immediate)"]
62816#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
62817#[inline]
62818#[cfg(target_arch = "arm")]
62819#[target_feature(enable = "neon,v7")]
62820#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62821#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62822#[rustc_legacy_const_generics(2)]
62823pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
62824 static_assert_uimm_bits!(N, 3);
62825 unsafe {
62826 transmute(vshiftins_v16i8(
62827 transmute(a),
62828 transmute(b),
62829 int8x16_t::splat(N as i8),
62830 ))
62831 }
62832}
62833#[doc = "Shift Left and Insert (immediate)"]
62834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
62835#[inline]
62836#[cfg(target_arch = "arm")]
62837#[target_feature(enable = "neon,v7")]
62838#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62839#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
62840#[rustc_legacy_const_generics(2)]
62841pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
62842 static_assert_uimm_bits!(N, 4);
62843 unsafe {
62844 transmute(vshiftins_v4i16(
62845 transmute(a),
62846 transmute(b),
62847 int16x4_t::splat(N as i16),
62848 ))
62849 }
62850}
62851#[doc = "Shift Left and Insert (immediate)"]
62852#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
62853#[inline]
62854#[cfg(target_arch = "arm")]
62855#[target_feature(enable = "neon,v7")]
62856#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62857#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
62858#[rustc_legacy_const_generics(2)]
62859pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
62860 static_assert_uimm_bits!(N, 4);
62861 unsafe {
62862 transmute(vshiftins_v8i16(
62863 transmute(a),
62864 transmute(b),
62865 int16x8_t::splat(N as i16),
62866 ))
62867 }
62868}
62869#[doc = "Shift Left and Insert (immediate)"]
62870#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
62871#[inline]
62872#[cfg(target_arch = "arm")]
62873#[target_feature(enable = "neon,v7")]
62874#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62875#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
62876#[rustc_legacy_const_generics(2)]
62877pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
62878 static_assert!(N >= 0 && N <= 31);
62879 unsafe {
62880 transmute(vshiftins_v2i32(
62881 transmute(a),
62882 transmute(b),
62883 int32x2_t::splat(N),
62884 ))
62885 }
62886}
62887#[doc = "Shift Left and Insert (immediate)"]
62888#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
62889#[inline]
62890#[cfg(target_arch = "arm")]
62891#[target_feature(enable = "neon,v7")]
62892#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62893#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.32", N = 1))]
62894#[rustc_legacy_const_generics(2)]
62895pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
62896 static_assert!(N >= 0 && N <= 31);
62897 unsafe {
62898 transmute(vshiftins_v4i32(
62899 transmute(a),
62900 transmute(b),
62901 int32x4_t::splat(N),
62902 ))
62903 }
62904}
62905#[doc = "Shift Left and Insert (immediate)"]
62906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
62907#[inline]
62908#[cfg(target_arch = "arm")]
62909#[target_feature(enable = "neon,v7")]
62910#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62911#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
62912#[rustc_legacy_const_generics(2)]
62913pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
62914 static_assert!(N >= 0 && N <= 63);
62915 unsafe {
62916 transmute(vshiftins_v1i64(
62917 transmute(a),
62918 transmute(b),
62919 int64x1_t::splat(N as i64),
62920 ))
62921 }
62922}
62923#[doc = "Shift Left and Insert (immediate)"]
62924#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
62925#[inline]
62926#[cfg(target_arch = "arm")]
62927#[target_feature(enable = "neon,v7")]
62928#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62929#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.64", N = 1))]
62930#[rustc_legacy_const_generics(2)]
62931pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
62932 static_assert!(N >= 0 && N <= 63);
62933 unsafe {
62934 transmute(vshiftins_v2i64(
62935 transmute(a),
62936 transmute(b),
62937 int64x2_t::splat(N as i64),
62938 ))
62939 }
62940}
62941#[doc = "Shift Left and Insert (immediate)"]
62942#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
62943#[inline]
62944#[cfg(target_arch = "arm")]
62945#[target_feature(enable = "neon,v7")]
62946#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62947#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62948#[rustc_legacy_const_generics(2)]
62949pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
62950 static_assert_uimm_bits!(N, 3);
62951 unsafe {
62952 transmute(vshiftins_v8i8(
62953 transmute(a),
62954 transmute(b),
62955 int8x8_t::splat(N as i8),
62956 ))
62957 }
62958}
62959#[doc = "Shift Left and Insert (immediate)"]
62960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
62961#[inline]
62962#[cfg(target_arch = "arm")]
62963#[target_feature(enable = "neon,v7")]
62964#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62965#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.8", N = 1))]
62966#[rustc_legacy_const_generics(2)]
62967pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
62968 static_assert_uimm_bits!(N, 3);
62969 unsafe {
62970 transmute(vshiftins_v16i8(
62971 transmute(a),
62972 transmute(b),
62973 int8x16_t::splat(N as i8),
62974 ))
62975 }
62976}
62977#[doc = "Shift Left and Insert (immediate)"]
62978#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
62979#[inline]
62980#[cfg(target_arch = "arm")]
62981#[target_feature(enable = "neon,v7")]
62982#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
62983#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
62984#[rustc_legacy_const_generics(2)]
62985pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
62986 static_assert_uimm_bits!(N, 4);
62987 unsafe {
62988 transmute(vshiftins_v4i16(
62989 transmute(a),
62990 transmute(b),
62991 int16x4_t::splat(N as i16),
62992 ))
62993 }
62994}
62995#[doc = "Shift Left and Insert (immediate)"]
62996#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
62997#[inline]
62998#[cfg(target_arch = "arm")]
62999#[target_feature(enable = "neon,v7")]
63000#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63001#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsli.16", N = 1))]
63002#[rustc_legacy_const_generics(2)]
63003pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
63004 static_assert_uimm_bits!(N, 4);
63005 unsafe {
63006 transmute(vshiftins_v8i16(
63007 transmute(a),
63008 transmute(b),
63009 int16x8_t::splat(N as i16),
63010 ))
63011 }
63012}
63013#[doc = "Signed shift right and accumulate"]
63014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
63015#[inline]
63016#[target_feature(enable = "neon")]
63017#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63018#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63019#[cfg_attr(
63020 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63021 assert_instr(ssra, N = 2)
63022)]
63023#[rustc_legacy_const_generics(2)]
63024#[cfg_attr(
63025 not(target_arch = "arm"),
63026 stable(feature = "neon_intrinsics", since = "1.59.0")
63027)]
63028#[cfg_attr(
63029 target_arch = "arm",
63030 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63031)]
63032pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63033 static_assert!(N >= 1 && N <= 8);
63034 unsafe { simd_add(a, vshr_n_s8::<N>(b)) }
63035}
63036#[doc = "Signed shift right and accumulate"]
63037#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
63038#[inline]
63039#[target_feature(enable = "neon")]
63040#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63041#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63042#[cfg_attr(
63043 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63044 assert_instr(ssra, N = 2)
63045)]
63046#[rustc_legacy_const_generics(2)]
63047#[cfg_attr(
63048 not(target_arch = "arm"),
63049 stable(feature = "neon_intrinsics", since = "1.59.0")
63050)]
63051#[cfg_attr(
63052 target_arch = "arm",
63053 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63054)]
63055pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63056 static_assert!(N >= 1 && N <= 8);
63057 unsafe { simd_add(a, vshrq_n_s8::<N>(b)) }
63058}
63059#[doc = "Signed shift right and accumulate"]
63060#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
63061#[inline]
63062#[target_feature(enable = "neon")]
63063#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63064#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63065#[cfg_attr(
63066 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63067 assert_instr(ssra, N = 2)
63068)]
63069#[rustc_legacy_const_generics(2)]
63070#[cfg_attr(
63071 not(target_arch = "arm"),
63072 stable(feature = "neon_intrinsics", since = "1.59.0")
63073)]
63074#[cfg_attr(
63075 target_arch = "arm",
63076 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63077)]
63078pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63079 static_assert!(N >= 1 && N <= 16);
63080 unsafe { simd_add(a, vshr_n_s16::<N>(b)) }
63081}
63082#[doc = "Signed shift right and accumulate"]
63083#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
63084#[inline]
63085#[target_feature(enable = "neon")]
63086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63087#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63088#[cfg_attr(
63089 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63090 assert_instr(ssra, N = 2)
63091)]
63092#[rustc_legacy_const_generics(2)]
63093#[cfg_attr(
63094 not(target_arch = "arm"),
63095 stable(feature = "neon_intrinsics", since = "1.59.0")
63096)]
63097#[cfg_attr(
63098 target_arch = "arm",
63099 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63100)]
63101pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63102 static_assert!(N >= 1 && N <= 16);
63103 unsafe { simd_add(a, vshrq_n_s16::<N>(b)) }
63104}
63105#[doc = "Signed shift right and accumulate"]
63106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
63107#[inline]
63108#[target_feature(enable = "neon")]
63109#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63110#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63111#[cfg_attr(
63112 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63113 assert_instr(ssra, N = 2)
63114)]
63115#[rustc_legacy_const_generics(2)]
63116#[cfg_attr(
63117 not(target_arch = "arm"),
63118 stable(feature = "neon_intrinsics", since = "1.59.0")
63119)]
63120#[cfg_attr(
63121 target_arch = "arm",
63122 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63123)]
63124pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63125 static_assert!(N >= 1 && N <= 32);
63126 unsafe { simd_add(a, vshr_n_s32::<N>(b)) }
63127}
63128#[doc = "Signed shift right and accumulate"]
63129#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
63130#[inline]
63131#[target_feature(enable = "neon")]
63132#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63133#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63134#[cfg_attr(
63135 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63136 assert_instr(ssra, N = 2)
63137)]
63138#[rustc_legacy_const_generics(2)]
63139#[cfg_attr(
63140 not(target_arch = "arm"),
63141 stable(feature = "neon_intrinsics", since = "1.59.0")
63142)]
63143#[cfg_attr(
63144 target_arch = "arm",
63145 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63146)]
63147pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63148 static_assert!(N >= 1 && N <= 32);
63149 unsafe { simd_add(a, vshrq_n_s32::<N>(b)) }
63150}
63151#[doc = "Signed shift right and accumulate"]
63152#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
63153#[inline]
63154#[target_feature(enable = "neon")]
63155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63156#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63157#[cfg_attr(
63158 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63159 assert_instr(ssra, N = 2)
63160)]
63161#[rustc_legacy_const_generics(2)]
63162#[cfg_attr(
63163 not(target_arch = "arm"),
63164 stable(feature = "neon_intrinsics", since = "1.59.0")
63165)]
63166#[cfg_attr(
63167 target_arch = "arm",
63168 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63169)]
63170pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63171 static_assert!(N >= 1 && N <= 64);
63172 unsafe { simd_add(a, vshr_n_s64::<N>(b)) }
63173}
63174#[doc = "Signed shift right and accumulate"]
63175#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
63176#[inline]
63177#[target_feature(enable = "neon")]
63178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63179#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63180#[cfg_attr(
63181 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63182 assert_instr(ssra, N = 2)
63183)]
63184#[rustc_legacy_const_generics(2)]
63185#[cfg_attr(
63186 not(target_arch = "arm"),
63187 stable(feature = "neon_intrinsics", since = "1.59.0")
63188)]
63189#[cfg_attr(
63190 target_arch = "arm",
63191 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63192)]
63193pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63194 static_assert!(N >= 1 && N <= 64);
63195 unsafe { simd_add(a, vshrq_n_s64::<N>(b)) }
63196}
63197#[doc = "Unsigned shift right and accumulate"]
63198#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
63199#[inline]
63200#[target_feature(enable = "neon")]
63201#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63202#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63203#[cfg_attr(
63204 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63205 assert_instr(usra, N = 2)
63206)]
63207#[rustc_legacy_const_generics(2)]
63208#[cfg_attr(
63209 not(target_arch = "arm"),
63210 stable(feature = "neon_intrinsics", since = "1.59.0")
63211)]
63212#[cfg_attr(
63213 target_arch = "arm",
63214 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63215)]
63216pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63217 static_assert!(N >= 1 && N <= 8);
63218 unsafe { simd_add(a, vshr_n_u8::<N>(b)) }
63219}
63220#[doc = "Unsigned shift right and accumulate"]
63221#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
63222#[inline]
63223#[target_feature(enable = "neon")]
63224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63226#[cfg_attr(
63227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63228 assert_instr(usra, N = 2)
63229)]
63230#[rustc_legacy_const_generics(2)]
63231#[cfg_attr(
63232 not(target_arch = "arm"),
63233 stable(feature = "neon_intrinsics", since = "1.59.0")
63234)]
63235#[cfg_attr(
63236 target_arch = "arm",
63237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63238)]
63239pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63240 static_assert!(N >= 1 && N <= 8);
63241 unsafe { simd_add(a, vshrq_n_u8::<N>(b)) }
63242}
63243#[doc = "Unsigned shift right and accumulate"]
63244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
63245#[inline]
63246#[target_feature(enable = "neon")]
63247#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63248#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63249#[cfg_attr(
63250 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63251 assert_instr(usra, N = 2)
63252)]
63253#[rustc_legacy_const_generics(2)]
63254#[cfg_attr(
63255 not(target_arch = "arm"),
63256 stable(feature = "neon_intrinsics", since = "1.59.0")
63257)]
63258#[cfg_attr(
63259 target_arch = "arm",
63260 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63261)]
63262pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63263 static_assert!(N >= 1 && N <= 16);
63264 unsafe { simd_add(a, vshr_n_u16::<N>(b)) }
63265}
63266#[doc = "Unsigned shift right and accumulate"]
63267#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
63268#[inline]
63269#[target_feature(enable = "neon")]
63270#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63271#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63272#[cfg_attr(
63273 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63274 assert_instr(usra, N = 2)
63275)]
63276#[rustc_legacy_const_generics(2)]
63277#[cfg_attr(
63278 not(target_arch = "arm"),
63279 stable(feature = "neon_intrinsics", since = "1.59.0")
63280)]
63281#[cfg_attr(
63282 target_arch = "arm",
63283 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63284)]
63285pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63286 static_assert!(N >= 1 && N <= 16);
63287 unsafe { simd_add(a, vshrq_n_u16::<N>(b)) }
63288}
63289#[doc = "Unsigned shift right and accumulate"]
63290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
63291#[inline]
63292#[target_feature(enable = "neon")]
63293#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63294#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63295#[cfg_attr(
63296 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63297 assert_instr(usra, N = 2)
63298)]
63299#[rustc_legacy_const_generics(2)]
63300#[cfg_attr(
63301 not(target_arch = "arm"),
63302 stable(feature = "neon_intrinsics", since = "1.59.0")
63303)]
63304#[cfg_attr(
63305 target_arch = "arm",
63306 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63307)]
63308pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63309 static_assert!(N >= 1 && N <= 32);
63310 unsafe { simd_add(a, vshr_n_u32::<N>(b)) }
63311}
63312#[doc = "Unsigned shift right and accumulate"]
63313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
63314#[inline]
63315#[target_feature(enable = "neon")]
63316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63317#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63318#[cfg_attr(
63319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63320 assert_instr(usra, N = 2)
63321)]
63322#[rustc_legacy_const_generics(2)]
63323#[cfg_attr(
63324 not(target_arch = "arm"),
63325 stable(feature = "neon_intrinsics", since = "1.59.0")
63326)]
63327#[cfg_attr(
63328 target_arch = "arm",
63329 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63330)]
63331pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63332 static_assert!(N >= 1 && N <= 32);
63333 unsafe { simd_add(a, vshrq_n_u32::<N>(b)) }
63334}
63335#[doc = "Unsigned shift right and accumulate"]
63336#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
63337#[inline]
63338#[target_feature(enable = "neon")]
63339#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63340#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63341#[cfg_attr(
63342 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63343 assert_instr(usra, N = 2)
63344)]
63345#[rustc_legacy_const_generics(2)]
63346#[cfg_attr(
63347 not(target_arch = "arm"),
63348 stable(feature = "neon_intrinsics", since = "1.59.0")
63349)]
63350#[cfg_attr(
63351 target_arch = "arm",
63352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63353)]
63354pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63355 static_assert!(N >= 1 && N <= 64);
63356 unsafe { simd_add(a, vshr_n_u64::<N>(b)) }
63357}
63358#[doc = "Unsigned shift right and accumulate"]
63359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
63360#[inline]
63361#[target_feature(enable = "neon")]
63362#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63363#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
63364#[cfg_attr(
63365 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
63366 assert_instr(usra, N = 2)
63367)]
63368#[rustc_legacy_const_generics(2)]
63369#[cfg_attr(
63370 not(target_arch = "arm"),
63371 stable(feature = "neon_intrinsics", since = "1.59.0")
63372)]
63373#[cfg_attr(
63374 target_arch = "arm",
63375 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
63376)]
63377pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63378 static_assert!(N >= 1 && N <= 64);
63379 unsafe { simd_add(a, vshrq_n_u64::<N>(b)) }
63380}
63381#[doc = "Shift Right and Insert (immediate)"]
63382#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
63383#[inline]
63384#[target_feature(enable = "neon,v7")]
63385#[cfg(target_arch = "arm")]
63386#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63387#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63388#[rustc_legacy_const_generics(2)]
63389pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
63390 static_assert!(1 <= N && N <= 8);
63391 vshiftins_v8i8(a, b, int8x8_t::splat(-N as i8))
63392}
63393#[doc = "Shift Right and Insert (immediate)"]
63394#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
63395#[inline]
63396#[target_feature(enable = "neon,v7")]
63397#[cfg(target_arch = "arm")]
63398#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63399#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63400#[rustc_legacy_const_generics(2)]
63401pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
63402 static_assert!(1 <= N && N <= 8);
63403 vshiftins_v16i8(a, b, int8x16_t::splat(-N as i8))
63404}
63405#[doc = "Shift Right and Insert (immediate)"]
63406#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
63407#[inline]
63408#[target_feature(enable = "neon,v7")]
63409#[cfg(target_arch = "arm")]
63410#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63411#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63412#[rustc_legacy_const_generics(2)]
63413pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
63414 static_assert!(1 <= N && N <= 16);
63415 vshiftins_v4i16(a, b, int16x4_t::splat(-N as i16))
63416}
63417#[doc = "Shift Right and Insert (immediate)"]
63418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
63419#[inline]
63420#[target_feature(enable = "neon,v7")]
63421#[cfg(target_arch = "arm")]
63422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63423#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63424#[rustc_legacy_const_generics(2)]
63425pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
63426 static_assert!(1 <= N && N <= 16);
63427 vshiftins_v8i16(a, b, int16x8_t::splat(-N as i16))
63428}
63429#[doc = "Shift Right and Insert (immediate)"]
63430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
63431#[inline]
63432#[target_feature(enable = "neon,v7")]
63433#[cfg(target_arch = "arm")]
63434#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63435#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63436#[rustc_legacy_const_generics(2)]
63437pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
63438 static_assert!(1 <= N && N <= 32);
63439 vshiftins_v2i32(a, b, int32x2_t::splat(-N))
63440}
63441#[doc = "Shift Right and Insert (immediate)"]
63442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
63443#[inline]
63444#[target_feature(enable = "neon,v7")]
63445#[cfg(target_arch = "arm")]
63446#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63447#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63448#[rustc_legacy_const_generics(2)]
63449pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
63450 static_assert!(1 <= N && N <= 32);
63451 vshiftins_v4i32(a, b, int32x4_t::splat(-N))
63452}
63453#[doc = "Shift Right and Insert (immediate)"]
63454#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
63455#[inline]
63456#[target_feature(enable = "neon,v7")]
63457#[cfg(target_arch = "arm")]
63458#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63459#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63460#[rustc_legacy_const_generics(2)]
63461pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
63462 static_assert!(1 <= N && N <= 64);
63463 vshiftins_v1i64(a, b, int64x1_t::splat(-N as i64))
63464}
63465#[doc = "Shift Right and Insert (immediate)"]
63466#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
63467#[inline]
63468#[target_feature(enable = "neon,v7")]
63469#[cfg(target_arch = "arm")]
63470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63471#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63472#[rustc_legacy_const_generics(2)]
63473pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
63474 static_assert!(1 <= N && N <= 64);
63475 vshiftins_v2i64(a, b, int64x2_t::splat(-N as i64))
63476}
63477#[doc = "Shift Right and Insert (immediate)"]
63478#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
63479#[inline]
63480#[cfg(target_arch = "arm")]
63481#[target_feature(enable = "neon,v7")]
63482#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63483#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63484#[rustc_legacy_const_generics(2)]
63485pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
63486 static_assert!(1 <= N && N <= 8);
63487 unsafe {
63488 transmute(vshiftins_v8i8(
63489 transmute(a),
63490 transmute(b),
63491 int8x8_t::splat(-N as i8),
63492 ))
63493 }
63494}
63495#[doc = "Shift Right and Insert (immediate)"]
63496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
63497#[inline]
63498#[cfg(target_arch = "arm")]
63499#[target_feature(enable = "neon,v7")]
63500#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63501#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63502#[rustc_legacy_const_generics(2)]
63503pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
63504 static_assert!(1 <= N && N <= 8);
63505 unsafe {
63506 transmute(vshiftins_v16i8(
63507 transmute(a),
63508 transmute(b),
63509 int8x16_t::splat(-N as i8),
63510 ))
63511 }
63512}
63513#[doc = "Shift Right and Insert (immediate)"]
63514#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
63515#[inline]
63516#[cfg(target_arch = "arm")]
63517#[target_feature(enable = "neon,v7")]
63518#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63519#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63520#[rustc_legacy_const_generics(2)]
63521pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
63522 static_assert!(1 <= N && N <= 16);
63523 unsafe {
63524 transmute(vshiftins_v4i16(
63525 transmute(a),
63526 transmute(b),
63527 int16x4_t::splat(-N as i16),
63528 ))
63529 }
63530}
63531#[doc = "Shift Right and Insert (immediate)"]
63532#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
63533#[inline]
63534#[cfg(target_arch = "arm")]
63535#[target_feature(enable = "neon,v7")]
63536#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63537#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63538#[rustc_legacy_const_generics(2)]
63539pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
63540 static_assert!(1 <= N && N <= 16);
63541 unsafe {
63542 transmute(vshiftins_v8i16(
63543 transmute(a),
63544 transmute(b),
63545 int16x8_t::splat(-N as i16),
63546 ))
63547 }
63548}
63549#[doc = "Shift Right and Insert (immediate)"]
63550#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
63551#[inline]
63552#[cfg(target_arch = "arm")]
63553#[target_feature(enable = "neon,v7")]
63554#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63555#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63556#[rustc_legacy_const_generics(2)]
63557pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
63558 static_assert!(1 <= N && N <= 32);
63559 unsafe {
63560 transmute(vshiftins_v2i32(
63561 transmute(a),
63562 transmute(b),
63563 int32x2_t::splat(-N),
63564 ))
63565 }
63566}
63567#[doc = "Shift Right and Insert (immediate)"]
63568#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
63569#[inline]
63570#[cfg(target_arch = "arm")]
63571#[target_feature(enable = "neon,v7")]
63572#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63573#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.32", N = 1))]
63574#[rustc_legacy_const_generics(2)]
63575pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
63576 static_assert!(1 <= N && N <= 32);
63577 unsafe {
63578 transmute(vshiftins_v4i32(
63579 transmute(a),
63580 transmute(b),
63581 int32x4_t::splat(-N),
63582 ))
63583 }
63584}
63585#[doc = "Shift Right and Insert (immediate)"]
63586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
63587#[inline]
63588#[cfg(target_arch = "arm")]
63589#[target_feature(enable = "neon,v7")]
63590#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63591#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63592#[rustc_legacy_const_generics(2)]
63593pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
63594 static_assert!(1 <= N && N <= 64);
63595 unsafe {
63596 transmute(vshiftins_v1i64(
63597 transmute(a),
63598 transmute(b),
63599 int64x1_t::splat(-N as i64),
63600 ))
63601 }
63602}
63603#[doc = "Shift Right and Insert (immediate)"]
63604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
63605#[inline]
63606#[cfg(target_arch = "arm")]
63607#[target_feature(enable = "neon,v7")]
63608#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63609#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.64", N = 1))]
63610#[rustc_legacy_const_generics(2)]
63611pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
63612 static_assert!(1 <= N && N <= 64);
63613 unsafe {
63614 transmute(vshiftins_v2i64(
63615 transmute(a),
63616 transmute(b),
63617 int64x2_t::splat(-N as i64),
63618 ))
63619 }
63620}
63621#[doc = "Shift Right and Insert (immediate)"]
63622#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
63623#[inline]
63624#[cfg(target_arch = "arm")]
63625#[target_feature(enable = "neon,v7")]
63626#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63627#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63628#[rustc_legacy_const_generics(2)]
63629pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
63630 static_assert!(1 <= N && N <= 8);
63631 unsafe {
63632 transmute(vshiftins_v8i8(
63633 transmute(a),
63634 transmute(b),
63635 int8x8_t::splat(-N as i8),
63636 ))
63637 }
63638}
63639#[doc = "Shift Right and Insert (immediate)"]
63640#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
63641#[inline]
63642#[cfg(target_arch = "arm")]
63643#[target_feature(enable = "neon,v7")]
63644#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63645#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.8", N = 1))]
63646#[rustc_legacy_const_generics(2)]
63647pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
63648 static_assert!(1 <= N && N <= 8);
63649 unsafe {
63650 transmute(vshiftins_v16i8(
63651 transmute(a),
63652 transmute(b),
63653 int8x16_t::splat(-N as i8),
63654 ))
63655 }
63656}
63657#[doc = "Shift Right and Insert (immediate)"]
63658#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
63659#[inline]
63660#[cfg(target_arch = "arm")]
63661#[target_feature(enable = "neon,v7")]
63662#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63663#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63664#[rustc_legacy_const_generics(2)]
63665pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
63666 static_assert!(1 <= N && N <= 16);
63667 unsafe {
63668 transmute(vshiftins_v4i16(
63669 transmute(a),
63670 transmute(b),
63671 int16x4_t::splat(-N as i16),
63672 ))
63673 }
63674}
63675#[doc = "Shift Right and Insert (immediate)"]
63676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
63677#[inline]
63678#[cfg(target_arch = "arm")]
63679#[target_feature(enable = "neon,v7")]
63680#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63681#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsri.16", N = 1))]
63682#[rustc_legacy_const_generics(2)]
63683pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
63684 static_assert!(1 <= N && N <= 16);
63685 unsafe {
63686 transmute(vshiftins_v8i16(
63687 transmute(a),
63688 transmute(b),
63689 int16x8_t::splat(-N as i16),
63690 ))
63691 }
63692}
63693#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
63694#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
63695#[doc = "## Safety"]
63696#[doc = " * Neon instrinsic unsafe"]
63697#[inline]
63698#[cfg(target_arch = "arm")]
63699#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63700#[target_feature(enable = "neon,fp16")]
63701#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63702#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
63703pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
63704 vst1_v4f16(
63705 ptr as *const i8,
63706 transmute(a),
63707 crate::mem::align_of::<f16>() as i32,
63708 )
63709}
63710#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
63711#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
63712#[doc = "## Safety"]
63713#[doc = " * Neon instrinsic unsafe"]
63714#[inline]
63715#[cfg(target_arch = "arm")]
63716#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63717#[target_feature(enable = "neon,fp16")]
63718#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63719#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
63720pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
63721 vst1q_v8f16(
63722 ptr as *const i8,
63723 transmute(a),
63724 crate::mem::align_of::<f16>() as i32,
63725 )
63726}
63727#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
63729#[doc = "## Safety"]
63730#[doc = " * Neon instrinsic unsafe"]
63731#[inline]
63732#[cfg(target_arch = "arm")]
63733#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63734#[cfg_attr(test, assert_instr(vst1))]
63735#[target_feature(enable = "neon,fp16")]
63736#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63737pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
63738 unsafe extern "unadjusted" {
63739 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0.v4f16")]
63740 fn _vst1_f16_x2(ptr: *mut f16, a: float16x4_t, b: float16x4_t);
63741 }
63742 _vst1_f16_x2(a, b.0, b.1)
63743}
63744#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63745#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
63746#[doc = "## Safety"]
63747#[doc = " * Neon instrinsic unsafe"]
63748#[inline]
63749#[cfg(target_arch = "arm")]
63750#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63751#[cfg_attr(test, assert_instr(vst1))]
63752#[target_feature(enable = "neon,fp16")]
63753#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63754pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
63755 unsafe extern "unadjusted" {
63756 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0.v8f16")]
63757 fn _vst1q_f16_x2(ptr: *mut f16, a: float16x8_t, b: float16x8_t);
63758 }
63759 _vst1q_f16_x2(a, b.0, b.1)
63760}
63761#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63762#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
63763#[doc = "## Safety"]
63764#[doc = " * Neon instrinsic unsafe"]
63765#[inline]
63766#[cfg(not(target_arch = "arm"))]
63767#[cfg_attr(test, assert_instr(st1))]
63768#[target_feature(enable = "neon,fp16")]
63769#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63770pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
63771 unsafe extern "unadjusted" {
63772 #[cfg_attr(
63773 any(target_arch = "aarch64", target_arch = "arm64ec"),
63774 link_name = "llvm.aarch64.neon.st1x2.v4f16.p0"
63775 )]
63776 fn _vst1_f16_x2(a: float16x4_t, b: float16x4_t, ptr: *mut f16);
63777 }
63778 _vst1_f16_x2(b.0, b.1, a)
63779}
63780#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
63782#[doc = "## Safety"]
63783#[doc = " * Neon instrinsic unsafe"]
63784#[inline]
63785#[cfg(not(target_arch = "arm"))]
63786#[cfg_attr(test, assert_instr(st1))]
63787#[target_feature(enable = "neon,fp16")]
63788#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63789pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
63790 unsafe extern "unadjusted" {
63791 #[cfg_attr(
63792 any(target_arch = "aarch64", target_arch = "arm64ec"),
63793 link_name = "llvm.aarch64.neon.st1x2.v8f16.p0"
63794 )]
63795 fn _vst1q_f16_x2(a: float16x8_t, b: float16x8_t, ptr: *mut f16);
63796 }
63797 _vst1q_f16_x2(b.0, b.1, a)
63798}
63799#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
63801#[doc = "## Safety"]
63802#[doc = " * Neon instrinsic unsafe"]
63803#[inline]
63804#[cfg(target_arch = "arm")]
63805#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63806#[cfg_attr(test, assert_instr(vst1))]
63807#[target_feature(enable = "neon,fp16")]
63808#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63809pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
63810 unsafe extern "unadjusted" {
63811 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4f16")]
63812 fn _vst1_f16_x3(ptr: *mut f16, a: float16x4_t, b: float16x4_t, c: float16x4_t);
63813 }
63814 _vst1_f16_x3(a, b.0, b.1, b.2)
63815}
63816#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63817#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
63818#[doc = "## Safety"]
63819#[doc = " * Neon instrinsic unsafe"]
63820#[inline]
63821#[cfg(target_arch = "arm")]
63822#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63823#[cfg_attr(test, assert_instr(vst1))]
63824#[target_feature(enable = "neon,fp16")]
63825#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63826pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
63827 unsafe extern "unadjusted" {
63828 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8f16")]
63829 fn _vst1q_f16_x3(ptr: *mut f16, a: float16x8_t, b: float16x8_t, c: float16x8_t);
63830 }
63831 _vst1q_f16_x3(a, b.0, b.1, b.2)
63832}
63833#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63834#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
63835#[doc = "## Safety"]
63836#[doc = " * Neon instrinsic unsafe"]
63837#[inline]
63838#[cfg(not(target_arch = "arm"))]
63839#[cfg_attr(test, assert_instr(st1))]
63840#[target_feature(enable = "neon,fp16")]
63841#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63842pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
63843 unsafe extern "unadjusted" {
63844 #[cfg_attr(
63845 any(target_arch = "aarch64", target_arch = "arm64ec"),
63846 link_name = "llvm.aarch64.neon.st1x3.v4f16.p0"
63847 )]
63848 fn _vst1_f16_x3(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut f16);
63849 }
63850 _vst1_f16_x3(b.0, b.1, b.2, a)
63851}
63852#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63853#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
63854#[doc = "## Safety"]
63855#[doc = " * Neon instrinsic unsafe"]
63856#[inline]
63857#[cfg(not(target_arch = "arm"))]
63858#[cfg_attr(test, assert_instr(st1))]
63859#[target_feature(enable = "neon,fp16")]
63860#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63861pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
63862 unsafe extern "unadjusted" {
63863 #[cfg_attr(
63864 any(target_arch = "aarch64", target_arch = "arm64ec"),
63865 link_name = "llvm.aarch64.neon.st1x3.v8f16.p0"
63866 )]
63867 fn _vst1q_f16_x3(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut f16);
63868 }
63869 _vst1q_f16_x3(b.0, b.1, b.2, a)
63870}
63871#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63872#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
63873#[doc = "## Safety"]
63874#[doc = " * Neon instrinsic unsafe"]
63875#[inline]
63876#[cfg(target_arch = "arm")]
63877#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63878#[target_feature(enable = "neon,fp16")]
63879#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63880#[cfg_attr(test, assert_instr(vst1))]
63881pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
63882 unsafe extern "unadjusted" {
63883 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4f16")]
63884 fn _vst1_f16_x4(
63885 ptr: *mut f16,
63886 a: float16x4_t,
63887 b: float16x4_t,
63888 c: float16x4_t,
63889 d: float16x4_t,
63890 );
63891 }
63892 _vst1_f16_x4(a, b.0, b.1, b.2, b.3)
63893}
63894#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
63896#[doc = "## Safety"]
63897#[doc = " * Neon instrinsic unsafe"]
63898#[inline]
63899#[cfg(target_arch = "arm")]
63900#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63901#[target_feature(enable = "neon,fp16")]
63902#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63903#[cfg_attr(test, assert_instr(vst1))]
63904pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
63905 unsafe extern "unadjusted" {
63906 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8f16")]
63907 fn _vst1q_f16_x4(
63908 ptr: *mut f16,
63909 a: float16x8_t,
63910 b: float16x8_t,
63911 c: float16x8_t,
63912 d: float16x8_t,
63913 );
63914 }
63915 _vst1q_f16_x4(a, b.0, b.1, b.2, b.3)
63916}
63917#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63918#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
63919#[doc = "## Safety"]
63920#[doc = " * Neon instrinsic unsafe"]
63921#[inline]
63922#[cfg(not(target_arch = "arm"))]
63923#[cfg_attr(test, assert_instr(st1))]
63924#[target_feature(enable = "neon,fp16")]
63925#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63926pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
63927 unsafe extern "unadjusted" {
63928 #[cfg_attr(
63929 any(target_arch = "aarch64", target_arch = "arm64ec"),
63930 link_name = "llvm.aarch64.neon.st1x4.v4f16.p0"
63931 )]
63932 fn _vst1_f16_x4(
63933 a: float16x4_t,
63934 b: float16x4_t,
63935 c: float16x4_t,
63936 d: float16x4_t,
63937 ptr: *mut f16,
63938 );
63939 }
63940 _vst1_f16_x4(b.0, b.1, b.2, b.3, a)
63941}
63942#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
63943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
63944#[doc = "## Safety"]
63945#[doc = " * Neon instrinsic unsafe"]
63946#[inline]
63947#[cfg(not(target_arch = "arm"))]
63948#[cfg_attr(test, assert_instr(st1))]
63949#[target_feature(enable = "neon,fp16")]
63950#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
63951pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
63952 unsafe extern "unadjusted" {
63953 #[cfg_attr(
63954 any(target_arch = "aarch64", target_arch = "arm64ec"),
63955 link_name = "llvm.aarch64.neon.st1x4.v8f16.p0"
63956 )]
63957 fn _vst1q_f16_x4(
63958 a: float16x8_t,
63959 b: float16x8_t,
63960 c: float16x8_t,
63961 d: float16x8_t,
63962 ptr: *mut f16,
63963 );
63964 }
63965 _vst1q_f16_x4(b.0, b.1, b.2, b.3, a)
63966}
63967#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
63968#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
63969#[doc = "## Safety"]
63970#[doc = " * Neon instrinsic unsafe"]
63971#[inline]
63972#[target_feature(enable = "neon")]
63973#[cfg(target_arch = "arm")]
63974#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63975#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63976#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
63977pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
63978 vst1_v2f32(
63979 ptr as *const i8,
63980 transmute(a),
63981 crate::mem::align_of::<f32>() as i32,
63982 )
63983}
63984#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
63985#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
63986#[doc = "## Safety"]
63987#[doc = " * Neon instrinsic unsafe"]
63988#[inline]
63989#[target_feature(enable = "neon")]
63990#[cfg(target_arch = "arm")]
63991#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
63992#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
63993#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
63994pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
63995 vst1q_v4f32(
63996 ptr as *const i8,
63997 transmute(a),
63998 crate::mem::align_of::<f32>() as i32,
63999 )
64000}
64001#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
64003#[doc = "## Safety"]
64004#[doc = " * Neon instrinsic unsafe"]
64005#[inline]
64006#[target_feature(enable = "neon")]
64007#[cfg(target_arch = "arm")]
64008#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64009#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64010#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64011pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
64012 vst1_v8i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64013}
64014#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64015#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
64016#[doc = "## Safety"]
64017#[doc = " * Neon instrinsic unsafe"]
64018#[inline]
64019#[target_feature(enable = "neon")]
64020#[cfg(target_arch = "arm")]
64021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64022#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64023#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64024pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
64025 vst1q_v16i8(ptr as *const i8, a, crate::mem::align_of::<i8>() as i32)
64026}
64027#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64028#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
64029#[doc = "## Safety"]
64030#[doc = " * Neon instrinsic unsafe"]
64031#[inline]
64032#[target_feature(enable = "neon")]
64033#[cfg(target_arch = "arm")]
64034#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64035#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64036#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64037pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
64038 vst1_v4i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64039}
64040#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64041#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
64042#[doc = "## Safety"]
64043#[doc = " * Neon instrinsic unsafe"]
64044#[inline]
64045#[target_feature(enable = "neon")]
64046#[cfg(target_arch = "arm")]
64047#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64048#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64049#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64050pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
64051 vst1q_v8i16(ptr as *const i8, a, crate::mem::align_of::<i16>() as i32)
64052}
64053#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64054#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
64055#[doc = "## Safety"]
64056#[doc = " * Neon instrinsic unsafe"]
64057#[inline]
64058#[target_feature(enable = "neon")]
64059#[cfg(target_arch = "arm")]
64060#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64061#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64062#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64063pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
64064 vst1_v2i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64065}
64066#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64067#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
64068#[doc = "## Safety"]
64069#[doc = " * Neon instrinsic unsafe"]
64070#[inline]
64071#[target_feature(enable = "neon")]
64072#[cfg(target_arch = "arm")]
64073#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64074#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64075#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64076pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
64077 vst1q_v4i32(ptr as *const i8, a, crate::mem::align_of::<i32>() as i32)
64078}
64079#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64080#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
64081#[doc = "## Safety"]
64082#[doc = " * Neon instrinsic unsafe"]
64083#[inline]
64084#[target_feature(enable = "neon")]
64085#[cfg(target_arch = "arm")]
64086#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64087#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64088#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64089pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
64090 vst1_v1i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64091}
64092#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
64094#[doc = "## Safety"]
64095#[doc = " * Neon instrinsic unsafe"]
64096#[inline]
64097#[target_feature(enable = "neon")]
64098#[cfg(target_arch = "arm")]
64099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64100#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64101#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64102pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
64103 vst1q_v2i64(ptr as *const i8, a, crate::mem::align_of::<i64>() as i32)
64104}
64105#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
64107#[doc = "## Safety"]
64108#[doc = " * Neon instrinsic unsafe"]
64109#[inline]
64110#[target_feature(enable = "neon")]
64111#[cfg(target_arch = "arm")]
64112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64113#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64114#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64115pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
64116 vst1_v8i8(
64117 ptr as *const i8,
64118 transmute(a),
64119 crate::mem::align_of::<u8>() as i32,
64120 )
64121}
64122#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
64124#[doc = "## Safety"]
64125#[doc = " * Neon instrinsic unsafe"]
64126#[inline]
64127#[target_feature(enable = "neon")]
64128#[cfg(target_arch = "arm")]
64129#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64130#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64131#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64132pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
64133 vst1q_v16i8(
64134 ptr as *const i8,
64135 transmute(a),
64136 crate::mem::align_of::<u8>() as i32,
64137 )
64138}
64139#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64140#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
64141#[doc = "## Safety"]
64142#[doc = " * Neon instrinsic unsafe"]
64143#[inline]
64144#[target_feature(enable = "neon")]
64145#[cfg(target_arch = "arm")]
64146#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64147#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64148#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64149pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
64150 vst1_v4i16(
64151 ptr as *const i8,
64152 transmute(a),
64153 crate::mem::align_of::<u16>() as i32,
64154 )
64155}
64156#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
64158#[doc = "## Safety"]
64159#[doc = " * Neon instrinsic unsafe"]
64160#[inline]
64161#[target_feature(enable = "neon")]
64162#[cfg(target_arch = "arm")]
64163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64164#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64165#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64166pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
64167 vst1q_v8i16(
64168 ptr as *const i8,
64169 transmute(a),
64170 crate::mem::align_of::<u16>() as i32,
64171 )
64172}
64173#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64174#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
64175#[doc = "## Safety"]
64176#[doc = " * Neon instrinsic unsafe"]
64177#[inline]
64178#[target_feature(enable = "neon")]
64179#[cfg(target_arch = "arm")]
64180#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64181#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64182#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64183pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
64184 vst1_v2i32(
64185 ptr as *const i8,
64186 transmute(a),
64187 crate::mem::align_of::<u32>() as i32,
64188 )
64189}
64190#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64191#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
64192#[doc = "## Safety"]
64193#[doc = " * Neon instrinsic unsafe"]
64194#[inline]
64195#[target_feature(enable = "neon")]
64196#[cfg(target_arch = "arm")]
64197#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64198#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64199#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
64200pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
64201 vst1q_v4i32(
64202 ptr as *const i8,
64203 transmute(a),
64204 crate::mem::align_of::<u32>() as i32,
64205 )
64206}
64207#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
64209#[doc = "## Safety"]
64210#[doc = " * Neon instrinsic unsafe"]
64211#[inline]
64212#[target_feature(enable = "neon")]
64213#[cfg(target_arch = "arm")]
64214#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64215#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64216#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64217pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
64218 vst1_v1i64(
64219 ptr as *const i8,
64220 transmute(a),
64221 crate::mem::align_of::<u64>() as i32,
64222 )
64223}
64224#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
64226#[doc = "## Safety"]
64227#[doc = " * Neon instrinsic unsafe"]
64228#[inline]
64229#[target_feature(enable = "neon")]
64230#[cfg(target_arch = "arm")]
64231#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64232#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64233#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64234pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
64235 vst1q_v2i64(
64236 ptr as *const i8,
64237 transmute(a),
64238 crate::mem::align_of::<u64>() as i32,
64239 )
64240}
64241#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64242#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
64243#[doc = "## Safety"]
64244#[doc = " * Neon instrinsic unsafe"]
64245#[inline]
64246#[target_feature(enable = "neon")]
64247#[cfg(target_arch = "arm")]
64248#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64249#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64250#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64251pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
64252 vst1_v8i8(
64253 ptr as *const i8,
64254 transmute(a),
64255 crate::mem::align_of::<p8>() as i32,
64256 )
64257}
64258#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
64260#[doc = "## Safety"]
64261#[doc = " * Neon instrinsic unsafe"]
64262#[inline]
64263#[target_feature(enable = "neon")]
64264#[cfg(target_arch = "arm")]
64265#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64266#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64267#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
64268pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
64269 vst1q_v16i8(
64270 ptr as *const i8,
64271 transmute(a),
64272 crate::mem::align_of::<p8>() as i32,
64273 )
64274}
64275#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64276#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
64277#[doc = "## Safety"]
64278#[doc = " * Neon instrinsic unsafe"]
64279#[inline]
64280#[target_feature(enable = "neon")]
64281#[cfg(target_arch = "arm")]
64282#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64283#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64284#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64285pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
64286 vst1_v4i16(
64287 ptr as *const i8,
64288 transmute(a),
64289 crate::mem::align_of::<p16>() as i32,
64290 )
64291}
64292#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
64294#[doc = "## Safety"]
64295#[doc = " * Neon instrinsic unsafe"]
64296#[inline]
64297#[target_feature(enable = "neon")]
64298#[cfg(target_arch = "arm")]
64299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64300#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64301#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
64302pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
64303 vst1q_v8i16(
64304 ptr as *const i8,
64305 transmute(a),
64306 crate::mem::align_of::<p16>() as i32,
64307 )
64308}
64309#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64310#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
64311#[doc = "## Safety"]
64312#[doc = " * Neon instrinsic unsafe"]
64313#[inline]
64314#[target_feature(enable = "neon")]
64315#[cfg(target_arch = "arm")]
64316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64317#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64318#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64319pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
64320 vst1_v1i64(
64321 ptr as *const i8,
64322 transmute(a),
64323 crate::mem::align_of::<p64>() as i32,
64324 )
64325}
64326#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
64327#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
64328#[doc = "## Safety"]
64329#[doc = " * Neon instrinsic unsafe"]
64330#[inline]
64331#[target_feature(enable = "neon")]
64332#[cfg(target_arch = "arm")]
64333#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64334#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64335#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
64336pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
64337 vst1q_v2i64(
64338 ptr as *const i8,
64339 transmute(a),
64340 crate::mem::align_of::<p64>() as i32,
64341 )
64342}
64343#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64345#[doc = "## Safety"]
64346#[doc = " * Neon instrinsic unsafe"]
64347#[inline]
64348#[cfg(target_arch = "arm")]
64349#[target_feature(enable = "neon,v7")]
64350#[cfg_attr(test, assert_instr(vst1))]
64351#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64352pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64353 unsafe extern "unadjusted" {
64354 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2f32.p0")]
64355 fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t);
64356 }
64357 _vst1_f32_x2(a, b.0, b.1)
64358}
64359#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64361#[doc = "## Safety"]
64362#[doc = " * Neon instrinsic unsafe"]
64363#[inline]
64364#[cfg(target_arch = "arm")]
64365#[target_feature(enable = "neon,v7")]
64366#[cfg_attr(test, assert_instr(vst1))]
64367#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64368pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64369 unsafe extern "unadjusted" {
64370 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4f32.p0")]
64371 fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t);
64372 }
64373 _vst1q_f32_x2(a, b.0, b.1)
64374}
64375#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
64377#[doc = "## Safety"]
64378#[doc = " * Neon instrinsic unsafe"]
64379#[inline]
64380#[target_feature(enable = "neon")]
64381#[cfg(not(target_arch = "arm"))]
64382#[cfg_attr(test, assert_instr(st1))]
64383#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64384pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
64385 unsafe extern "unadjusted" {
64386 #[cfg_attr(
64387 any(target_arch = "aarch64", target_arch = "arm64ec"),
64388 link_name = "llvm.aarch64.neon.st1x2.v2f32.p0"
64389 )]
64390 fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32);
64391 }
64392 _vst1_f32_x2(b.0, b.1, a)
64393}
64394#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64395#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
64396#[doc = "## Safety"]
64397#[doc = " * Neon instrinsic unsafe"]
64398#[inline]
64399#[target_feature(enable = "neon")]
64400#[cfg(not(target_arch = "arm"))]
64401#[cfg_attr(test, assert_instr(st1))]
64402#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64403pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
64404 unsafe extern "unadjusted" {
64405 #[cfg_attr(
64406 any(target_arch = "aarch64", target_arch = "arm64ec"),
64407 link_name = "llvm.aarch64.neon.st1x2.v4f32.p0"
64408 )]
64409 fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32);
64410 }
64411 _vst1q_f32_x2(b.0, b.1, a)
64412}
64413#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64414#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
64415#[doc = "## Safety"]
64416#[doc = " * Neon instrinsic unsafe"]
64417#[inline]
64418#[target_feature(enable = "neon")]
64419#[cfg(not(target_arch = "arm"))]
64420#[cfg_attr(test, assert_instr(st1))]
64421#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64422pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
64423 unsafe extern "unadjusted" {
64424 #[cfg_attr(
64425 any(target_arch = "aarch64", target_arch = "arm64ec"),
64426 link_name = "llvm.aarch64.neon.st1x3.v2f32.p0"
64427 )]
64428 fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32);
64429 }
64430 _vst1_f32_x3(b.0, b.1, b.2, a)
64431}
64432#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64433#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
64434#[doc = "## Safety"]
64435#[doc = " * Neon instrinsic unsafe"]
64436#[inline]
64437#[target_feature(enable = "neon")]
64438#[cfg(not(target_arch = "arm"))]
64439#[cfg_attr(test, assert_instr(st1))]
64440#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64441pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
64442 unsafe extern "unadjusted" {
64443 #[cfg_attr(
64444 any(target_arch = "aarch64", target_arch = "arm64ec"),
64445 link_name = "llvm.aarch64.neon.st1x3.v4f32.p0"
64446 )]
64447 fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32);
64448 }
64449 _vst1q_f32_x3(b.0, b.1, b.2, a)
64450}
64451#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64452#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64453#[doc = "## Safety"]
64454#[doc = " * Neon instrinsic unsafe"]
64455#[inline]
64456#[cfg(target_arch = "arm")]
64457#[target_feature(enable = "neon,v7")]
64458#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64459#[cfg_attr(test, assert_instr(vst1))]
64460pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64461 unsafe extern "unadjusted" {
64462 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2f32.p0")]
64463 fn _vst1_f32_x4(
64464 ptr: *mut f32,
64465 a: float32x2_t,
64466 b: float32x2_t,
64467 c: float32x2_t,
64468 d: float32x2_t,
64469 );
64470 }
64471 _vst1_f32_x4(a, b.0, b.1, b.2, b.3)
64472}
64473#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64474#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64475#[doc = "## Safety"]
64476#[doc = " * Neon instrinsic unsafe"]
64477#[inline]
64478#[cfg(target_arch = "arm")]
64479#[target_feature(enable = "neon,v7")]
64480#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
64481#[cfg_attr(test, assert_instr(vst1))]
64482pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64483 unsafe extern "unadjusted" {
64484 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4f32.p0")]
64485 fn _vst1q_f32_x4(
64486 ptr: *mut f32,
64487 a: float32x4_t,
64488 b: float32x4_t,
64489 c: float32x4_t,
64490 d: float32x4_t,
64491 );
64492 }
64493 _vst1q_f32_x4(a, b.0, b.1, b.2, b.3)
64494}
64495#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
64497#[doc = "## Safety"]
64498#[doc = " * Neon instrinsic unsafe"]
64499#[inline]
64500#[target_feature(enable = "neon")]
64501#[cfg(not(target_arch = "arm"))]
64502#[cfg_attr(test, assert_instr(st1))]
64503#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64504pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
64505 unsafe extern "unadjusted" {
64506 #[cfg_attr(
64507 any(target_arch = "aarch64", target_arch = "arm64ec"),
64508 link_name = "llvm.aarch64.neon.st1x4.v2f32.p0"
64509 )]
64510 fn _vst1_f32_x4(
64511 a: float32x2_t,
64512 b: float32x2_t,
64513 c: float32x2_t,
64514 d: float32x2_t,
64515 ptr: *mut f32,
64516 );
64517 }
64518 _vst1_f32_x4(b.0, b.1, b.2, b.3, a)
64519}
64520#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
64521#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
64522#[doc = "## Safety"]
64523#[doc = " * Neon instrinsic unsafe"]
64524#[inline]
64525#[target_feature(enable = "neon")]
64526#[cfg(not(target_arch = "arm"))]
64527#[cfg_attr(test, assert_instr(st1))]
64528#[stable(feature = "neon_intrinsics", since = "1.59.0")]
64529pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
64530 unsafe extern "unadjusted" {
64531 #[cfg_attr(
64532 any(target_arch = "aarch64", target_arch = "arm64ec"),
64533 link_name = "llvm.aarch64.neon.st1x4.v4f32.p0"
64534 )]
64535 fn _vst1q_f32_x4(
64536 a: float32x4_t,
64537 b: float32x4_t,
64538 c: float32x4_t,
64539 d: float32x4_t,
64540 ptr: *mut f32,
64541 );
64542 }
64543 _vst1q_f32_x4(b.0, b.1, b.2, b.3, a)
64544}
64545#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64546#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
64547#[doc = "## Safety"]
64548#[doc = " * Neon instrinsic unsafe"]
64549#[inline]
64550#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64551#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64552#[cfg_attr(
64553 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64554 assert_instr(nop, LANE = 0)
64555)]
64556#[rustc_legacy_const_generics(2)]
64557#[target_feature(enable = "neon,fp16")]
64558#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64559pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
64560 static_assert_uimm_bits!(LANE, 2);
64561 *a = simd_extract!(b, LANE as u32);
64562}
64563#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64564#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
64565#[doc = "## Safety"]
64566#[doc = " * Neon instrinsic unsafe"]
64567#[inline]
64568#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64569#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64570#[cfg_attr(
64571 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64572 assert_instr(nop, LANE = 0)
64573)]
64574#[rustc_legacy_const_generics(2)]
64575#[target_feature(enable = "neon,fp16")]
64576#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
64577pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
64578 static_assert_uimm_bits!(LANE, 3);
64579 *a = simd_extract!(b, LANE as u32);
64580}
64581#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64582#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
64583#[doc = "## Safety"]
64584#[doc = " * Neon instrinsic unsafe"]
64585#[inline]
64586#[target_feature(enable = "neon")]
64587#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64588#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64589#[cfg_attr(
64590 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64591 assert_instr(nop, LANE = 0)
64592)]
64593#[rustc_legacy_const_generics(2)]
64594#[cfg_attr(
64595 not(target_arch = "arm"),
64596 stable(feature = "neon_intrinsics", since = "1.59.0")
64597)]
64598#[cfg_attr(
64599 target_arch = "arm",
64600 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64601)]
64602pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
64603 static_assert_uimm_bits!(LANE, 1);
64604 *a = simd_extract!(b, LANE as u32);
64605}
64606#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64607#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
64608#[doc = "## Safety"]
64609#[doc = " * Neon instrinsic unsafe"]
64610#[inline]
64611#[target_feature(enable = "neon")]
64612#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64613#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64614#[cfg_attr(
64615 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64616 assert_instr(nop, LANE = 0)
64617)]
64618#[rustc_legacy_const_generics(2)]
64619#[cfg_attr(
64620 not(target_arch = "arm"),
64621 stable(feature = "neon_intrinsics", since = "1.59.0")
64622)]
64623#[cfg_attr(
64624 target_arch = "arm",
64625 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64626)]
64627pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
64628 static_assert_uimm_bits!(LANE, 2);
64629 *a = simd_extract!(b, LANE as u32);
64630}
64631#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
64633#[doc = "## Safety"]
64634#[doc = " * Neon instrinsic unsafe"]
64635#[inline]
64636#[target_feature(enable = "neon")]
64637#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64638#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64639#[cfg_attr(
64640 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64641 assert_instr(nop, LANE = 0)
64642)]
64643#[rustc_legacy_const_generics(2)]
64644#[cfg_attr(
64645 not(target_arch = "arm"),
64646 stable(feature = "neon_intrinsics", since = "1.59.0")
64647)]
64648#[cfg_attr(
64649 target_arch = "arm",
64650 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64651)]
64652pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
64653 static_assert_uimm_bits!(LANE, 3);
64654 *a = simd_extract!(b, LANE as u32);
64655}
64656#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
64658#[doc = "## Safety"]
64659#[doc = " * Neon instrinsic unsafe"]
64660#[inline]
64661#[target_feature(enable = "neon")]
64662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64664#[cfg_attr(
64665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64666 assert_instr(nop, LANE = 0)
64667)]
64668#[rustc_legacy_const_generics(2)]
64669#[cfg_attr(
64670 not(target_arch = "arm"),
64671 stable(feature = "neon_intrinsics", since = "1.59.0")
64672)]
64673#[cfg_attr(
64674 target_arch = "arm",
64675 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64676)]
64677pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
64678 static_assert_uimm_bits!(LANE, 4);
64679 *a = simd_extract!(b, LANE as u32);
64680}
64681#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64682#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
64683#[doc = "## Safety"]
64684#[doc = " * Neon instrinsic unsafe"]
64685#[inline]
64686#[target_feature(enable = "neon")]
64687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64689#[cfg_attr(
64690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64691 assert_instr(nop, LANE = 0)
64692)]
64693#[rustc_legacy_const_generics(2)]
64694#[cfg_attr(
64695 not(target_arch = "arm"),
64696 stable(feature = "neon_intrinsics", since = "1.59.0")
64697)]
64698#[cfg_attr(
64699 target_arch = "arm",
64700 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64701)]
64702pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
64703 static_assert_uimm_bits!(LANE, 2);
64704 *a = simd_extract!(b, LANE as u32);
64705}
64706#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64707#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
64708#[doc = "## Safety"]
64709#[doc = " * Neon instrinsic unsafe"]
64710#[inline]
64711#[target_feature(enable = "neon")]
64712#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64713#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64714#[cfg_attr(
64715 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64716 assert_instr(nop, LANE = 0)
64717)]
64718#[rustc_legacy_const_generics(2)]
64719#[cfg_attr(
64720 not(target_arch = "arm"),
64721 stable(feature = "neon_intrinsics", since = "1.59.0")
64722)]
64723#[cfg_attr(
64724 target_arch = "arm",
64725 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64726)]
64727pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
64728 static_assert_uimm_bits!(LANE, 3);
64729 *a = simd_extract!(b, LANE as u32);
64730}
64731#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64732#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
64733#[doc = "## Safety"]
64734#[doc = " * Neon instrinsic unsafe"]
64735#[inline]
64736#[target_feature(enable = "neon")]
64737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64738#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64739#[cfg_attr(
64740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64741 assert_instr(nop, LANE = 0)
64742)]
64743#[rustc_legacy_const_generics(2)]
64744#[cfg_attr(
64745 not(target_arch = "arm"),
64746 stable(feature = "neon_intrinsics", since = "1.59.0")
64747)]
64748#[cfg_attr(
64749 target_arch = "arm",
64750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64751)]
64752pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
64753 static_assert_uimm_bits!(LANE, 1);
64754 *a = simd_extract!(b, LANE as u32);
64755}
64756#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
64758#[doc = "## Safety"]
64759#[doc = " * Neon instrinsic unsafe"]
64760#[inline]
64761#[target_feature(enable = "neon")]
64762#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64763#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64764#[cfg_attr(
64765 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64766 assert_instr(nop, LANE = 0)
64767)]
64768#[rustc_legacy_const_generics(2)]
64769#[cfg_attr(
64770 not(target_arch = "arm"),
64771 stable(feature = "neon_intrinsics", since = "1.59.0")
64772)]
64773#[cfg_attr(
64774 target_arch = "arm",
64775 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64776)]
64777pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
64778 static_assert_uimm_bits!(LANE, 2);
64779 *a = simd_extract!(b, LANE as u32);
64780}
64781#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64782#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
64783#[doc = "## Safety"]
64784#[doc = " * Neon instrinsic unsafe"]
64785#[inline]
64786#[target_feature(enable = "neon")]
64787#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64788#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64789#[cfg_attr(
64790 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64791 assert_instr(nop, LANE = 0)
64792)]
64793#[rustc_legacy_const_generics(2)]
64794#[cfg_attr(
64795 not(target_arch = "arm"),
64796 stable(feature = "neon_intrinsics", since = "1.59.0")
64797)]
64798#[cfg_attr(
64799 target_arch = "arm",
64800 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64801)]
64802pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
64803 static_assert_uimm_bits!(LANE, 1);
64804 *a = simd_extract!(b, LANE as u32);
64805}
64806#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
64808#[doc = "## Safety"]
64809#[doc = " * Neon instrinsic unsafe"]
64810#[inline]
64811#[target_feature(enable = "neon")]
64812#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64813#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64814#[cfg_attr(
64815 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64816 assert_instr(nop, LANE = 0)
64817)]
64818#[rustc_legacy_const_generics(2)]
64819#[cfg_attr(
64820 not(target_arch = "arm"),
64821 stable(feature = "neon_intrinsics", since = "1.59.0")
64822)]
64823#[cfg_attr(
64824 target_arch = "arm",
64825 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64826)]
64827pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
64828 static_assert_uimm_bits!(LANE, 3);
64829 *a = simd_extract!(b, LANE as u32);
64830}
64831#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64832#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
64833#[doc = "## Safety"]
64834#[doc = " * Neon instrinsic unsafe"]
64835#[inline]
64836#[target_feature(enable = "neon")]
64837#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64838#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64839#[cfg_attr(
64840 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64841 assert_instr(nop, LANE = 0)
64842)]
64843#[rustc_legacy_const_generics(2)]
64844#[cfg_attr(
64845 not(target_arch = "arm"),
64846 stable(feature = "neon_intrinsics", since = "1.59.0")
64847)]
64848#[cfg_attr(
64849 target_arch = "arm",
64850 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64851)]
64852pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
64853 static_assert_uimm_bits!(LANE, 4);
64854 *a = simd_extract!(b, LANE as u32);
64855}
64856#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64857#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
64858#[doc = "## Safety"]
64859#[doc = " * Neon instrinsic unsafe"]
64860#[inline]
64861#[target_feature(enable = "neon")]
64862#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64863#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64864#[cfg_attr(
64865 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64866 assert_instr(nop, LANE = 0)
64867)]
64868#[rustc_legacy_const_generics(2)]
64869#[cfg_attr(
64870 not(target_arch = "arm"),
64871 stable(feature = "neon_intrinsics", since = "1.59.0")
64872)]
64873#[cfg_attr(
64874 target_arch = "arm",
64875 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64876)]
64877pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
64878 static_assert_uimm_bits!(LANE, 2);
64879 *a = simd_extract!(b, LANE as u32);
64880}
64881#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64882#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
64883#[doc = "## Safety"]
64884#[doc = " * Neon instrinsic unsafe"]
64885#[inline]
64886#[target_feature(enable = "neon")]
64887#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64888#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64889#[cfg_attr(
64890 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64891 assert_instr(nop, LANE = 0)
64892)]
64893#[rustc_legacy_const_generics(2)]
64894#[cfg_attr(
64895 not(target_arch = "arm"),
64896 stable(feature = "neon_intrinsics", since = "1.59.0")
64897)]
64898#[cfg_attr(
64899 target_arch = "arm",
64900 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64901)]
64902pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
64903 static_assert_uimm_bits!(LANE, 3);
64904 *a = simd_extract!(b, LANE as u32);
64905}
64906#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64907#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
64908#[doc = "## Safety"]
64909#[doc = " * Neon instrinsic unsafe"]
64910#[inline]
64911#[target_feature(enable = "neon")]
64912#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64913#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64914#[cfg_attr(
64915 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64916 assert_instr(nop, LANE = 0)
64917)]
64918#[rustc_legacy_const_generics(2)]
64919#[cfg_attr(
64920 not(target_arch = "arm"),
64921 stable(feature = "neon_intrinsics", since = "1.59.0")
64922)]
64923#[cfg_attr(
64924 target_arch = "arm",
64925 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64926)]
64927pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
64928 static_assert_uimm_bits!(LANE, 1);
64929 *a = simd_extract!(b, LANE as u32);
64930}
64931#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64932#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
64933#[doc = "## Safety"]
64934#[doc = " * Neon instrinsic unsafe"]
64935#[inline]
64936#[target_feature(enable = "neon")]
64937#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64938#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64939#[cfg_attr(
64940 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64941 assert_instr(nop, LANE = 0)
64942)]
64943#[rustc_legacy_const_generics(2)]
64944#[cfg_attr(
64945 not(target_arch = "arm"),
64946 stable(feature = "neon_intrinsics", since = "1.59.0")
64947)]
64948#[cfg_attr(
64949 target_arch = "arm",
64950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64951)]
64952pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
64953 static_assert_uimm_bits!(LANE, 2);
64954 *a = simd_extract!(b, LANE as u32);
64955}
64956#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64957#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
64958#[doc = "## Safety"]
64959#[doc = " * Neon instrinsic unsafe"]
64960#[inline]
64961#[target_feature(enable = "neon")]
64962#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64963#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64964#[cfg_attr(
64965 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64966 assert_instr(nop, LANE = 0)
64967)]
64968#[rustc_legacy_const_generics(2)]
64969#[cfg_attr(
64970 not(target_arch = "arm"),
64971 stable(feature = "neon_intrinsics", since = "1.59.0")
64972)]
64973#[cfg_attr(
64974 target_arch = "arm",
64975 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
64976)]
64977pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
64978 static_assert_uimm_bits!(LANE, 1);
64979 *a = simd_extract!(b, LANE as u32);
64980}
64981#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
64982#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
64983#[doc = "## Safety"]
64984#[doc = " * Neon instrinsic unsafe"]
64985#[inline]
64986#[target_feature(enable = "neon")]
64987#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
64988#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
64989#[cfg_attr(
64990 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
64991 assert_instr(nop, LANE = 0)
64992)]
64993#[rustc_legacy_const_generics(2)]
64994#[cfg_attr(
64995 not(target_arch = "arm"),
64996 stable(feature = "neon_intrinsics", since = "1.59.0")
64997)]
64998#[cfg_attr(
64999 target_arch = "arm",
65000 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65001)]
65002pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
65003 static_assert_uimm_bits!(LANE, 3);
65004 *a = simd_extract!(b, LANE as u32);
65005}
65006#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
65008#[doc = "## Safety"]
65009#[doc = " * Neon instrinsic unsafe"]
65010#[inline]
65011#[target_feature(enable = "neon")]
65012#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65013#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65014#[cfg_attr(
65015 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65016 assert_instr(nop, LANE = 0)
65017)]
65018#[rustc_legacy_const_generics(2)]
65019#[cfg_attr(
65020 not(target_arch = "arm"),
65021 stable(feature = "neon_intrinsics", since = "1.59.0")
65022)]
65023#[cfg_attr(
65024 target_arch = "arm",
65025 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65026)]
65027pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
65028 static_assert_uimm_bits!(LANE, 4);
65029 *a = simd_extract!(b, LANE as u32);
65030}
65031#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65032#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
65033#[doc = "## Safety"]
65034#[doc = " * Neon instrinsic unsafe"]
65035#[inline]
65036#[target_feature(enable = "neon")]
65037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65038#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65039#[cfg_attr(
65040 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65041 assert_instr(nop, LANE = 0)
65042)]
65043#[rustc_legacy_const_generics(2)]
65044#[cfg_attr(
65045 not(target_arch = "arm"),
65046 stable(feature = "neon_intrinsics", since = "1.59.0")
65047)]
65048#[cfg_attr(
65049 target_arch = "arm",
65050 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65051)]
65052pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
65053 static_assert_uimm_bits!(LANE, 2);
65054 *a = simd_extract!(b, LANE as u32);
65055}
65056#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
65058#[doc = "## Safety"]
65059#[doc = " * Neon instrinsic unsafe"]
65060#[inline]
65061#[target_feature(enable = "neon")]
65062#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65063#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65064#[cfg_attr(
65065 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65066 assert_instr(nop, LANE = 0)
65067)]
65068#[rustc_legacy_const_generics(2)]
65069#[cfg_attr(
65070 not(target_arch = "arm"),
65071 stable(feature = "neon_intrinsics", since = "1.59.0")
65072)]
65073#[cfg_attr(
65074 target_arch = "arm",
65075 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65076)]
65077pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
65078 static_assert_uimm_bits!(LANE, 3);
65079 *a = simd_extract!(b, LANE as u32);
65080}
65081#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
65083#[doc = "## Safety"]
65084#[doc = " * Neon instrinsic unsafe"]
65085#[inline]
65086#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65087#[target_feature(enable = "neon,aes")]
65088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65089#[cfg_attr(
65090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65091 assert_instr(nop, LANE = 0)
65092)]
65093#[rustc_legacy_const_generics(2)]
65094#[cfg_attr(
65095 not(target_arch = "arm"),
65096 stable(feature = "neon_intrinsics", since = "1.59.0")
65097)]
65098#[cfg_attr(
65099 target_arch = "arm",
65100 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65101)]
65102pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
65103 static_assert!(LANE == 0);
65104 *a = simd_extract!(b, LANE as u32);
65105}
65106#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65107#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
65108#[doc = "## Safety"]
65109#[doc = " * Neon instrinsic unsafe"]
65110#[inline]
65111#[target_feature(enable = "neon")]
65112#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65113#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65114#[cfg_attr(
65115 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65116 assert_instr(nop, LANE = 0)
65117)]
65118#[rustc_legacy_const_generics(2)]
65119#[cfg_attr(
65120 not(target_arch = "arm"),
65121 stable(feature = "neon_intrinsics", since = "1.59.0")
65122)]
65123#[cfg_attr(
65124 target_arch = "arm",
65125 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65126)]
65127pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
65128 static_assert!(LANE == 0);
65129 *a = simd_extract!(b, LANE as u32);
65130}
65131#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65132#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
65133#[doc = "## Safety"]
65134#[doc = " * Neon instrinsic unsafe"]
65135#[inline]
65136#[target_feature(enable = "neon")]
65137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
65138#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
65139#[cfg_attr(
65140 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65141 assert_instr(nop, LANE = 0)
65142)]
65143#[rustc_legacy_const_generics(2)]
65144#[cfg_attr(
65145 not(target_arch = "arm"),
65146 stable(feature = "neon_intrinsics", since = "1.59.0")
65147)]
65148#[cfg_attr(
65149 target_arch = "arm",
65150 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65151)]
65152pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
65153 static_assert!(LANE == 0);
65154 *a = simd_extract!(b, LANE as u32);
65155}
65156#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65157#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
65158#[doc = "## Safety"]
65159#[doc = " * Neon instrinsic unsafe"]
65160#[inline]
65161#[target_feature(enable = "neon,aes")]
65162#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65163#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
65164#[cfg_attr(
65165 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65166 assert_instr(st1)
65167)]
65168#[cfg_attr(
65169 not(target_arch = "arm"),
65170 stable(feature = "neon_intrinsics", since = "1.59.0")
65171)]
65172#[cfg_attr(
65173 target_arch = "arm",
65174 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65175)]
65176pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
65177 vst1_s64_x2(transmute(a), transmute(b))
65178}
65179#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
65181#[doc = "## Safety"]
65182#[doc = " * Neon instrinsic unsafe"]
65183#[inline]
65184#[target_feature(enable = "neon,aes")]
65185#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65186#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65187#[cfg_attr(
65188 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65189 assert_instr(st1)
65190)]
65191#[cfg_attr(
65192 not(target_arch = "arm"),
65193 stable(feature = "neon_intrinsics", since = "1.59.0")
65194)]
65195#[cfg_attr(
65196 target_arch = "arm",
65197 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65198)]
65199pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
65200 vst1_s64_x3(transmute(a), transmute(b))
65201}
65202#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65203#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
65204#[doc = "## Safety"]
65205#[doc = " * Neon instrinsic unsafe"]
65206#[inline]
65207#[target_feature(enable = "neon,aes")]
65208#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65209#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65210#[cfg_attr(
65211 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65212 assert_instr(st1)
65213)]
65214#[cfg_attr(
65215 not(target_arch = "arm"),
65216 stable(feature = "neon_intrinsics", since = "1.59.0")
65217)]
65218#[cfg_attr(
65219 target_arch = "arm",
65220 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65221)]
65222pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
65223 vst1_s64_x4(transmute(a), transmute(b))
65224}
65225#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65226#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
65227#[doc = "## Safety"]
65228#[doc = " * Neon instrinsic unsafe"]
65229#[inline]
65230#[target_feature(enable = "neon,aes")]
65231#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65232#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65233#[cfg_attr(
65234 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65235 assert_instr(st1)
65236)]
65237#[cfg_attr(
65238 not(target_arch = "arm"),
65239 stable(feature = "neon_intrinsics", since = "1.59.0")
65240)]
65241#[cfg_attr(
65242 target_arch = "arm",
65243 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65244)]
65245pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
65246 vst1q_s64_x2(transmute(a), transmute(b))
65247}
65248#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65249#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
65250#[doc = "## Safety"]
65251#[doc = " * Neon instrinsic unsafe"]
65252#[inline]
65253#[target_feature(enable = "neon,aes")]
65254#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65255#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65256#[cfg_attr(
65257 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65258 assert_instr(st1)
65259)]
65260#[cfg_attr(
65261 not(target_arch = "arm"),
65262 stable(feature = "neon_intrinsics", since = "1.59.0")
65263)]
65264#[cfg_attr(
65265 target_arch = "arm",
65266 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65267)]
65268pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
65269 vst1q_s64_x3(transmute(a), transmute(b))
65270}
65271#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
65272#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
65273#[doc = "## Safety"]
65274#[doc = " * Neon instrinsic unsafe"]
65275#[inline]
65276#[target_feature(enable = "neon,aes")]
65277#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
65278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
65279#[cfg_attr(
65280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
65281 assert_instr(st1)
65282)]
65283#[cfg_attr(
65284 not(target_arch = "arm"),
65285 stable(feature = "neon_intrinsics", since = "1.59.0")
65286)]
65287#[cfg_attr(
65288 target_arch = "arm",
65289 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
65290)]
65291pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
65292 vst1q_s64_x4(transmute(a), transmute(b))
65293}
65294#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65295#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65296#[doc = "## Safety"]
65297#[doc = " * Neon instrinsic unsafe"]
65298#[inline]
65299#[target_feature(enable = "neon")]
65300#[cfg(not(target_arch = "arm"))]
65301#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65302#[cfg_attr(test, assert_instr(st1))]
65303pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65304 unsafe extern "unadjusted" {
65305 #[cfg_attr(
65306 any(target_arch = "aarch64", target_arch = "arm64ec"),
65307 link_name = "llvm.aarch64.neon.st1x2.v8i8.p0"
65308 )]
65309 fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
65310 }
65311 _vst1_s8_x2(b.0, b.1, a)
65312}
65313#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65314#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65315#[doc = "## Safety"]
65316#[doc = " * Neon instrinsic unsafe"]
65317#[inline]
65318#[target_feature(enable = "neon")]
65319#[cfg(not(target_arch = "arm"))]
65320#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65321#[cfg_attr(test, assert_instr(st1))]
65322pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65323 unsafe extern "unadjusted" {
65324 #[cfg_attr(
65325 any(target_arch = "aarch64", target_arch = "arm64ec"),
65326 link_name = "llvm.aarch64.neon.st1x2.v16i8.p0"
65327 )]
65328 fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
65329 }
65330 _vst1q_s8_x2(b.0, b.1, a)
65331}
65332#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65334#[doc = "## Safety"]
65335#[doc = " * Neon instrinsic unsafe"]
65336#[inline]
65337#[target_feature(enable = "neon")]
65338#[cfg(not(target_arch = "arm"))]
65339#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65340#[cfg_attr(test, assert_instr(st1))]
65341pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65342 unsafe extern "unadjusted" {
65343 #[cfg_attr(
65344 any(target_arch = "aarch64", target_arch = "arm64ec"),
65345 link_name = "llvm.aarch64.neon.st1x2.v4i16.p0"
65346 )]
65347 fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16);
65348 }
65349 _vst1_s16_x2(b.0, b.1, a)
65350}
65351#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65352#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65353#[doc = "## Safety"]
65354#[doc = " * Neon instrinsic unsafe"]
65355#[inline]
65356#[target_feature(enable = "neon")]
65357#[cfg(not(target_arch = "arm"))]
65358#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65359#[cfg_attr(test, assert_instr(st1))]
65360pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65361 unsafe extern "unadjusted" {
65362 #[cfg_attr(
65363 any(target_arch = "aarch64", target_arch = "arm64ec"),
65364 link_name = "llvm.aarch64.neon.st1x2.v8i16.p0"
65365 )]
65366 fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16);
65367 }
65368 _vst1q_s16_x2(b.0, b.1, a)
65369}
65370#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65371#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65372#[doc = "## Safety"]
65373#[doc = " * Neon instrinsic unsafe"]
65374#[inline]
65375#[target_feature(enable = "neon")]
65376#[cfg(not(target_arch = "arm"))]
65377#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65378#[cfg_attr(test, assert_instr(st1))]
65379pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65380 unsafe extern "unadjusted" {
65381 #[cfg_attr(
65382 any(target_arch = "aarch64", target_arch = "arm64ec"),
65383 link_name = "llvm.aarch64.neon.st1x2.v2i32.p0"
65384 )]
65385 fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32);
65386 }
65387 _vst1_s32_x2(b.0, b.1, a)
65388}
65389#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65390#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65391#[doc = "## Safety"]
65392#[doc = " * Neon instrinsic unsafe"]
65393#[inline]
65394#[target_feature(enable = "neon")]
65395#[cfg(not(target_arch = "arm"))]
65396#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65397#[cfg_attr(test, assert_instr(st1))]
65398pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65399 unsafe extern "unadjusted" {
65400 #[cfg_attr(
65401 any(target_arch = "aarch64", target_arch = "arm64ec"),
65402 link_name = "llvm.aarch64.neon.st1x2.v4i32.p0"
65403 )]
65404 fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32);
65405 }
65406 _vst1q_s32_x2(b.0, b.1, a)
65407}
65408#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65409#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65410#[doc = "## Safety"]
65411#[doc = " * Neon instrinsic unsafe"]
65412#[inline]
65413#[target_feature(enable = "neon")]
65414#[cfg(not(target_arch = "arm"))]
65415#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65416#[cfg_attr(test, assert_instr(st1))]
65417pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65418 unsafe extern "unadjusted" {
65419 #[cfg_attr(
65420 any(target_arch = "aarch64", target_arch = "arm64ec"),
65421 link_name = "llvm.aarch64.neon.st1x2.v1i64.p0"
65422 )]
65423 fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64);
65424 }
65425 _vst1_s64_x2(b.0, b.1, a)
65426}
65427#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65429#[doc = "## Safety"]
65430#[doc = " * Neon instrinsic unsafe"]
65431#[inline]
65432#[target_feature(enable = "neon")]
65433#[cfg(not(target_arch = "arm"))]
65434#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65435#[cfg_attr(test, assert_instr(st1))]
65436pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65437 unsafe extern "unadjusted" {
65438 #[cfg_attr(
65439 any(target_arch = "aarch64", target_arch = "arm64ec"),
65440 link_name = "llvm.aarch64.neon.st1x2.v2i64.p0"
65441 )]
65442 fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64);
65443 }
65444 _vst1q_s64_x2(b.0, b.1, a)
65445}
65446#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65447#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
65448#[doc = "## Safety"]
65449#[doc = " * Neon instrinsic unsafe"]
65450#[inline]
65451#[target_feature(enable = "neon,v7")]
65452#[cfg(target_arch = "arm")]
65453#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65454#[cfg_attr(test, assert_instr(vst1))]
65455pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
65456 unsafe extern "unadjusted" {
65457 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i8.p0")]
65458 fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t);
65459 }
65460 _vst1_s8_x2(a, b.0, b.1)
65461}
65462#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65463#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
65464#[doc = "## Safety"]
65465#[doc = " * Neon instrinsic unsafe"]
65466#[inline]
65467#[target_feature(enable = "neon,v7")]
65468#[cfg(target_arch = "arm")]
65469#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65470#[cfg_attr(test, assert_instr(vst1))]
65471pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
65472 unsafe extern "unadjusted" {
65473 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v16i8.p0")]
65474 fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t);
65475 }
65476 _vst1q_s8_x2(a, b.0, b.1)
65477}
65478#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65479#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
65480#[doc = "## Safety"]
65481#[doc = " * Neon instrinsic unsafe"]
65482#[inline]
65483#[target_feature(enable = "neon,v7")]
65484#[cfg(target_arch = "arm")]
65485#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65486#[cfg_attr(test, assert_instr(vst1))]
65487pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
65488 unsafe extern "unadjusted" {
65489 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i16.p0")]
65490 fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t);
65491 }
65492 _vst1_s16_x2(a, b.0, b.1)
65493}
65494#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65495#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
65496#[doc = "## Safety"]
65497#[doc = " * Neon instrinsic unsafe"]
65498#[inline]
65499#[target_feature(enable = "neon,v7")]
65500#[cfg(target_arch = "arm")]
65501#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65502#[cfg_attr(test, assert_instr(vst1))]
65503pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
65504 unsafe extern "unadjusted" {
65505 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v8i16.p0")]
65506 fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t);
65507 }
65508 _vst1q_s16_x2(a, b.0, b.1)
65509}
65510#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65511#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
65512#[doc = "## Safety"]
65513#[doc = " * Neon instrinsic unsafe"]
65514#[inline]
65515#[target_feature(enable = "neon,v7")]
65516#[cfg(target_arch = "arm")]
65517#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65518#[cfg_attr(test, assert_instr(vst1))]
65519pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
65520 unsafe extern "unadjusted" {
65521 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i32.p0")]
65522 fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t);
65523 }
65524 _vst1_s32_x2(a, b.0, b.1)
65525}
65526#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65527#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
65528#[doc = "## Safety"]
65529#[doc = " * Neon instrinsic unsafe"]
65530#[inline]
65531#[target_feature(enable = "neon,v7")]
65532#[cfg(target_arch = "arm")]
65533#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65534#[cfg_attr(test, assert_instr(vst1))]
65535pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
65536 unsafe extern "unadjusted" {
65537 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v4i32.p0")]
65538 fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t);
65539 }
65540 _vst1q_s32_x2(a, b.0, b.1)
65541}
65542#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65543#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
65544#[doc = "## Safety"]
65545#[doc = " * Neon instrinsic unsafe"]
65546#[inline]
65547#[target_feature(enable = "neon,v7")]
65548#[cfg(target_arch = "arm")]
65549#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65550#[cfg_attr(test, assert_instr(vst1))]
65551pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
65552 unsafe extern "unadjusted" {
65553 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v1i64.p0")]
65554 fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t);
65555 }
65556 _vst1_s64_x2(a, b.0, b.1)
65557}
65558#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
65560#[doc = "## Safety"]
65561#[doc = " * Neon instrinsic unsafe"]
65562#[inline]
65563#[target_feature(enable = "neon,v7")]
65564#[cfg(target_arch = "arm")]
65565#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65566#[cfg_attr(test, assert_instr(vst1))]
65567pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
65568 unsafe extern "unadjusted" {
65569 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.v2i64.p0")]
65570 fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t);
65571 }
65572 _vst1q_s64_x2(a, b.0, b.1)
65573}
65574#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65575#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
65576#[doc = "## Safety"]
65577#[doc = " * Neon instrinsic unsafe"]
65578#[inline]
65579#[target_feature(enable = "neon")]
65580#[cfg(not(target_arch = "arm"))]
65581#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65582#[cfg_attr(test, assert_instr(st1))]
65583pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
65584 unsafe extern "unadjusted" {
65585 #[cfg_attr(
65586 any(target_arch = "aarch64", target_arch = "arm64ec"),
65587 link_name = "llvm.aarch64.neon.st1x3.v8i8.p0"
65588 )]
65589 fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
65590 }
65591 _vst1_s8_x3(b.0, b.1, b.2, a)
65592}
65593#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65594#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
65595#[doc = "## Safety"]
65596#[doc = " * Neon instrinsic unsafe"]
65597#[inline]
65598#[target_feature(enable = "neon")]
65599#[cfg(not(target_arch = "arm"))]
65600#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65601#[cfg_attr(test, assert_instr(st1))]
65602pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
65603 unsafe extern "unadjusted" {
65604 #[cfg_attr(
65605 any(target_arch = "aarch64", target_arch = "arm64ec"),
65606 link_name = "llvm.aarch64.neon.st1x3.v16i8.p0"
65607 )]
65608 fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
65609 }
65610 _vst1q_s8_x3(b.0, b.1, b.2, a)
65611}
65612#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65613#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
65614#[doc = "## Safety"]
65615#[doc = " * Neon instrinsic unsafe"]
65616#[inline]
65617#[target_feature(enable = "neon")]
65618#[cfg(not(target_arch = "arm"))]
65619#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65620#[cfg_attr(test, assert_instr(st1))]
65621pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
65622 unsafe extern "unadjusted" {
65623 #[cfg_attr(
65624 any(target_arch = "aarch64", target_arch = "arm64ec"),
65625 link_name = "llvm.aarch64.neon.st1x3.v4i16.p0"
65626 )]
65627 fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16);
65628 }
65629 _vst1_s16_x3(b.0, b.1, b.2, a)
65630}
65631#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65632#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
65633#[doc = "## Safety"]
65634#[doc = " * Neon instrinsic unsafe"]
65635#[inline]
65636#[target_feature(enable = "neon")]
65637#[cfg(not(target_arch = "arm"))]
65638#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65639#[cfg_attr(test, assert_instr(st1))]
65640pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
65641 unsafe extern "unadjusted" {
65642 #[cfg_attr(
65643 any(target_arch = "aarch64", target_arch = "arm64ec"),
65644 link_name = "llvm.aarch64.neon.st1x3.v8i16.p0"
65645 )]
65646 fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16);
65647 }
65648 _vst1q_s16_x3(b.0, b.1, b.2, a)
65649}
65650#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
65652#[doc = "## Safety"]
65653#[doc = " * Neon instrinsic unsafe"]
65654#[inline]
65655#[target_feature(enable = "neon")]
65656#[cfg(not(target_arch = "arm"))]
65657#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65658#[cfg_attr(test, assert_instr(st1))]
65659pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
65660 unsafe extern "unadjusted" {
65661 #[cfg_attr(
65662 any(target_arch = "aarch64", target_arch = "arm64ec"),
65663 link_name = "llvm.aarch64.neon.st1x3.v2i32.p0"
65664 )]
65665 fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32);
65666 }
65667 _vst1_s32_x3(b.0, b.1, b.2, a)
65668}
65669#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
65671#[doc = "## Safety"]
65672#[doc = " * Neon instrinsic unsafe"]
65673#[inline]
65674#[target_feature(enable = "neon")]
65675#[cfg(not(target_arch = "arm"))]
65676#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65677#[cfg_attr(test, assert_instr(st1))]
65678pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
65679 unsafe extern "unadjusted" {
65680 #[cfg_attr(
65681 any(target_arch = "aarch64", target_arch = "arm64ec"),
65682 link_name = "llvm.aarch64.neon.st1x3.v4i32.p0"
65683 )]
65684 fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32);
65685 }
65686 _vst1q_s32_x3(b.0, b.1, b.2, a)
65687}
65688#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65689#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
65690#[doc = "## Safety"]
65691#[doc = " * Neon instrinsic unsafe"]
65692#[inline]
65693#[target_feature(enable = "neon")]
65694#[cfg(not(target_arch = "arm"))]
65695#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65696#[cfg_attr(test, assert_instr(st1))]
65697pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
65698 unsafe extern "unadjusted" {
65699 #[cfg_attr(
65700 any(target_arch = "aarch64", target_arch = "arm64ec"),
65701 link_name = "llvm.aarch64.neon.st1x3.v1i64.p0"
65702 )]
65703 fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64);
65704 }
65705 _vst1_s64_x3(b.0, b.1, b.2, a)
65706}
65707#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
65709#[doc = "## Safety"]
65710#[doc = " * Neon instrinsic unsafe"]
65711#[inline]
65712#[target_feature(enable = "neon")]
65713#[cfg(not(target_arch = "arm"))]
65714#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65715#[cfg_attr(test, assert_instr(st1))]
65716pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
65717 unsafe extern "unadjusted" {
65718 #[cfg_attr(
65719 any(target_arch = "aarch64", target_arch = "arm64ec"),
65720 link_name = "llvm.aarch64.neon.st1x3.v2i64.p0"
65721 )]
65722 fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64);
65723 }
65724 _vst1q_s64_x3(b.0, b.1, b.2, a)
65725}
65726#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65727#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
65728#[doc = "## Safety"]
65729#[doc = " * Neon instrinsic unsafe"]
65730#[inline]
65731#[target_feature(enable = "neon,v7")]
65732#[cfg(target_arch = "arm")]
65733#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65734#[cfg_attr(test, assert_instr(vst1))]
65735pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
65736 unsafe extern "unadjusted" {
65737 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8i8.p0")]
65738 fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t);
65739 }
65740 _vst1_s8_x3(a, b.0, b.1, b.2)
65741}
65742#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
65744#[doc = "## Safety"]
65745#[doc = " * Neon instrinsic unsafe"]
65746#[inline]
65747#[target_feature(enable = "neon,v7")]
65748#[cfg(target_arch = "arm")]
65749#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65750#[cfg_attr(test, assert_instr(vst1))]
65751pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
65752 unsafe extern "unadjusted" {
65753 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v16i8.p0")]
65754 fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t);
65755 }
65756 _vst1q_s8_x3(a, b.0, b.1, b.2)
65757}
65758#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65759#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
65760#[doc = "## Safety"]
65761#[doc = " * Neon instrinsic unsafe"]
65762#[inline]
65763#[target_feature(enable = "neon,v7")]
65764#[cfg(target_arch = "arm")]
65765#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65766#[cfg_attr(test, assert_instr(vst1))]
65767pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
65768 unsafe extern "unadjusted" {
65769 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4i16.p0")]
65770 fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t);
65771 }
65772 _vst1_s16_x3(a, b.0, b.1, b.2)
65773}
65774#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65775#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
65776#[doc = "## Safety"]
65777#[doc = " * Neon instrinsic unsafe"]
65778#[inline]
65779#[target_feature(enable = "neon,v7")]
65780#[cfg(target_arch = "arm")]
65781#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65782#[cfg_attr(test, assert_instr(vst1))]
65783pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
65784 unsafe extern "unadjusted" {
65785 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v8i16.p0")]
65786 fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t);
65787 }
65788 _vst1q_s16_x3(a, b.0, b.1, b.2)
65789}
65790#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65791#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
65792#[doc = "## Safety"]
65793#[doc = " * Neon instrinsic unsafe"]
65794#[inline]
65795#[target_feature(enable = "neon,v7")]
65796#[cfg(target_arch = "arm")]
65797#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65798#[cfg_attr(test, assert_instr(vst1))]
65799pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
65800 unsafe extern "unadjusted" {
65801 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v2i32.p0")]
65802 fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t);
65803 }
65804 _vst1_s32_x3(a, b.0, b.1, b.2)
65805}
65806#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
65808#[doc = "## Safety"]
65809#[doc = " * Neon instrinsic unsafe"]
65810#[inline]
65811#[target_feature(enable = "neon,v7")]
65812#[cfg(target_arch = "arm")]
65813#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65814#[cfg_attr(test, assert_instr(vst1))]
65815pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
65816 unsafe extern "unadjusted" {
65817 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v4i32.p0")]
65818 fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t);
65819 }
65820 _vst1q_s32_x3(a, b.0, b.1, b.2)
65821}
65822#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65823#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
65824#[doc = "## Safety"]
65825#[doc = " * Neon instrinsic unsafe"]
65826#[inline]
65827#[target_feature(enable = "neon,v7")]
65828#[cfg(target_arch = "arm")]
65829#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65830#[cfg_attr(test, assert_instr(vst1))]
65831pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
65832 unsafe extern "unadjusted" {
65833 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v1i64.p0")]
65834 fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t);
65835 }
65836 _vst1_s64_x3(a, b.0, b.1, b.2)
65837}
65838#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65839#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
65840#[doc = "## Safety"]
65841#[doc = " * Neon instrinsic unsafe"]
65842#[inline]
65843#[target_feature(enable = "neon,v7")]
65844#[cfg(target_arch = "arm")]
65845#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
65846#[cfg_attr(test, assert_instr(vst1))]
65847pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
65848 unsafe extern "unadjusted" {
65849 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0.v2i64.p0")]
65850 fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t);
65851 }
65852 _vst1q_s64_x3(a, b.0, b.1, b.2)
65853}
65854#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65855#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
65856#[doc = "## Safety"]
65857#[doc = " * Neon instrinsic unsafe"]
65858#[inline]
65859#[target_feature(enable = "neon")]
65860#[cfg(not(target_arch = "arm"))]
65861#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65862#[cfg_attr(test, assert_instr(st1))]
65863pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
65864 unsafe extern "unadjusted" {
65865 #[cfg_attr(
65866 any(target_arch = "aarch64", target_arch = "arm64ec"),
65867 link_name = "llvm.aarch64.neon.st1x4.v8i8.p0"
65868 )]
65869 fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
65870 }
65871 _vst1_s8_x4(b.0, b.1, b.2, b.3, a)
65872}
65873#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
65875#[doc = "## Safety"]
65876#[doc = " * Neon instrinsic unsafe"]
65877#[inline]
65878#[target_feature(enable = "neon")]
65879#[cfg(not(target_arch = "arm"))]
65880#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65881#[cfg_attr(test, assert_instr(st1))]
65882pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
65883 unsafe extern "unadjusted" {
65884 #[cfg_attr(
65885 any(target_arch = "aarch64", target_arch = "arm64ec"),
65886 link_name = "llvm.aarch64.neon.st1x4.v16i8.p0"
65887 )]
65888 fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
65889 }
65890 _vst1q_s8_x4(b.0, b.1, b.2, b.3, a)
65891}
65892#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65893#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
65894#[doc = "## Safety"]
65895#[doc = " * Neon instrinsic unsafe"]
65896#[inline]
65897#[target_feature(enable = "neon")]
65898#[cfg(not(target_arch = "arm"))]
65899#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65900#[cfg_attr(test, assert_instr(st1))]
65901pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
65902 unsafe extern "unadjusted" {
65903 #[cfg_attr(
65904 any(target_arch = "aarch64", target_arch = "arm64ec"),
65905 link_name = "llvm.aarch64.neon.st1x4.v4i16.p0"
65906 )]
65907 fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16);
65908 }
65909 _vst1_s16_x4(b.0, b.1, b.2, b.3, a)
65910}
65911#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
65913#[doc = "## Safety"]
65914#[doc = " * Neon instrinsic unsafe"]
65915#[inline]
65916#[target_feature(enable = "neon")]
65917#[cfg(not(target_arch = "arm"))]
65918#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65919#[cfg_attr(test, assert_instr(st1))]
65920pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
65921 unsafe extern "unadjusted" {
65922 #[cfg_attr(
65923 any(target_arch = "aarch64", target_arch = "arm64ec"),
65924 link_name = "llvm.aarch64.neon.st1x4.v8i16.p0"
65925 )]
65926 fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16);
65927 }
65928 _vst1q_s16_x4(b.0, b.1, b.2, b.3, a)
65929}
65930#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
65932#[doc = "## Safety"]
65933#[doc = " * Neon instrinsic unsafe"]
65934#[inline]
65935#[target_feature(enable = "neon")]
65936#[cfg(not(target_arch = "arm"))]
65937#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65938#[cfg_attr(test, assert_instr(st1))]
65939pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
65940 unsafe extern "unadjusted" {
65941 #[cfg_attr(
65942 any(target_arch = "aarch64", target_arch = "arm64ec"),
65943 link_name = "llvm.aarch64.neon.st1x4.v2i32.p0"
65944 )]
65945 fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32);
65946 }
65947 _vst1_s32_x4(b.0, b.1, b.2, b.3, a)
65948}
65949#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65950#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
65951#[doc = "## Safety"]
65952#[doc = " * Neon instrinsic unsafe"]
65953#[inline]
65954#[target_feature(enable = "neon")]
65955#[cfg(not(target_arch = "arm"))]
65956#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65957#[cfg_attr(test, assert_instr(st1))]
65958pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
65959 unsafe extern "unadjusted" {
65960 #[cfg_attr(
65961 any(target_arch = "aarch64", target_arch = "arm64ec"),
65962 link_name = "llvm.aarch64.neon.st1x4.v4i32.p0"
65963 )]
65964 fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32);
65965 }
65966 _vst1q_s32_x4(b.0, b.1, b.2, b.3, a)
65967}
65968#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65969#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
65970#[doc = "## Safety"]
65971#[doc = " * Neon instrinsic unsafe"]
65972#[inline]
65973#[target_feature(enable = "neon")]
65974#[cfg(not(target_arch = "arm"))]
65975#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65976#[cfg_attr(test, assert_instr(st1))]
65977pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
65978 unsafe extern "unadjusted" {
65979 #[cfg_attr(
65980 any(target_arch = "aarch64", target_arch = "arm64ec"),
65981 link_name = "llvm.aarch64.neon.st1x4.v1i64.p0"
65982 )]
65983 fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64);
65984 }
65985 _vst1_s64_x4(b.0, b.1, b.2, b.3, a)
65986}
65987#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
65988#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
65989#[doc = "## Safety"]
65990#[doc = " * Neon instrinsic unsafe"]
65991#[inline]
65992#[target_feature(enable = "neon")]
65993#[cfg(not(target_arch = "arm"))]
65994#[stable(feature = "neon_intrinsics", since = "1.59.0")]
65995#[cfg_attr(test, assert_instr(st1))]
65996pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
65997 unsafe extern "unadjusted" {
65998 #[cfg_attr(
65999 any(target_arch = "aarch64", target_arch = "arm64ec"),
66000 link_name = "llvm.aarch64.neon.st1x4.v2i64.p0"
66001 )]
66002 fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64);
66003 }
66004 _vst1q_s64_x4(b.0, b.1, b.2, b.3, a)
66005}
66006#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66007#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
66008#[doc = "## Safety"]
66009#[doc = " * Neon instrinsic unsafe"]
66010#[inline]
66011#[cfg(target_arch = "arm")]
66012#[target_feature(enable = "neon,v7")]
66013#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66014#[cfg_attr(test, assert_instr(vst1))]
66015pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
66016 unsafe extern "unadjusted" {
66017 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8i8.p0")]
66018 fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t);
66019 }
66020 _vst1_s8_x4(a, b.0, b.1, b.2, b.3)
66021}
66022#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66023#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
66024#[doc = "## Safety"]
66025#[doc = " * Neon instrinsic unsafe"]
66026#[inline]
66027#[cfg(target_arch = "arm")]
66028#[target_feature(enable = "neon,v7")]
66029#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66030#[cfg_attr(test, assert_instr(vst1))]
66031pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
66032 unsafe extern "unadjusted" {
66033 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v16i8.p0")]
66034 fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t);
66035 }
66036 _vst1q_s8_x4(a, b.0, b.1, b.2, b.3)
66037}
66038#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66039#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
66040#[doc = "## Safety"]
66041#[doc = " * Neon instrinsic unsafe"]
66042#[inline]
66043#[cfg(target_arch = "arm")]
66044#[target_feature(enable = "neon,v7")]
66045#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66046#[cfg_attr(test, assert_instr(vst1))]
66047pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
66048 unsafe extern "unadjusted" {
66049 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4i16.p0")]
66050 fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t);
66051 }
66052 _vst1_s16_x4(a, b.0, b.1, b.2, b.3)
66053}
66054#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66055#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
66056#[doc = "## Safety"]
66057#[doc = " * Neon instrinsic unsafe"]
66058#[inline]
66059#[cfg(target_arch = "arm")]
66060#[target_feature(enable = "neon,v7")]
66061#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66062#[cfg_attr(test, assert_instr(vst1))]
66063pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
66064 unsafe extern "unadjusted" {
66065 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v8i16.p0")]
66066 fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t);
66067 }
66068 _vst1q_s16_x4(a, b.0, b.1, b.2, b.3)
66069}
66070#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
66072#[doc = "## Safety"]
66073#[doc = " * Neon instrinsic unsafe"]
66074#[inline]
66075#[cfg(target_arch = "arm")]
66076#[target_feature(enable = "neon,v7")]
66077#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66078#[cfg_attr(test, assert_instr(vst1))]
66079pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
66080 unsafe extern "unadjusted" {
66081 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2i32.p0")]
66082 fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t);
66083 }
66084 _vst1_s32_x4(a, b.0, b.1, b.2, b.3)
66085}
66086#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66087#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
66088#[doc = "## Safety"]
66089#[doc = " * Neon instrinsic unsafe"]
66090#[inline]
66091#[cfg(target_arch = "arm")]
66092#[target_feature(enable = "neon,v7")]
66093#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66094#[cfg_attr(test, assert_instr(vst1))]
66095pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
66096 unsafe extern "unadjusted" {
66097 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v4i32.p0")]
66098 fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t);
66099 }
66100 _vst1q_s32_x4(a, b.0, b.1, b.2, b.3)
66101}
66102#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66103#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
66104#[doc = "## Safety"]
66105#[doc = " * Neon instrinsic unsafe"]
66106#[inline]
66107#[cfg(target_arch = "arm")]
66108#[target_feature(enable = "neon,v7")]
66109#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66110#[cfg_attr(test, assert_instr(vst1))]
66111pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
66112 unsafe extern "unadjusted" {
66113 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v1i64.p0")]
66114 fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t);
66115 }
66116 _vst1_s64_x4(a, b.0, b.1, b.2, b.3)
66117}
66118#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
66119#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
66120#[doc = "## Safety"]
66121#[doc = " * Neon instrinsic unsafe"]
66122#[inline]
66123#[cfg(target_arch = "arm")]
66124#[target_feature(enable = "neon,v7")]
66125#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66126#[cfg_attr(test, assert_instr(vst1))]
66127pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
66128 unsafe extern "unadjusted" {
66129 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0.v2i64.p0")]
66130 fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t);
66131 }
66132 _vst1q_s64_x4(a, b.0, b.1, b.2, b.3)
66133}
66134#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66135#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
66136#[doc = "## Safety"]
66137#[doc = " * Neon instrinsic unsafe"]
66138#[inline]
66139#[target_feature(enable = "neon")]
66140#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66141#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66142#[cfg_attr(
66143 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66144 assert_instr(st1)
66145)]
66146#[cfg_attr(
66147 not(target_arch = "arm"),
66148 stable(feature = "neon_intrinsics", since = "1.59.0")
66149)]
66150#[cfg_attr(
66151 target_arch = "arm",
66152 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66153)]
66154pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
66155 vst1_s8_x2(transmute(a), transmute(b))
66156}
66157#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66158#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
66159#[doc = "## Safety"]
66160#[doc = " * Neon instrinsic unsafe"]
66161#[inline]
66162#[target_feature(enable = "neon")]
66163#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66164#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66165#[cfg_attr(
66166 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66167 assert_instr(st1)
66168)]
66169#[cfg_attr(
66170 not(target_arch = "arm"),
66171 stable(feature = "neon_intrinsics", since = "1.59.0")
66172)]
66173#[cfg_attr(
66174 target_arch = "arm",
66175 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66176)]
66177pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
66178 vst1_s8_x3(transmute(a), transmute(b))
66179}
66180#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66181#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
66182#[doc = "## Safety"]
66183#[doc = " * Neon instrinsic unsafe"]
66184#[inline]
66185#[target_feature(enable = "neon")]
66186#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66187#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66188#[cfg_attr(
66189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66190 assert_instr(st1)
66191)]
66192#[cfg_attr(
66193 not(target_arch = "arm"),
66194 stable(feature = "neon_intrinsics", since = "1.59.0")
66195)]
66196#[cfg_attr(
66197 target_arch = "arm",
66198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66199)]
66200pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
66201 vst1_s8_x4(transmute(a), transmute(b))
66202}
66203#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66204#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
66205#[doc = "## Safety"]
66206#[doc = " * Neon instrinsic unsafe"]
66207#[inline]
66208#[target_feature(enable = "neon")]
66209#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66210#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66211#[cfg_attr(
66212 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66213 assert_instr(st1)
66214)]
66215#[cfg_attr(
66216 not(target_arch = "arm"),
66217 stable(feature = "neon_intrinsics", since = "1.59.0")
66218)]
66219#[cfg_attr(
66220 target_arch = "arm",
66221 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66222)]
66223pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
66224 vst1q_s8_x2(transmute(a), transmute(b))
66225}
66226#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66227#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
66228#[doc = "## Safety"]
66229#[doc = " * Neon instrinsic unsafe"]
66230#[inline]
66231#[target_feature(enable = "neon")]
66232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66233#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66234#[cfg_attr(
66235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66236 assert_instr(st1)
66237)]
66238#[cfg_attr(
66239 not(target_arch = "arm"),
66240 stable(feature = "neon_intrinsics", since = "1.59.0")
66241)]
66242#[cfg_attr(
66243 target_arch = "arm",
66244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66245)]
66246pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
66247 vst1q_s8_x3(transmute(a), transmute(b))
66248}
66249#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
66251#[doc = "## Safety"]
66252#[doc = " * Neon instrinsic unsafe"]
66253#[inline]
66254#[target_feature(enable = "neon")]
66255#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66256#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66257#[cfg_attr(
66258 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66259 assert_instr(st1)
66260)]
66261#[cfg_attr(
66262 not(target_arch = "arm"),
66263 stable(feature = "neon_intrinsics", since = "1.59.0")
66264)]
66265#[cfg_attr(
66266 target_arch = "arm",
66267 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66268)]
66269pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
66270 vst1q_s8_x4(transmute(a), transmute(b))
66271}
66272#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66273#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
66274#[doc = "## Safety"]
66275#[doc = " * Neon instrinsic unsafe"]
66276#[inline]
66277#[target_feature(enable = "neon")]
66278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66280#[cfg_attr(
66281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66282 assert_instr(st1)
66283)]
66284#[cfg_attr(
66285 not(target_arch = "arm"),
66286 stable(feature = "neon_intrinsics", since = "1.59.0")
66287)]
66288#[cfg_attr(
66289 target_arch = "arm",
66290 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66291)]
66292pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
66293 vst1_s16_x2(transmute(a), transmute(b))
66294}
66295#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66296#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
66297#[doc = "## Safety"]
66298#[doc = " * Neon instrinsic unsafe"]
66299#[inline]
66300#[target_feature(enable = "neon")]
66301#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66302#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66303#[cfg_attr(
66304 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66305 assert_instr(st1)
66306)]
66307#[cfg_attr(
66308 not(target_arch = "arm"),
66309 stable(feature = "neon_intrinsics", since = "1.59.0")
66310)]
66311#[cfg_attr(
66312 target_arch = "arm",
66313 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66314)]
66315pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
66316 vst1_s16_x3(transmute(a), transmute(b))
66317}
66318#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
66320#[doc = "## Safety"]
66321#[doc = " * Neon instrinsic unsafe"]
66322#[inline]
66323#[target_feature(enable = "neon")]
66324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66326#[cfg_attr(
66327 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66328 assert_instr(st1)
66329)]
66330#[cfg_attr(
66331 not(target_arch = "arm"),
66332 stable(feature = "neon_intrinsics", since = "1.59.0")
66333)]
66334#[cfg_attr(
66335 target_arch = "arm",
66336 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66337)]
66338pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
66339 vst1_s16_x4(transmute(a), transmute(b))
66340}
66341#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66342#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
66343#[doc = "## Safety"]
66344#[doc = " * Neon instrinsic unsafe"]
66345#[inline]
66346#[target_feature(enable = "neon")]
66347#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66348#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66349#[cfg_attr(
66350 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66351 assert_instr(st1)
66352)]
66353#[cfg_attr(
66354 not(target_arch = "arm"),
66355 stable(feature = "neon_intrinsics", since = "1.59.0")
66356)]
66357#[cfg_attr(
66358 target_arch = "arm",
66359 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66360)]
66361pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
66362 vst1q_s16_x2(transmute(a), transmute(b))
66363}
66364#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66365#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
66366#[doc = "## Safety"]
66367#[doc = " * Neon instrinsic unsafe"]
66368#[inline]
66369#[target_feature(enable = "neon")]
66370#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66371#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66372#[cfg_attr(
66373 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66374 assert_instr(st1)
66375)]
66376#[cfg_attr(
66377 not(target_arch = "arm"),
66378 stable(feature = "neon_intrinsics", since = "1.59.0")
66379)]
66380#[cfg_attr(
66381 target_arch = "arm",
66382 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66383)]
66384pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
66385 vst1q_s16_x3(transmute(a), transmute(b))
66386}
66387#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66388#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
66389#[doc = "## Safety"]
66390#[doc = " * Neon instrinsic unsafe"]
66391#[inline]
66392#[target_feature(enable = "neon")]
66393#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66394#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66395#[cfg_attr(
66396 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66397 assert_instr(st1)
66398)]
66399#[cfg_attr(
66400 not(target_arch = "arm"),
66401 stable(feature = "neon_intrinsics", since = "1.59.0")
66402)]
66403#[cfg_attr(
66404 target_arch = "arm",
66405 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66406)]
66407pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
66408 vst1q_s16_x4(transmute(a), transmute(b))
66409}
66410#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
66412#[doc = "## Safety"]
66413#[doc = " * Neon instrinsic unsafe"]
66414#[inline]
66415#[target_feature(enable = "neon")]
66416#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66417#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66418#[cfg_attr(
66419 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66420 assert_instr(st1)
66421)]
66422#[cfg_attr(
66423 not(target_arch = "arm"),
66424 stable(feature = "neon_intrinsics", since = "1.59.0")
66425)]
66426#[cfg_attr(
66427 target_arch = "arm",
66428 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66429)]
66430pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
66431 vst1_s32_x2(transmute(a), transmute(b))
66432}
66433#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66434#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
66435#[doc = "## Safety"]
66436#[doc = " * Neon instrinsic unsafe"]
66437#[inline]
66438#[target_feature(enable = "neon")]
66439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66441#[cfg_attr(
66442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66443 assert_instr(st1)
66444)]
66445#[cfg_attr(
66446 not(target_arch = "arm"),
66447 stable(feature = "neon_intrinsics", since = "1.59.0")
66448)]
66449#[cfg_attr(
66450 target_arch = "arm",
66451 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66452)]
66453pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
66454 vst1_s32_x3(transmute(a), transmute(b))
66455}
66456#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
66458#[doc = "## Safety"]
66459#[doc = " * Neon instrinsic unsafe"]
66460#[inline]
66461#[target_feature(enable = "neon")]
66462#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66463#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66464#[cfg_attr(
66465 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66466 assert_instr(st1)
66467)]
66468#[cfg_attr(
66469 not(target_arch = "arm"),
66470 stable(feature = "neon_intrinsics", since = "1.59.0")
66471)]
66472#[cfg_attr(
66473 target_arch = "arm",
66474 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66475)]
66476pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
66477 vst1_s32_x4(transmute(a), transmute(b))
66478}
66479#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
66481#[doc = "## Safety"]
66482#[doc = " * Neon instrinsic unsafe"]
66483#[inline]
66484#[target_feature(enable = "neon")]
66485#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66486#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66487#[cfg_attr(
66488 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66489 assert_instr(st1)
66490)]
66491#[cfg_attr(
66492 not(target_arch = "arm"),
66493 stable(feature = "neon_intrinsics", since = "1.59.0")
66494)]
66495#[cfg_attr(
66496 target_arch = "arm",
66497 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66498)]
66499pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
66500 vst1q_s32_x2(transmute(a), transmute(b))
66501}
66502#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66503#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
66504#[doc = "## Safety"]
66505#[doc = " * Neon instrinsic unsafe"]
66506#[inline]
66507#[target_feature(enable = "neon")]
66508#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66509#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66510#[cfg_attr(
66511 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66512 assert_instr(st1)
66513)]
66514#[cfg_attr(
66515 not(target_arch = "arm"),
66516 stable(feature = "neon_intrinsics", since = "1.59.0")
66517)]
66518#[cfg_attr(
66519 target_arch = "arm",
66520 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66521)]
66522pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
66523 vst1q_s32_x3(transmute(a), transmute(b))
66524}
66525#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66526#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
66527#[doc = "## Safety"]
66528#[doc = " * Neon instrinsic unsafe"]
66529#[inline]
66530#[target_feature(enable = "neon")]
66531#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66532#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66533#[cfg_attr(
66534 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66535 assert_instr(st1)
66536)]
66537#[cfg_attr(
66538 not(target_arch = "arm"),
66539 stable(feature = "neon_intrinsics", since = "1.59.0")
66540)]
66541#[cfg_attr(
66542 target_arch = "arm",
66543 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66544)]
66545pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
66546 vst1q_s32_x4(transmute(a), transmute(b))
66547}
66548#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66549#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
66550#[doc = "## Safety"]
66551#[doc = " * Neon instrinsic unsafe"]
66552#[inline]
66553#[target_feature(enable = "neon")]
66554#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66555#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66556#[cfg_attr(
66557 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66558 assert_instr(st1)
66559)]
66560#[cfg_attr(
66561 not(target_arch = "arm"),
66562 stable(feature = "neon_intrinsics", since = "1.59.0")
66563)]
66564#[cfg_attr(
66565 target_arch = "arm",
66566 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66567)]
66568pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
66569 vst1_s64_x2(transmute(a), transmute(b))
66570}
66571#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66572#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
66573#[doc = "## Safety"]
66574#[doc = " * Neon instrinsic unsafe"]
66575#[inline]
66576#[target_feature(enable = "neon")]
66577#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66578#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66579#[cfg_attr(
66580 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66581 assert_instr(st1)
66582)]
66583#[cfg_attr(
66584 not(target_arch = "arm"),
66585 stable(feature = "neon_intrinsics", since = "1.59.0")
66586)]
66587#[cfg_attr(
66588 target_arch = "arm",
66589 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66590)]
66591pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
66592 vst1_s64_x3(transmute(a), transmute(b))
66593}
66594#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66595#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
66596#[doc = "## Safety"]
66597#[doc = " * Neon instrinsic unsafe"]
66598#[inline]
66599#[target_feature(enable = "neon")]
66600#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66601#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66602#[cfg_attr(
66603 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66604 assert_instr(st1)
66605)]
66606#[cfg_attr(
66607 not(target_arch = "arm"),
66608 stable(feature = "neon_intrinsics", since = "1.59.0")
66609)]
66610#[cfg_attr(
66611 target_arch = "arm",
66612 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66613)]
66614pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
66615 vst1_s64_x4(transmute(a), transmute(b))
66616}
66617#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
66619#[doc = "## Safety"]
66620#[doc = " * Neon instrinsic unsafe"]
66621#[inline]
66622#[target_feature(enable = "neon")]
66623#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66624#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66625#[cfg_attr(
66626 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66627 assert_instr(st1)
66628)]
66629#[cfg_attr(
66630 not(target_arch = "arm"),
66631 stable(feature = "neon_intrinsics", since = "1.59.0")
66632)]
66633#[cfg_attr(
66634 target_arch = "arm",
66635 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66636)]
66637pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
66638 vst1q_s64_x2(transmute(a), transmute(b))
66639}
66640#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66641#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
66642#[doc = "## Safety"]
66643#[doc = " * Neon instrinsic unsafe"]
66644#[inline]
66645#[target_feature(enable = "neon")]
66646#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66647#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66648#[cfg_attr(
66649 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66650 assert_instr(st1)
66651)]
66652#[cfg_attr(
66653 not(target_arch = "arm"),
66654 stable(feature = "neon_intrinsics", since = "1.59.0")
66655)]
66656#[cfg_attr(
66657 target_arch = "arm",
66658 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66659)]
66660pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
66661 vst1q_s64_x3(transmute(a), transmute(b))
66662}
66663#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66664#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
66665#[doc = "## Safety"]
66666#[doc = " * Neon instrinsic unsafe"]
66667#[inline]
66668#[target_feature(enable = "neon")]
66669#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66670#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66671#[cfg_attr(
66672 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66673 assert_instr(st1)
66674)]
66675#[cfg_attr(
66676 not(target_arch = "arm"),
66677 stable(feature = "neon_intrinsics", since = "1.59.0")
66678)]
66679#[cfg_attr(
66680 target_arch = "arm",
66681 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66682)]
66683pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
66684 vst1q_s64_x4(transmute(a), transmute(b))
66685}
66686#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
66688#[doc = "## Safety"]
66689#[doc = " * Neon instrinsic unsafe"]
66690#[inline]
66691#[target_feature(enable = "neon")]
66692#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66693#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66694#[cfg_attr(
66695 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66696 assert_instr(st1)
66697)]
66698#[cfg_attr(
66699 not(target_arch = "arm"),
66700 stable(feature = "neon_intrinsics", since = "1.59.0")
66701)]
66702#[cfg_attr(
66703 target_arch = "arm",
66704 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66705)]
66706pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
66707 vst1_s8_x2(transmute(a), transmute(b))
66708}
66709#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66710#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
66711#[doc = "## Safety"]
66712#[doc = " * Neon instrinsic unsafe"]
66713#[inline]
66714#[target_feature(enable = "neon")]
66715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66716#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66717#[cfg_attr(
66718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66719 assert_instr(st1)
66720)]
66721#[cfg_attr(
66722 not(target_arch = "arm"),
66723 stable(feature = "neon_intrinsics", since = "1.59.0")
66724)]
66725#[cfg_attr(
66726 target_arch = "arm",
66727 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66728)]
66729pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
66730 vst1_s8_x3(transmute(a), transmute(b))
66731}
66732#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66733#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
66734#[doc = "## Safety"]
66735#[doc = " * Neon instrinsic unsafe"]
66736#[inline]
66737#[target_feature(enable = "neon")]
66738#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66739#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66740#[cfg_attr(
66741 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66742 assert_instr(st1)
66743)]
66744#[cfg_attr(
66745 not(target_arch = "arm"),
66746 stable(feature = "neon_intrinsics", since = "1.59.0")
66747)]
66748#[cfg_attr(
66749 target_arch = "arm",
66750 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66751)]
66752pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
66753 vst1_s8_x4(transmute(a), transmute(b))
66754}
66755#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
66757#[doc = "## Safety"]
66758#[doc = " * Neon instrinsic unsafe"]
66759#[inline]
66760#[target_feature(enable = "neon")]
66761#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66762#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66763#[cfg_attr(
66764 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66765 assert_instr(st1)
66766)]
66767#[cfg_attr(
66768 not(target_arch = "arm"),
66769 stable(feature = "neon_intrinsics", since = "1.59.0")
66770)]
66771#[cfg_attr(
66772 target_arch = "arm",
66773 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66774)]
66775pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
66776 vst1q_s8_x2(transmute(a), transmute(b))
66777}
66778#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66779#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
66780#[doc = "## Safety"]
66781#[doc = " * Neon instrinsic unsafe"]
66782#[inline]
66783#[target_feature(enable = "neon")]
66784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66786#[cfg_attr(
66787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66788 assert_instr(st1)
66789)]
66790#[cfg_attr(
66791 not(target_arch = "arm"),
66792 stable(feature = "neon_intrinsics", since = "1.59.0")
66793)]
66794#[cfg_attr(
66795 target_arch = "arm",
66796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66797)]
66798pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
66799 vst1q_s8_x3(transmute(a), transmute(b))
66800}
66801#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66802#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
66803#[doc = "## Safety"]
66804#[doc = " * Neon instrinsic unsafe"]
66805#[inline]
66806#[target_feature(enable = "neon")]
66807#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66808#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66809#[cfg_attr(
66810 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66811 assert_instr(st1)
66812)]
66813#[cfg_attr(
66814 not(target_arch = "arm"),
66815 stable(feature = "neon_intrinsics", since = "1.59.0")
66816)]
66817#[cfg_attr(
66818 target_arch = "arm",
66819 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66820)]
66821pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
66822 vst1q_s8_x4(transmute(a), transmute(b))
66823}
66824#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
66826#[doc = "## Safety"]
66827#[doc = " * Neon instrinsic unsafe"]
66828#[inline]
66829#[target_feature(enable = "neon")]
66830#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66831#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66832#[cfg_attr(
66833 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66834 assert_instr(st1)
66835)]
66836#[cfg_attr(
66837 not(target_arch = "arm"),
66838 stable(feature = "neon_intrinsics", since = "1.59.0")
66839)]
66840#[cfg_attr(
66841 target_arch = "arm",
66842 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66843)]
66844pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
66845 vst1_s16_x2(transmute(a), transmute(b))
66846}
66847#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66848#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
66849#[doc = "## Safety"]
66850#[doc = " * Neon instrinsic unsafe"]
66851#[inline]
66852#[target_feature(enable = "neon")]
66853#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66854#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66855#[cfg_attr(
66856 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66857 assert_instr(st1)
66858)]
66859#[cfg_attr(
66860 not(target_arch = "arm"),
66861 stable(feature = "neon_intrinsics", since = "1.59.0")
66862)]
66863#[cfg_attr(
66864 target_arch = "arm",
66865 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66866)]
66867pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
66868 vst1_s16_x3(transmute(a), transmute(b))
66869}
66870#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66871#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
66872#[doc = "## Safety"]
66873#[doc = " * Neon instrinsic unsafe"]
66874#[inline]
66875#[target_feature(enable = "neon")]
66876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66878#[cfg_attr(
66879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66880 assert_instr(st1)
66881)]
66882#[cfg_attr(
66883 not(target_arch = "arm"),
66884 stable(feature = "neon_intrinsics", since = "1.59.0")
66885)]
66886#[cfg_attr(
66887 target_arch = "arm",
66888 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66889)]
66890pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
66891 vst1_s16_x4(transmute(a), transmute(b))
66892}
66893#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66894#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
66895#[doc = "## Safety"]
66896#[doc = " * Neon instrinsic unsafe"]
66897#[inline]
66898#[target_feature(enable = "neon")]
66899#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66900#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66901#[cfg_attr(
66902 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66903 assert_instr(st1)
66904)]
66905#[cfg_attr(
66906 not(target_arch = "arm"),
66907 stable(feature = "neon_intrinsics", since = "1.59.0")
66908)]
66909#[cfg_attr(
66910 target_arch = "arm",
66911 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66912)]
66913pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
66914 vst1q_s16_x2(transmute(a), transmute(b))
66915}
66916#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66917#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
66918#[doc = "## Safety"]
66919#[doc = " * Neon instrinsic unsafe"]
66920#[inline]
66921#[target_feature(enable = "neon")]
66922#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66923#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66924#[cfg_attr(
66925 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66926 assert_instr(st1)
66927)]
66928#[cfg_attr(
66929 not(target_arch = "arm"),
66930 stable(feature = "neon_intrinsics", since = "1.59.0")
66931)]
66932#[cfg_attr(
66933 target_arch = "arm",
66934 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66935)]
66936pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
66937 vst1q_s16_x3(transmute(a), transmute(b))
66938}
66939#[doc = "Store multiple single-element structures to one, two, three, or four registers"]
66940#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
66941#[doc = "## Safety"]
66942#[doc = " * Neon instrinsic unsafe"]
66943#[inline]
66944#[target_feature(enable = "neon")]
66945#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66946#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
66947#[cfg_attr(
66948 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
66949 assert_instr(st1)
66950)]
66951#[cfg_attr(
66952 not(target_arch = "arm"),
66953 stable(feature = "neon_intrinsics", since = "1.59.0")
66954)]
66955#[cfg_attr(
66956 target_arch = "arm",
66957 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
66958)]
66959pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
66960 vst1q_s16_x4(transmute(a), transmute(b))
66961}
66962#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
66963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v1i64)"]
66964#[doc = "## Safety"]
66965#[doc = " * Neon instrinsic unsafe"]
66966#[inline]
66967#[target_feature(enable = "neon")]
66968#[cfg(target_arch = "arm")]
66969#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66970#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66971#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
66972unsafe fn vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32) {
66973 unsafe extern "unadjusted" {
66974 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v1i64.p0")]
66975 fn _vst1_v1i64(addr: *const i8, val: int64x1_t, align: i32);
66976 }
66977 _vst1_v1i64(addr, val, align)
66978}
66979#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
66980#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2f32)"]
66981#[doc = "## Safety"]
66982#[doc = " * Neon instrinsic unsafe"]
66983#[inline]
66984#[target_feature(enable = "neon")]
66985#[cfg(target_arch = "arm")]
66986#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
66987#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
66988#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
66989unsafe fn vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32) {
66990 unsafe extern "unadjusted" {
66991 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2f32.p0")]
66992 fn _vst1_v2f32(addr: *const i8, val: float32x2_t, align: i32);
66993 }
66994 _vst1_v2f32(addr, val, align)
66995}
66996#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
66997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v2i32)"]
66998#[doc = "## Safety"]
66999#[doc = " * Neon instrinsic unsafe"]
67000#[inline]
67001#[target_feature(enable = "neon")]
67002#[cfg(target_arch = "arm")]
67003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67004#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67005#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67006unsafe fn vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32) {
67007 unsafe extern "unadjusted" {
67008 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i32.p0")]
67009 fn _vst1_v2i32(addr: *const i8, val: int32x2_t, align: i32);
67010 }
67011 _vst1_v2i32(addr, val, align)
67012}
67013#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67014#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4i16)"]
67015#[doc = "## Safety"]
67016#[doc = " * Neon instrinsic unsafe"]
67017#[inline]
67018#[target_feature(enable = "neon")]
67019#[cfg(target_arch = "arm")]
67020#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67021#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67022#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67023unsafe fn vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32) {
67024 unsafe extern "unadjusted" {
67025 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i16.p0")]
67026 fn _vst1_v4i16(addr: *const i8, val: int16x4_t, align: i32);
67027 }
67028 _vst1_v4i16(addr, val, align)
67029}
67030#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67031#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v8i8)"]
67032#[doc = "## Safety"]
67033#[doc = " * Neon instrinsic unsafe"]
67034#[inline]
67035#[target_feature(enable = "neon")]
67036#[cfg(target_arch = "arm")]
67037#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67038#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67039#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67040unsafe fn vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32) {
67041 unsafe extern "unadjusted" {
67042 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i8.p0")]
67043 fn _vst1_v8i8(addr: *const i8, val: int8x8_t, align: i32);
67044 }
67045 _vst1_v8i8(addr, val, align)
67046}
67047#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v16i8)"]
67049#[doc = "## Safety"]
67050#[doc = " * Neon instrinsic unsafe"]
67051#[inline]
67052#[target_feature(enable = "neon")]
67053#[cfg(target_arch = "arm")]
67054#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67055#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67056#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.8"))]
67057unsafe fn vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32) {
67058 unsafe extern "unadjusted" {
67059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v16i8.p0")]
67060 fn _vst1q_v16i8(addr: *const i8, val: int8x16_t, align: i32);
67061 }
67062 _vst1q_v16i8(addr, val, align)
67063}
67064#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v2i64)"]
67066#[doc = "## Safety"]
67067#[doc = " * Neon instrinsic unsafe"]
67068#[inline]
67069#[target_feature(enable = "neon")]
67070#[cfg(target_arch = "arm")]
67071#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67072#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67073#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.64"))]
67074unsafe fn vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32) {
67075 unsafe extern "unadjusted" {
67076 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v2i64.p0")]
67077 fn _vst1q_v2i64(addr: *const i8, val: int64x2_t, align: i32);
67078 }
67079 _vst1q_v2i64(addr, val, align)
67080}
67081#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67082#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4f32)"]
67083#[doc = "## Safety"]
67084#[doc = " * Neon instrinsic unsafe"]
67085#[inline]
67086#[target_feature(enable = "neon")]
67087#[cfg(target_arch = "arm")]
67088#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67089#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67090#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67091unsafe fn vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32) {
67092 unsafe extern "unadjusted" {
67093 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f32.p0")]
67094 fn _vst1q_v4f32(addr: *const i8, val: float32x4_t, align: i32);
67095 }
67096 _vst1q_v4f32(addr, val, align)
67097}
67098#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67099#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v4i32)"]
67100#[doc = "## Safety"]
67101#[doc = " * Neon instrinsic unsafe"]
67102#[inline]
67103#[target_feature(enable = "neon")]
67104#[cfg(target_arch = "arm")]
67105#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67106#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67107#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.32"))]
67108unsafe fn vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32) {
67109 unsafe extern "unadjusted" {
67110 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4i32.p0")]
67111 fn _vst1q_v4i32(addr: *const i8, val: int32x4_t, align: i32);
67112 }
67113 _vst1q_v4i32(addr, val, align)
67114}
67115#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67116#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8i16)"]
67117#[doc = "## Safety"]
67118#[doc = " * Neon instrinsic unsafe"]
67119#[inline]
67120#[target_feature(enable = "neon")]
67121#[cfg(target_arch = "arm")]
67122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67123#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67124#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67125unsafe fn vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32) {
67126 unsafe extern "unadjusted" {
67127 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8i16.p0")]
67128 fn _vst1q_v8i16(addr: *const i8, val: int16x8_t, align: i32);
67129 }
67130 _vst1q_v8i16(addr, val, align)
67131}
67132#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
67134#[doc = "## Safety"]
67135#[doc = " * Neon instrinsic unsafe"]
67136#[inline]
67137#[cfg(target_arch = "arm")]
67138#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67139#[target_feature(enable = "neon,fp16")]
67140#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67141#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67142unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
67143 unsafe extern "unadjusted" {
67144 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v4f16.p0")]
67145 fn _vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32);
67146 }
67147 _vst1_v4f16(addr, val, align)
67148}
67149#[doc = "Store multiple single-element structures from one, two, three, or four registers."]
67150#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
67151#[doc = "## Safety"]
67152#[doc = " * Neon instrinsic unsafe"]
67153#[inline]
67154#[cfg(target_arch = "arm")]
67155#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67156#[target_feature(enable = "neon,fp16")]
67157#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67158#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vst1.16"))]
67159unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
67160 unsafe extern "unadjusted" {
67161 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1.v8f16.p0")]
67162 fn _vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32);
67163 }
67164 _vst1q_v8f16(addr, val, align)
67165}
67166#[doc = "Store multiple single-element structures from one, two, three, or four registers"]
67167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
67168#[doc = "## Safety"]
67169#[doc = " * Neon instrinsic unsafe"]
67170#[inline]
67171#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
67172#[target_feature(enable = "neon,aes")]
67173#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
67174#[cfg_attr(
67175 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67176 assert_instr(nop, LANE = 0)
67177)]
67178#[rustc_legacy_const_generics(2)]
67179#[cfg_attr(
67180 not(target_arch = "arm"),
67181 stable(feature = "neon_intrinsics", since = "1.59.0")
67182)]
67183#[cfg_attr(
67184 target_arch = "arm",
67185 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67186)]
67187pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
67188 static_assert_uimm_bits!(LANE, 1);
67189 *a = simd_extract!(b, LANE as u32);
67190}
67191#[doc = "Store multiple 2-element structures from two registers"]
67192#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67193#[doc = "## Safety"]
67194#[doc = " * Neon instrinsic unsafe"]
67195#[inline]
67196#[cfg(not(target_arch = "arm"))]
67197#[target_feature(enable = "neon,fp16")]
67198#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67199#[cfg_attr(test, assert_instr(st2))]
67200pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67201 unsafe extern "unadjusted" {
67202 #[cfg_attr(
67203 any(target_arch = "aarch64", target_arch = "arm64ec"),
67204 link_name = "llvm.aarch64.neon.st2.v4f16.p0"
67205 )]
67206 fn _vst2_f16(a: float16x4_t, b: float16x4_t, ptr: *mut i8);
67207 }
67208 _vst2_f16(b.0, b.1, a as _)
67209}
67210#[doc = "Store multiple 2-element structures from two registers"]
67211#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67212#[doc = "## Safety"]
67213#[doc = " * Neon instrinsic unsafe"]
67214#[inline]
67215#[cfg(not(target_arch = "arm"))]
67216#[target_feature(enable = "neon,fp16")]
67217#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67218#[cfg_attr(test, assert_instr(st2))]
67219pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67220 unsafe extern "unadjusted" {
67221 #[cfg_attr(
67222 any(target_arch = "aarch64", target_arch = "arm64ec"),
67223 link_name = "llvm.aarch64.neon.st2.v8f16.p0"
67224 )]
67225 fn _vst2q_f16(a: float16x8_t, b: float16x8_t, ptr: *mut i8);
67226 }
67227 _vst2q_f16(b.0, b.1, a as _)
67228}
67229#[doc = "Store multiple 2-element structures from two registers"]
67230#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
67231#[doc = "## Safety"]
67232#[doc = " * Neon instrinsic unsafe"]
67233#[inline]
67234#[cfg(target_arch = "arm")]
67235#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67236#[target_feature(enable = "neon,fp16")]
67237#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67238#[cfg_attr(test, assert_instr(vst2))]
67239pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
67240 unsafe extern "unadjusted" {
67241 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0.v4f16")]
67242 fn _vst2_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, size: i32);
67243 }
67244 _vst2_f16(a as _, b.0, b.1, 2)
67245}
67246#[doc = "Store multiple 2-element structures from two registers"]
67247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
67248#[doc = "## Safety"]
67249#[doc = " * Neon instrinsic unsafe"]
67250#[inline]
67251#[cfg(target_arch = "arm")]
67252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67253#[target_feature(enable = "neon,fp16")]
67254#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67255#[cfg_attr(test, assert_instr(vst2))]
67256pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
67257 unsafe extern "unadjusted" {
67258 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0.v8f16")]
67259 fn _vst2q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, size: i32);
67260 }
67261 _vst2q_f16(a as _, b.0, b.1, 2)
67262}
67263#[doc = "Store multiple 2-element structures from two registers"]
67264#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67265#[doc = "## Safety"]
67266#[doc = " * Neon instrinsic unsafe"]
67267#[inline]
67268#[target_feature(enable = "neon")]
67269#[cfg(not(target_arch = "arm"))]
67270#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67271#[cfg_attr(test, assert_instr(st2))]
67272pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67273 unsafe extern "unadjusted" {
67274 #[cfg_attr(
67275 any(target_arch = "aarch64", target_arch = "arm64ec"),
67276 link_name = "llvm.aarch64.neon.st2.v2f32.p0"
67277 )]
67278 fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8);
67279 }
67280 _vst2_f32(b.0, b.1, a as _)
67281}
67282#[doc = "Store multiple 2-element structures from two registers"]
67283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67284#[doc = "## Safety"]
67285#[doc = " * Neon instrinsic unsafe"]
67286#[inline]
67287#[target_feature(enable = "neon")]
67288#[cfg(not(target_arch = "arm"))]
67289#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67290#[cfg_attr(test, assert_instr(st2))]
67291pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67292 unsafe extern "unadjusted" {
67293 #[cfg_attr(
67294 any(target_arch = "aarch64", target_arch = "arm64ec"),
67295 link_name = "llvm.aarch64.neon.st2.v4f32.p0"
67296 )]
67297 fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8);
67298 }
67299 _vst2q_f32(b.0, b.1, a as _)
67300}
67301#[doc = "Store multiple 2-element structures from two registers"]
67302#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67303#[doc = "## Safety"]
67304#[doc = " * Neon instrinsic unsafe"]
67305#[inline]
67306#[target_feature(enable = "neon")]
67307#[cfg(not(target_arch = "arm"))]
67308#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67309#[cfg_attr(test, assert_instr(st2))]
67310pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67311 unsafe extern "unadjusted" {
67312 #[cfg_attr(
67313 any(target_arch = "aarch64", target_arch = "arm64ec"),
67314 link_name = "llvm.aarch64.neon.st2.v8i8.p0"
67315 )]
67316 fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8);
67317 }
67318 _vst2_s8(b.0, b.1, a as _)
67319}
67320#[doc = "Store multiple 2-element structures from two registers"]
67321#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67322#[doc = "## Safety"]
67323#[doc = " * Neon instrinsic unsafe"]
67324#[inline]
67325#[target_feature(enable = "neon")]
67326#[cfg(not(target_arch = "arm"))]
67327#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67328#[cfg_attr(test, assert_instr(st2))]
67329pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67330 unsafe extern "unadjusted" {
67331 #[cfg_attr(
67332 any(target_arch = "aarch64", target_arch = "arm64ec"),
67333 link_name = "llvm.aarch64.neon.st2.v16i8.p0"
67334 )]
67335 fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8);
67336 }
67337 _vst2q_s8(b.0, b.1, a as _)
67338}
67339#[doc = "Store multiple 2-element structures from two registers"]
67340#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67341#[doc = "## Safety"]
67342#[doc = " * Neon instrinsic unsafe"]
67343#[inline]
67344#[target_feature(enable = "neon")]
67345#[cfg(not(target_arch = "arm"))]
67346#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67347#[cfg_attr(test, assert_instr(st2))]
67348pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67349 unsafe extern "unadjusted" {
67350 #[cfg_attr(
67351 any(target_arch = "aarch64", target_arch = "arm64ec"),
67352 link_name = "llvm.aarch64.neon.st2.v4i16.p0"
67353 )]
67354 fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8);
67355 }
67356 _vst2_s16(b.0, b.1, a as _)
67357}
67358#[doc = "Store multiple 2-element structures from two registers"]
67359#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67360#[doc = "## Safety"]
67361#[doc = " * Neon instrinsic unsafe"]
67362#[inline]
67363#[target_feature(enable = "neon")]
67364#[cfg(not(target_arch = "arm"))]
67365#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67366#[cfg_attr(test, assert_instr(st2))]
67367pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67368 unsafe extern "unadjusted" {
67369 #[cfg_attr(
67370 any(target_arch = "aarch64", target_arch = "arm64ec"),
67371 link_name = "llvm.aarch64.neon.st2.v8i16.p0"
67372 )]
67373 fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8);
67374 }
67375 _vst2q_s16(b.0, b.1, a as _)
67376}
67377#[doc = "Store multiple 2-element structures from two registers"]
67378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67379#[doc = "## Safety"]
67380#[doc = " * Neon instrinsic unsafe"]
67381#[inline]
67382#[target_feature(enable = "neon")]
67383#[cfg(not(target_arch = "arm"))]
67384#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67385#[cfg_attr(test, assert_instr(st2))]
67386pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67387 unsafe extern "unadjusted" {
67388 #[cfg_attr(
67389 any(target_arch = "aarch64", target_arch = "arm64ec"),
67390 link_name = "llvm.aarch64.neon.st2.v2i32.p0"
67391 )]
67392 fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8);
67393 }
67394 _vst2_s32(b.0, b.1, a as _)
67395}
67396#[doc = "Store multiple 2-element structures from two registers"]
67397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67398#[doc = "## Safety"]
67399#[doc = " * Neon instrinsic unsafe"]
67400#[inline]
67401#[target_feature(enable = "neon")]
67402#[cfg(not(target_arch = "arm"))]
67403#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67404#[cfg_attr(test, assert_instr(st2))]
67405pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67406 unsafe extern "unadjusted" {
67407 #[cfg_attr(
67408 any(target_arch = "aarch64", target_arch = "arm64ec"),
67409 link_name = "llvm.aarch64.neon.st2.v4i32.p0"
67410 )]
67411 fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8);
67412 }
67413 _vst2q_s32(b.0, b.1, a as _)
67414}
67415#[doc = "Store multiple 2-element structures from two registers"]
67416#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
67417#[doc = "## Safety"]
67418#[doc = " * Neon instrinsic unsafe"]
67419#[inline]
67420#[cfg(target_arch = "arm")]
67421#[target_feature(enable = "neon,v7")]
67422#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67423#[cfg_attr(test, assert_instr(vst2))]
67424pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
67425 unsafe extern "unadjusted" {
67426 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2f32.p0")]
67427 fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32);
67428 }
67429 _vst2_f32(a as _, b.0, b.1, 4)
67430}
67431#[doc = "Store multiple 2-element structures from two registers"]
67432#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
67433#[doc = "## Safety"]
67434#[doc = " * Neon instrinsic unsafe"]
67435#[inline]
67436#[cfg(target_arch = "arm")]
67437#[target_feature(enable = "neon,v7")]
67438#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67439#[cfg_attr(test, assert_instr(vst2))]
67440pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
67441 unsafe extern "unadjusted" {
67442 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4f32.p0")]
67443 fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32);
67444 }
67445 _vst2q_f32(a as _, b.0, b.1, 4)
67446}
67447#[doc = "Store multiple 2-element structures from two registers"]
67448#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
67449#[doc = "## Safety"]
67450#[doc = " * Neon instrinsic unsafe"]
67451#[inline]
67452#[cfg(target_arch = "arm")]
67453#[target_feature(enable = "neon,v7")]
67454#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67455#[cfg_attr(test, assert_instr(vst2))]
67456pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
67457 unsafe extern "unadjusted" {
67458 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i8.p0")]
67459 fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32);
67460 }
67461 _vst2_s8(a as _, b.0, b.1, 1)
67462}
67463#[doc = "Store multiple 2-element structures from two registers"]
67464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
67465#[doc = "## Safety"]
67466#[doc = " * Neon instrinsic unsafe"]
67467#[inline]
67468#[cfg(target_arch = "arm")]
67469#[target_feature(enable = "neon,v7")]
67470#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67471#[cfg_attr(test, assert_instr(vst2))]
67472pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
67473 unsafe extern "unadjusted" {
67474 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v16i8.p0")]
67475 fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32);
67476 }
67477 _vst2q_s8(a as _, b.0, b.1, 1)
67478}
67479#[doc = "Store multiple 2-element structures from two registers"]
67480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
67481#[doc = "## Safety"]
67482#[doc = " * Neon instrinsic unsafe"]
67483#[inline]
67484#[cfg(target_arch = "arm")]
67485#[target_feature(enable = "neon,v7")]
67486#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67487#[cfg_attr(test, assert_instr(vst2))]
67488pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
67489 unsafe extern "unadjusted" {
67490 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i16.p0")]
67491 fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32);
67492 }
67493 _vst2_s16(a as _, b.0, b.1, 2)
67494}
67495#[doc = "Store multiple 2-element structures from two registers"]
67496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
67497#[doc = "## Safety"]
67498#[doc = " * Neon instrinsic unsafe"]
67499#[inline]
67500#[cfg(target_arch = "arm")]
67501#[target_feature(enable = "neon,v7")]
67502#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67503#[cfg_attr(test, assert_instr(vst2))]
67504pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
67505 unsafe extern "unadjusted" {
67506 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v8i16.p0")]
67507 fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32);
67508 }
67509 _vst2q_s16(a as _, b.0, b.1, 2)
67510}
67511#[doc = "Store multiple 2-element structures from two registers"]
67512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
67513#[doc = "## Safety"]
67514#[doc = " * Neon instrinsic unsafe"]
67515#[inline]
67516#[cfg(target_arch = "arm")]
67517#[target_feature(enable = "neon,v7")]
67518#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67519#[cfg_attr(test, assert_instr(vst2))]
67520pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
67521 unsafe extern "unadjusted" {
67522 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v2i32.p0")]
67523 fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32);
67524 }
67525 _vst2_s32(a as _, b.0, b.1, 4)
67526}
67527#[doc = "Store multiple 2-element structures from two registers"]
67528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
67529#[doc = "## Safety"]
67530#[doc = " * Neon instrinsic unsafe"]
67531#[inline]
67532#[cfg(target_arch = "arm")]
67533#[target_feature(enable = "neon,v7")]
67534#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67535#[cfg_attr(test, assert_instr(vst2))]
67536pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
67537 unsafe extern "unadjusted" {
67538 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v4i32.p0")]
67539 fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32);
67540 }
67541 _vst2q_s32(a as _, b.0, b.1, 4)
67542}
67543#[doc = "Store multiple 2-element structures from two registers"]
67544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67545#[doc = "## Safety"]
67546#[doc = " * Neon instrinsic unsafe"]
67547#[inline]
67548#[cfg(not(target_arch = "arm"))]
67549#[rustc_legacy_const_generics(2)]
67550#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67551#[target_feature(enable = "neon,fp16")]
67552#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67553pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
67554 static_assert_uimm_bits!(LANE, 2);
67555 unsafe extern "unadjusted" {
67556 #[cfg_attr(
67557 any(target_arch = "aarch64", target_arch = "arm64ec"),
67558 link_name = "llvm.aarch64.neon.st2lane.v4f16.p0"
67559 )]
67560 fn _vst2_lane_f16(a: float16x4_t, b: float16x4_t, n: i64, ptr: *mut i8);
67561 }
67562 _vst2_lane_f16(b.0, b.1, LANE as i64, a as _)
67563}
67564#[doc = "Store multiple 2-element structures from two registers"]
67565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
67566#[doc = "## Safety"]
67567#[doc = " * Neon instrinsic unsafe"]
67568#[inline]
67569#[cfg(not(target_arch = "arm"))]
67570#[rustc_legacy_const_generics(2)]
67571#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67572#[target_feature(enable = "neon,fp16")]
67573#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67574pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
67575 static_assert_uimm_bits!(LANE, 3);
67576 unsafe extern "unadjusted" {
67577 #[cfg_attr(
67578 any(target_arch = "aarch64", target_arch = "arm64ec"),
67579 link_name = "llvm.aarch64.neon.st2lane.v8f16.p0"
67580 )]
67581 fn _vst2q_lane_f16(a: float16x8_t, b: float16x8_t, n: i64, ptr: *mut i8);
67582 }
67583 _vst2q_lane_f16(b.0, b.1, LANE as i64, a as _)
67584}
67585#[doc = "Store multiple 2-element structures from two registers"]
67586#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
67587#[doc = "## Safety"]
67588#[doc = " * Neon instrinsic unsafe"]
67589#[inline]
67590#[cfg(target_arch = "arm")]
67591#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67592#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67593#[rustc_legacy_const_generics(2)]
67594#[target_feature(enable = "neon,fp16")]
67595#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67596pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
67597 static_assert_uimm_bits!(LANE, 2);
67598 unsafe extern "unadjusted" {
67599 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v4f16")]
67600 fn _vst2_lane_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, n: i32, size: i32);
67601 }
67602 _vst2_lane_f16(a as _, b.0, b.1, LANE, 2)
67603}
67604#[doc = "Store multiple 2-element structures from two registers"]
67605#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
67606#[doc = "## Safety"]
67607#[doc = " * Neon instrinsic unsafe"]
67608#[inline]
67609#[cfg(target_arch = "arm")]
67610#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67611#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67612#[rustc_legacy_const_generics(2)]
67613#[target_feature(enable = "neon,fp16")]
67614#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
67615pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
67616 static_assert_uimm_bits!(LANE, 1);
67617 unsafe extern "unadjusted" {
67618 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0.v8f16")]
67619 fn _vst2q_lane_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, n: i32, size: i32);
67620 }
67621 _vst2q_lane_f16(a as _, b.0, b.1, LANE, 2)
67622}
67623#[doc = "Store multiple 2-element structures from two registers"]
67624#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
67625#[doc = "## Safety"]
67626#[doc = " * Neon instrinsic unsafe"]
67627#[inline]
67628#[target_feature(enable = "neon")]
67629#[cfg(not(target_arch = "arm"))]
67630#[rustc_legacy_const_generics(2)]
67631#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67632#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67633pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
67634 static_assert_uimm_bits!(LANE, 1);
67635 unsafe extern "unadjusted" {
67636 #[cfg_attr(
67637 any(target_arch = "aarch64", target_arch = "arm64ec"),
67638 link_name = "llvm.aarch64.neon.st2lane.v2f32.p0"
67639 )]
67640 fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8);
67641 }
67642 _vst2_lane_f32(b.0, b.1, LANE as i64, a as _)
67643}
67644#[doc = "Store multiple 2-element structures from two registers"]
67645#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
67646#[doc = "## Safety"]
67647#[doc = " * Neon instrinsic unsafe"]
67648#[inline]
67649#[target_feature(enable = "neon")]
67650#[cfg(not(target_arch = "arm"))]
67651#[rustc_legacy_const_generics(2)]
67652#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67653#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67654pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
67655 static_assert_uimm_bits!(LANE, 2);
67656 unsafe extern "unadjusted" {
67657 #[cfg_attr(
67658 any(target_arch = "aarch64", target_arch = "arm64ec"),
67659 link_name = "llvm.aarch64.neon.st2lane.v4f32.p0"
67660 )]
67661 fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8);
67662 }
67663 _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _)
67664}
67665#[doc = "Store multiple 2-element structures from two registers"]
67666#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
67667#[doc = "## Safety"]
67668#[doc = " * Neon instrinsic unsafe"]
67669#[inline]
67670#[target_feature(enable = "neon")]
67671#[cfg(not(target_arch = "arm"))]
67672#[rustc_legacy_const_generics(2)]
67673#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67674#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67675pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
67676 static_assert_uimm_bits!(LANE, 3);
67677 unsafe extern "unadjusted" {
67678 #[cfg_attr(
67679 any(target_arch = "aarch64", target_arch = "arm64ec"),
67680 link_name = "llvm.aarch64.neon.st2lane.v8i8.p0"
67681 )]
67682 fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8);
67683 }
67684 _vst2_lane_s8(b.0, b.1, LANE as i64, a as _)
67685}
67686#[doc = "Store multiple 2-element structures from two registers"]
67687#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
67688#[doc = "## Safety"]
67689#[doc = " * Neon instrinsic unsafe"]
67690#[inline]
67691#[target_feature(enable = "neon")]
67692#[cfg(not(target_arch = "arm"))]
67693#[rustc_legacy_const_generics(2)]
67694#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67695#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67696pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
67697 static_assert_uimm_bits!(LANE, 2);
67698 unsafe extern "unadjusted" {
67699 #[cfg_attr(
67700 any(target_arch = "aarch64", target_arch = "arm64ec"),
67701 link_name = "llvm.aarch64.neon.st2lane.v4i16.p0"
67702 )]
67703 fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8);
67704 }
67705 _vst2_lane_s16(b.0, b.1, LANE as i64, a as _)
67706}
67707#[doc = "Store multiple 2-element structures from two registers"]
67708#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
67709#[doc = "## Safety"]
67710#[doc = " * Neon instrinsic unsafe"]
67711#[inline]
67712#[target_feature(enable = "neon")]
67713#[cfg(not(target_arch = "arm"))]
67714#[rustc_legacy_const_generics(2)]
67715#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67716#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67717pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
67718 static_assert_uimm_bits!(LANE, 3);
67719 unsafe extern "unadjusted" {
67720 #[cfg_attr(
67721 any(target_arch = "aarch64", target_arch = "arm64ec"),
67722 link_name = "llvm.aarch64.neon.st2lane.v8i16.p0"
67723 )]
67724 fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8);
67725 }
67726 _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _)
67727}
67728#[doc = "Store multiple 2-element structures from two registers"]
67729#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
67730#[doc = "## Safety"]
67731#[doc = " * Neon instrinsic unsafe"]
67732#[inline]
67733#[target_feature(enable = "neon")]
67734#[cfg(not(target_arch = "arm"))]
67735#[rustc_legacy_const_generics(2)]
67736#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67737#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67738pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
67739 static_assert_uimm_bits!(LANE, 1);
67740 unsafe extern "unadjusted" {
67741 #[cfg_attr(
67742 any(target_arch = "aarch64", target_arch = "arm64ec"),
67743 link_name = "llvm.aarch64.neon.st2lane.v2i32.p0"
67744 )]
67745 fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8);
67746 }
67747 _vst2_lane_s32(b.0, b.1, LANE as i64, a as _)
67748}
67749#[doc = "Store multiple 2-element structures from two registers"]
67750#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
67751#[doc = "## Safety"]
67752#[doc = " * Neon instrinsic unsafe"]
67753#[inline]
67754#[target_feature(enable = "neon")]
67755#[cfg(not(target_arch = "arm"))]
67756#[rustc_legacy_const_generics(2)]
67757#[cfg_attr(test, assert_instr(st2, LANE = 0))]
67758#[stable(feature = "neon_intrinsics", since = "1.59.0")]
67759pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
67760 static_assert_uimm_bits!(LANE, 2);
67761 unsafe extern "unadjusted" {
67762 #[cfg_attr(
67763 any(target_arch = "aarch64", target_arch = "arm64ec"),
67764 link_name = "llvm.aarch64.neon.st2lane.v4i32.p0"
67765 )]
67766 fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8);
67767 }
67768 _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _)
67769}
67770#[doc = "Store multiple 2-element structures from two registers"]
67771#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
67772#[doc = "## Safety"]
67773#[doc = " * Neon instrinsic unsafe"]
67774#[inline]
67775#[cfg(target_arch = "arm")]
67776#[target_feature(enable = "neon,v7")]
67777#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67778#[rustc_legacy_const_generics(2)]
67779#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67780pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
67781 static_assert_uimm_bits!(LANE, 1);
67782 unsafe extern "unadjusted" {
67783 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2f32.p0")]
67784 fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32);
67785 }
67786 _vst2_lane_f32(a as _, b.0, b.1, LANE, 4)
67787}
67788#[doc = "Store multiple 2-element structures from two registers"]
67789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
67790#[doc = "## Safety"]
67791#[doc = " * Neon instrinsic unsafe"]
67792#[inline]
67793#[cfg(target_arch = "arm")]
67794#[target_feature(enable = "neon,v7")]
67795#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67796#[rustc_legacy_const_generics(2)]
67797#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67798pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
67799 static_assert_uimm_bits!(LANE, 2);
67800 unsafe extern "unadjusted" {
67801 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4f32.p0")]
67802 fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32);
67803 }
67804 _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4)
67805}
67806#[doc = "Store multiple 2-element structures from two registers"]
67807#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
67808#[doc = "## Safety"]
67809#[doc = " * Neon instrinsic unsafe"]
67810#[inline]
67811#[cfg(target_arch = "arm")]
67812#[target_feature(enable = "neon,v7")]
67813#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67814#[rustc_legacy_const_generics(2)]
67815#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67816pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
67817 static_assert_uimm_bits!(LANE, 3);
67818 unsafe extern "unadjusted" {
67819 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i8.p0")]
67820 fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32);
67821 }
67822 _vst2_lane_s8(a as _, b.0, b.1, LANE, 1)
67823}
67824#[doc = "Store multiple 2-element structures from two registers"]
67825#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
67826#[doc = "## Safety"]
67827#[doc = " * Neon instrinsic unsafe"]
67828#[inline]
67829#[cfg(target_arch = "arm")]
67830#[target_feature(enable = "neon,v7")]
67831#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67832#[rustc_legacy_const_generics(2)]
67833#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67834pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
67835 static_assert_uimm_bits!(LANE, 2);
67836 unsafe extern "unadjusted" {
67837 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i16.p0")]
67838 fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32);
67839 }
67840 _vst2_lane_s16(a as _, b.0, b.1, LANE, 2)
67841}
67842#[doc = "Store multiple 2-element structures from two registers"]
67843#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
67844#[doc = "## Safety"]
67845#[doc = " * Neon instrinsic unsafe"]
67846#[inline]
67847#[cfg(target_arch = "arm")]
67848#[target_feature(enable = "neon,v7")]
67849#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67850#[rustc_legacy_const_generics(2)]
67851#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67852pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
67853 static_assert_uimm_bits!(LANE, 3);
67854 unsafe extern "unadjusted" {
67855 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v8i16.p0")]
67856 fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32);
67857 }
67858 _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2)
67859}
67860#[doc = "Store multiple 2-element structures from two registers"]
67861#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
67862#[doc = "## Safety"]
67863#[doc = " * Neon instrinsic unsafe"]
67864#[inline]
67865#[cfg(target_arch = "arm")]
67866#[target_feature(enable = "neon,v7")]
67867#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67868#[rustc_legacy_const_generics(2)]
67869#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67870pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
67871 static_assert_uimm_bits!(LANE, 1);
67872 unsafe extern "unadjusted" {
67873 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v2i32.p0")]
67874 fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32);
67875 }
67876 _vst2_lane_s32(a as _, b.0, b.1, LANE, 4)
67877}
67878#[doc = "Store multiple 2-element structures from two registers"]
67879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
67880#[doc = "## Safety"]
67881#[doc = " * Neon instrinsic unsafe"]
67882#[inline]
67883#[cfg(target_arch = "arm")]
67884#[target_feature(enable = "neon,v7")]
67885#[cfg_attr(test, assert_instr(vst2, LANE = 0))]
67886#[rustc_legacy_const_generics(2)]
67887#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
67888pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
67889 static_assert_uimm_bits!(LANE, 2);
67890 unsafe extern "unadjusted" {
67891 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.v4i32.p0")]
67892 fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32);
67893 }
67894 _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4)
67895}
67896#[doc = "Store multiple 2-element structures from two registers"]
67897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
67898#[doc = "## Safety"]
67899#[doc = " * Neon instrinsic unsafe"]
67900#[inline]
67901#[target_feature(enable = "neon")]
67902#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67903#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
67904#[cfg_attr(
67905 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67906 assert_instr(st2, LANE = 0)
67907)]
67908#[rustc_legacy_const_generics(2)]
67909#[cfg_attr(
67910 not(target_arch = "arm"),
67911 stable(feature = "neon_intrinsics", since = "1.59.0")
67912)]
67913#[cfg_attr(
67914 target_arch = "arm",
67915 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67916)]
67917pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
67918 static_assert_uimm_bits!(LANE, 3);
67919 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
67920}
67921#[doc = "Store multiple 2-element structures from two registers"]
67922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
67923#[doc = "## Safety"]
67924#[doc = " * Neon instrinsic unsafe"]
67925#[inline]
67926#[target_feature(enable = "neon")]
67927#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67928#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
67929#[cfg_attr(
67930 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67931 assert_instr(st2, LANE = 0)
67932)]
67933#[rustc_legacy_const_generics(2)]
67934#[cfg_attr(
67935 not(target_arch = "arm"),
67936 stable(feature = "neon_intrinsics", since = "1.59.0")
67937)]
67938#[cfg_attr(
67939 target_arch = "arm",
67940 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67941)]
67942pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
67943 static_assert_uimm_bits!(LANE, 2);
67944 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
67945}
67946#[doc = "Store multiple 2-element structures from two registers"]
67947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
67948#[doc = "## Safety"]
67949#[doc = " * Neon instrinsic unsafe"]
67950#[inline]
67951#[target_feature(enable = "neon")]
67952#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67953#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
67954#[cfg_attr(
67955 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67956 assert_instr(st2, LANE = 0)
67957)]
67958#[rustc_legacy_const_generics(2)]
67959#[cfg_attr(
67960 not(target_arch = "arm"),
67961 stable(feature = "neon_intrinsics", since = "1.59.0")
67962)]
67963#[cfg_attr(
67964 target_arch = "arm",
67965 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67966)]
67967pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
67968 static_assert_uimm_bits!(LANE, 3);
67969 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
67970}
67971#[doc = "Store multiple 2-element structures from two registers"]
67972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
67973#[doc = "## Safety"]
67974#[doc = " * Neon instrinsic unsafe"]
67975#[inline]
67976#[target_feature(enable = "neon")]
67977#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
67978#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
67979#[cfg_attr(
67980 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
67981 assert_instr(st2, LANE = 0)
67982)]
67983#[rustc_legacy_const_generics(2)]
67984#[cfg_attr(
67985 not(target_arch = "arm"),
67986 stable(feature = "neon_intrinsics", since = "1.59.0")
67987)]
67988#[cfg_attr(
67989 target_arch = "arm",
67990 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
67991)]
67992pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
67993 static_assert_uimm_bits!(LANE, 1);
67994 vst2_lane_s32::<LANE>(transmute(a), transmute(b))
67995}
67996#[doc = "Store multiple 2-element structures from two registers"]
67997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
67998#[doc = "## Safety"]
67999#[doc = " * Neon instrinsic unsafe"]
68000#[inline]
68001#[target_feature(enable = "neon")]
68002#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68003#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68004#[cfg_attr(
68005 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68006 assert_instr(st2, LANE = 0)
68007)]
68008#[rustc_legacy_const_generics(2)]
68009#[cfg_attr(
68010 not(target_arch = "arm"),
68011 stable(feature = "neon_intrinsics", since = "1.59.0")
68012)]
68013#[cfg_attr(
68014 target_arch = "arm",
68015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68016)]
68017pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
68018 static_assert_uimm_bits!(LANE, 2);
68019 vst2q_lane_s32::<LANE>(transmute(a), transmute(b))
68020}
68021#[doc = "Store multiple 2-element structures from two registers"]
68022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
68023#[doc = "## Safety"]
68024#[doc = " * Neon instrinsic unsafe"]
68025#[inline]
68026#[target_feature(enable = "neon")]
68027#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68028#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68029#[cfg_attr(
68030 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68031 assert_instr(st2, LANE = 0)
68032)]
68033#[rustc_legacy_const_generics(2)]
68034#[cfg_attr(
68035 not(target_arch = "arm"),
68036 stable(feature = "neon_intrinsics", since = "1.59.0")
68037)]
68038#[cfg_attr(
68039 target_arch = "arm",
68040 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68041)]
68042pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
68043 static_assert_uimm_bits!(LANE, 3);
68044 vst2_lane_s8::<LANE>(transmute(a), transmute(b))
68045}
68046#[doc = "Store multiple 2-element structures from two registers"]
68047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
68048#[doc = "## Safety"]
68049#[doc = " * Neon instrinsic unsafe"]
68050#[inline]
68051#[target_feature(enable = "neon")]
68052#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68053#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68054#[cfg_attr(
68055 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68056 assert_instr(st2, LANE = 0)
68057)]
68058#[rustc_legacy_const_generics(2)]
68059#[cfg_attr(
68060 not(target_arch = "arm"),
68061 stable(feature = "neon_intrinsics", since = "1.59.0")
68062)]
68063#[cfg_attr(
68064 target_arch = "arm",
68065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68066)]
68067pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
68068 static_assert_uimm_bits!(LANE, 2);
68069 vst2_lane_s16::<LANE>(transmute(a), transmute(b))
68070}
68071#[doc = "Store multiple 2-element structures from two registers"]
68072#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
68073#[doc = "## Safety"]
68074#[doc = " * Neon instrinsic unsafe"]
68075#[inline]
68076#[target_feature(enable = "neon")]
68077#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68078#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
68079#[cfg_attr(
68080 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68081 assert_instr(st2, LANE = 0)
68082)]
68083#[rustc_legacy_const_generics(2)]
68084#[cfg_attr(
68085 not(target_arch = "arm"),
68086 stable(feature = "neon_intrinsics", since = "1.59.0")
68087)]
68088#[cfg_attr(
68089 target_arch = "arm",
68090 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68091)]
68092pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
68093 static_assert_uimm_bits!(LANE, 3);
68094 vst2q_lane_s16::<LANE>(transmute(a), transmute(b))
68095}
68096#[doc = "Store multiple 2-element structures from two registers"]
68097#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
68098#[doc = "## Safety"]
68099#[doc = " * Neon instrinsic unsafe"]
68100#[inline]
68101#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
68102#[target_feature(enable = "neon,aes")]
68103#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68104#[cfg_attr(
68105 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68106 assert_instr(nop)
68107)]
68108#[cfg_attr(
68109 not(target_arch = "arm"),
68110 stable(feature = "neon_intrinsics", since = "1.59.0")
68111)]
68112#[cfg_attr(
68113 target_arch = "arm",
68114 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68115)]
68116pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
68117 vst2_s64(transmute(a), transmute(b))
68118}
68119#[doc = "Store multiple 2-element structures from two registers"]
68120#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68121#[doc = "## Safety"]
68122#[doc = " * Neon instrinsic unsafe"]
68123#[inline]
68124#[cfg(target_arch = "arm")]
68125#[target_feature(enable = "neon,v7")]
68126#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68127#[cfg_attr(test, assert_instr(nop))]
68128pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68129 unsafe extern "unadjusted" {
68130 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.v1i64.p0")]
68131 fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32);
68132 }
68133 _vst2_s64(a as _, b.0, b.1, 8)
68134}
68135#[doc = "Store multiple 2-element structures from two registers"]
68136#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
68137#[doc = "## Safety"]
68138#[doc = " * Neon instrinsic unsafe"]
68139#[inline]
68140#[target_feature(enable = "neon")]
68141#[cfg(not(target_arch = "arm"))]
68142#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68143#[cfg_attr(test, assert_instr(nop))]
68144pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
68145 unsafe extern "unadjusted" {
68146 #[cfg_attr(
68147 any(target_arch = "aarch64", target_arch = "arm64ec"),
68148 link_name = "llvm.aarch64.neon.st2.v1i64.p0"
68149 )]
68150 fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8);
68151 }
68152 _vst2_s64(b.0, b.1, a as _)
68153}
68154#[doc = "Store multiple 2-element structures from two registers"]
68155#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
68156#[doc = "## Safety"]
68157#[doc = " * Neon instrinsic unsafe"]
68158#[inline]
68159#[target_feature(enable = "neon")]
68160#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68161#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
68162#[cfg_attr(
68163 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68164 assert_instr(nop)
68165)]
68166#[cfg_attr(
68167 not(target_arch = "arm"),
68168 stable(feature = "neon_intrinsics", since = "1.59.0")
68169)]
68170#[cfg_attr(
68171 target_arch = "arm",
68172 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68173)]
68174pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
68175 vst2_s64(transmute(a), transmute(b))
68176}
68177#[doc = "Store multiple 2-element structures from two registers"]
68178#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
68179#[doc = "## Safety"]
68180#[doc = " * Neon instrinsic unsafe"]
68181#[inline]
68182#[target_feature(enable = "neon")]
68183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68185#[cfg_attr(
68186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68187 assert_instr(st2)
68188)]
68189#[cfg_attr(
68190 not(target_arch = "arm"),
68191 stable(feature = "neon_intrinsics", since = "1.59.0")
68192)]
68193#[cfg_attr(
68194 target_arch = "arm",
68195 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68196)]
68197pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
68198 vst2_s8(transmute(a), transmute(b))
68199}
68200#[doc = "Store multiple 2-element structures from two registers"]
68201#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
68202#[doc = "## Safety"]
68203#[doc = " * Neon instrinsic unsafe"]
68204#[inline]
68205#[target_feature(enable = "neon")]
68206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68207#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68208#[cfg_attr(
68209 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68210 assert_instr(st2)
68211)]
68212#[cfg_attr(
68213 not(target_arch = "arm"),
68214 stable(feature = "neon_intrinsics", since = "1.59.0")
68215)]
68216#[cfg_attr(
68217 target_arch = "arm",
68218 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68219)]
68220pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
68221 vst2q_s8(transmute(a), transmute(b))
68222}
68223#[doc = "Store multiple 2-element structures from two registers"]
68224#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
68225#[doc = "## Safety"]
68226#[doc = " * Neon instrinsic unsafe"]
68227#[inline]
68228#[target_feature(enable = "neon")]
68229#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68230#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68231#[cfg_attr(
68232 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68233 assert_instr(st2)
68234)]
68235#[cfg_attr(
68236 not(target_arch = "arm"),
68237 stable(feature = "neon_intrinsics", since = "1.59.0")
68238)]
68239#[cfg_attr(
68240 target_arch = "arm",
68241 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68242)]
68243pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
68244 vst2_s16(transmute(a), transmute(b))
68245}
68246#[doc = "Store multiple 2-element structures from two registers"]
68247#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
68248#[doc = "## Safety"]
68249#[doc = " * Neon instrinsic unsafe"]
68250#[inline]
68251#[target_feature(enable = "neon")]
68252#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68253#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68254#[cfg_attr(
68255 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68256 assert_instr(st2)
68257)]
68258#[cfg_attr(
68259 not(target_arch = "arm"),
68260 stable(feature = "neon_intrinsics", since = "1.59.0")
68261)]
68262#[cfg_attr(
68263 target_arch = "arm",
68264 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68265)]
68266pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
68267 vst2q_s16(transmute(a), transmute(b))
68268}
68269#[doc = "Store multiple 2-element structures from two registers"]
68270#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
68271#[doc = "## Safety"]
68272#[doc = " * Neon instrinsic unsafe"]
68273#[inline]
68274#[target_feature(enable = "neon")]
68275#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68276#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68277#[cfg_attr(
68278 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68279 assert_instr(st2)
68280)]
68281#[cfg_attr(
68282 not(target_arch = "arm"),
68283 stable(feature = "neon_intrinsics", since = "1.59.0")
68284)]
68285#[cfg_attr(
68286 target_arch = "arm",
68287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68288)]
68289pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
68290 vst2_s32(transmute(a), transmute(b))
68291}
68292#[doc = "Store multiple 2-element structures from two registers"]
68293#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
68294#[doc = "## Safety"]
68295#[doc = " * Neon instrinsic unsafe"]
68296#[inline]
68297#[target_feature(enable = "neon")]
68298#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68299#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68300#[cfg_attr(
68301 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68302 assert_instr(st2)
68303)]
68304#[cfg_attr(
68305 not(target_arch = "arm"),
68306 stable(feature = "neon_intrinsics", since = "1.59.0")
68307)]
68308#[cfg_attr(
68309 target_arch = "arm",
68310 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68311)]
68312pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
68313 vst2q_s32(transmute(a), transmute(b))
68314}
68315#[doc = "Store multiple 2-element structures from two registers"]
68316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
68317#[doc = "## Safety"]
68318#[doc = " * Neon instrinsic unsafe"]
68319#[inline]
68320#[target_feature(enable = "neon")]
68321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68322#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68323#[cfg_attr(
68324 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68325 assert_instr(st2)
68326)]
68327#[cfg_attr(
68328 not(target_arch = "arm"),
68329 stable(feature = "neon_intrinsics", since = "1.59.0")
68330)]
68331#[cfg_attr(
68332 target_arch = "arm",
68333 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68334)]
68335pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
68336 vst2_s8(transmute(a), transmute(b))
68337}
68338#[doc = "Store multiple 2-element structures from two registers"]
68339#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
68340#[doc = "## Safety"]
68341#[doc = " * Neon instrinsic unsafe"]
68342#[inline]
68343#[target_feature(enable = "neon")]
68344#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68345#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68346#[cfg_attr(
68347 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68348 assert_instr(st2)
68349)]
68350#[cfg_attr(
68351 not(target_arch = "arm"),
68352 stable(feature = "neon_intrinsics", since = "1.59.0")
68353)]
68354#[cfg_attr(
68355 target_arch = "arm",
68356 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68357)]
68358pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
68359 vst2q_s8(transmute(a), transmute(b))
68360}
68361#[doc = "Store multiple 2-element structures from two registers"]
68362#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
68363#[doc = "## Safety"]
68364#[doc = " * Neon instrinsic unsafe"]
68365#[inline]
68366#[target_feature(enable = "neon")]
68367#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68368#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68369#[cfg_attr(
68370 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68371 assert_instr(st2)
68372)]
68373#[cfg_attr(
68374 not(target_arch = "arm"),
68375 stable(feature = "neon_intrinsics", since = "1.59.0")
68376)]
68377#[cfg_attr(
68378 target_arch = "arm",
68379 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68380)]
68381pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
68382 vst2_s16(transmute(a), transmute(b))
68383}
68384#[doc = "Store multiple 2-element structures from two registers"]
68385#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
68386#[doc = "## Safety"]
68387#[doc = " * Neon instrinsic unsafe"]
68388#[inline]
68389#[target_feature(enable = "neon")]
68390#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68391#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
68392#[cfg_attr(
68393 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
68394 assert_instr(st2)
68395)]
68396#[cfg_attr(
68397 not(target_arch = "arm"),
68398 stable(feature = "neon_intrinsics", since = "1.59.0")
68399)]
68400#[cfg_attr(
68401 target_arch = "arm",
68402 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
68403)]
68404pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
68405 vst2q_s16(transmute(a), transmute(b))
68406}
68407#[doc = "Store multiple 3-element structures from three registers"]
68408#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68409#[doc = "## Safety"]
68410#[doc = " * Neon instrinsic unsafe"]
68411#[inline]
68412#[cfg(target_arch = "arm")]
68413#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68414#[target_feature(enable = "neon,fp16")]
68415#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68416#[cfg_attr(test, assert_instr(vst3))]
68417pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68418 unsafe extern "unadjusted" {
68419 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f16")]
68420 fn _vst3_f16(ptr: *mut i8, a: float16x4_t, b: float16x4_t, c: float16x4_t, size: i32);
68421 }
68422 _vst3_f16(a as _, b.0, b.1, b.2, 2)
68423}
68424#[doc = "Store multiple 3-element structures from three registers"]
68425#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68426#[doc = "## Safety"]
68427#[doc = " * Neon instrinsic unsafe"]
68428#[inline]
68429#[cfg(target_arch = "arm")]
68430#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68431#[target_feature(enable = "neon,fp16")]
68432#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68433#[cfg_attr(test, assert_instr(vst3))]
68434pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68435 unsafe extern "unadjusted" {
68436 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8f16")]
68437 fn _vst3q_f16(ptr: *mut i8, a: float16x8_t, b: float16x8_t, c: float16x8_t, size: i32);
68438 }
68439 _vst3q_f16(a as _, b.0, b.1, b.2, 2)
68440}
68441#[doc = "Store multiple 3-element structures from three registers"]
68442#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
68443#[doc = "## Safety"]
68444#[doc = " * Neon instrinsic unsafe"]
68445#[inline]
68446#[cfg(not(target_arch = "arm"))]
68447#[target_feature(enable = "neon,fp16")]
68448#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68449#[cfg_attr(test, assert_instr(st3))]
68450pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
68451 unsafe extern "unadjusted" {
68452 #[cfg_attr(
68453 any(target_arch = "aarch64", target_arch = "arm64ec"),
68454 link_name = "llvm.aarch64.neon.st3.v4f16.p0"
68455 )]
68456 fn _vst3_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, ptr: *mut i8);
68457 }
68458 _vst3_f16(b.0, b.1, b.2, a as _)
68459}
68460#[doc = "Store multiple 3-element structures from three registers"]
68461#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
68462#[doc = "## Safety"]
68463#[doc = " * Neon instrinsic unsafe"]
68464#[inline]
68465#[cfg(not(target_arch = "arm"))]
68466#[target_feature(enable = "neon,fp16")]
68467#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68468#[cfg_attr(test, assert_instr(st3))]
68469pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
68470 unsafe extern "unadjusted" {
68471 #[cfg_attr(
68472 any(target_arch = "aarch64", target_arch = "arm64ec"),
68473 link_name = "llvm.aarch64.neon.st3.v8f16.p0"
68474 )]
68475 fn _vst3q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, ptr: *mut i8);
68476 }
68477 _vst3q_f16(b.0, b.1, b.2, a as _)
68478}
68479#[doc = "Store multiple 3-element structures from three registers"]
68480#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68481#[doc = "## Safety"]
68482#[doc = " * Neon instrinsic unsafe"]
68483#[inline]
68484#[cfg(target_arch = "arm")]
68485#[target_feature(enable = "neon,v7")]
68486#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68487#[cfg_attr(test, assert_instr(vst3))]
68488pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68489 unsafe extern "unadjusted" {
68490 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2f32")]
68491 fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32);
68492 }
68493 _vst3_f32(a as _, b.0, b.1, b.2, 4)
68494}
68495#[doc = "Store multiple 3-element structures from three registers"]
68496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
68497#[doc = "## Safety"]
68498#[doc = " * Neon instrinsic unsafe"]
68499#[inline]
68500#[cfg(target_arch = "arm")]
68501#[target_feature(enable = "neon,v7")]
68502#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68503#[cfg_attr(test, assert_instr(vst3))]
68504pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
68505 unsafe extern "unadjusted" {
68506 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4f32")]
68507 fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32);
68508 }
68509 _vst3q_f32(a as _, b.0, b.1, b.2, 4)
68510}
68511#[doc = "Store multiple 3-element structures from three registers"]
68512#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
68513#[doc = "## Safety"]
68514#[doc = " * Neon instrinsic unsafe"]
68515#[inline]
68516#[cfg(target_arch = "arm")]
68517#[target_feature(enable = "neon,v7")]
68518#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68519#[cfg_attr(test, assert_instr(vst3))]
68520pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
68521 unsafe extern "unadjusted" {
68522 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i8")]
68523 fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32);
68524 }
68525 _vst3_s8(a as _, b.0, b.1, b.2, 1)
68526}
68527#[doc = "Store multiple 3-element structures from three registers"]
68528#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
68529#[doc = "## Safety"]
68530#[doc = " * Neon instrinsic unsafe"]
68531#[inline]
68532#[cfg(target_arch = "arm")]
68533#[target_feature(enable = "neon,v7")]
68534#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68535#[cfg_attr(test, assert_instr(vst3))]
68536pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
68537 unsafe extern "unadjusted" {
68538 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v16i8")]
68539 fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32);
68540 }
68541 _vst3q_s8(a as _, b.0, b.1, b.2, 1)
68542}
68543#[doc = "Store multiple 3-element structures from three registers"]
68544#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
68545#[doc = "## Safety"]
68546#[doc = " * Neon instrinsic unsafe"]
68547#[inline]
68548#[cfg(target_arch = "arm")]
68549#[target_feature(enable = "neon,v7")]
68550#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68551#[cfg_attr(test, assert_instr(vst3))]
68552pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
68553 unsafe extern "unadjusted" {
68554 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i16")]
68555 fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32);
68556 }
68557 _vst3_s16(a as _, b.0, b.1, b.2, 2)
68558}
68559#[doc = "Store multiple 3-element structures from three registers"]
68560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
68561#[doc = "## Safety"]
68562#[doc = " * Neon instrinsic unsafe"]
68563#[inline]
68564#[cfg(target_arch = "arm")]
68565#[target_feature(enable = "neon,v7")]
68566#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68567#[cfg_attr(test, assert_instr(vst3))]
68568pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
68569 unsafe extern "unadjusted" {
68570 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v8i16")]
68571 fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32);
68572 }
68573 _vst3q_s16(a as _, b.0, b.1, b.2, 2)
68574}
68575#[doc = "Store multiple 3-element structures from three registers"]
68576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
68577#[doc = "## Safety"]
68578#[doc = " * Neon instrinsic unsafe"]
68579#[inline]
68580#[cfg(target_arch = "arm")]
68581#[target_feature(enable = "neon,v7")]
68582#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68583#[cfg_attr(test, assert_instr(vst3))]
68584pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
68585 unsafe extern "unadjusted" {
68586 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v2i32")]
68587 fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32);
68588 }
68589 _vst3_s32(a as _, b.0, b.1, b.2, 4)
68590}
68591#[doc = "Store multiple 3-element structures from three registers"]
68592#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
68593#[doc = "## Safety"]
68594#[doc = " * Neon instrinsic unsafe"]
68595#[inline]
68596#[cfg(target_arch = "arm")]
68597#[target_feature(enable = "neon,v7")]
68598#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68599#[cfg_attr(test, assert_instr(vst3))]
68600pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
68601 unsafe extern "unadjusted" {
68602 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v4i32")]
68603 fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32);
68604 }
68605 _vst3q_s32(a as _, b.0, b.1, b.2, 4)
68606}
68607#[doc = "Store multiple 3-element structures from three registers"]
68608#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
68609#[doc = "## Safety"]
68610#[doc = " * Neon instrinsic unsafe"]
68611#[inline]
68612#[target_feature(enable = "neon")]
68613#[cfg(not(target_arch = "arm"))]
68614#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68615#[cfg_attr(test, assert_instr(st3))]
68616pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
68617 unsafe extern "unadjusted" {
68618 #[cfg_attr(
68619 any(target_arch = "aarch64", target_arch = "arm64ec"),
68620 link_name = "llvm.aarch64.neon.st3.v2f32.p0"
68621 )]
68622 fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8);
68623 }
68624 _vst3_f32(b.0, b.1, b.2, a as _)
68625}
68626#[doc = "Store multiple 3-element structures from three registers"]
68627#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
68628#[doc = "## Safety"]
68629#[doc = " * Neon instrinsic unsafe"]
68630#[inline]
68631#[target_feature(enable = "neon")]
68632#[cfg(not(target_arch = "arm"))]
68633#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68634#[cfg_attr(test, assert_instr(st3))]
68635pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
68636 unsafe extern "unadjusted" {
68637 #[cfg_attr(
68638 any(target_arch = "aarch64", target_arch = "arm64ec"),
68639 link_name = "llvm.aarch64.neon.st3.v4f32.p0"
68640 )]
68641 fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8);
68642 }
68643 _vst3q_f32(b.0, b.1, b.2, a as _)
68644}
68645#[doc = "Store multiple 3-element structures from three registers"]
68646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
68647#[doc = "## Safety"]
68648#[doc = " * Neon instrinsic unsafe"]
68649#[inline]
68650#[target_feature(enable = "neon")]
68651#[cfg(not(target_arch = "arm"))]
68652#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68653#[cfg_attr(test, assert_instr(st3))]
68654pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
68655 unsafe extern "unadjusted" {
68656 #[cfg_attr(
68657 any(target_arch = "aarch64", target_arch = "arm64ec"),
68658 link_name = "llvm.aarch64.neon.st3.v8i8.p0"
68659 )]
68660 fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8);
68661 }
68662 _vst3_s8(b.0, b.1, b.2, a as _)
68663}
68664#[doc = "Store multiple 3-element structures from three registers"]
68665#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
68666#[doc = "## Safety"]
68667#[doc = " * Neon instrinsic unsafe"]
68668#[inline]
68669#[target_feature(enable = "neon")]
68670#[cfg(not(target_arch = "arm"))]
68671#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68672#[cfg_attr(test, assert_instr(st3))]
68673pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
68674 unsafe extern "unadjusted" {
68675 #[cfg_attr(
68676 any(target_arch = "aarch64", target_arch = "arm64ec"),
68677 link_name = "llvm.aarch64.neon.st3.v16i8.p0"
68678 )]
68679 fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8);
68680 }
68681 _vst3q_s8(b.0, b.1, b.2, a as _)
68682}
68683#[doc = "Store multiple 3-element structures from three registers"]
68684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
68685#[doc = "## Safety"]
68686#[doc = " * Neon instrinsic unsafe"]
68687#[inline]
68688#[target_feature(enable = "neon")]
68689#[cfg(not(target_arch = "arm"))]
68690#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68691#[cfg_attr(test, assert_instr(st3))]
68692pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
68693 unsafe extern "unadjusted" {
68694 #[cfg_attr(
68695 any(target_arch = "aarch64", target_arch = "arm64ec"),
68696 link_name = "llvm.aarch64.neon.st3.v4i16.p0"
68697 )]
68698 fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8);
68699 }
68700 _vst3_s16(b.0, b.1, b.2, a as _)
68701}
68702#[doc = "Store multiple 3-element structures from three registers"]
68703#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
68704#[doc = "## Safety"]
68705#[doc = " * Neon instrinsic unsafe"]
68706#[inline]
68707#[target_feature(enable = "neon")]
68708#[cfg(not(target_arch = "arm"))]
68709#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68710#[cfg_attr(test, assert_instr(st3))]
68711pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
68712 unsafe extern "unadjusted" {
68713 #[cfg_attr(
68714 any(target_arch = "aarch64", target_arch = "arm64ec"),
68715 link_name = "llvm.aarch64.neon.st3.v8i16.p0"
68716 )]
68717 fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8);
68718 }
68719 _vst3q_s16(b.0, b.1, b.2, a as _)
68720}
68721#[doc = "Store multiple 3-element structures from three registers"]
68722#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
68723#[doc = "## Safety"]
68724#[doc = " * Neon instrinsic unsafe"]
68725#[inline]
68726#[target_feature(enable = "neon")]
68727#[cfg(not(target_arch = "arm"))]
68728#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68729#[cfg_attr(test, assert_instr(st3))]
68730pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
68731 unsafe extern "unadjusted" {
68732 #[cfg_attr(
68733 any(target_arch = "aarch64", target_arch = "arm64ec"),
68734 link_name = "llvm.aarch64.neon.st3.v2i32.p0"
68735 )]
68736 fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8);
68737 }
68738 _vst3_s32(b.0, b.1, b.2, a as _)
68739}
68740#[doc = "Store multiple 3-element structures from three registers"]
68741#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
68742#[doc = "## Safety"]
68743#[doc = " * Neon instrinsic unsafe"]
68744#[inline]
68745#[target_feature(enable = "neon")]
68746#[cfg(not(target_arch = "arm"))]
68747#[stable(feature = "neon_intrinsics", since = "1.59.0")]
68748#[cfg_attr(test, assert_instr(st3))]
68749pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
68750 unsafe extern "unadjusted" {
68751 #[cfg_attr(
68752 any(target_arch = "aarch64", target_arch = "arm64ec"),
68753 link_name = "llvm.aarch64.neon.st3.v4i32.p0"
68754 )]
68755 fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8);
68756 }
68757 _vst3q_s32(b.0, b.1, b.2, a as _)
68758}
68759#[doc = "Store multiple 3-element structures from three registers"]
68760#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
68761#[doc = "## Safety"]
68762#[doc = " * Neon instrinsic unsafe"]
68763#[inline]
68764#[cfg(target_arch = "arm")]
68765#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68766#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68767#[rustc_legacy_const_generics(2)]
68768#[target_feature(enable = "neon,fp16")]
68769#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68770pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
68771 static_assert_uimm_bits!(LANE, 2);
68772 unsafe extern "unadjusted" {
68773 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4f16")]
68774 fn _vst3_lane_f16(
68775 ptr: *mut i8,
68776 a: float16x4_t,
68777 b: float16x4_t,
68778 c: float16x4_t,
68779 n: i32,
68780 size: i32,
68781 );
68782 }
68783 _vst3_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
68784}
68785#[doc = "Store multiple 3-element structures from three registers"]
68786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
68787#[doc = "## Safety"]
68788#[doc = " * Neon instrinsic unsafe"]
68789#[inline]
68790#[cfg(target_arch = "arm")]
68791#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
68792#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68793#[rustc_legacy_const_generics(2)]
68794#[target_feature(enable = "neon,fp16")]
68795#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68796pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
68797 static_assert_uimm_bits!(LANE, 3);
68798 unsafe extern "unadjusted" {
68799 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8f16")]
68800 fn _vst3q_lane_f16(
68801 ptr: *mut i8,
68802 a: float16x8_t,
68803 b: float16x8_t,
68804 c: float16x8_t,
68805 n: i32,
68806 size: i32,
68807 );
68808 }
68809 _vst3q_lane_f16(a as _, b.0, b.1, b.2, LANE, 4)
68810}
68811#[doc = "Store multiple 3-element structures from three registers"]
68812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
68813#[doc = "## Safety"]
68814#[doc = " * Neon instrinsic unsafe"]
68815#[inline]
68816#[cfg(not(target_arch = "arm"))]
68817#[rustc_legacy_const_generics(2)]
68818#[cfg_attr(test, assert_instr(st3, LANE = 0))]
68819#[target_feature(enable = "neon,fp16")]
68820#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68821pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
68822 static_assert_uimm_bits!(LANE, 2);
68823 unsafe extern "unadjusted" {
68824 #[cfg_attr(
68825 any(target_arch = "aarch64", target_arch = "arm64ec"),
68826 link_name = "llvm.aarch64.neon.st3lane.v4f16.p0"
68827 )]
68828 fn _vst3_lane_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, n: i64, ptr: *mut i8);
68829 }
68830 _vst3_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
68831}
68832#[doc = "Store multiple 3-element structures from three registers"]
68833#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
68834#[doc = "## Safety"]
68835#[doc = " * Neon instrinsic unsafe"]
68836#[inline]
68837#[cfg(not(target_arch = "arm"))]
68838#[rustc_legacy_const_generics(2)]
68839#[cfg_attr(test, assert_instr(st3, LANE = 0))]
68840#[target_feature(enable = "neon,fp16")]
68841#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
68842pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
68843 static_assert_uimm_bits!(LANE, 3);
68844 unsafe extern "unadjusted" {
68845 #[cfg_attr(
68846 any(target_arch = "aarch64", target_arch = "arm64ec"),
68847 link_name = "llvm.aarch64.neon.st3lane.v8f16.p0"
68848 )]
68849 fn _vst3q_lane_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, n: i64, ptr: *mut i8);
68850 }
68851 _vst3q_lane_f16(b.0, b.1, b.2, LANE as i64, a as _)
68852}
68853#[doc = "Store multiple 3-element structures from three registers"]
68854#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
68855#[doc = "## Safety"]
68856#[doc = " * Neon instrinsic unsafe"]
68857#[inline]
68858#[cfg(target_arch = "arm")]
68859#[target_feature(enable = "neon,v7")]
68860#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68861#[rustc_legacy_const_generics(2)]
68862#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68863pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
68864 static_assert_uimm_bits!(LANE, 1);
68865 unsafe extern "unadjusted" {
68866 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v2f32")]
68867 fn _vst3_lane_f32(
68868 ptr: *mut i8,
68869 a: float32x2_t,
68870 b: float32x2_t,
68871 c: float32x2_t,
68872 n: i32,
68873 size: i32,
68874 );
68875 }
68876 _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
68877}
68878#[doc = "Store multiple 3-element structures from three registers"]
68879#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
68880#[doc = "## Safety"]
68881#[doc = " * Neon instrinsic unsafe"]
68882#[inline]
68883#[cfg(target_arch = "arm")]
68884#[target_feature(enable = "neon,v7")]
68885#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68886#[rustc_legacy_const_generics(2)]
68887#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68888pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
68889 static_assert_uimm_bits!(LANE, 2);
68890 unsafe extern "unadjusted" {
68891 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4f32")]
68892 fn _vst3q_lane_f32(
68893 ptr: *mut i8,
68894 a: float32x4_t,
68895 b: float32x4_t,
68896 c: float32x4_t,
68897 n: i32,
68898 size: i32,
68899 );
68900 }
68901 _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4)
68902}
68903#[doc = "Store multiple 3-element structures from three registers"]
68904#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
68905#[doc = "## Safety"]
68906#[doc = " * Neon instrinsic unsafe"]
68907#[inline]
68908#[cfg(target_arch = "arm")]
68909#[target_feature(enable = "neon,v7")]
68910#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68911#[rustc_legacy_const_generics(2)]
68912#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68913pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
68914 static_assert_uimm_bits!(LANE, 3);
68915 unsafe extern "unadjusted" {
68916 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8i8")]
68917 fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32);
68918 }
68919 _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1)
68920}
68921#[doc = "Store multiple 3-element structures from three registers"]
68922#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
68923#[doc = "## Safety"]
68924#[doc = " * Neon instrinsic unsafe"]
68925#[inline]
68926#[cfg(target_arch = "arm")]
68927#[target_feature(enable = "neon,v7")]
68928#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68929#[rustc_legacy_const_generics(2)]
68930#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68931pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
68932 static_assert_uimm_bits!(LANE, 2);
68933 unsafe extern "unadjusted" {
68934 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4i16")]
68935 fn _vst3_lane_s16(
68936 ptr: *mut i8,
68937 a: int16x4_t,
68938 b: int16x4_t,
68939 c: int16x4_t,
68940 n: i32,
68941 size: i32,
68942 );
68943 }
68944 _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
68945}
68946#[doc = "Store multiple 3-element structures from three registers"]
68947#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
68948#[doc = "## Safety"]
68949#[doc = " * Neon instrinsic unsafe"]
68950#[inline]
68951#[cfg(target_arch = "arm")]
68952#[target_feature(enable = "neon,v7")]
68953#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68954#[rustc_legacy_const_generics(2)]
68955#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68956pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
68957 static_assert_uimm_bits!(LANE, 3);
68958 unsafe extern "unadjusted" {
68959 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v8i16")]
68960 fn _vst3q_lane_s16(
68961 ptr: *mut i8,
68962 a: int16x8_t,
68963 b: int16x8_t,
68964 c: int16x8_t,
68965 n: i32,
68966 size: i32,
68967 );
68968 }
68969 _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2)
68970}
68971#[doc = "Store multiple 3-element structures from three registers"]
68972#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
68973#[doc = "## Safety"]
68974#[doc = " * Neon instrinsic unsafe"]
68975#[inline]
68976#[cfg(target_arch = "arm")]
68977#[target_feature(enable = "neon,v7")]
68978#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
68979#[rustc_legacy_const_generics(2)]
68980#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
68981pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
68982 static_assert_uimm_bits!(LANE, 1);
68983 unsafe extern "unadjusted" {
68984 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v2i32")]
68985 fn _vst3_lane_s32(
68986 ptr: *mut i8,
68987 a: int32x2_t,
68988 b: int32x2_t,
68989 c: int32x2_t,
68990 n: i32,
68991 size: i32,
68992 );
68993 }
68994 _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
68995}
68996#[doc = "Store multiple 3-element structures from three registers"]
68997#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
68998#[doc = "## Safety"]
68999#[doc = " * Neon instrinsic unsafe"]
69000#[inline]
69001#[cfg(target_arch = "arm")]
69002#[target_feature(enable = "neon,v7")]
69003#[cfg_attr(test, assert_instr(vst3, LANE = 0))]
69004#[rustc_legacy_const_generics(2)]
69005#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69006pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69007 static_assert_uimm_bits!(LANE, 2);
69008 unsafe extern "unadjusted" {
69009 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0.v4i32")]
69010 fn _vst3q_lane_s32(
69011 ptr: *mut i8,
69012 a: int32x4_t,
69013 b: int32x4_t,
69014 c: int32x4_t,
69015 n: i32,
69016 size: i32,
69017 );
69018 }
69019 _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4)
69020}
69021#[doc = "Store multiple 3-element structures from three registers"]
69022#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
69023#[doc = "## Safety"]
69024#[doc = " * Neon instrinsic unsafe"]
69025#[inline]
69026#[target_feature(enable = "neon")]
69027#[cfg(not(target_arch = "arm"))]
69028#[rustc_legacy_const_generics(2)]
69029#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69030#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69031pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
69032 static_assert_uimm_bits!(LANE, 1);
69033 unsafe extern "unadjusted" {
69034 #[cfg_attr(
69035 any(target_arch = "aarch64", target_arch = "arm64ec"),
69036 link_name = "llvm.aarch64.neon.st3lane.v2f32.p0"
69037 )]
69038 fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8);
69039 }
69040 _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69041}
69042#[doc = "Store multiple 3-element structures from three registers"]
69043#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
69044#[doc = "## Safety"]
69045#[doc = " * Neon instrinsic unsafe"]
69046#[inline]
69047#[target_feature(enable = "neon")]
69048#[cfg(not(target_arch = "arm"))]
69049#[rustc_legacy_const_generics(2)]
69050#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69051#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69052pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
69053 static_assert_uimm_bits!(LANE, 2);
69054 unsafe extern "unadjusted" {
69055 #[cfg_attr(
69056 any(target_arch = "aarch64", target_arch = "arm64ec"),
69057 link_name = "llvm.aarch64.neon.st3lane.v4f32.p0"
69058 )]
69059 fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8);
69060 }
69061 _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _)
69062}
69063#[doc = "Store multiple 3-element structures from three registers"]
69064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
69065#[doc = "## Safety"]
69066#[doc = " * Neon instrinsic unsafe"]
69067#[inline]
69068#[target_feature(enable = "neon")]
69069#[cfg(not(target_arch = "arm"))]
69070#[rustc_legacy_const_generics(2)]
69071#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69072#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69073pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
69074 static_assert_uimm_bits!(LANE, 3);
69075 unsafe extern "unadjusted" {
69076 #[cfg_attr(
69077 any(target_arch = "aarch64", target_arch = "arm64ec"),
69078 link_name = "llvm.aarch64.neon.st3lane.v8i8.p0"
69079 )]
69080 fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8);
69081 }
69082 _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _)
69083}
69084#[doc = "Store multiple 3-element structures from three registers"]
69085#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
69086#[doc = "## Safety"]
69087#[doc = " * Neon instrinsic unsafe"]
69088#[inline]
69089#[target_feature(enable = "neon")]
69090#[cfg(not(target_arch = "arm"))]
69091#[rustc_legacy_const_generics(2)]
69092#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69093#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69094pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
69095 static_assert_uimm_bits!(LANE, 2);
69096 unsafe extern "unadjusted" {
69097 #[cfg_attr(
69098 any(target_arch = "aarch64", target_arch = "arm64ec"),
69099 link_name = "llvm.aarch64.neon.st3lane.v4i16.p0"
69100 )]
69101 fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8);
69102 }
69103 _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69104}
69105#[doc = "Store multiple 3-element structures from three registers"]
69106#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
69107#[doc = "## Safety"]
69108#[doc = " * Neon instrinsic unsafe"]
69109#[inline]
69110#[target_feature(enable = "neon")]
69111#[cfg(not(target_arch = "arm"))]
69112#[rustc_legacy_const_generics(2)]
69113#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69114#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69115pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
69116 static_assert_uimm_bits!(LANE, 3);
69117 unsafe extern "unadjusted" {
69118 #[cfg_attr(
69119 any(target_arch = "aarch64", target_arch = "arm64ec"),
69120 link_name = "llvm.aarch64.neon.st3lane.v8i16.p0"
69121 )]
69122 fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8);
69123 }
69124 _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _)
69125}
69126#[doc = "Store multiple 3-element structures from three registers"]
69127#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
69128#[doc = "## Safety"]
69129#[doc = " * Neon instrinsic unsafe"]
69130#[inline]
69131#[target_feature(enable = "neon")]
69132#[cfg(not(target_arch = "arm"))]
69133#[rustc_legacy_const_generics(2)]
69134#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69135#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69136pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
69137 static_assert_uimm_bits!(LANE, 1);
69138 unsafe extern "unadjusted" {
69139 #[cfg_attr(
69140 any(target_arch = "aarch64", target_arch = "arm64ec"),
69141 link_name = "llvm.aarch64.neon.st3lane.v2i32.p0"
69142 )]
69143 fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8);
69144 }
69145 _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69146}
69147#[doc = "Store multiple 3-element structures from three registers"]
69148#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
69149#[doc = "## Safety"]
69150#[doc = " * Neon instrinsic unsafe"]
69151#[inline]
69152#[target_feature(enable = "neon")]
69153#[cfg(not(target_arch = "arm"))]
69154#[rustc_legacy_const_generics(2)]
69155#[cfg_attr(test, assert_instr(st3, LANE = 0))]
69156#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69157pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
69158 static_assert_uimm_bits!(LANE, 2);
69159 unsafe extern "unadjusted" {
69160 #[cfg_attr(
69161 any(target_arch = "aarch64", target_arch = "arm64ec"),
69162 link_name = "llvm.aarch64.neon.st3lane.v4i32.p0"
69163 )]
69164 fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8);
69165 }
69166 _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _)
69167}
69168#[doc = "Store multiple 3-element structures from three registers"]
69169#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
69170#[doc = "## Safety"]
69171#[doc = " * Neon instrinsic unsafe"]
69172#[inline]
69173#[target_feature(enable = "neon")]
69174#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69175#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69176#[cfg_attr(
69177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69178 assert_instr(st3, LANE = 0)
69179)]
69180#[rustc_legacy_const_generics(2)]
69181#[cfg_attr(
69182 not(target_arch = "arm"),
69183 stable(feature = "neon_intrinsics", since = "1.59.0")
69184)]
69185#[cfg_attr(
69186 target_arch = "arm",
69187 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69188)]
69189pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
69190 static_assert_uimm_bits!(LANE, 3);
69191 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69192}
69193#[doc = "Store multiple 3-element structures from three registers"]
69194#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
69195#[doc = "## Safety"]
69196#[doc = " * Neon instrinsic unsafe"]
69197#[inline]
69198#[target_feature(enable = "neon")]
69199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69201#[cfg_attr(
69202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69203 assert_instr(st3, LANE = 0)
69204)]
69205#[rustc_legacy_const_generics(2)]
69206#[cfg_attr(
69207 not(target_arch = "arm"),
69208 stable(feature = "neon_intrinsics", since = "1.59.0")
69209)]
69210#[cfg_attr(
69211 target_arch = "arm",
69212 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69213)]
69214pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
69215 static_assert_uimm_bits!(LANE, 2);
69216 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69217}
69218#[doc = "Store multiple 3-element structures from three registers"]
69219#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
69220#[doc = "## Safety"]
69221#[doc = " * Neon instrinsic unsafe"]
69222#[inline]
69223#[target_feature(enable = "neon")]
69224#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69225#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69226#[cfg_attr(
69227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69228 assert_instr(st3, LANE = 0)
69229)]
69230#[rustc_legacy_const_generics(2)]
69231#[cfg_attr(
69232 not(target_arch = "arm"),
69233 stable(feature = "neon_intrinsics", since = "1.59.0")
69234)]
69235#[cfg_attr(
69236 target_arch = "arm",
69237 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69238)]
69239pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
69240 static_assert_uimm_bits!(LANE, 3);
69241 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69242}
69243#[doc = "Store multiple 3-element structures from three registers"]
69244#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
69245#[doc = "## Safety"]
69246#[doc = " * Neon instrinsic unsafe"]
69247#[inline]
69248#[target_feature(enable = "neon")]
69249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69251#[cfg_attr(
69252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69253 assert_instr(st3, LANE = 0)
69254)]
69255#[rustc_legacy_const_generics(2)]
69256#[cfg_attr(
69257 not(target_arch = "arm"),
69258 stable(feature = "neon_intrinsics", since = "1.59.0")
69259)]
69260#[cfg_attr(
69261 target_arch = "arm",
69262 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69263)]
69264pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
69265 static_assert_uimm_bits!(LANE, 1);
69266 vst3_lane_s32::<LANE>(transmute(a), transmute(b))
69267}
69268#[doc = "Store multiple 3-element structures from three registers"]
69269#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
69270#[doc = "## Safety"]
69271#[doc = " * Neon instrinsic unsafe"]
69272#[inline]
69273#[target_feature(enable = "neon")]
69274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69275#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69276#[cfg_attr(
69277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69278 assert_instr(st3, LANE = 0)
69279)]
69280#[rustc_legacy_const_generics(2)]
69281#[cfg_attr(
69282 not(target_arch = "arm"),
69283 stable(feature = "neon_intrinsics", since = "1.59.0")
69284)]
69285#[cfg_attr(
69286 target_arch = "arm",
69287 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69288)]
69289pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
69290 static_assert_uimm_bits!(LANE, 2);
69291 vst3q_lane_s32::<LANE>(transmute(a), transmute(b))
69292}
69293#[doc = "Store multiple 3-element structures from three registers"]
69294#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
69295#[doc = "## Safety"]
69296#[doc = " * Neon instrinsic unsafe"]
69297#[inline]
69298#[target_feature(enable = "neon")]
69299#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69300#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69301#[cfg_attr(
69302 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69303 assert_instr(st3, LANE = 0)
69304)]
69305#[rustc_legacy_const_generics(2)]
69306#[cfg_attr(
69307 not(target_arch = "arm"),
69308 stable(feature = "neon_intrinsics", since = "1.59.0")
69309)]
69310#[cfg_attr(
69311 target_arch = "arm",
69312 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69313)]
69314pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
69315 static_assert_uimm_bits!(LANE, 3);
69316 vst3_lane_s8::<LANE>(transmute(a), transmute(b))
69317}
69318#[doc = "Store multiple 3-element structures from three registers"]
69319#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
69320#[doc = "## Safety"]
69321#[doc = " * Neon instrinsic unsafe"]
69322#[inline]
69323#[target_feature(enable = "neon")]
69324#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69325#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69326#[cfg_attr(
69327 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69328 assert_instr(st3, LANE = 0)
69329)]
69330#[rustc_legacy_const_generics(2)]
69331#[cfg_attr(
69332 not(target_arch = "arm"),
69333 stable(feature = "neon_intrinsics", since = "1.59.0")
69334)]
69335#[cfg_attr(
69336 target_arch = "arm",
69337 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69338)]
69339pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
69340 static_assert_uimm_bits!(LANE, 2);
69341 vst3_lane_s16::<LANE>(transmute(a), transmute(b))
69342}
69343#[doc = "Store multiple 3-element structures from three registers"]
69344#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
69345#[doc = "## Safety"]
69346#[doc = " * Neon instrinsic unsafe"]
69347#[inline]
69348#[target_feature(enable = "neon")]
69349#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69350#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
69351#[cfg_attr(
69352 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69353 assert_instr(st3, LANE = 0)
69354)]
69355#[rustc_legacy_const_generics(2)]
69356#[cfg_attr(
69357 not(target_arch = "arm"),
69358 stable(feature = "neon_intrinsics", since = "1.59.0")
69359)]
69360#[cfg_attr(
69361 target_arch = "arm",
69362 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69363)]
69364pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
69365 static_assert_uimm_bits!(LANE, 3);
69366 vst3q_lane_s16::<LANE>(transmute(a), transmute(b))
69367}
69368#[doc = "Store multiple 3-element structures from three registers"]
69369#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
69370#[doc = "## Safety"]
69371#[doc = " * Neon instrinsic unsafe"]
69372#[inline]
69373#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
69374#[target_feature(enable = "neon,aes")]
69375#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69376#[cfg_attr(
69377 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69378 assert_instr(nop)
69379)]
69380#[cfg_attr(
69381 not(target_arch = "arm"),
69382 stable(feature = "neon_intrinsics", since = "1.59.0")
69383)]
69384#[cfg_attr(
69385 target_arch = "arm",
69386 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69387)]
69388pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
69389 vst3_s64(transmute(a), transmute(b))
69390}
69391#[doc = "Store multiple 3-element structures from three registers"]
69392#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69393#[doc = "## Safety"]
69394#[doc = " * Neon instrinsic unsafe"]
69395#[inline]
69396#[target_feature(enable = "neon")]
69397#[cfg(not(target_arch = "arm"))]
69398#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69399#[cfg_attr(test, assert_instr(nop))]
69400pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69401 unsafe extern "unadjusted" {
69402 #[cfg_attr(
69403 any(target_arch = "aarch64", target_arch = "arm64ec"),
69404 link_name = "llvm.aarch64.neon.st3.v1i64.p0"
69405 )]
69406 fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8);
69407 }
69408 _vst3_s64(b.0, b.1, b.2, a as _)
69409}
69410#[doc = "Store multiple 3-element structures from three registers"]
69411#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
69412#[doc = "## Safety"]
69413#[doc = " * Neon instrinsic unsafe"]
69414#[inline]
69415#[cfg(target_arch = "arm")]
69416#[target_feature(enable = "neon,v7")]
69417#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69418#[cfg_attr(test, assert_instr(nop))]
69419pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
69420 unsafe extern "unadjusted" {
69421 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0.v1i64")]
69422 fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32);
69423 }
69424 _vst3_s64(a as _, b.0, b.1, b.2, 8)
69425}
69426#[doc = "Store multiple 3-element structures from three registers"]
69427#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
69428#[doc = "## Safety"]
69429#[doc = " * Neon instrinsic unsafe"]
69430#[inline]
69431#[target_feature(enable = "neon")]
69432#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69433#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
69434#[cfg_attr(
69435 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69436 assert_instr(nop)
69437)]
69438#[cfg_attr(
69439 not(target_arch = "arm"),
69440 stable(feature = "neon_intrinsics", since = "1.59.0")
69441)]
69442#[cfg_attr(
69443 target_arch = "arm",
69444 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69445)]
69446pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
69447 vst3_s64(transmute(a), transmute(b))
69448}
69449#[doc = "Store multiple 3-element structures from three registers"]
69450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
69451#[doc = "## Safety"]
69452#[doc = " * Neon instrinsic unsafe"]
69453#[inline]
69454#[target_feature(enable = "neon")]
69455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69456#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69457#[cfg_attr(
69458 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69459 assert_instr(st3)
69460)]
69461#[cfg_attr(
69462 not(target_arch = "arm"),
69463 stable(feature = "neon_intrinsics", since = "1.59.0")
69464)]
69465#[cfg_attr(
69466 target_arch = "arm",
69467 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69468)]
69469pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
69470 vst3_s8(transmute(a), transmute(b))
69471}
69472#[doc = "Store multiple 3-element structures from three registers"]
69473#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
69474#[doc = "## Safety"]
69475#[doc = " * Neon instrinsic unsafe"]
69476#[inline]
69477#[target_feature(enable = "neon")]
69478#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69479#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69480#[cfg_attr(
69481 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69482 assert_instr(st3)
69483)]
69484#[cfg_attr(
69485 not(target_arch = "arm"),
69486 stable(feature = "neon_intrinsics", since = "1.59.0")
69487)]
69488#[cfg_attr(
69489 target_arch = "arm",
69490 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69491)]
69492pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
69493 vst3q_s8(transmute(a), transmute(b))
69494}
69495#[doc = "Store multiple 3-element structures from three registers"]
69496#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
69497#[doc = "## Safety"]
69498#[doc = " * Neon instrinsic unsafe"]
69499#[inline]
69500#[target_feature(enable = "neon")]
69501#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69502#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69503#[cfg_attr(
69504 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69505 assert_instr(st3)
69506)]
69507#[cfg_attr(
69508 not(target_arch = "arm"),
69509 stable(feature = "neon_intrinsics", since = "1.59.0")
69510)]
69511#[cfg_attr(
69512 target_arch = "arm",
69513 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69514)]
69515pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
69516 vst3_s16(transmute(a), transmute(b))
69517}
69518#[doc = "Store multiple 3-element structures from three registers"]
69519#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
69520#[doc = "## Safety"]
69521#[doc = " * Neon instrinsic unsafe"]
69522#[inline]
69523#[target_feature(enable = "neon")]
69524#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69525#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69526#[cfg_attr(
69527 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69528 assert_instr(st3)
69529)]
69530#[cfg_attr(
69531 not(target_arch = "arm"),
69532 stable(feature = "neon_intrinsics", since = "1.59.0")
69533)]
69534#[cfg_attr(
69535 target_arch = "arm",
69536 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69537)]
69538pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
69539 vst3q_s16(transmute(a), transmute(b))
69540}
69541#[doc = "Store multiple 3-element structures from three registers"]
69542#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
69543#[doc = "## Safety"]
69544#[doc = " * Neon instrinsic unsafe"]
69545#[inline]
69546#[target_feature(enable = "neon")]
69547#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69548#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69549#[cfg_attr(
69550 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69551 assert_instr(st3)
69552)]
69553#[cfg_attr(
69554 not(target_arch = "arm"),
69555 stable(feature = "neon_intrinsics", since = "1.59.0")
69556)]
69557#[cfg_attr(
69558 target_arch = "arm",
69559 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69560)]
69561pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
69562 vst3_s32(transmute(a), transmute(b))
69563}
69564#[doc = "Store multiple 3-element structures from three registers"]
69565#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
69566#[doc = "## Safety"]
69567#[doc = " * Neon instrinsic unsafe"]
69568#[inline]
69569#[target_feature(enable = "neon")]
69570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69572#[cfg_attr(
69573 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69574 assert_instr(st3)
69575)]
69576#[cfg_attr(
69577 not(target_arch = "arm"),
69578 stable(feature = "neon_intrinsics", since = "1.59.0")
69579)]
69580#[cfg_attr(
69581 target_arch = "arm",
69582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69583)]
69584pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
69585 vst3q_s32(transmute(a), transmute(b))
69586}
69587#[doc = "Store multiple 3-element structures from three registers"]
69588#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
69589#[doc = "## Safety"]
69590#[doc = " * Neon instrinsic unsafe"]
69591#[inline]
69592#[target_feature(enable = "neon")]
69593#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69594#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69595#[cfg_attr(
69596 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69597 assert_instr(st3)
69598)]
69599#[cfg_attr(
69600 not(target_arch = "arm"),
69601 stable(feature = "neon_intrinsics", since = "1.59.0")
69602)]
69603#[cfg_attr(
69604 target_arch = "arm",
69605 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69606)]
69607pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
69608 vst3_s8(transmute(a), transmute(b))
69609}
69610#[doc = "Store multiple 3-element structures from three registers"]
69611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
69612#[doc = "## Safety"]
69613#[doc = " * Neon instrinsic unsafe"]
69614#[inline]
69615#[target_feature(enable = "neon")]
69616#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69617#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69618#[cfg_attr(
69619 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69620 assert_instr(st3)
69621)]
69622#[cfg_attr(
69623 not(target_arch = "arm"),
69624 stable(feature = "neon_intrinsics", since = "1.59.0")
69625)]
69626#[cfg_attr(
69627 target_arch = "arm",
69628 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69629)]
69630pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
69631 vst3q_s8(transmute(a), transmute(b))
69632}
69633#[doc = "Store multiple 3-element structures from three registers"]
69634#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
69635#[doc = "## Safety"]
69636#[doc = " * Neon instrinsic unsafe"]
69637#[inline]
69638#[target_feature(enable = "neon")]
69639#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69640#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69641#[cfg_attr(
69642 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69643 assert_instr(st3)
69644)]
69645#[cfg_attr(
69646 not(target_arch = "arm"),
69647 stable(feature = "neon_intrinsics", since = "1.59.0")
69648)]
69649#[cfg_attr(
69650 target_arch = "arm",
69651 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69652)]
69653pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
69654 vst3_s16(transmute(a), transmute(b))
69655}
69656#[doc = "Store multiple 3-element structures from three registers"]
69657#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
69658#[doc = "## Safety"]
69659#[doc = " * Neon instrinsic unsafe"]
69660#[inline]
69661#[target_feature(enable = "neon")]
69662#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69663#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
69664#[cfg_attr(
69665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
69666 assert_instr(st3)
69667)]
69668#[cfg_attr(
69669 not(target_arch = "arm"),
69670 stable(feature = "neon_intrinsics", since = "1.59.0")
69671)]
69672#[cfg_attr(
69673 target_arch = "arm",
69674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
69675)]
69676pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
69677 vst3q_s16(transmute(a), transmute(b))
69678}
69679#[doc = "Store multiple 4-element structures from four registers"]
69680#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
69681#[doc = "## Safety"]
69682#[doc = " * Neon instrinsic unsafe"]
69683#[inline]
69684#[cfg(target_arch = "arm")]
69685#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69686#[target_feature(enable = "neon,fp16")]
69687#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69688#[cfg_attr(test, assert_instr(vst4))]
69689pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
69690 unsafe extern "unadjusted" {
69691 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4f16")]
69692 fn _vst4_f16(
69693 ptr: *mut i8,
69694 a: float16x4_t,
69695 b: float16x4_t,
69696 c: float16x4_t,
69697 d: float16x4_t,
69698 size: i32,
69699 );
69700 }
69701 _vst4_f16(a as _, b.0, b.1, b.2, b.3, 2)
69702}
69703#[doc = "Store multiple 4-element structures from four registers"]
69704#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
69705#[doc = "## Safety"]
69706#[doc = " * Neon instrinsic unsafe"]
69707#[inline]
69708#[cfg(target_arch = "arm")]
69709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
69710#[target_feature(enable = "neon,fp16")]
69711#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69712#[cfg_attr(test, assert_instr(vst4))]
69713pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
69714 unsafe extern "unadjusted" {
69715 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8f16")]
69716 fn _vst4q_f16(
69717 ptr: *mut i8,
69718 a: float16x8_t,
69719 b: float16x8_t,
69720 c: float16x8_t,
69721 d: float16x8_t,
69722 size: i32,
69723 );
69724 }
69725 _vst4q_f16(a as _, b.0, b.1, b.2, b.3, 2)
69726}
69727#[doc = "Store multiple 4-element structures from four registers"]
69728#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
69729#[doc = "## Safety"]
69730#[doc = " * Neon instrinsic unsafe"]
69731#[inline]
69732#[cfg(not(target_arch = "arm"))]
69733#[target_feature(enable = "neon,fp16")]
69734#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69735#[cfg_attr(test, assert_instr(st4))]
69736pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
69737 unsafe extern "unadjusted" {
69738 #[cfg_attr(
69739 any(target_arch = "aarch64", target_arch = "arm64ec"),
69740 link_name = "llvm.aarch64.neon.st4.v4f16.p0"
69741 )]
69742 fn _vst4_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t, d: float16x4_t, ptr: *mut i8);
69743 }
69744 _vst4_f16(b.0, b.1, b.2, b.3, a as _)
69745}
69746#[doc = "Store multiple 4-element structures from four registers"]
69747#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
69748#[doc = "## Safety"]
69749#[doc = " * Neon instrinsic unsafe"]
69750#[inline]
69751#[cfg(not(target_arch = "arm"))]
69752#[target_feature(enable = "neon,fp16")]
69753#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
69754#[cfg_attr(test, assert_instr(st4))]
69755pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
69756 unsafe extern "unadjusted" {
69757 #[cfg_attr(
69758 any(target_arch = "aarch64", target_arch = "arm64ec"),
69759 link_name = "llvm.aarch64.neon.st4.v8f16.p0"
69760 )]
69761 fn _vst4q_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t, d: float16x8_t, ptr: *mut i8);
69762 }
69763 _vst4q_f16(b.0, b.1, b.2, b.3, a as _)
69764}
69765#[doc = "Store multiple 4-element structures from four registers"]
69766#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
69767#[doc = "## Safety"]
69768#[doc = " * Neon instrinsic unsafe"]
69769#[inline]
69770#[cfg(target_arch = "arm")]
69771#[target_feature(enable = "neon,v7")]
69772#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69773#[cfg_attr(test, assert_instr(vst4))]
69774pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
69775 unsafe extern "unadjusted" {
69776 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v2f32")]
69777 fn _vst4_f32(
69778 ptr: *mut i8,
69779 a: float32x2_t,
69780 b: float32x2_t,
69781 c: float32x2_t,
69782 d: float32x2_t,
69783 size: i32,
69784 );
69785 }
69786 _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4)
69787}
69788#[doc = "Store multiple 4-element structures from four registers"]
69789#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
69790#[doc = "## Safety"]
69791#[doc = " * Neon instrinsic unsafe"]
69792#[inline]
69793#[cfg(target_arch = "arm")]
69794#[target_feature(enable = "neon,v7")]
69795#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69796#[cfg_attr(test, assert_instr(vst4))]
69797pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
69798 unsafe extern "unadjusted" {
69799 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4f32")]
69800 fn _vst4q_f32(
69801 ptr: *mut i8,
69802 a: float32x4_t,
69803 b: float32x4_t,
69804 c: float32x4_t,
69805 d: float32x4_t,
69806 size: i32,
69807 );
69808 }
69809 _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4)
69810}
69811#[doc = "Store multiple 4-element structures from four registers"]
69812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
69813#[doc = "## Safety"]
69814#[doc = " * Neon instrinsic unsafe"]
69815#[inline]
69816#[cfg(target_arch = "arm")]
69817#[target_feature(enable = "neon,v7")]
69818#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69819#[cfg_attr(test, assert_instr(vst4))]
69820pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
69821 unsafe extern "unadjusted" {
69822 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8i8")]
69823 fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32);
69824 }
69825 _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1)
69826}
69827#[doc = "Store multiple 4-element structures from four registers"]
69828#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
69829#[doc = "## Safety"]
69830#[doc = " * Neon instrinsic unsafe"]
69831#[inline]
69832#[cfg(target_arch = "arm")]
69833#[target_feature(enable = "neon,v7")]
69834#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69835#[cfg_attr(test, assert_instr(vst4))]
69836pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
69837 unsafe extern "unadjusted" {
69838 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v16i8")]
69839 fn _vst4q_s8(
69840 ptr: *mut i8,
69841 a: int8x16_t,
69842 b: int8x16_t,
69843 c: int8x16_t,
69844 d: int8x16_t,
69845 size: i32,
69846 );
69847 }
69848 _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1)
69849}
69850#[doc = "Store multiple 4-element structures from four registers"]
69851#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
69852#[doc = "## Safety"]
69853#[doc = " * Neon instrinsic unsafe"]
69854#[inline]
69855#[cfg(target_arch = "arm")]
69856#[target_feature(enable = "neon,v7")]
69857#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69858#[cfg_attr(test, assert_instr(vst4))]
69859pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
69860 unsafe extern "unadjusted" {
69861 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4i16")]
69862 fn _vst4_s16(
69863 ptr: *mut i8,
69864 a: int16x4_t,
69865 b: int16x4_t,
69866 c: int16x4_t,
69867 d: int16x4_t,
69868 size: i32,
69869 );
69870 }
69871 _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2)
69872}
69873#[doc = "Store multiple 4-element structures from four registers"]
69874#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
69875#[doc = "## Safety"]
69876#[doc = " * Neon instrinsic unsafe"]
69877#[inline]
69878#[cfg(target_arch = "arm")]
69879#[target_feature(enable = "neon,v7")]
69880#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69881#[cfg_attr(test, assert_instr(vst4))]
69882pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
69883 unsafe extern "unadjusted" {
69884 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v8i16")]
69885 fn _vst4q_s16(
69886 ptr: *mut i8,
69887 a: int16x8_t,
69888 b: int16x8_t,
69889 c: int16x8_t,
69890 d: int16x8_t,
69891 size: i32,
69892 );
69893 }
69894 _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2)
69895}
69896#[doc = "Store multiple 4-element structures from four registers"]
69897#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
69898#[doc = "## Safety"]
69899#[doc = " * Neon instrinsic unsafe"]
69900#[inline]
69901#[cfg(target_arch = "arm")]
69902#[target_feature(enable = "neon,v7")]
69903#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69904#[cfg_attr(test, assert_instr(vst4))]
69905pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
69906 unsafe extern "unadjusted" {
69907 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v2i32")]
69908 fn _vst4_s32(
69909 ptr: *mut i8,
69910 a: int32x2_t,
69911 b: int32x2_t,
69912 c: int32x2_t,
69913 d: int32x2_t,
69914 size: i32,
69915 );
69916 }
69917 _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4)
69918}
69919#[doc = "Store multiple 4-element structures from four registers"]
69920#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
69921#[doc = "## Safety"]
69922#[doc = " * Neon instrinsic unsafe"]
69923#[inline]
69924#[cfg(target_arch = "arm")]
69925#[target_feature(enable = "neon,v7")]
69926#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
69927#[cfg_attr(test, assert_instr(vst4))]
69928pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
69929 unsafe extern "unadjusted" {
69930 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v4i32")]
69931 fn _vst4q_s32(
69932 ptr: *mut i8,
69933 a: int32x4_t,
69934 b: int32x4_t,
69935 c: int32x4_t,
69936 d: int32x4_t,
69937 size: i32,
69938 );
69939 }
69940 _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4)
69941}
69942#[doc = "Store multiple 4-element structures from four registers"]
69943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
69944#[doc = "## Safety"]
69945#[doc = " * Neon instrinsic unsafe"]
69946#[inline]
69947#[target_feature(enable = "neon")]
69948#[cfg(not(target_arch = "arm"))]
69949#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69950#[cfg_attr(test, assert_instr(st4))]
69951pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
69952 unsafe extern "unadjusted" {
69953 #[cfg_attr(
69954 any(target_arch = "aarch64", target_arch = "arm64ec"),
69955 link_name = "llvm.aarch64.neon.st4.v2f32.p0"
69956 )]
69957 fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8);
69958 }
69959 _vst4_f32(b.0, b.1, b.2, b.3, a as _)
69960}
69961#[doc = "Store multiple 4-element structures from four registers"]
69962#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
69963#[doc = "## Safety"]
69964#[doc = " * Neon instrinsic unsafe"]
69965#[inline]
69966#[target_feature(enable = "neon")]
69967#[cfg(not(target_arch = "arm"))]
69968#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69969#[cfg_attr(test, assert_instr(st4))]
69970pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
69971 unsafe extern "unadjusted" {
69972 #[cfg_attr(
69973 any(target_arch = "aarch64", target_arch = "arm64ec"),
69974 link_name = "llvm.aarch64.neon.st4.v4f32.p0"
69975 )]
69976 fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8);
69977 }
69978 _vst4q_f32(b.0, b.1, b.2, b.3, a as _)
69979}
69980#[doc = "Store multiple 4-element structures from four registers"]
69981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
69982#[doc = "## Safety"]
69983#[doc = " * Neon instrinsic unsafe"]
69984#[inline]
69985#[target_feature(enable = "neon")]
69986#[cfg(not(target_arch = "arm"))]
69987#[stable(feature = "neon_intrinsics", since = "1.59.0")]
69988#[cfg_attr(test, assert_instr(st4))]
69989pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
69990 unsafe extern "unadjusted" {
69991 #[cfg_attr(
69992 any(target_arch = "aarch64", target_arch = "arm64ec"),
69993 link_name = "llvm.aarch64.neon.st4.v8i8.p0"
69994 )]
69995 fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8);
69996 }
69997 _vst4_s8(b.0, b.1, b.2, b.3, a as _)
69998}
69999#[doc = "Store multiple 4-element structures from four registers"]
70000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
70001#[doc = "## Safety"]
70002#[doc = " * Neon instrinsic unsafe"]
70003#[inline]
70004#[target_feature(enable = "neon")]
70005#[cfg(not(target_arch = "arm"))]
70006#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70007#[cfg_attr(test, assert_instr(st4))]
70008pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
70009 unsafe extern "unadjusted" {
70010 #[cfg_attr(
70011 any(target_arch = "aarch64", target_arch = "arm64ec"),
70012 link_name = "llvm.aarch64.neon.st4.v16i8.p0"
70013 )]
70014 fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8);
70015 }
70016 _vst4q_s8(b.0, b.1, b.2, b.3, a as _)
70017}
70018#[doc = "Store multiple 4-element structures from four registers"]
70019#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
70020#[doc = "## Safety"]
70021#[doc = " * Neon instrinsic unsafe"]
70022#[inline]
70023#[target_feature(enable = "neon")]
70024#[cfg(not(target_arch = "arm"))]
70025#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70026#[cfg_attr(test, assert_instr(st4))]
70027pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
70028 unsafe extern "unadjusted" {
70029 #[cfg_attr(
70030 any(target_arch = "aarch64", target_arch = "arm64ec"),
70031 link_name = "llvm.aarch64.neon.st4.v4i16.p0"
70032 )]
70033 fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8);
70034 }
70035 _vst4_s16(b.0, b.1, b.2, b.3, a as _)
70036}
70037#[doc = "Store multiple 4-element structures from four registers"]
70038#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
70039#[doc = "## Safety"]
70040#[doc = " * Neon instrinsic unsafe"]
70041#[inline]
70042#[target_feature(enable = "neon")]
70043#[cfg(not(target_arch = "arm"))]
70044#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70045#[cfg_attr(test, assert_instr(st4))]
70046pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
70047 unsafe extern "unadjusted" {
70048 #[cfg_attr(
70049 any(target_arch = "aarch64", target_arch = "arm64ec"),
70050 link_name = "llvm.aarch64.neon.st4.v8i16.p0"
70051 )]
70052 fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8);
70053 }
70054 _vst4q_s16(b.0, b.1, b.2, b.3, a as _)
70055}
70056#[doc = "Store multiple 4-element structures from four registers"]
70057#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
70058#[doc = "## Safety"]
70059#[doc = " * Neon instrinsic unsafe"]
70060#[inline]
70061#[target_feature(enable = "neon")]
70062#[cfg(not(target_arch = "arm"))]
70063#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70064#[cfg_attr(test, assert_instr(st4))]
70065pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
70066 unsafe extern "unadjusted" {
70067 #[cfg_attr(
70068 any(target_arch = "aarch64", target_arch = "arm64ec"),
70069 link_name = "llvm.aarch64.neon.st4.v2i32.p0"
70070 )]
70071 fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8);
70072 }
70073 _vst4_s32(b.0, b.1, b.2, b.3, a as _)
70074}
70075#[doc = "Store multiple 4-element structures from four registers"]
70076#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
70077#[doc = "## Safety"]
70078#[doc = " * Neon instrinsic unsafe"]
70079#[inline]
70080#[target_feature(enable = "neon")]
70081#[cfg(not(target_arch = "arm"))]
70082#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70083#[cfg_attr(test, assert_instr(st4))]
70084pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
70085 unsafe extern "unadjusted" {
70086 #[cfg_attr(
70087 any(target_arch = "aarch64", target_arch = "arm64ec"),
70088 link_name = "llvm.aarch64.neon.st4.v4i32.p0"
70089 )]
70090 fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8);
70091 }
70092 _vst4q_s32(b.0, b.1, b.2, b.3, a as _)
70093}
70094#[doc = "Store multiple 4-element structures from four registers"]
70095#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70096#[doc = "## Safety"]
70097#[doc = " * Neon instrinsic unsafe"]
70098#[inline]
70099#[cfg(target_arch = "arm")]
70100#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70101#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70102#[rustc_legacy_const_generics(2)]
70103#[target_feature(enable = "neon,fp16")]
70104#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70105pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70106 static_assert_uimm_bits!(LANE, 2);
70107 unsafe extern "unadjusted" {
70108 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f16")]
70109 fn _vst4_lane_f16(
70110 ptr: *mut i8,
70111 a: float16x4_t,
70112 b: float16x4_t,
70113 c: float16x4_t,
70114 d: float16x4_t,
70115 n: i32,
70116 size: i32,
70117 );
70118 }
70119 _vst4_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70120}
70121#[doc = "Store multiple 4-element structures from four registers"]
70122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70123#[doc = "## Safety"]
70124#[doc = " * Neon instrinsic unsafe"]
70125#[inline]
70126#[cfg(target_arch = "arm")]
70127#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70128#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70129#[rustc_legacy_const_generics(2)]
70130#[target_feature(enable = "neon,fp16")]
70131#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70132pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70133 static_assert_uimm_bits!(LANE, 3);
70134 unsafe extern "unadjusted" {
70135 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8f16")]
70136 fn _vst4q_lane_f16(
70137 ptr: *mut i8,
70138 a: float16x8_t,
70139 b: float16x8_t,
70140 c: float16x8_t,
70141 d: float16x8_t,
70142 n: i32,
70143 size: i32,
70144 );
70145 }
70146 _vst4q_lane_f16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70147}
70148#[doc = "Store multiple 4-element structures from four registers"]
70149#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
70150#[doc = "## Safety"]
70151#[doc = " * Neon instrinsic unsafe"]
70152#[inline]
70153#[cfg(not(target_arch = "arm"))]
70154#[rustc_legacy_const_generics(2)]
70155#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70156#[target_feature(enable = "neon,fp16")]
70157#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70158pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
70159 static_assert_uimm_bits!(LANE, 2);
70160 unsafe extern "unadjusted" {
70161 #[cfg_attr(
70162 any(target_arch = "aarch64", target_arch = "arm64ec"),
70163 link_name = "llvm.aarch64.neon.st4lane.v4f16.p0"
70164 )]
70165 fn _vst4_lane_f16(
70166 a: float16x4_t,
70167 b: float16x4_t,
70168 c: float16x4_t,
70169 d: float16x4_t,
70170 n: i64,
70171 ptr: *mut i8,
70172 );
70173 }
70174 _vst4_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70175}
70176#[doc = "Store multiple 4-element structures from four registers"]
70177#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
70178#[doc = "## Safety"]
70179#[doc = " * Neon instrinsic unsafe"]
70180#[inline]
70181#[cfg(not(target_arch = "arm"))]
70182#[rustc_legacy_const_generics(2)]
70183#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70184#[target_feature(enable = "neon,fp16")]
70185#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
70186pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
70187 static_assert_uimm_bits!(LANE, 3);
70188 unsafe extern "unadjusted" {
70189 #[cfg_attr(
70190 any(target_arch = "aarch64", target_arch = "arm64ec"),
70191 link_name = "llvm.aarch64.neon.st4lane.v8f16.p0"
70192 )]
70193 fn _vst4q_lane_f16(
70194 a: float16x8_t,
70195 b: float16x8_t,
70196 c: float16x8_t,
70197 d: float16x8_t,
70198 n: i64,
70199 ptr: *mut i8,
70200 );
70201 }
70202 _vst4q_lane_f16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70203}
70204#[doc = "Store multiple 4-element structures from four registers"]
70205#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70206#[doc = "## Safety"]
70207#[doc = " * Neon instrinsic unsafe"]
70208#[inline]
70209#[cfg(target_arch = "arm")]
70210#[target_feature(enable = "neon,v7")]
70211#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70212#[rustc_legacy_const_generics(2)]
70213#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70214pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70215 static_assert_uimm_bits!(LANE, 1);
70216 unsafe extern "unadjusted" {
70217 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2f32")]
70218 fn _vst4_lane_f32(
70219 ptr: *mut i8,
70220 a: float32x2_t,
70221 b: float32x2_t,
70222 c: float32x2_t,
70223 d: float32x2_t,
70224 n: i32,
70225 size: i32,
70226 );
70227 }
70228 _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70229}
70230#[doc = "Store multiple 4-element structures from four registers"]
70231#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70232#[doc = "## Safety"]
70233#[doc = " * Neon instrinsic unsafe"]
70234#[inline]
70235#[cfg(target_arch = "arm")]
70236#[target_feature(enable = "neon,v7")]
70237#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70238#[rustc_legacy_const_generics(2)]
70239#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70240pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70241 static_assert_uimm_bits!(LANE, 2);
70242 unsafe extern "unadjusted" {
70243 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4f32")]
70244 fn _vst4q_lane_f32(
70245 ptr: *mut i8,
70246 a: float32x4_t,
70247 b: float32x4_t,
70248 c: float32x4_t,
70249 d: float32x4_t,
70250 n: i32,
70251 size: i32,
70252 );
70253 }
70254 _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70255}
70256#[doc = "Store multiple 4-element structures from four registers"]
70257#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70258#[doc = "## Safety"]
70259#[doc = " * Neon instrinsic unsafe"]
70260#[inline]
70261#[cfg(target_arch = "arm")]
70262#[target_feature(enable = "neon,v7")]
70263#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70264#[rustc_legacy_const_generics(2)]
70265#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70266pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70267 static_assert_uimm_bits!(LANE, 3);
70268 unsafe extern "unadjusted" {
70269 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i8")]
70270 fn _vst4_lane_s8(
70271 ptr: *mut i8,
70272 a: int8x8_t,
70273 b: int8x8_t,
70274 c: int8x8_t,
70275 d: int8x8_t,
70276 n: i32,
70277 size: i32,
70278 );
70279 }
70280 _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1)
70281}
70282#[doc = "Store multiple 4-element structures from four registers"]
70283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70284#[doc = "## Safety"]
70285#[doc = " * Neon instrinsic unsafe"]
70286#[inline]
70287#[cfg(target_arch = "arm")]
70288#[target_feature(enable = "neon,v7")]
70289#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70290#[rustc_legacy_const_generics(2)]
70291#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70292pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70293 static_assert_uimm_bits!(LANE, 2);
70294 unsafe extern "unadjusted" {
70295 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i16")]
70296 fn _vst4_lane_s16(
70297 ptr: *mut i8,
70298 a: int16x4_t,
70299 b: int16x4_t,
70300 c: int16x4_t,
70301 d: int16x4_t,
70302 n: i32,
70303 size: i32,
70304 );
70305 }
70306 _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70307}
70308#[doc = "Store multiple 4-element structures from four registers"]
70309#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70310#[doc = "## Safety"]
70311#[doc = " * Neon instrinsic unsafe"]
70312#[inline]
70313#[cfg(target_arch = "arm")]
70314#[target_feature(enable = "neon,v7")]
70315#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70316#[rustc_legacy_const_generics(2)]
70317#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70318pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70319 static_assert_uimm_bits!(LANE, 3);
70320 unsafe extern "unadjusted" {
70321 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v8i16")]
70322 fn _vst4q_lane_s16(
70323 ptr: *mut i8,
70324 a: int16x8_t,
70325 b: int16x8_t,
70326 c: int16x8_t,
70327 d: int16x8_t,
70328 n: i32,
70329 size: i32,
70330 );
70331 }
70332 _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2)
70333}
70334#[doc = "Store multiple 4-element structures from four registers"]
70335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70336#[doc = "## Safety"]
70337#[doc = " * Neon instrinsic unsafe"]
70338#[inline]
70339#[cfg(target_arch = "arm")]
70340#[target_feature(enable = "neon,v7")]
70341#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70342#[rustc_legacy_const_generics(2)]
70343#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70344pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70345 static_assert_uimm_bits!(LANE, 1);
70346 unsafe extern "unadjusted" {
70347 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v2i32")]
70348 fn _vst4_lane_s32(
70349 ptr: *mut i8,
70350 a: int32x2_t,
70351 b: int32x2_t,
70352 c: int32x2_t,
70353 d: int32x2_t,
70354 n: i32,
70355 size: i32,
70356 );
70357 }
70358 _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70359}
70360#[doc = "Store multiple 4-element structures from four registers"]
70361#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70362#[doc = "## Safety"]
70363#[doc = " * Neon instrinsic unsafe"]
70364#[inline]
70365#[cfg(target_arch = "arm")]
70366#[target_feature(enable = "neon,v7")]
70367#[cfg_attr(test, assert_instr(vst4, LANE = 0))]
70368#[rustc_legacy_const_generics(2)]
70369#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70370pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70371 static_assert_uimm_bits!(LANE, 2);
70372 unsafe extern "unadjusted" {
70373 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0.v4i32")]
70374 fn _vst4q_lane_s32(
70375 ptr: *mut i8,
70376 a: int32x4_t,
70377 b: int32x4_t,
70378 c: int32x4_t,
70379 d: int32x4_t,
70380 n: i32,
70381 size: i32,
70382 );
70383 }
70384 _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4)
70385}
70386#[doc = "Store multiple 4-element structures from four registers"]
70387#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
70388#[doc = "## Safety"]
70389#[doc = " * Neon instrinsic unsafe"]
70390#[inline]
70391#[target_feature(enable = "neon")]
70392#[cfg(not(target_arch = "arm"))]
70393#[rustc_legacy_const_generics(2)]
70394#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70395#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70396pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
70397 static_assert_uimm_bits!(LANE, 1);
70398 unsafe extern "unadjusted" {
70399 #[cfg_attr(
70400 any(target_arch = "aarch64", target_arch = "arm64ec"),
70401 link_name = "llvm.aarch64.neon.st4lane.v2f32.p0"
70402 )]
70403 fn _vst4_lane_f32(
70404 a: float32x2_t,
70405 b: float32x2_t,
70406 c: float32x2_t,
70407 d: float32x2_t,
70408 n: i64,
70409 ptr: *mut i8,
70410 );
70411 }
70412 _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70413}
70414#[doc = "Store multiple 4-element structures from four registers"]
70415#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
70416#[doc = "## Safety"]
70417#[doc = " * Neon instrinsic unsafe"]
70418#[inline]
70419#[target_feature(enable = "neon")]
70420#[cfg(not(target_arch = "arm"))]
70421#[rustc_legacy_const_generics(2)]
70422#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70423#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70424pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
70425 static_assert_uimm_bits!(LANE, 2);
70426 unsafe extern "unadjusted" {
70427 #[cfg_attr(
70428 any(target_arch = "aarch64", target_arch = "arm64ec"),
70429 link_name = "llvm.aarch64.neon.st4lane.v4f32.p0"
70430 )]
70431 fn _vst4q_lane_f32(
70432 a: float32x4_t,
70433 b: float32x4_t,
70434 c: float32x4_t,
70435 d: float32x4_t,
70436 n: i64,
70437 ptr: *mut i8,
70438 );
70439 }
70440 _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70441}
70442#[doc = "Store multiple 4-element structures from four registers"]
70443#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
70444#[doc = "## Safety"]
70445#[doc = " * Neon instrinsic unsafe"]
70446#[inline]
70447#[target_feature(enable = "neon")]
70448#[cfg(not(target_arch = "arm"))]
70449#[rustc_legacy_const_generics(2)]
70450#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70451#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70452pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
70453 static_assert_uimm_bits!(LANE, 3);
70454 unsafe extern "unadjusted" {
70455 #[cfg_attr(
70456 any(target_arch = "aarch64", target_arch = "arm64ec"),
70457 link_name = "llvm.aarch64.neon.st4lane.v8i8.p0"
70458 )]
70459 fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8);
70460 }
70461 _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70462}
70463#[doc = "Store multiple 4-element structures from four registers"]
70464#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
70465#[doc = "## Safety"]
70466#[doc = " * Neon instrinsic unsafe"]
70467#[inline]
70468#[target_feature(enable = "neon")]
70469#[cfg(not(target_arch = "arm"))]
70470#[rustc_legacy_const_generics(2)]
70471#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70472#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70473pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
70474 static_assert_uimm_bits!(LANE, 2);
70475 unsafe extern "unadjusted" {
70476 #[cfg_attr(
70477 any(target_arch = "aarch64", target_arch = "arm64ec"),
70478 link_name = "llvm.aarch64.neon.st4lane.v4i16.p0"
70479 )]
70480 fn _vst4_lane_s16(
70481 a: int16x4_t,
70482 b: int16x4_t,
70483 c: int16x4_t,
70484 d: int16x4_t,
70485 n: i64,
70486 ptr: *mut i8,
70487 );
70488 }
70489 _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70490}
70491#[doc = "Store multiple 4-element structures from four registers"]
70492#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
70493#[doc = "## Safety"]
70494#[doc = " * Neon instrinsic unsafe"]
70495#[inline]
70496#[target_feature(enable = "neon")]
70497#[cfg(not(target_arch = "arm"))]
70498#[rustc_legacy_const_generics(2)]
70499#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70500#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70501pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
70502 static_assert_uimm_bits!(LANE, 3);
70503 unsafe extern "unadjusted" {
70504 #[cfg_attr(
70505 any(target_arch = "aarch64", target_arch = "arm64ec"),
70506 link_name = "llvm.aarch64.neon.st4lane.v8i16.p0"
70507 )]
70508 fn _vst4q_lane_s16(
70509 a: int16x8_t,
70510 b: int16x8_t,
70511 c: int16x8_t,
70512 d: int16x8_t,
70513 n: i64,
70514 ptr: *mut i8,
70515 );
70516 }
70517 _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70518}
70519#[doc = "Store multiple 4-element structures from four registers"]
70520#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
70521#[doc = "## Safety"]
70522#[doc = " * Neon instrinsic unsafe"]
70523#[inline]
70524#[target_feature(enable = "neon")]
70525#[cfg(not(target_arch = "arm"))]
70526#[rustc_legacy_const_generics(2)]
70527#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70528#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70529pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
70530 static_assert_uimm_bits!(LANE, 1);
70531 unsafe extern "unadjusted" {
70532 #[cfg_attr(
70533 any(target_arch = "aarch64", target_arch = "arm64ec"),
70534 link_name = "llvm.aarch64.neon.st4lane.v2i32.p0"
70535 )]
70536 fn _vst4_lane_s32(
70537 a: int32x2_t,
70538 b: int32x2_t,
70539 c: int32x2_t,
70540 d: int32x2_t,
70541 n: i64,
70542 ptr: *mut i8,
70543 );
70544 }
70545 _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70546}
70547#[doc = "Store multiple 4-element structures from four registers"]
70548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
70549#[doc = "## Safety"]
70550#[doc = " * Neon instrinsic unsafe"]
70551#[inline]
70552#[target_feature(enable = "neon")]
70553#[cfg(not(target_arch = "arm"))]
70554#[rustc_legacy_const_generics(2)]
70555#[cfg_attr(test, assert_instr(st4, LANE = 0))]
70556#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70557pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
70558 static_assert_uimm_bits!(LANE, 2);
70559 unsafe extern "unadjusted" {
70560 #[cfg_attr(
70561 any(target_arch = "aarch64", target_arch = "arm64ec"),
70562 link_name = "llvm.aarch64.neon.st4lane.v4i32.p0"
70563 )]
70564 fn _vst4q_lane_s32(
70565 a: int32x4_t,
70566 b: int32x4_t,
70567 c: int32x4_t,
70568 d: int32x4_t,
70569 n: i64,
70570 ptr: *mut i8,
70571 );
70572 }
70573 _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _)
70574}
70575#[doc = "Store multiple 4-element structures from four registers"]
70576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
70577#[doc = "## Safety"]
70578#[doc = " * Neon instrinsic unsafe"]
70579#[inline]
70580#[target_feature(enable = "neon")]
70581#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70582#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70583#[cfg_attr(
70584 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70585 assert_instr(st4, LANE = 0)
70586)]
70587#[rustc_legacy_const_generics(2)]
70588#[cfg_attr(
70589 not(target_arch = "arm"),
70590 stable(feature = "neon_intrinsics", since = "1.59.0")
70591)]
70592#[cfg_attr(
70593 target_arch = "arm",
70594 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70595)]
70596pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
70597 static_assert_uimm_bits!(LANE, 3);
70598 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
70599}
70600#[doc = "Store multiple 4-element structures from four registers"]
70601#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
70602#[doc = "## Safety"]
70603#[doc = " * Neon instrinsic unsafe"]
70604#[inline]
70605#[target_feature(enable = "neon")]
70606#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70607#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70608#[cfg_attr(
70609 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70610 assert_instr(st4, LANE = 0)
70611)]
70612#[rustc_legacy_const_generics(2)]
70613#[cfg_attr(
70614 not(target_arch = "arm"),
70615 stable(feature = "neon_intrinsics", since = "1.59.0")
70616)]
70617#[cfg_attr(
70618 target_arch = "arm",
70619 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70620)]
70621pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
70622 static_assert_uimm_bits!(LANE, 2);
70623 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
70624}
70625#[doc = "Store multiple 4-element structures from four registers"]
70626#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
70627#[doc = "## Safety"]
70628#[doc = " * Neon instrinsic unsafe"]
70629#[inline]
70630#[target_feature(enable = "neon")]
70631#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70632#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70633#[cfg_attr(
70634 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70635 assert_instr(st4, LANE = 0)
70636)]
70637#[rustc_legacy_const_generics(2)]
70638#[cfg_attr(
70639 not(target_arch = "arm"),
70640 stable(feature = "neon_intrinsics", since = "1.59.0")
70641)]
70642#[cfg_attr(
70643 target_arch = "arm",
70644 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70645)]
70646pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
70647 static_assert_uimm_bits!(LANE, 3);
70648 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
70649}
70650#[doc = "Store multiple 4-element structures from four registers"]
70651#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
70652#[doc = "## Safety"]
70653#[doc = " * Neon instrinsic unsafe"]
70654#[inline]
70655#[target_feature(enable = "neon")]
70656#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70657#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70658#[cfg_attr(
70659 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70660 assert_instr(st4, LANE = 0)
70661)]
70662#[rustc_legacy_const_generics(2)]
70663#[cfg_attr(
70664 not(target_arch = "arm"),
70665 stable(feature = "neon_intrinsics", since = "1.59.0")
70666)]
70667#[cfg_attr(
70668 target_arch = "arm",
70669 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70670)]
70671pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
70672 static_assert_uimm_bits!(LANE, 1);
70673 vst4_lane_s32::<LANE>(transmute(a), transmute(b))
70674}
70675#[doc = "Store multiple 4-element structures from four registers"]
70676#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
70677#[doc = "## Safety"]
70678#[doc = " * Neon instrinsic unsafe"]
70679#[inline]
70680#[target_feature(enable = "neon")]
70681#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70682#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70683#[cfg_attr(
70684 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70685 assert_instr(st4, LANE = 0)
70686)]
70687#[rustc_legacy_const_generics(2)]
70688#[cfg_attr(
70689 not(target_arch = "arm"),
70690 stable(feature = "neon_intrinsics", since = "1.59.0")
70691)]
70692#[cfg_attr(
70693 target_arch = "arm",
70694 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70695)]
70696pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
70697 static_assert_uimm_bits!(LANE, 2);
70698 vst4q_lane_s32::<LANE>(transmute(a), transmute(b))
70699}
70700#[doc = "Store multiple 4-element structures from four registers"]
70701#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
70702#[doc = "## Safety"]
70703#[doc = " * Neon instrinsic unsafe"]
70704#[inline]
70705#[target_feature(enable = "neon")]
70706#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70707#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70708#[cfg_attr(
70709 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70710 assert_instr(st4, LANE = 0)
70711)]
70712#[rustc_legacy_const_generics(2)]
70713#[cfg_attr(
70714 not(target_arch = "arm"),
70715 stable(feature = "neon_intrinsics", since = "1.59.0")
70716)]
70717#[cfg_attr(
70718 target_arch = "arm",
70719 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70720)]
70721pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
70722 static_assert_uimm_bits!(LANE, 3);
70723 vst4_lane_s8::<LANE>(transmute(a), transmute(b))
70724}
70725#[doc = "Store multiple 4-element structures from four registers"]
70726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
70727#[doc = "## Safety"]
70728#[doc = " * Neon instrinsic unsafe"]
70729#[inline]
70730#[target_feature(enable = "neon")]
70731#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70732#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70733#[cfg_attr(
70734 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70735 assert_instr(st4, LANE = 0)
70736)]
70737#[rustc_legacy_const_generics(2)]
70738#[cfg_attr(
70739 not(target_arch = "arm"),
70740 stable(feature = "neon_intrinsics", since = "1.59.0")
70741)]
70742#[cfg_attr(
70743 target_arch = "arm",
70744 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70745)]
70746pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
70747 static_assert_uimm_bits!(LANE, 2);
70748 vst4_lane_s16::<LANE>(transmute(a), transmute(b))
70749}
70750#[doc = "Store multiple 4-element structures from four registers"]
70751#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
70752#[doc = "## Safety"]
70753#[doc = " * Neon instrinsic unsafe"]
70754#[inline]
70755#[target_feature(enable = "neon")]
70756#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70757#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
70758#[cfg_attr(
70759 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70760 assert_instr(st4, LANE = 0)
70761)]
70762#[rustc_legacy_const_generics(2)]
70763#[cfg_attr(
70764 not(target_arch = "arm"),
70765 stable(feature = "neon_intrinsics", since = "1.59.0")
70766)]
70767#[cfg_attr(
70768 target_arch = "arm",
70769 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70770)]
70771pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
70772 static_assert_uimm_bits!(LANE, 3);
70773 vst4q_lane_s16::<LANE>(transmute(a), transmute(b))
70774}
70775#[doc = "Store multiple 4-element structures from four registers"]
70776#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
70777#[doc = "## Safety"]
70778#[doc = " * Neon instrinsic unsafe"]
70779#[inline]
70780#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
70781#[target_feature(enable = "neon,aes")]
70782#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
70783#[cfg_attr(
70784 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70785 assert_instr(nop)
70786)]
70787#[cfg_attr(
70788 not(target_arch = "arm"),
70789 stable(feature = "neon_intrinsics", since = "1.59.0")
70790)]
70791#[cfg_attr(
70792 target_arch = "arm",
70793 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70794)]
70795pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
70796 vst4_s64(transmute(a), transmute(b))
70797}
70798#[doc = "Store multiple 4-element structures from four registers"]
70799#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
70800#[doc = "## Safety"]
70801#[doc = " * Neon instrinsic unsafe"]
70802#[inline]
70803#[cfg(target_arch = "arm")]
70804#[target_feature(enable = "neon,v7")]
70805#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
70806#[cfg_attr(test, assert_instr(nop))]
70807pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
70808 unsafe extern "unadjusted" {
70809 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0.v1i64")]
70810 fn _vst4_s64(
70811 ptr: *mut i8,
70812 a: int64x1_t,
70813 b: int64x1_t,
70814 c: int64x1_t,
70815 d: int64x1_t,
70816 size: i32,
70817 );
70818 }
70819 _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8)
70820}
70821#[doc = "Store multiple 4-element structures from four registers"]
70822#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
70823#[doc = "## Safety"]
70824#[doc = " * Neon instrinsic unsafe"]
70825#[inline]
70826#[target_feature(enable = "neon")]
70827#[cfg(not(target_arch = "arm"))]
70828#[stable(feature = "neon_intrinsics", since = "1.59.0")]
70829#[cfg_attr(test, assert_instr(nop))]
70830pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
70831 unsafe extern "unadjusted" {
70832 #[cfg_attr(
70833 any(target_arch = "aarch64", target_arch = "arm64ec"),
70834 link_name = "llvm.aarch64.neon.st4.v1i64.p0"
70835 )]
70836 fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8);
70837 }
70838 _vst4_s64(b.0, b.1, b.2, b.3, a as _)
70839}
70840#[doc = "Store multiple 4-element structures from four registers"]
70841#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
70842#[doc = "## Safety"]
70843#[doc = " * Neon instrinsic unsafe"]
70844#[inline]
70845#[target_feature(enable = "neon")]
70846#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70847#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
70848#[cfg_attr(
70849 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70850 assert_instr(nop)
70851)]
70852#[cfg_attr(
70853 not(target_arch = "arm"),
70854 stable(feature = "neon_intrinsics", since = "1.59.0")
70855)]
70856#[cfg_attr(
70857 target_arch = "arm",
70858 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70859)]
70860pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
70861 vst4_s64(transmute(a), transmute(b))
70862}
70863#[doc = "Store multiple 4-element structures from four registers"]
70864#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
70865#[doc = "## Safety"]
70866#[doc = " * Neon instrinsic unsafe"]
70867#[inline]
70868#[target_feature(enable = "neon")]
70869#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70870#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70871#[cfg_attr(
70872 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70873 assert_instr(st4)
70874)]
70875#[cfg_attr(
70876 not(target_arch = "arm"),
70877 stable(feature = "neon_intrinsics", since = "1.59.0")
70878)]
70879#[cfg_attr(
70880 target_arch = "arm",
70881 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70882)]
70883pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
70884 vst4_s8(transmute(a), transmute(b))
70885}
70886#[doc = "Store multiple 4-element structures from four registers"]
70887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
70888#[doc = "## Safety"]
70889#[doc = " * Neon instrinsic unsafe"]
70890#[inline]
70891#[target_feature(enable = "neon")]
70892#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70893#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70894#[cfg_attr(
70895 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70896 assert_instr(st4)
70897)]
70898#[cfg_attr(
70899 not(target_arch = "arm"),
70900 stable(feature = "neon_intrinsics", since = "1.59.0")
70901)]
70902#[cfg_attr(
70903 target_arch = "arm",
70904 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70905)]
70906pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
70907 vst4q_s8(transmute(a), transmute(b))
70908}
70909#[doc = "Store multiple 4-element structures from four registers"]
70910#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
70911#[doc = "## Safety"]
70912#[doc = " * Neon instrinsic unsafe"]
70913#[inline]
70914#[target_feature(enable = "neon")]
70915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70917#[cfg_attr(
70918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70919 assert_instr(st4)
70920)]
70921#[cfg_attr(
70922 not(target_arch = "arm"),
70923 stable(feature = "neon_intrinsics", since = "1.59.0")
70924)]
70925#[cfg_attr(
70926 target_arch = "arm",
70927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70928)]
70929pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
70930 vst4_s16(transmute(a), transmute(b))
70931}
70932#[doc = "Store multiple 4-element structures from four registers"]
70933#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
70934#[doc = "## Safety"]
70935#[doc = " * Neon instrinsic unsafe"]
70936#[inline]
70937#[target_feature(enable = "neon")]
70938#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70939#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70940#[cfg_attr(
70941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70942 assert_instr(st4)
70943)]
70944#[cfg_attr(
70945 not(target_arch = "arm"),
70946 stable(feature = "neon_intrinsics", since = "1.59.0")
70947)]
70948#[cfg_attr(
70949 target_arch = "arm",
70950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70951)]
70952pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
70953 vst4q_s16(transmute(a), transmute(b))
70954}
70955#[doc = "Store multiple 4-element structures from four registers"]
70956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
70957#[doc = "## Safety"]
70958#[doc = " * Neon instrinsic unsafe"]
70959#[inline]
70960#[target_feature(enable = "neon")]
70961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70963#[cfg_attr(
70964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70965 assert_instr(st4)
70966)]
70967#[cfg_attr(
70968 not(target_arch = "arm"),
70969 stable(feature = "neon_intrinsics", since = "1.59.0")
70970)]
70971#[cfg_attr(
70972 target_arch = "arm",
70973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70974)]
70975pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
70976 vst4_s32(transmute(a), transmute(b))
70977}
70978#[doc = "Store multiple 4-element structures from four registers"]
70979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
70980#[doc = "## Safety"]
70981#[doc = " * Neon instrinsic unsafe"]
70982#[inline]
70983#[target_feature(enable = "neon")]
70984#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
70985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
70986#[cfg_attr(
70987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
70988 assert_instr(st4)
70989)]
70990#[cfg_attr(
70991 not(target_arch = "arm"),
70992 stable(feature = "neon_intrinsics", since = "1.59.0")
70993)]
70994#[cfg_attr(
70995 target_arch = "arm",
70996 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
70997)]
70998pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
70999 vst4q_s32(transmute(a), transmute(b))
71000}
71001#[doc = "Store multiple 4-element structures from four registers"]
71002#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
71003#[doc = "## Safety"]
71004#[doc = " * Neon instrinsic unsafe"]
71005#[inline]
71006#[target_feature(enable = "neon")]
71007#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71008#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71009#[cfg_attr(
71010 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71011 assert_instr(st4)
71012)]
71013#[cfg_attr(
71014 not(target_arch = "arm"),
71015 stable(feature = "neon_intrinsics", since = "1.59.0")
71016)]
71017#[cfg_attr(
71018 target_arch = "arm",
71019 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71020)]
71021pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
71022 vst4_s8(transmute(a), transmute(b))
71023}
71024#[doc = "Store multiple 4-element structures from four registers"]
71025#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
71026#[doc = "## Safety"]
71027#[doc = " * Neon instrinsic unsafe"]
71028#[inline]
71029#[target_feature(enable = "neon")]
71030#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71031#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71032#[cfg_attr(
71033 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71034 assert_instr(st4)
71035)]
71036#[cfg_attr(
71037 not(target_arch = "arm"),
71038 stable(feature = "neon_intrinsics", since = "1.59.0")
71039)]
71040#[cfg_attr(
71041 target_arch = "arm",
71042 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71043)]
71044pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
71045 vst4q_s8(transmute(a), transmute(b))
71046}
71047#[doc = "Store multiple 4-element structures from four registers"]
71048#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
71049#[doc = "## Safety"]
71050#[doc = " * Neon instrinsic unsafe"]
71051#[inline]
71052#[target_feature(enable = "neon")]
71053#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71054#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71055#[cfg_attr(
71056 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71057 assert_instr(st4)
71058)]
71059#[cfg_attr(
71060 not(target_arch = "arm"),
71061 stable(feature = "neon_intrinsics", since = "1.59.0")
71062)]
71063#[cfg_attr(
71064 target_arch = "arm",
71065 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71066)]
71067pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
71068 vst4_s16(transmute(a), transmute(b))
71069}
71070#[doc = "Store multiple 4-element structures from four registers"]
71071#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
71072#[doc = "## Safety"]
71073#[doc = " * Neon instrinsic unsafe"]
71074#[inline]
71075#[target_feature(enable = "neon")]
71076#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71077#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
71078#[cfg_attr(
71079 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71080 assert_instr(st4)
71081)]
71082#[cfg_attr(
71083 not(target_arch = "arm"),
71084 stable(feature = "neon_intrinsics", since = "1.59.0")
71085)]
71086#[cfg_attr(
71087 target_arch = "arm",
71088 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71089)]
71090pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
71091 vst4q_s16(transmute(a), transmute(b))
71092}
71093#[doc = "Store SIMD&FP register (immediate offset)"]
71094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
71095#[doc = "## Safety"]
71096#[doc = " * Neon instrinsic unsafe"]
71097#[inline]
71098#[target_feature(enable = "neon")]
71099#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71100#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
71101#[cfg_attr(
71102 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71103 assert_instr(nop)
71104)]
71105#[cfg_attr(
71106 not(target_arch = "arm"),
71107 stable(feature = "neon_intrinsics", since = "1.59.0")
71108)]
71109#[cfg_attr(
71110 target_arch = "arm",
71111 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71112)]
71113pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
71114 *a = b
71115}
71116#[doc = "Subtract"]
71117#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
71118#[inline]
71119#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71120#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71121#[cfg_attr(
71122 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71123 assert_instr(fsub)
71124)]
71125#[target_feature(enable = "neon,fp16")]
71126#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71127pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
71128 unsafe { simd_sub(a, b) }
71129}
71130#[doc = "Subtract"]
71131#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
71132#[inline]
71133#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
71134#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
71135#[cfg_attr(
71136 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71137 assert_instr(fsub)
71138)]
71139#[target_feature(enable = "neon,fp16")]
71140#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
71141pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
71142 unsafe { simd_sub(a, b) }
71143}
71144#[doc = "Subtract"]
71145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
71146#[inline]
71147#[target_feature(enable = "neon")]
71148#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71149#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71150#[cfg_attr(
71151 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71152 assert_instr(fsub)
71153)]
71154#[cfg_attr(
71155 not(target_arch = "arm"),
71156 stable(feature = "neon_intrinsics", since = "1.59.0")
71157)]
71158#[cfg_attr(
71159 target_arch = "arm",
71160 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71161)]
71162pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
71163 unsafe { simd_sub(a, b) }
71164}
71165#[doc = "Subtract"]
71166#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
71167#[inline]
71168#[target_feature(enable = "neon")]
71169#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71170#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
71171#[cfg_attr(
71172 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71173 assert_instr(fsub)
71174)]
71175#[cfg_attr(
71176 not(target_arch = "arm"),
71177 stable(feature = "neon_intrinsics", since = "1.59.0")
71178)]
71179#[cfg_attr(
71180 target_arch = "arm",
71181 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71182)]
71183pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
71184 unsafe { simd_sub(a, b) }
71185}
71186#[doc = "Subtract"]
71187#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
71188#[inline]
71189#[target_feature(enable = "neon")]
71190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71191#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71192#[cfg_attr(
71193 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71194 assert_instr(sub)
71195)]
71196#[cfg_attr(
71197 not(target_arch = "arm"),
71198 stable(feature = "neon_intrinsics", since = "1.59.0")
71199)]
71200#[cfg_attr(
71201 target_arch = "arm",
71202 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71203)]
71204pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
71205 unsafe { simd_sub(a, b) }
71206}
71207#[doc = "Subtract"]
71208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
71209#[inline]
71210#[target_feature(enable = "neon")]
71211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71212#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71213#[cfg_attr(
71214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71215 assert_instr(sub)
71216)]
71217#[cfg_attr(
71218 not(target_arch = "arm"),
71219 stable(feature = "neon_intrinsics", since = "1.59.0")
71220)]
71221#[cfg_attr(
71222 target_arch = "arm",
71223 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71224)]
71225pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
71226 unsafe { simd_sub(a, b) }
71227}
71228#[doc = "Subtract"]
71229#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
71230#[inline]
71231#[target_feature(enable = "neon")]
71232#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71233#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71234#[cfg_attr(
71235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71236 assert_instr(sub)
71237)]
71238#[cfg_attr(
71239 not(target_arch = "arm"),
71240 stable(feature = "neon_intrinsics", since = "1.59.0")
71241)]
71242#[cfg_attr(
71243 target_arch = "arm",
71244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71245)]
71246pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
71247 unsafe { simd_sub(a, b) }
71248}
71249#[doc = "Subtract"]
71250#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
71251#[inline]
71252#[target_feature(enable = "neon")]
71253#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71254#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
71255#[cfg_attr(
71256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71257 assert_instr(sub)
71258)]
71259#[cfg_attr(
71260 not(target_arch = "arm"),
71261 stable(feature = "neon_intrinsics", since = "1.59.0")
71262)]
71263#[cfg_attr(
71264 target_arch = "arm",
71265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71266)]
71267pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
71268 unsafe { simd_sub(a, b) }
71269}
71270#[doc = "Subtract"]
71271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
71272#[inline]
71273#[target_feature(enable = "neon")]
71274#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71275#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71276#[cfg_attr(
71277 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71278 assert_instr(sub)
71279)]
71280#[cfg_attr(
71281 not(target_arch = "arm"),
71282 stable(feature = "neon_intrinsics", since = "1.59.0")
71283)]
71284#[cfg_attr(
71285 target_arch = "arm",
71286 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71287)]
71288pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
71289 unsafe { simd_sub(a, b) }
71290}
71291#[doc = "Subtract"]
71292#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
71293#[inline]
71294#[target_feature(enable = "neon")]
71295#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71296#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71297#[cfg_attr(
71298 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71299 assert_instr(sub)
71300)]
71301#[cfg_attr(
71302 not(target_arch = "arm"),
71303 stable(feature = "neon_intrinsics", since = "1.59.0")
71304)]
71305#[cfg_attr(
71306 target_arch = "arm",
71307 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71308)]
71309pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
71310 unsafe { simd_sub(a, b) }
71311}
71312#[doc = "Subtract"]
71313#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
71314#[inline]
71315#[target_feature(enable = "neon")]
71316#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71317#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71318#[cfg_attr(
71319 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71320 assert_instr(sub)
71321)]
71322#[cfg_attr(
71323 not(target_arch = "arm"),
71324 stable(feature = "neon_intrinsics", since = "1.59.0")
71325)]
71326#[cfg_attr(
71327 target_arch = "arm",
71328 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71329)]
71330pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
71331 unsafe { simd_sub(a, b) }
71332}
71333#[doc = "Subtract"]
71334#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
71335#[inline]
71336#[target_feature(enable = "neon")]
71337#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71338#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
71339#[cfg_attr(
71340 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71341 assert_instr(sub)
71342)]
71343#[cfg_attr(
71344 not(target_arch = "arm"),
71345 stable(feature = "neon_intrinsics", since = "1.59.0")
71346)]
71347#[cfg_attr(
71348 target_arch = "arm",
71349 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71350)]
71351pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
71352 unsafe { simd_sub(a, b) }
71353}
71354#[doc = "Subtract"]
71355#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
71356#[inline]
71357#[target_feature(enable = "neon")]
71358#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71359#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71360#[cfg_attr(
71361 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71362 assert_instr(sub)
71363)]
71364#[cfg_attr(
71365 not(target_arch = "arm"),
71366 stable(feature = "neon_intrinsics", since = "1.59.0")
71367)]
71368#[cfg_attr(
71369 target_arch = "arm",
71370 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71371)]
71372pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
71373 unsafe { simd_sub(a, b) }
71374}
71375#[doc = "Subtract"]
71376#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
71377#[inline]
71378#[target_feature(enable = "neon")]
71379#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71380#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71381#[cfg_attr(
71382 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71383 assert_instr(sub)
71384)]
71385#[cfg_attr(
71386 not(target_arch = "arm"),
71387 stable(feature = "neon_intrinsics", since = "1.59.0")
71388)]
71389#[cfg_attr(
71390 target_arch = "arm",
71391 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71392)]
71393pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
71394 unsafe { simd_sub(a, b) }
71395}
71396#[doc = "Subtract"]
71397#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
71398#[inline]
71399#[target_feature(enable = "neon")]
71400#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71401#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71402#[cfg_attr(
71403 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71404 assert_instr(sub)
71405)]
71406#[cfg_attr(
71407 not(target_arch = "arm"),
71408 stable(feature = "neon_intrinsics", since = "1.59.0")
71409)]
71410#[cfg_attr(
71411 target_arch = "arm",
71412 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71413)]
71414pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
71415 unsafe { simd_sub(a, b) }
71416}
71417#[doc = "Subtract"]
71418#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
71419#[inline]
71420#[target_feature(enable = "neon")]
71421#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71422#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
71423#[cfg_attr(
71424 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71425 assert_instr(sub)
71426)]
71427#[cfg_attr(
71428 not(target_arch = "arm"),
71429 stable(feature = "neon_intrinsics", since = "1.59.0")
71430)]
71431#[cfg_attr(
71432 target_arch = "arm",
71433 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71434)]
71435pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
71436 unsafe { simd_sub(a, b) }
71437}
71438#[doc = "Subtract"]
71439#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
71440#[inline]
71441#[target_feature(enable = "neon")]
71442#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71443#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71444#[cfg_attr(
71445 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71446 assert_instr(sub)
71447)]
71448#[cfg_attr(
71449 not(target_arch = "arm"),
71450 stable(feature = "neon_intrinsics", since = "1.59.0")
71451)]
71452#[cfg_attr(
71453 target_arch = "arm",
71454 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71455)]
71456pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
71457 unsafe { simd_sub(a, b) }
71458}
71459#[doc = "Subtract"]
71460#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
71461#[inline]
71462#[target_feature(enable = "neon")]
71463#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71464#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71465#[cfg_attr(
71466 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71467 assert_instr(sub)
71468)]
71469#[cfg_attr(
71470 not(target_arch = "arm"),
71471 stable(feature = "neon_intrinsics", since = "1.59.0")
71472)]
71473#[cfg_attr(
71474 target_arch = "arm",
71475 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71476)]
71477pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
71478 unsafe { simd_sub(a, b) }
71479}
71480#[doc = "Subtract"]
71481#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
71482#[inline]
71483#[target_feature(enable = "neon")]
71484#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71485#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71486#[cfg_attr(
71487 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71488 assert_instr(sub)
71489)]
71490#[cfg_attr(
71491 not(target_arch = "arm"),
71492 stable(feature = "neon_intrinsics", since = "1.59.0")
71493)]
71494#[cfg_attr(
71495 target_arch = "arm",
71496 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71497)]
71498pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
71499 unsafe { simd_sub(a, b) }
71500}
71501#[doc = "Subtract"]
71502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
71503#[inline]
71504#[target_feature(enable = "neon")]
71505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71506#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
71507#[cfg_attr(
71508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71509 assert_instr(sub)
71510)]
71511#[cfg_attr(
71512 not(target_arch = "arm"),
71513 stable(feature = "neon_intrinsics", since = "1.59.0")
71514)]
71515#[cfg_attr(
71516 target_arch = "arm",
71517 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71518)]
71519pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
71520 unsafe { simd_sub(a, b) }
71521}
71522#[doc = "Subtract returning high narrow"]
71523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
71524#[inline]
71525#[target_feature(enable = "neon")]
71526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71528#[cfg_attr(
71529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71530 assert_instr(subhn2)
71531)]
71532#[cfg_attr(
71533 not(target_arch = "arm"),
71534 stable(feature = "neon_intrinsics", since = "1.59.0")
71535)]
71536#[cfg_attr(
71537 target_arch = "arm",
71538 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71539)]
71540pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
71541 let d: int8x8_t = vsubhn_s16(b, c);
71542 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71543}
71544#[doc = "Subtract returning high narrow"]
71545#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
71546#[inline]
71547#[target_feature(enable = "neon")]
71548#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71549#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71550#[cfg_attr(
71551 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71552 assert_instr(subhn2)
71553)]
71554#[cfg_attr(
71555 not(target_arch = "arm"),
71556 stable(feature = "neon_intrinsics", since = "1.59.0")
71557)]
71558#[cfg_attr(
71559 target_arch = "arm",
71560 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71561)]
71562pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
71563 let d: int16x4_t = vsubhn_s32(b, c);
71564 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
71565}
71566#[doc = "Subtract returning high narrow"]
71567#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
71568#[inline]
71569#[target_feature(enable = "neon")]
71570#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71571#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71572#[cfg_attr(
71573 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71574 assert_instr(subhn2)
71575)]
71576#[cfg_attr(
71577 not(target_arch = "arm"),
71578 stable(feature = "neon_intrinsics", since = "1.59.0")
71579)]
71580#[cfg_attr(
71581 target_arch = "arm",
71582 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71583)]
71584pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
71585 let d: int32x2_t = vsubhn_s64(b, c);
71586 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
71587}
71588#[doc = "Subtract returning high narrow"]
71589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
71590#[inline]
71591#[target_feature(enable = "neon")]
71592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71594#[cfg_attr(
71595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71596 assert_instr(subhn2)
71597)]
71598#[cfg_attr(
71599 not(target_arch = "arm"),
71600 stable(feature = "neon_intrinsics", since = "1.59.0")
71601)]
71602#[cfg_attr(
71603 target_arch = "arm",
71604 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71605)]
71606pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t {
71607 let d: uint8x8_t = vsubhn_u16(b, c);
71608 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) }
71609}
71610#[doc = "Subtract returning high narrow"]
71611#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
71612#[inline]
71613#[target_feature(enable = "neon")]
71614#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71615#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71616#[cfg_attr(
71617 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71618 assert_instr(subhn2)
71619)]
71620#[cfg_attr(
71621 not(target_arch = "arm"),
71622 stable(feature = "neon_intrinsics", since = "1.59.0")
71623)]
71624#[cfg_attr(
71625 target_arch = "arm",
71626 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71627)]
71628pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t {
71629 let d: uint16x4_t = vsubhn_u32(b, c);
71630 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) }
71631}
71632#[doc = "Subtract returning high narrow"]
71633#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
71634#[inline]
71635#[target_feature(enable = "neon")]
71636#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71637#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71638#[cfg_attr(
71639 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71640 assert_instr(subhn2)
71641)]
71642#[cfg_attr(
71643 not(target_arch = "arm"),
71644 stable(feature = "neon_intrinsics", since = "1.59.0")
71645)]
71646#[cfg_attr(
71647 target_arch = "arm",
71648 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71649)]
71650pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t {
71651 let d: uint32x2_t = vsubhn_u64(b, c);
71652 unsafe { simd_shuffle!(a, d, [0, 1, 2, 3]) }
71653}
71654#[doc = "Subtract returning high narrow"]
71655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
71656#[inline]
71657#[target_feature(enable = "neon")]
71658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71660#[cfg_attr(
71661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71662 assert_instr(subhn)
71663)]
71664#[cfg_attr(
71665 not(target_arch = "arm"),
71666 stable(feature = "neon_intrinsics", since = "1.59.0")
71667)]
71668#[cfg_attr(
71669 target_arch = "arm",
71670 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71671)]
71672pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
71673 let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
71674 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71675}
71676#[doc = "Subtract returning high narrow"]
71677#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
71678#[inline]
71679#[target_feature(enable = "neon")]
71680#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71681#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71682#[cfg_attr(
71683 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71684 assert_instr(subhn)
71685)]
71686#[cfg_attr(
71687 not(target_arch = "arm"),
71688 stable(feature = "neon_intrinsics", since = "1.59.0")
71689)]
71690#[cfg_attr(
71691 target_arch = "arm",
71692 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71693)]
71694pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
71695 let c: i32x4 = i32x4::new(16, 16, 16, 16);
71696 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71697}
71698#[doc = "Subtract returning high narrow"]
71699#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
71700#[inline]
71701#[target_feature(enable = "neon")]
71702#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71703#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71704#[cfg_attr(
71705 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71706 assert_instr(subhn)
71707)]
71708#[cfg_attr(
71709 not(target_arch = "arm"),
71710 stable(feature = "neon_intrinsics", since = "1.59.0")
71711)]
71712#[cfg_attr(
71713 target_arch = "arm",
71714 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71715)]
71716pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
71717 let c: i64x2 = i64x2::new(32, 32);
71718 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71719}
71720#[doc = "Subtract returning high narrow"]
71721#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
71722#[inline]
71723#[target_feature(enable = "neon")]
71724#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71725#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71726#[cfg_attr(
71727 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71728 assert_instr(subhn)
71729)]
71730#[cfg_attr(
71731 not(target_arch = "arm"),
71732 stable(feature = "neon_intrinsics", since = "1.59.0")
71733)]
71734#[cfg_attr(
71735 target_arch = "arm",
71736 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71737)]
71738pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
71739 let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8);
71740 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71741}
71742#[doc = "Subtract returning high narrow"]
71743#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
71744#[inline]
71745#[target_feature(enable = "neon")]
71746#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71747#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71748#[cfg_attr(
71749 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71750 assert_instr(subhn)
71751)]
71752#[cfg_attr(
71753 not(target_arch = "arm"),
71754 stable(feature = "neon_intrinsics", since = "1.59.0")
71755)]
71756#[cfg_attr(
71757 target_arch = "arm",
71758 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71759)]
71760pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
71761 let c: u32x4 = u32x4::new(16, 16, 16, 16);
71762 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71763}
71764#[doc = "Subtract returning high narrow"]
71765#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
71766#[inline]
71767#[target_feature(enable = "neon")]
71768#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71769#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
71770#[cfg_attr(
71771 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71772 assert_instr(subhn)
71773)]
71774#[cfg_attr(
71775 not(target_arch = "arm"),
71776 stable(feature = "neon_intrinsics", since = "1.59.0")
71777)]
71778#[cfg_attr(
71779 target_arch = "arm",
71780 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71781)]
71782pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
71783 let c: u64x2 = u64x2::new(32, 32);
71784 unsafe { simd_cast(simd_shr(simd_sub(a, b), transmute(c))) }
71785}
71786#[doc = "Signed Subtract Long"]
71787#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
71788#[inline]
71789#[target_feature(enable = "neon")]
71790#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71791#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71792#[cfg_attr(
71793 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71794 assert_instr(ssubl)
71795)]
71796#[cfg_attr(
71797 not(target_arch = "arm"),
71798 stable(feature = "neon_intrinsics", since = "1.59.0")
71799)]
71800#[cfg_attr(
71801 target_arch = "arm",
71802 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71803)]
71804pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
71805 unsafe {
71806 let c: int16x8_t = simd_cast(a);
71807 let d: int16x8_t = simd_cast(b);
71808 simd_sub(c, d)
71809 }
71810}
71811#[doc = "Signed Subtract Long"]
71812#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
71813#[inline]
71814#[target_feature(enable = "neon")]
71815#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71816#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71817#[cfg_attr(
71818 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71819 assert_instr(ssubl)
71820)]
71821#[cfg_attr(
71822 not(target_arch = "arm"),
71823 stable(feature = "neon_intrinsics", since = "1.59.0")
71824)]
71825#[cfg_attr(
71826 target_arch = "arm",
71827 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71828)]
71829pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
71830 unsafe {
71831 let c: int32x4_t = simd_cast(a);
71832 let d: int32x4_t = simd_cast(b);
71833 simd_sub(c, d)
71834 }
71835}
71836#[doc = "Signed Subtract Long"]
71837#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
71838#[inline]
71839#[target_feature(enable = "neon")]
71840#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71841#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71842#[cfg_attr(
71843 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71844 assert_instr(ssubl)
71845)]
71846#[cfg_attr(
71847 not(target_arch = "arm"),
71848 stable(feature = "neon_intrinsics", since = "1.59.0")
71849)]
71850#[cfg_attr(
71851 target_arch = "arm",
71852 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71853)]
71854pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
71855 unsafe {
71856 let c: int64x2_t = simd_cast(a);
71857 let d: int64x2_t = simd_cast(b);
71858 simd_sub(c, d)
71859 }
71860}
71861#[doc = "Unsigned Subtract Long"]
71862#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
71863#[inline]
71864#[target_feature(enable = "neon")]
71865#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71866#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71867#[cfg_attr(
71868 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71869 assert_instr(usubl)
71870)]
71871#[cfg_attr(
71872 not(target_arch = "arm"),
71873 stable(feature = "neon_intrinsics", since = "1.59.0")
71874)]
71875#[cfg_attr(
71876 target_arch = "arm",
71877 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71878)]
71879pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
71880 unsafe {
71881 let c: uint16x8_t = simd_cast(a);
71882 let d: uint16x8_t = simd_cast(b);
71883 simd_sub(c, d)
71884 }
71885}
71886#[doc = "Unsigned Subtract Long"]
71887#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
71888#[inline]
71889#[target_feature(enable = "neon")]
71890#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71891#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71892#[cfg_attr(
71893 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71894 assert_instr(usubl)
71895)]
71896#[cfg_attr(
71897 not(target_arch = "arm"),
71898 stable(feature = "neon_intrinsics", since = "1.59.0")
71899)]
71900#[cfg_attr(
71901 target_arch = "arm",
71902 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71903)]
71904pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
71905 unsafe {
71906 let c: uint32x4_t = simd_cast(a);
71907 let d: uint32x4_t = simd_cast(b);
71908 simd_sub(c, d)
71909 }
71910}
71911#[doc = "Unsigned Subtract Long"]
71912#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
71913#[inline]
71914#[target_feature(enable = "neon")]
71915#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71916#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
71917#[cfg_attr(
71918 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71919 assert_instr(usubl)
71920)]
71921#[cfg_attr(
71922 not(target_arch = "arm"),
71923 stable(feature = "neon_intrinsics", since = "1.59.0")
71924)]
71925#[cfg_attr(
71926 target_arch = "arm",
71927 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71928)]
71929pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
71930 unsafe {
71931 let c: uint64x2_t = simd_cast(a);
71932 let d: uint64x2_t = simd_cast(b);
71933 simd_sub(c, d)
71934 }
71935}
71936#[doc = "Signed Subtract Wide"]
71937#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
71938#[inline]
71939#[target_feature(enable = "neon")]
71940#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71941#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
71942#[cfg_attr(
71943 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71944 assert_instr(ssubw)
71945)]
71946#[cfg_attr(
71947 not(target_arch = "arm"),
71948 stable(feature = "neon_intrinsics", since = "1.59.0")
71949)]
71950#[cfg_attr(
71951 target_arch = "arm",
71952 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71953)]
71954pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
71955 unsafe { simd_sub(a, simd_cast(b)) }
71956}
71957#[doc = "Signed Subtract Wide"]
71958#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
71959#[inline]
71960#[target_feature(enable = "neon")]
71961#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71962#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
71963#[cfg_attr(
71964 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71965 assert_instr(ssubw)
71966)]
71967#[cfg_attr(
71968 not(target_arch = "arm"),
71969 stable(feature = "neon_intrinsics", since = "1.59.0")
71970)]
71971#[cfg_attr(
71972 target_arch = "arm",
71973 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71974)]
71975pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
71976 unsafe { simd_sub(a, simd_cast(b)) }
71977}
71978#[doc = "Signed Subtract Wide"]
71979#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
71980#[inline]
71981#[target_feature(enable = "neon")]
71982#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
71983#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
71984#[cfg_attr(
71985 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
71986 assert_instr(ssubw)
71987)]
71988#[cfg_attr(
71989 not(target_arch = "arm"),
71990 stable(feature = "neon_intrinsics", since = "1.59.0")
71991)]
71992#[cfg_attr(
71993 target_arch = "arm",
71994 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
71995)]
71996pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
71997 unsafe { simd_sub(a, simd_cast(b)) }
71998}
71999#[doc = "Unsigned Subtract Wide"]
72000#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
72001#[inline]
72002#[target_feature(enable = "neon")]
72003#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72004#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72005#[cfg_attr(
72006 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72007 assert_instr(usubw)
72008)]
72009#[cfg_attr(
72010 not(target_arch = "arm"),
72011 stable(feature = "neon_intrinsics", since = "1.59.0")
72012)]
72013#[cfg_attr(
72014 target_arch = "arm",
72015 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72016)]
72017pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
72018 unsafe { simd_sub(a, simd_cast(b)) }
72019}
72020#[doc = "Unsigned Subtract Wide"]
72021#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
72022#[inline]
72023#[target_feature(enable = "neon")]
72024#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72025#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72026#[cfg_attr(
72027 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72028 assert_instr(usubw)
72029)]
72030#[cfg_attr(
72031 not(target_arch = "arm"),
72032 stable(feature = "neon_intrinsics", since = "1.59.0")
72033)]
72034#[cfg_attr(
72035 target_arch = "arm",
72036 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72037)]
72038pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
72039 unsafe { simd_sub(a, simd_cast(b)) }
72040}
72041#[doc = "Unsigned Subtract Wide"]
72042#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
72043#[inline]
72044#[target_feature(enable = "neon")]
72045#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72046#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
72047#[cfg_attr(
72048 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72049 assert_instr(usubw)
72050)]
72051#[cfg_attr(
72052 not(target_arch = "arm"),
72053 stable(feature = "neon_intrinsics", since = "1.59.0")
72054)]
72055#[cfg_attr(
72056 target_arch = "arm",
72057 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72058)]
72059pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
72060 unsafe { simd_sub(a, simd_cast(b)) }
72061}
72062#[doc = "Dot product index form with signed and unsigned integers"]
72063#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
72064#[inline]
72065#[target_feature(enable = "neon,i8mm")]
72066#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72067#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72068#[cfg_attr(
72069 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72070 assert_instr(sudot, LANE = 0)
72071)]
72072#[rustc_legacy_const_generics(3)]
72073#[cfg_attr(
72074 not(target_arch = "arm"),
72075 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72076)]
72077#[cfg_attr(
72078 target_arch = "arm",
72079 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72080)]
72081pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t {
72082 static_assert_uimm_bits!(LANE, 1);
72083 unsafe {
72084 let c: uint32x2_t = transmute(c);
72085 let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
72086 vusdot_s32(a, transmute(c), b)
72087 }
72088}
72089#[doc = "Dot product index form with signed and unsigned integers"]
72090#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
72091#[inline]
72092#[target_feature(enable = "neon,i8mm")]
72093#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
72094#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))]
72095#[cfg_attr(
72096 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72097 assert_instr(sudot, LANE = 0)
72098)]
72099#[rustc_legacy_const_generics(3)]
72100#[cfg_attr(
72101 not(target_arch = "arm"),
72102 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
72103)]
72104#[cfg_attr(
72105 target_arch = "arm",
72106 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
72107)]
72108pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t {
72109 static_assert_uimm_bits!(LANE, 1);
72110 unsafe {
72111 let c: uint32x2_t = transmute(c);
72112 let c: uint32x4_t =
72113 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
72114 vusdotq_s32(a, transmute(c), b)
72115 }
72116}
72117#[doc = "Table look-up"]
72118#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
72119#[inline]
72120#[target_feature(enable = "neon")]
72121#[cfg(target_arch = "arm")]
72122#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72123#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72124#[cfg_attr(test, assert_instr(vtbl))]
72125fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72126 unsafe extern "unadjusted" {
72127 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl1")]
72128 fn _vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
72129 }
72130 unsafe { _vtbl1(a, b) }
72131}
72132#[doc = "Table look-up"]
72133#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
72134#[inline]
72135#[target_feature(enable = "neon")]
72136#[cfg(target_arch = "arm")]
72137#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72138#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72139#[cfg_attr(test, assert_instr(vtbl))]
72140pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
72141 vtbl1(a, b)
72142}
72143#[doc = "Table look-up"]
72144#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72145#[inline]
72146#[cfg(target_endian = "little")]
72147#[target_feature(enable = "neon")]
72148#[cfg(target_arch = "arm")]
72149#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72150#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72151#[cfg_attr(test, assert_instr(vtbl))]
72152pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72153 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72154}
72155#[doc = "Table look-up"]
72156#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
72157#[inline]
72158#[cfg(target_endian = "big")]
72159#[target_feature(enable = "neon")]
72160#[cfg(target_arch = "arm")]
72161#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72162#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72163#[cfg_attr(test, assert_instr(vtbl))]
72164pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
72165 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72166 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72167 unsafe {
72168 let ret_val: uint8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72169 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72170 }
72171}
72172#[doc = "Table look-up"]
72173#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72174#[inline]
72175#[cfg(target_endian = "little")]
72176#[target_feature(enable = "neon")]
72177#[cfg(target_arch = "arm")]
72178#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72179#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72180#[cfg_attr(test, assert_instr(vtbl))]
72181pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72182 unsafe { transmute(vtbl1(transmute(a), transmute(b))) }
72183}
72184#[doc = "Table look-up"]
72185#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
72186#[inline]
72187#[cfg(target_endian = "big")]
72188#[target_feature(enable = "neon")]
72189#[cfg(target_arch = "arm")]
72190#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72191#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72192#[cfg_attr(test, assert_instr(vtbl))]
72193pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
72194 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72195 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72196 unsafe {
72197 let ret_val: poly8x8_t = transmute(vtbl1(transmute(a), transmute(b)));
72198 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72199 }
72200}
72201#[doc = "Table look-up"]
72202#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
72203#[inline]
72204#[target_feature(enable = "neon")]
72205#[cfg(target_arch = "arm")]
72206#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72207#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72208#[cfg_attr(test, assert_instr(vtbl))]
72209fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72210 unsafe extern "unadjusted" {
72211 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl2")]
72212 fn _vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72213 }
72214 unsafe { _vtbl2(a, b, c) }
72215}
72216#[doc = "Table look-up"]
72217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
72218#[inline]
72219#[target_feature(enable = "neon")]
72220#[cfg(target_arch = "arm")]
72221#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72222#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72223#[cfg_attr(test, assert_instr(vtbl))]
72224pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
72225 vtbl2(a.0, a.1, b)
72226}
72227#[doc = "Table look-up"]
72228#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72229#[inline]
72230#[cfg(target_endian = "little")]
72231#[target_feature(enable = "neon")]
72232#[cfg(target_arch = "arm")]
72233#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72234#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72235#[cfg_attr(test, assert_instr(vtbl))]
72236pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72237 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72238}
72239#[doc = "Table look-up"]
72240#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
72241#[inline]
72242#[cfg(target_endian = "big")]
72243#[target_feature(enable = "neon")]
72244#[cfg(target_arch = "arm")]
72245#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72246#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72247#[cfg_attr(test, assert_instr(vtbl))]
72248pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
72249 let mut a: uint8x8x2_t = a;
72250 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72251 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72252 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72253 unsafe {
72254 let ret_val: uint8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72255 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72256 }
72257}
72258#[doc = "Table look-up"]
72259#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72260#[inline]
72261#[cfg(target_endian = "little")]
72262#[target_feature(enable = "neon")]
72263#[cfg(target_arch = "arm")]
72264#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72265#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72266#[cfg_attr(test, assert_instr(vtbl))]
72267pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72268 unsafe { transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b))) }
72269}
72270#[doc = "Table look-up"]
72271#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
72272#[inline]
72273#[cfg(target_endian = "big")]
72274#[target_feature(enable = "neon")]
72275#[cfg(target_arch = "arm")]
72276#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72277#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72278#[cfg_attr(test, assert_instr(vtbl))]
72279pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
72280 let mut a: poly8x8x2_t = a;
72281 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72282 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72283 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72284 unsafe {
72285 let ret_val: poly8x8_t = transmute(vtbl2(transmute(a.0), transmute(a.1), transmute(b)));
72286 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72287 }
72288}
72289#[doc = "Table look-up"]
72290#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
72291#[inline]
72292#[target_feature(enable = "neon")]
72293#[cfg(target_arch = "arm")]
72294#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72295#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72296#[cfg_attr(test, assert_instr(vtbl))]
72297fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72298 unsafe extern "unadjusted" {
72299 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl3")]
72300 fn _vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72301 }
72302 unsafe { _vtbl3(a, b, c, d) }
72303}
72304#[doc = "Table look-up"]
72305#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
72306#[inline]
72307#[target_feature(enable = "neon")]
72308#[cfg(target_arch = "arm")]
72309#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72310#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72311#[cfg_attr(test, assert_instr(vtbl))]
72312pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
72313 vtbl3(a.0, a.1, a.2, b)
72314}
72315#[doc = "Table look-up"]
72316#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72317#[inline]
72318#[cfg(target_endian = "little")]
72319#[target_feature(enable = "neon")]
72320#[cfg(target_arch = "arm")]
72321#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72322#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72323#[cfg_attr(test, assert_instr(vtbl))]
72324pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72325 unsafe {
72326 transmute(vtbl3(
72327 transmute(a.0),
72328 transmute(a.1),
72329 transmute(a.2),
72330 transmute(b),
72331 ))
72332 }
72333}
72334#[doc = "Table look-up"]
72335#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
72336#[inline]
72337#[cfg(target_endian = "big")]
72338#[target_feature(enable = "neon")]
72339#[cfg(target_arch = "arm")]
72340#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72341#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72342#[cfg_attr(test, assert_instr(vtbl))]
72343pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
72344 let mut a: uint8x8x3_t = a;
72345 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72346 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72347 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72348 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72349 unsafe {
72350 let ret_val: uint8x8_t = transmute(vtbl3(
72351 transmute(a.0),
72352 transmute(a.1),
72353 transmute(a.2),
72354 transmute(b),
72355 ));
72356 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72357 }
72358}
72359#[doc = "Table look-up"]
72360#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72361#[inline]
72362#[cfg(target_endian = "little")]
72363#[target_feature(enable = "neon")]
72364#[cfg(target_arch = "arm")]
72365#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72366#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72367#[cfg_attr(test, assert_instr(vtbl))]
72368pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72369 unsafe {
72370 transmute(vtbl3(
72371 transmute(a.0),
72372 transmute(a.1),
72373 transmute(a.2),
72374 transmute(b),
72375 ))
72376 }
72377}
72378#[doc = "Table look-up"]
72379#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
72380#[inline]
72381#[cfg(target_endian = "big")]
72382#[target_feature(enable = "neon")]
72383#[cfg(target_arch = "arm")]
72384#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72385#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72386#[cfg_attr(test, assert_instr(vtbl))]
72387pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
72388 let mut a: poly8x8x3_t = a;
72389 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72390 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72391 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72392 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72393 unsafe {
72394 let ret_val: poly8x8_t = transmute(vtbl3(
72395 transmute(a.0),
72396 transmute(a.1),
72397 transmute(a.2),
72398 transmute(b),
72399 ));
72400 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72401 }
72402}
72403#[doc = "Table look-up"]
72404#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
72405#[inline]
72406#[target_feature(enable = "neon")]
72407#[cfg(target_arch = "arm")]
72408#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72409#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72410#[cfg_attr(test, assert_instr(vtbl))]
72411fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
72412 unsafe extern "unadjusted" {
72413 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbl4")]
72414 fn _vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
72415 }
72416 unsafe { _vtbl4(a, b, c, d, e) }
72417}
72418#[doc = "Table look-up"]
72419#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
72420#[inline]
72421#[target_feature(enable = "neon")]
72422#[cfg(target_arch = "arm")]
72423#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72424#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72425#[cfg_attr(test, assert_instr(vtbl))]
72426pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
72427 vtbl4(a.0, a.1, a.2, a.3, b)
72428}
72429#[doc = "Table look-up"]
72430#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72431#[inline]
72432#[cfg(target_endian = "little")]
72433#[target_feature(enable = "neon")]
72434#[cfg(target_arch = "arm")]
72435#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72436#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72437#[cfg_attr(test, assert_instr(vtbl))]
72438pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72439 unsafe {
72440 transmute(vtbl4(
72441 transmute(a.0),
72442 transmute(a.1),
72443 transmute(a.2),
72444 transmute(a.3),
72445 transmute(b),
72446 ))
72447 }
72448}
72449#[doc = "Table look-up"]
72450#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
72451#[inline]
72452#[cfg(target_endian = "big")]
72453#[target_feature(enable = "neon")]
72454#[cfg(target_arch = "arm")]
72455#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72456#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72457#[cfg_attr(test, assert_instr(vtbl))]
72458pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
72459 let mut a: uint8x8x4_t = a;
72460 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72461 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72462 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72463 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72464 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72465 unsafe {
72466 let ret_val: uint8x8_t = transmute(vtbl4(
72467 transmute(a.0),
72468 transmute(a.1),
72469 transmute(a.2),
72470 transmute(a.3),
72471 transmute(b),
72472 ));
72473 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72474 }
72475}
72476#[doc = "Table look-up"]
72477#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72478#[inline]
72479#[cfg(target_endian = "little")]
72480#[target_feature(enable = "neon")]
72481#[cfg(target_arch = "arm")]
72482#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72483#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72484#[cfg_attr(test, assert_instr(vtbl))]
72485pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72486 unsafe {
72487 transmute(vtbl4(
72488 transmute(a.0),
72489 transmute(a.1),
72490 transmute(a.2),
72491 transmute(a.3),
72492 transmute(b),
72493 ))
72494 }
72495}
72496#[doc = "Table look-up"]
72497#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
72498#[inline]
72499#[cfg(target_endian = "big")]
72500#[target_feature(enable = "neon")]
72501#[cfg(target_arch = "arm")]
72502#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72503#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72504#[cfg_attr(test, assert_instr(vtbl))]
72505pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
72506 let mut a: poly8x8x4_t = a;
72507 a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72508 a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72509 a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72510 a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72511 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72512 unsafe {
72513 let ret_val: poly8x8_t = transmute(vtbl4(
72514 transmute(a.0),
72515 transmute(a.1),
72516 transmute(a.2),
72517 transmute(a.3),
72518 transmute(b),
72519 ));
72520 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72521 }
72522}
72523#[doc = "Extended table look-up"]
72524#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
72525#[inline]
72526#[target_feature(enable = "neon,v7")]
72527#[cfg(target_arch = "arm")]
72528#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72529#[cfg_attr(test, assert_instr(vtbx))]
72530fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72531 unsafe extern "unadjusted" {
72532 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx1")]
72533 fn _vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t;
72534 }
72535 unsafe { _vtbx1(a, b, c) }
72536}
72537#[doc = "Extended table look-up"]
72538#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
72539#[inline]
72540#[target_feature(enable = "neon,v7")]
72541#[cfg(target_arch = "arm")]
72542#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72543#[cfg_attr(test, assert_instr(vtbx))]
72544pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
72545 vtbx1(a, b, c)
72546}
72547#[doc = "Extended table look-up"]
72548#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72549#[inline]
72550#[cfg(target_endian = "little")]
72551#[target_feature(enable = "neon,v7")]
72552#[cfg(target_arch = "arm")]
72553#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72554#[cfg_attr(test, assert_instr(vtbx))]
72555pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
72556 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
72557}
72558#[doc = "Extended table look-up"]
72559#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
72560#[inline]
72561#[cfg(target_endian = "big")]
72562#[target_feature(enable = "neon,v7")]
72563#[cfg(target_arch = "arm")]
72564#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72565#[cfg_attr(test, assert_instr(vtbx))]
72566pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
72567 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72568 let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72569 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72570 unsafe {
72571 let ret_val: uint8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
72572 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72573 }
72574}
72575#[doc = "Extended table look-up"]
72576#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
72577#[inline]
72578#[cfg(target_endian = "little")]
72579#[target_feature(enable = "neon,v7")]
72580#[cfg(target_arch = "arm")]
72581#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72582#[cfg_attr(test, assert_instr(vtbx))]
72583pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
72584 unsafe { transmute(vtbx1(transmute(a), transmute(b), transmute(c))) }
72585}
72586#[doc = "Extended table look-up"]
72587#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
72588#[inline]
72589#[cfg(target_endian = "big")]
72590#[target_feature(enable = "neon,v7")]
72591#[cfg(target_arch = "arm")]
72592#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72593#[cfg_attr(test, assert_instr(vtbx))]
72594pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
72595 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72596 let b: poly8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
72597 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72598 unsafe {
72599 let ret_val: poly8x8_t = transmute(vtbx1(transmute(a), transmute(b), transmute(c)));
72600 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72601 }
72602}
72603#[doc = "Extended table look-up"]
72604#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
72605#[inline]
72606#[target_feature(enable = "neon,v7")]
72607#[cfg(target_arch = "arm")]
72608#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72609#[cfg_attr(test, assert_instr(vtbx))]
72610fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
72611 unsafe extern "unadjusted" {
72612 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx2")]
72613 fn _vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t;
72614 }
72615 unsafe { _vtbx2(a, b, c, d) }
72616}
72617#[doc = "Extended table look-up"]
72618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
72619#[inline]
72620#[target_feature(enable = "neon,v7")]
72621#[cfg(target_arch = "arm")]
72622#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72623#[cfg_attr(test, assert_instr(vtbx))]
72624pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
72625 vtbx2(a, b.0, b.1, c)
72626}
72627#[doc = "Extended table look-up"]
72628#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
72629#[inline]
72630#[cfg(target_endian = "little")]
72631#[target_feature(enable = "neon,v7")]
72632#[cfg(target_arch = "arm")]
72633#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72634#[cfg_attr(test, assert_instr(vtbx))]
72635pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
72636 unsafe {
72637 transmute(vtbx2(
72638 transmute(a),
72639 transmute(b.0),
72640 transmute(b.1),
72641 transmute(c),
72642 ))
72643 }
72644}
72645#[doc = "Extended table look-up"]
72646#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
72647#[inline]
72648#[cfg(target_endian = "big")]
72649#[target_feature(enable = "neon,v7")]
72650#[cfg(target_arch = "arm")]
72651#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72652#[cfg_attr(test, assert_instr(vtbx))]
72653pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
72654 let mut b: uint8x8x2_t = b;
72655 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72656 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72657 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72658 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72659 unsafe {
72660 let ret_val: uint8x8_t = transmute(vtbx2(
72661 transmute(a),
72662 transmute(b.0),
72663 transmute(b.1),
72664 transmute(c),
72665 ));
72666 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72667 }
72668}
72669#[doc = "Extended table look-up"]
72670#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
72671#[inline]
72672#[cfg(target_endian = "little")]
72673#[target_feature(enable = "neon,v7")]
72674#[cfg(target_arch = "arm")]
72675#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72676#[cfg_attr(test, assert_instr(vtbx))]
72677pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
72678 unsafe {
72679 transmute(vtbx2(
72680 transmute(a),
72681 transmute(b.0),
72682 transmute(b.1),
72683 transmute(c),
72684 ))
72685 }
72686}
72687#[doc = "Extended table look-up"]
72688#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
72689#[inline]
72690#[cfg(target_endian = "big")]
72691#[target_feature(enable = "neon,v7")]
72692#[cfg(target_arch = "arm")]
72693#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72694#[cfg_attr(test, assert_instr(vtbx))]
72695pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
72696 let mut b: poly8x8x2_t = b;
72697 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72698 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72699 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72700 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72701 unsafe {
72702 let ret_val: poly8x8_t = transmute(vtbx2(
72703 transmute(a),
72704 transmute(b.0),
72705 transmute(b.1),
72706 transmute(c),
72707 ));
72708 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72709 }
72710}
72711#[doc = "Extended table look-up"]
72712#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
72713#[inline]
72714#[target_feature(enable = "neon,v7")]
72715#[cfg(target_arch = "arm")]
72716#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72717#[cfg_attr(test, assert_instr(vtbx))]
72718fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t {
72719 unsafe extern "unadjusted" {
72720 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx3")]
72721 fn _vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int8x8_t;
72722 }
72723 unsafe { _vtbx3(a, b, c, d, e) }
72724}
72725#[doc = "Extended table look-up"]
72726#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
72727#[inline]
72728#[target_feature(enable = "neon,v7")]
72729#[cfg(target_arch = "arm")]
72730#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72731#[cfg_attr(test, assert_instr(vtbx))]
72732pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
72733 vtbx3(a, b.0, b.1, b.2, c)
72734}
72735#[doc = "Extended table look-up"]
72736#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
72737#[inline]
72738#[cfg(target_endian = "little")]
72739#[target_feature(enable = "neon,v7")]
72740#[cfg(target_arch = "arm")]
72741#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72742#[cfg_attr(test, assert_instr(vtbx))]
72743pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
72744 unsafe {
72745 transmute(vtbx3(
72746 transmute(a),
72747 transmute(b.0),
72748 transmute(b.1),
72749 transmute(b.2),
72750 transmute(c),
72751 ))
72752 }
72753}
72754#[doc = "Extended table look-up"]
72755#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
72756#[inline]
72757#[cfg(target_endian = "big")]
72758#[target_feature(enable = "neon,v7")]
72759#[cfg(target_arch = "arm")]
72760#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72761#[cfg_attr(test, assert_instr(vtbx))]
72762pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
72763 let mut b: uint8x8x3_t = b;
72764 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72765 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72766 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72767 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72768 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72769 unsafe {
72770 let ret_val: uint8x8_t = transmute(vtbx3(
72771 transmute(a),
72772 transmute(b.0),
72773 transmute(b.1),
72774 transmute(b.2),
72775 transmute(c),
72776 ));
72777 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72778 }
72779}
72780#[doc = "Extended table look-up"]
72781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
72782#[inline]
72783#[cfg(target_endian = "little")]
72784#[target_feature(enable = "neon,v7")]
72785#[cfg(target_arch = "arm")]
72786#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72787#[cfg_attr(test, assert_instr(vtbx))]
72788pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
72789 unsafe {
72790 transmute(vtbx3(
72791 transmute(a),
72792 transmute(b.0),
72793 transmute(b.1),
72794 transmute(b.2),
72795 transmute(c),
72796 ))
72797 }
72798}
72799#[doc = "Extended table look-up"]
72800#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
72801#[inline]
72802#[cfg(target_endian = "big")]
72803#[target_feature(enable = "neon,v7")]
72804#[cfg(target_arch = "arm")]
72805#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72806#[cfg_attr(test, assert_instr(vtbx))]
72807pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
72808 let mut b: poly8x8x3_t = b;
72809 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72810 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72811 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72812 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72813 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72814 unsafe {
72815 let ret_val: poly8x8_t = transmute(vtbx3(
72816 transmute(a),
72817 transmute(b.0),
72818 transmute(b.1),
72819 transmute(b.2),
72820 transmute(c),
72821 ));
72822 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72823 }
72824}
72825#[doc = "Extended table look-up"]
72826#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
72827#[inline]
72828#[target_feature(enable = "neon,v7")]
72829#[cfg(target_arch = "arm")]
72830#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72831#[cfg_attr(test, assert_instr(vtbx))]
72832fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int8x8_t) -> int8x8_t {
72833 unsafe extern "unadjusted" {
72834 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vtbx4")]
72835 fn _vtbx4(
72836 a: int8x8_t,
72837 b: int8x8_t,
72838 c: int8x8_t,
72839 d: int8x8_t,
72840 e: int8x8_t,
72841 f: int8x8_t,
72842 ) -> int8x8_t;
72843 }
72844 unsafe { _vtbx4(a, b, c, d, e, f) }
72845}
72846#[doc = "Extended table look-up"]
72847#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
72848#[inline]
72849#[cfg(target_endian = "little")]
72850#[target_feature(enable = "neon,v7")]
72851#[cfg(target_arch = "arm")]
72852#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72853#[cfg_attr(test, assert_instr(vtbx))]
72854pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
72855 unsafe {
72856 vtbx4(
72857 a,
72858 transmute(b.0),
72859 transmute(b.1),
72860 transmute(b.2),
72861 transmute(b.3),
72862 c,
72863 )
72864 }
72865}
72866#[doc = "Extended table look-up"]
72867#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
72868#[inline]
72869#[cfg(target_endian = "big")]
72870#[target_feature(enable = "neon,v7")]
72871#[cfg(target_arch = "arm")]
72872#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72873#[cfg_attr(test, assert_instr(vtbx))]
72874pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
72875 let mut b: int8x8x4_t = b;
72876 let a: int8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72877 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72878 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72879 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72880 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72881 let c: int8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72882 unsafe {
72883 let ret_val: int8x8_t = vtbx4(
72884 a,
72885 transmute(b.0),
72886 transmute(b.1),
72887 transmute(b.2),
72888 transmute(b.3),
72889 c,
72890 );
72891 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72892 }
72893}
72894#[doc = "Extended table look-up"]
72895#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
72896#[inline]
72897#[cfg(target_endian = "little")]
72898#[target_feature(enable = "neon,v7")]
72899#[cfg(target_arch = "arm")]
72900#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72901#[cfg_attr(test, assert_instr(vtbx))]
72902pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
72903 unsafe {
72904 transmute(vtbx4(
72905 transmute(a),
72906 transmute(b.0),
72907 transmute(b.1),
72908 transmute(b.2),
72909 transmute(b.3),
72910 transmute(c),
72911 ))
72912 }
72913}
72914#[doc = "Extended table look-up"]
72915#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
72916#[inline]
72917#[cfg(target_endian = "big")]
72918#[target_feature(enable = "neon,v7")]
72919#[cfg(target_arch = "arm")]
72920#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72921#[cfg_attr(test, assert_instr(vtbx))]
72922pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
72923 let mut b: uint8x8x4_t = b;
72924 let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72925 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72926 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72927 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72928 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72929 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72930 unsafe {
72931 let ret_val: uint8x8_t = transmute(vtbx4(
72932 transmute(a),
72933 transmute(b.0),
72934 transmute(b.1),
72935 transmute(b.2),
72936 transmute(b.3),
72937 transmute(c),
72938 ));
72939 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72940 }
72941}
72942#[doc = "Extended table look-up"]
72943#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
72944#[inline]
72945#[cfg(target_endian = "little")]
72946#[target_feature(enable = "neon,v7")]
72947#[cfg(target_arch = "arm")]
72948#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72949#[cfg_attr(test, assert_instr(vtbx))]
72950pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
72951 unsafe {
72952 transmute(vtbx4(
72953 transmute(a),
72954 transmute(b.0),
72955 transmute(b.1),
72956 transmute(b.2),
72957 transmute(b.3),
72958 transmute(c),
72959 ))
72960 }
72961}
72962#[doc = "Extended table look-up"]
72963#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
72964#[inline]
72965#[cfg(target_endian = "big")]
72966#[target_feature(enable = "neon,v7")]
72967#[cfg(target_arch = "arm")]
72968#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
72969#[cfg_attr(test, assert_instr(vtbx))]
72970pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
72971 let mut b: poly8x8x4_t = b;
72972 let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) };
72973 b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) };
72974 b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) };
72975 b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) };
72976 b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
72977 let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) };
72978 unsafe {
72979 let ret_val: poly8x8_t = transmute(vtbx4(
72980 transmute(a),
72981 transmute(b.0),
72982 transmute(b.1),
72983 transmute(b.2),
72984 transmute(b.3),
72985 transmute(c),
72986 ));
72987 simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0])
72988 }
72989}
72990#[doc = "Transpose elements"]
72991#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
72992#[inline]
72993#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
72994#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
72995#[cfg_attr(
72996 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
72997 assert_instr(trn1)
72998)]
72999#[cfg_attr(
73000 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73001 assert_instr(trn2)
73002)]
73003#[target_feature(enable = "neon,fp16")]
73004#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73005pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
73006 unsafe {
73007 let a1: float16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73008 let b1: float16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73009 transmute((a1, b1))
73010 }
73011}
73012#[doc = "Transpose elements"]
73013#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
73014#[inline]
73015#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73016#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73017#[cfg_attr(
73018 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73019 assert_instr(trn1)
73020)]
73021#[cfg_attr(
73022 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73023 assert_instr(trn2)
73024)]
73025#[target_feature(enable = "neon,fp16")]
73026#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
73027pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
73028 unsafe {
73029 let a1: float16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73030 let b1: float16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73031 transmute((a1, b1))
73032 }
73033}
73034#[doc = "Transpose elements"]
73035#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
73036#[inline]
73037#[target_feature(enable = "neon")]
73038#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73039#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73040#[cfg_attr(
73041 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73042 assert_instr(zip1)
73043)]
73044#[cfg_attr(
73045 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73046 assert_instr(zip2)
73047)]
73048#[cfg_attr(
73049 not(target_arch = "arm"),
73050 stable(feature = "neon_intrinsics", since = "1.59.0")
73051)]
73052#[cfg_attr(
73053 target_arch = "arm",
73054 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73055)]
73056pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
73057 unsafe {
73058 let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]);
73059 let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]);
73060 transmute((a1, b1))
73061 }
73062}
73063#[doc = "Transpose elements"]
73064#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
73065#[inline]
73066#[target_feature(enable = "neon")]
73067#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73068#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73069#[cfg_attr(
73070 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73071 assert_instr(zip1)
73072)]
73073#[cfg_attr(
73074 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73075 assert_instr(zip2)
73076)]
73077#[cfg_attr(
73078 not(target_arch = "arm"),
73079 stable(feature = "neon_intrinsics", since = "1.59.0")
73080)]
73081#[cfg_attr(
73082 target_arch = "arm",
73083 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73084)]
73085pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
73086 unsafe {
73087 let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]);
73088 let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]);
73089 transmute((a1, b1))
73090 }
73091}
73092#[doc = "Transpose elements"]
73093#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
73094#[inline]
73095#[target_feature(enable = "neon")]
73096#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73097#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73098#[cfg_attr(
73099 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73100 assert_instr(zip1)
73101)]
73102#[cfg_attr(
73103 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73104 assert_instr(zip2)
73105)]
73106#[cfg_attr(
73107 not(target_arch = "arm"),
73108 stable(feature = "neon_intrinsics", since = "1.59.0")
73109)]
73110#[cfg_attr(
73111 target_arch = "arm",
73112 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73113)]
73114pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
73115 unsafe {
73116 let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
73117 let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
73118 transmute((a1, b1))
73119 }
73120}
73121#[doc = "Transpose elements"]
73122#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
73123#[inline]
73124#[target_feature(enable = "neon")]
73125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73127#[cfg_attr(
73128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73129 assert_instr(trn1)
73130)]
73131#[cfg_attr(
73132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73133 assert_instr(trn2)
73134)]
73135#[cfg_attr(
73136 not(target_arch = "arm"),
73137 stable(feature = "neon_intrinsics", since = "1.59.0")
73138)]
73139#[cfg_attr(
73140 target_arch = "arm",
73141 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73142)]
73143pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
73144 unsafe {
73145 let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73146 let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73147 transmute((a1, b1))
73148 }
73149}
73150#[doc = "Transpose elements"]
73151#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
73152#[inline]
73153#[target_feature(enable = "neon")]
73154#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73155#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73156#[cfg_attr(
73157 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73158 assert_instr(trn1)
73159)]
73160#[cfg_attr(
73161 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73162 assert_instr(trn2)
73163)]
73164#[cfg_attr(
73165 not(target_arch = "arm"),
73166 stable(feature = "neon_intrinsics", since = "1.59.0")
73167)]
73168#[cfg_attr(
73169 target_arch = "arm",
73170 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73171)]
73172pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
73173 unsafe {
73174 let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73175 let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73176 transmute((a1, b1))
73177 }
73178}
73179#[doc = "Transpose elements"]
73180#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
73181#[inline]
73182#[target_feature(enable = "neon")]
73183#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73184#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73185#[cfg_attr(
73186 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73187 assert_instr(trn1)
73188)]
73189#[cfg_attr(
73190 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73191 assert_instr(trn2)
73192)]
73193#[cfg_attr(
73194 not(target_arch = "arm"),
73195 stable(feature = "neon_intrinsics", since = "1.59.0")
73196)]
73197#[cfg_attr(
73198 target_arch = "arm",
73199 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73200)]
73201pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
73202 unsafe {
73203 let a1: int8x16_t = simd_shuffle!(
73204 a,
73205 b,
73206 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73207 );
73208 let b1: int8x16_t = simd_shuffle!(
73209 a,
73210 b,
73211 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73212 );
73213 transmute((a1, b1))
73214 }
73215}
73216#[doc = "Transpose elements"]
73217#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
73218#[inline]
73219#[target_feature(enable = "neon")]
73220#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73221#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73222#[cfg_attr(
73223 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73224 assert_instr(trn1)
73225)]
73226#[cfg_attr(
73227 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73228 assert_instr(trn2)
73229)]
73230#[cfg_attr(
73231 not(target_arch = "arm"),
73232 stable(feature = "neon_intrinsics", since = "1.59.0")
73233)]
73234#[cfg_attr(
73235 target_arch = "arm",
73236 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73237)]
73238pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
73239 unsafe {
73240 let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73241 let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73242 transmute((a1, b1))
73243 }
73244}
73245#[doc = "Transpose elements"]
73246#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
73247#[inline]
73248#[target_feature(enable = "neon")]
73249#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73250#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73251#[cfg_attr(
73252 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73253 assert_instr(trn1)
73254)]
73255#[cfg_attr(
73256 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73257 assert_instr(trn2)
73258)]
73259#[cfg_attr(
73260 not(target_arch = "arm"),
73261 stable(feature = "neon_intrinsics", since = "1.59.0")
73262)]
73263#[cfg_attr(
73264 target_arch = "arm",
73265 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73266)]
73267pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
73268 unsafe {
73269 let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73270 let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73271 transmute((a1, b1))
73272 }
73273}
73274#[doc = "Transpose elements"]
73275#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
73276#[inline]
73277#[target_feature(enable = "neon")]
73278#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73279#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73280#[cfg_attr(
73281 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73282 assert_instr(trn1)
73283)]
73284#[cfg_attr(
73285 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73286 assert_instr(trn2)
73287)]
73288#[cfg_attr(
73289 not(target_arch = "arm"),
73290 stable(feature = "neon_intrinsics", since = "1.59.0")
73291)]
73292#[cfg_attr(
73293 target_arch = "arm",
73294 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73295)]
73296pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
73297 unsafe {
73298 let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73299 let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73300 transmute((a1, b1))
73301 }
73302}
73303#[doc = "Transpose elements"]
73304#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
73305#[inline]
73306#[target_feature(enable = "neon")]
73307#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73308#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73309#[cfg_attr(
73310 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73311 assert_instr(trn1)
73312)]
73313#[cfg_attr(
73314 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73315 assert_instr(trn2)
73316)]
73317#[cfg_attr(
73318 not(target_arch = "arm"),
73319 stable(feature = "neon_intrinsics", since = "1.59.0")
73320)]
73321#[cfg_attr(
73322 target_arch = "arm",
73323 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73324)]
73325pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
73326 unsafe {
73327 let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73328 let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73329 transmute((a1, b1))
73330 }
73331}
73332#[doc = "Transpose elements"]
73333#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
73334#[inline]
73335#[target_feature(enable = "neon")]
73336#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73337#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73338#[cfg_attr(
73339 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73340 assert_instr(trn1)
73341)]
73342#[cfg_attr(
73343 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73344 assert_instr(trn2)
73345)]
73346#[cfg_attr(
73347 not(target_arch = "arm"),
73348 stable(feature = "neon_intrinsics", since = "1.59.0")
73349)]
73350#[cfg_attr(
73351 target_arch = "arm",
73352 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73353)]
73354pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
73355 unsafe {
73356 let a1: uint8x16_t = simd_shuffle!(
73357 a,
73358 b,
73359 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73360 );
73361 let b1: uint8x16_t = simd_shuffle!(
73362 a,
73363 b,
73364 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73365 );
73366 transmute((a1, b1))
73367 }
73368}
73369#[doc = "Transpose elements"]
73370#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
73371#[inline]
73372#[target_feature(enable = "neon")]
73373#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73374#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73375#[cfg_attr(
73376 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73377 assert_instr(trn1)
73378)]
73379#[cfg_attr(
73380 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73381 assert_instr(trn2)
73382)]
73383#[cfg_attr(
73384 not(target_arch = "arm"),
73385 stable(feature = "neon_intrinsics", since = "1.59.0")
73386)]
73387#[cfg_attr(
73388 target_arch = "arm",
73389 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73390)]
73391pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
73392 unsafe {
73393 let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73394 let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73395 transmute((a1, b1))
73396 }
73397}
73398#[doc = "Transpose elements"]
73399#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
73400#[inline]
73401#[target_feature(enable = "neon")]
73402#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73403#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73404#[cfg_attr(
73405 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73406 assert_instr(trn1)
73407)]
73408#[cfg_attr(
73409 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73410 assert_instr(trn2)
73411)]
73412#[cfg_attr(
73413 not(target_arch = "arm"),
73414 stable(feature = "neon_intrinsics", since = "1.59.0")
73415)]
73416#[cfg_attr(
73417 target_arch = "arm",
73418 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73419)]
73420pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
73421 unsafe {
73422 let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73423 let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73424 transmute((a1, b1))
73425 }
73426}
73427#[doc = "Transpose elements"]
73428#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
73429#[inline]
73430#[target_feature(enable = "neon")]
73431#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73432#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73433#[cfg_attr(
73434 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73435 assert_instr(trn1)
73436)]
73437#[cfg_attr(
73438 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73439 assert_instr(trn2)
73440)]
73441#[cfg_attr(
73442 not(target_arch = "arm"),
73443 stable(feature = "neon_intrinsics", since = "1.59.0")
73444)]
73445#[cfg_attr(
73446 target_arch = "arm",
73447 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73448)]
73449pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
73450 unsafe {
73451 let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73452 let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73453 transmute((a1, b1))
73454 }
73455}
73456#[doc = "Transpose elements"]
73457#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
73458#[inline]
73459#[target_feature(enable = "neon")]
73460#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73461#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73462#[cfg_attr(
73463 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73464 assert_instr(trn1)
73465)]
73466#[cfg_attr(
73467 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73468 assert_instr(trn2)
73469)]
73470#[cfg_attr(
73471 not(target_arch = "arm"),
73472 stable(feature = "neon_intrinsics", since = "1.59.0")
73473)]
73474#[cfg_attr(
73475 target_arch = "arm",
73476 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73477)]
73478pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
73479 unsafe {
73480 let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73481 let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73482 transmute((a1, b1))
73483 }
73484}
73485#[doc = "Transpose elements"]
73486#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
73487#[inline]
73488#[target_feature(enable = "neon")]
73489#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73490#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73491#[cfg_attr(
73492 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73493 assert_instr(trn1)
73494)]
73495#[cfg_attr(
73496 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73497 assert_instr(trn2)
73498)]
73499#[cfg_attr(
73500 not(target_arch = "arm"),
73501 stable(feature = "neon_intrinsics", since = "1.59.0")
73502)]
73503#[cfg_attr(
73504 target_arch = "arm",
73505 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73506)]
73507pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
73508 unsafe {
73509 let a1: poly8x16_t = simd_shuffle!(
73510 a,
73511 b,
73512 [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]
73513 );
73514 let b1: poly8x16_t = simd_shuffle!(
73515 a,
73516 b,
73517 [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]
73518 );
73519 transmute((a1, b1))
73520 }
73521}
73522#[doc = "Transpose elements"]
73523#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
73524#[inline]
73525#[target_feature(enable = "neon")]
73526#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73527#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73528#[cfg_attr(
73529 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73530 assert_instr(trn1)
73531)]
73532#[cfg_attr(
73533 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73534 assert_instr(trn2)
73535)]
73536#[cfg_attr(
73537 not(target_arch = "arm"),
73538 stable(feature = "neon_intrinsics", since = "1.59.0")
73539)]
73540#[cfg_attr(
73541 target_arch = "arm",
73542 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73543)]
73544pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
73545 unsafe {
73546 let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]);
73547 let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]);
73548 transmute((a1, b1))
73549 }
73550}
73551#[doc = "Transpose elements"]
73552#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
73553#[inline]
73554#[target_feature(enable = "neon")]
73555#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73556#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
73557#[cfg_attr(
73558 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73559 assert_instr(trn1)
73560)]
73561#[cfg_attr(
73562 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73563 assert_instr(trn2)
73564)]
73565#[cfg_attr(
73566 not(target_arch = "arm"),
73567 stable(feature = "neon_intrinsics", since = "1.59.0")
73568)]
73569#[cfg_attr(
73570 target_arch = "arm",
73571 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73572)]
73573pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
73574 unsafe {
73575 let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]);
73576 let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]);
73577 transmute((a1, b1))
73578 }
73579}
73580#[doc = "Signed compare bitwise Test bits nonzero"]
73581#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
73582#[inline]
73583#[target_feature(enable = "neon")]
73584#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73585#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73586#[cfg_attr(
73587 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73588 assert_instr(cmtst)
73589)]
73590#[cfg_attr(
73591 not(target_arch = "arm"),
73592 stable(feature = "neon_intrinsics", since = "1.59.0")
73593)]
73594#[cfg_attr(
73595 target_arch = "arm",
73596 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73597)]
73598pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
73599 unsafe {
73600 let c: int8x8_t = simd_and(a, b);
73601 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73602 simd_ne(c, transmute(d))
73603 }
73604}
73605#[doc = "Signed compare bitwise Test bits nonzero"]
73606#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
73607#[inline]
73608#[target_feature(enable = "neon")]
73609#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73610#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73611#[cfg_attr(
73612 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73613 assert_instr(cmtst)
73614)]
73615#[cfg_attr(
73616 not(target_arch = "arm"),
73617 stable(feature = "neon_intrinsics", since = "1.59.0")
73618)]
73619#[cfg_attr(
73620 target_arch = "arm",
73621 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73622)]
73623pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
73624 unsafe {
73625 let c: int8x16_t = simd_and(a, b);
73626 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73627 simd_ne(c, transmute(d))
73628 }
73629}
73630#[doc = "Signed compare bitwise Test bits nonzero"]
73631#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
73632#[inline]
73633#[target_feature(enable = "neon")]
73634#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73635#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73636#[cfg_attr(
73637 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73638 assert_instr(cmtst)
73639)]
73640#[cfg_attr(
73641 not(target_arch = "arm"),
73642 stable(feature = "neon_intrinsics", since = "1.59.0")
73643)]
73644#[cfg_attr(
73645 target_arch = "arm",
73646 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73647)]
73648pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
73649 unsafe {
73650 let c: int16x4_t = simd_and(a, b);
73651 let d: i16x4 = i16x4::new(0, 0, 0, 0);
73652 simd_ne(c, transmute(d))
73653 }
73654}
73655#[doc = "Signed compare bitwise Test bits nonzero"]
73656#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
73657#[inline]
73658#[target_feature(enable = "neon")]
73659#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73660#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73661#[cfg_attr(
73662 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73663 assert_instr(cmtst)
73664)]
73665#[cfg_attr(
73666 not(target_arch = "arm"),
73667 stable(feature = "neon_intrinsics", since = "1.59.0")
73668)]
73669#[cfg_attr(
73670 target_arch = "arm",
73671 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73672)]
73673pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
73674 unsafe {
73675 let c: int16x8_t = simd_and(a, b);
73676 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73677 simd_ne(c, transmute(d))
73678 }
73679}
73680#[doc = "Signed compare bitwise Test bits nonzero"]
73681#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
73682#[inline]
73683#[target_feature(enable = "neon")]
73684#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73685#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73686#[cfg_attr(
73687 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73688 assert_instr(cmtst)
73689)]
73690#[cfg_attr(
73691 not(target_arch = "arm"),
73692 stable(feature = "neon_intrinsics", since = "1.59.0")
73693)]
73694#[cfg_attr(
73695 target_arch = "arm",
73696 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73697)]
73698pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
73699 unsafe {
73700 let c: int32x2_t = simd_and(a, b);
73701 let d: i32x2 = i32x2::new(0, 0);
73702 simd_ne(c, transmute(d))
73703 }
73704}
73705#[doc = "Signed compare bitwise Test bits nonzero"]
73706#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
73707#[inline]
73708#[target_feature(enable = "neon")]
73709#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73710#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73711#[cfg_attr(
73712 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73713 assert_instr(cmtst)
73714)]
73715#[cfg_attr(
73716 not(target_arch = "arm"),
73717 stable(feature = "neon_intrinsics", since = "1.59.0")
73718)]
73719#[cfg_attr(
73720 target_arch = "arm",
73721 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73722)]
73723pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
73724 unsafe {
73725 let c: int32x4_t = simd_and(a, b);
73726 let d: i32x4 = i32x4::new(0, 0, 0, 0);
73727 simd_ne(c, transmute(d))
73728 }
73729}
73730#[doc = "Signed compare bitwise Test bits nonzero"]
73731#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
73732#[inline]
73733#[target_feature(enable = "neon")]
73734#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73735#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73736#[cfg_attr(
73737 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73738 assert_instr(cmtst)
73739)]
73740#[cfg_attr(
73741 not(target_arch = "arm"),
73742 stable(feature = "neon_intrinsics", since = "1.59.0")
73743)]
73744#[cfg_attr(
73745 target_arch = "arm",
73746 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73747)]
73748pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
73749 unsafe {
73750 let c: poly8x8_t = simd_and(a, b);
73751 let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73752 simd_ne(c, transmute(d))
73753 }
73754}
73755#[doc = "Signed compare bitwise Test bits nonzero"]
73756#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
73757#[inline]
73758#[target_feature(enable = "neon")]
73759#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73760#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73761#[cfg_attr(
73762 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73763 assert_instr(cmtst)
73764)]
73765#[cfg_attr(
73766 not(target_arch = "arm"),
73767 stable(feature = "neon_intrinsics", since = "1.59.0")
73768)]
73769#[cfg_attr(
73770 target_arch = "arm",
73771 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73772)]
73773pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
73774 unsafe {
73775 let c: poly8x16_t = simd_and(a, b);
73776 let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73777 simd_ne(c, transmute(d))
73778 }
73779}
73780#[doc = "Signed compare bitwise Test bits nonzero"]
73781#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
73782#[inline]
73783#[target_feature(enable = "neon")]
73784#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73785#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73786#[cfg_attr(
73787 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73788 assert_instr(cmtst)
73789)]
73790#[cfg_attr(
73791 not(target_arch = "arm"),
73792 stable(feature = "neon_intrinsics", since = "1.59.0")
73793)]
73794#[cfg_attr(
73795 target_arch = "arm",
73796 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73797)]
73798pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
73799 unsafe {
73800 let c: poly16x4_t = simd_and(a, b);
73801 let d: i16x4 = i16x4::new(0, 0, 0, 0);
73802 simd_ne(c, transmute(d))
73803 }
73804}
73805#[doc = "Signed compare bitwise Test bits nonzero"]
73806#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
73807#[inline]
73808#[target_feature(enable = "neon")]
73809#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73810#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73811#[cfg_attr(
73812 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73813 assert_instr(cmtst)
73814)]
73815#[cfg_attr(
73816 not(target_arch = "arm"),
73817 stable(feature = "neon_intrinsics", since = "1.59.0")
73818)]
73819#[cfg_attr(
73820 target_arch = "arm",
73821 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73822)]
73823pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
73824 unsafe {
73825 let c: poly16x8_t = simd_and(a, b);
73826 let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73827 simd_ne(c, transmute(d))
73828 }
73829}
73830#[doc = "Unsigned compare bitwise Test bits nonzero"]
73831#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
73832#[inline]
73833#[target_feature(enable = "neon")]
73834#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73835#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73836#[cfg_attr(
73837 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73838 assert_instr(cmtst)
73839)]
73840#[cfg_attr(
73841 not(target_arch = "arm"),
73842 stable(feature = "neon_intrinsics", since = "1.59.0")
73843)]
73844#[cfg_attr(
73845 target_arch = "arm",
73846 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73847)]
73848pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
73849 unsafe {
73850 let c: uint8x8_t = simd_and(a, b);
73851 let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73852 simd_ne(c, transmute(d))
73853 }
73854}
73855#[doc = "Unsigned compare bitwise Test bits nonzero"]
73856#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
73857#[inline]
73858#[target_feature(enable = "neon")]
73859#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73860#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73861#[cfg_attr(
73862 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73863 assert_instr(cmtst)
73864)]
73865#[cfg_attr(
73866 not(target_arch = "arm"),
73867 stable(feature = "neon_intrinsics", since = "1.59.0")
73868)]
73869#[cfg_attr(
73870 target_arch = "arm",
73871 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73872)]
73873pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
73874 unsafe {
73875 let c: uint8x16_t = simd_and(a, b);
73876 let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
73877 simd_ne(c, transmute(d))
73878 }
73879}
73880#[doc = "Unsigned compare bitwise Test bits nonzero"]
73881#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
73882#[inline]
73883#[target_feature(enable = "neon")]
73884#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73885#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73886#[cfg_attr(
73887 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73888 assert_instr(cmtst)
73889)]
73890#[cfg_attr(
73891 not(target_arch = "arm"),
73892 stable(feature = "neon_intrinsics", since = "1.59.0")
73893)]
73894#[cfg_attr(
73895 target_arch = "arm",
73896 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73897)]
73898pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
73899 unsafe {
73900 let c: uint16x4_t = simd_and(a, b);
73901 let d: u16x4 = u16x4::new(0, 0, 0, 0);
73902 simd_ne(c, transmute(d))
73903 }
73904}
73905#[doc = "Unsigned compare bitwise Test bits nonzero"]
73906#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
73907#[inline]
73908#[target_feature(enable = "neon")]
73909#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73910#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73911#[cfg_attr(
73912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73913 assert_instr(cmtst)
73914)]
73915#[cfg_attr(
73916 not(target_arch = "arm"),
73917 stable(feature = "neon_intrinsics", since = "1.59.0")
73918)]
73919#[cfg_attr(
73920 target_arch = "arm",
73921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73922)]
73923pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
73924 unsafe {
73925 let c: uint16x8_t = simd_and(a, b);
73926 let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0);
73927 simd_ne(c, transmute(d))
73928 }
73929}
73930#[doc = "Unsigned compare bitwise Test bits nonzero"]
73931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
73932#[inline]
73933#[target_feature(enable = "neon")]
73934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73936#[cfg_attr(
73937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73938 assert_instr(cmtst)
73939)]
73940#[cfg_attr(
73941 not(target_arch = "arm"),
73942 stable(feature = "neon_intrinsics", since = "1.59.0")
73943)]
73944#[cfg_attr(
73945 target_arch = "arm",
73946 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73947)]
73948pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
73949 unsafe {
73950 let c: uint32x2_t = simd_and(a, b);
73951 let d: u32x2 = u32x2::new(0, 0);
73952 simd_ne(c, transmute(d))
73953 }
73954}
73955#[doc = "Unsigned compare bitwise Test bits nonzero"]
73956#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
73957#[inline]
73958#[target_feature(enable = "neon")]
73959#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
73960#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
73961#[cfg_attr(
73962 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73963 assert_instr(cmtst)
73964)]
73965#[cfg_attr(
73966 not(target_arch = "arm"),
73967 stable(feature = "neon_intrinsics", since = "1.59.0")
73968)]
73969#[cfg_attr(
73970 target_arch = "arm",
73971 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73972)]
73973pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
73974 unsafe {
73975 let c: uint32x4_t = simd_and(a, b);
73976 let d: u32x4 = u32x4::new(0, 0, 0, 0);
73977 simd_ne(c, transmute(d))
73978 }
73979}
73980#[doc = "Dot product index form with unsigned and signed integers"]
73981#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
73982#[inline]
73983#[target_feature(enable = "neon,i8mm")]
73984#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
73985#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
73986#[cfg_attr(
73987 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
73988 assert_instr(usdot, LANE = 0)
73989)]
73990#[rustc_legacy_const_generics(3)]
73991#[cfg_attr(
73992 not(target_arch = "arm"),
73993 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
73994)]
73995#[cfg_attr(
73996 target_arch = "arm",
73997 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
73998)]
73999pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74000 static_assert_uimm_bits!(LANE, 1);
74001 unsafe {
74002 let c: int32x2_t = transmute(c);
74003 let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
74004 vusdot_s32(a, b, transmute(c))
74005 }
74006}
74007#[doc = "Dot product index form with unsigned and signed integers"]
74008#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
74009#[inline]
74010#[target_feature(enable = "neon,i8mm")]
74011#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74012#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))]
74013#[cfg_attr(
74014 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74015 assert_instr(usdot, LANE = 0)
74016)]
74017#[rustc_legacy_const_generics(3)]
74018#[cfg_attr(
74019 not(target_arch = "arm"),
74020 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74021)]
74022#[cfg_attr(
74023 target_arch = "arm",
74024 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74025)]
74026pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t {
74027 static_assert_uimm_bits!(LANE, 1);
74028 unsafe {
74029 let c: int32x2_t = transmute(c);
74030 let c: int32x4_t =
74031 simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
74032 vusdotq_s32(a, b, transmute(c))
74033 }
74034}
74035#[doc = "Dot product vector form with unsigned and signed integers"]
74036#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
74037#[inline]
74038#[target_feature(enable = "neon,i8mm")]
74039#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74040#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74041#[cfg_attr(
74042 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74043 assert_instr(usdot)
74044)]
74045#[cfg_attr(
74046 not(target_arch = "arm"),
74047 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74048)]
74049#[cfg_attr(
74050 target_arch = "arm",
74051 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74052)]
74053pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
74054 unsafe extern "unadjusted" {
74055 #[cfg_attr(
74056 any(target_arch = "aarch64", target_arch = "arm64ec"),
74057 link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8"
74058 )]
74059 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")]
74060 fn _vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t;
74061 }
74062 unsafe { _vusdot_s32(a, b, c) }
74063}
74064#[doc = "Dot product vector form with unsigned and signed integers"]
74065#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
74066#[inline]
74067#[target_feature(enable = "neon,i8mm")]
74068#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74069#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
74070#[cfg_attr(
74071 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74072 assert_instr(usdot)
74073)]
74074#[cfg_attr(
74075 not(target_arch = "arm"),
74076 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74077)]
74078#[cfg_attr(
74079 target_arch = "arm",
74080 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74081)]
74082pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74083 unsafe extern "unadjusted" {
74084 #[cfg_attr(
74085 any(target_arch = "aarch64", target_arch = "arm64ec"),
74086 link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8"
74087 )]
74088 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")]
74089 fn _vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74090 }
74091 unsafe { _vusdotq_s32(a, b, c) }
74092}
74093#[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
74094#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
74095#[inline]
74096#[target_feature(enable = "neon,i8mm")]
74097#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
74098#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
74099#[cfg_attr(
74100 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74101 assert_instr(usmmla)
74102)]
74103#[cfg_attr(
74104 not(target_arch = "arm"),
74105 unstable(feature = "stdarch_neon_i8mm", issue = "117223")
74106)]
74107#[cfg_attr(
74108 target_arch = "arm",
74109 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74110)]
74111pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
74112 unsafe extern "unadjusted" {
74113 #[cfg_attr(
74114 any(target_arch = "aarch64", target_arch = "arm64ec"),
74115 link_name = "llvm.aarch64.neon.usmmla.v4i32.v16i8"
74116 )]
74117 #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usmmla.v4i32.v16i8")]
74118 fn _vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t;
74119 }
74120 unsafe { _vusmmlaq_s32(a, b, c) }
74121}
74122#[doc = "Unzip vectors"]
74123#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
74124#[inline]
74125#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74126#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74127#[cfg_attr(
74128 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74129 assert_instr(uzp1)
74130)]
74131#[cfg_attr(
74132 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74133 assert_instr(uzp2)
74134)]
74135#[target_feature(enable = "neon,fp16")]
74136#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74137pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74138 unsafe {
74139 let a0: float16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74140 let b0: float16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74141 transmute((a0, b0))
74142 }
74143}
74144#[doc = "Unzip vectors"]
74145#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
74146#[inline]
74147#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74148#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74149#[cfg_attr(
74150 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74151 assert_instr(uzp1)
74152)]
74153#[cfg_attr(
74154 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74155 assert_instr(uzp2)
74156)]
74157#[target_feature(enable = "neon,fp16")]
74158#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74159pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74160 unsafe {
74161 let a0: float16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74162 let b0: float16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74163 transmute((a0, b0))
74164 }
74165}
74166#[doc = "Unzip vectors"]
74167#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
74168#[inline]
74169#[target_feature(enable = "neon")]
74170#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74171#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74172#[cfg_attr(
74173 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74174 assert_instr(zip1)
74175)]
74176#[cfg_attr(
74177 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74178 assert_instr(zip2)
74179)]
74180#[cfg_attr(
74181 not(target_arch = "arm"),
74182 stable(feature = "neon_intrinsics", since = "1.59.0")
74183)]
74184#[cfg_attr(
74185 target_arch = "arm",
74186 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74187)]
74188pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74189 unsafe {
74190 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74191 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74192 transmute((a0, b0))
74193 }
74194}
74195#[doc = "Unzip vectors"]
74196#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
74197#[inline]
74198#[target_feature(enable = "neon")]
74199#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74200#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74201#[cfg_attr(
74202 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74203 assert_instr(zip1)
74204)]
74205#[cfg_attr(
74206 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74207 assert_instr(zip2)
74208)]
74209#[cfg_attr(
74210 not(target_arch = "arm"),
74211 stable(feature = "neon_intrinsics", since = "1.59.0")
74212)]
74213#[cfg_attr(
74214 target_arch = "arm",
74215 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74216)]
74217pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
74218 unsafe {
74219 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
74220 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
74221 transmute((a0, b0))
74222 }
74223}
74224#[doc = "Unzip vectors"]
74225#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
74226#[inline]
74227#[target_feature(enable = "neon")]
74228#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74229#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74230#[cfg_attr(
74231 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74232 assert_instr(zip1)
74233)]
74234#[cfg_attr(
74235 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74236 assert_instr(zip2)
74237)]
74238#[cfg_attr(
74239 not(target_arch = "arm"),
74240 stable(feature = "neon_intrinsics", since = "1.59.0")
74241)]
74242#[cfg_attr(
74243 target_arch = "arm",
74244 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74245)]
74246pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
74247 unsafe {
74248 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
74249 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
74250 transmute((a0, b0))
74251 }
74252}
74253#[doc = "Unzip vectors"]
74254#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
74255#[inline]
74256#[target_feature(enable = "neon")]
74257#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74258#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74259#[cfg_attr(
74260 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74261 assert_instr(uzp1)
74262)]
74263#[cfg_attr(
74264 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74265 assert_instr(uzp2)
74266)]
74267#[cfg_attr(
74268 not(target_arch = "arm"),
74269 stable(feature = "neon_intrinsics", since = "1.59.0")
74270)]
74271#[cfg_attr(
74272 target_arch = "arm",
74273 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74274)]
74275pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
74276 unsafe {
74277 let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74278 let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74279 transmute((a0, b0))
74280 }
74281}
74282#[doc = "Unzip vectors"]
74283#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
74284#[inline]
74285#[target_feature(enable = "neon")]
74286#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74287#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74288#[cfg_attr(
74289 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74290 assert_instr(uzp1)
74291)]
74292#[cfg_attr(
74293 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74294 assert_instr(uzp2)
74295)]
74296#[cfg_attr(
74297 not(target_arch = "arm"),
74298 stable(feature = "neon_intrinsics", since = "1.59.0")
74299)]
74300#[cfg_attr(
74301 target_arch = "arm",
74302 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74303)]
74304pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
74305 unsafe {
74306 let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74307 let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74308 transmute((a0, b0))
74309 }
74310}
74311#[doc = "Unzip vectors"]
74312#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
74313#[inline]
74314#[target_feature(enable = "neon")]
74315#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74316#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74317#[cfg_attr(
74318 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74319 assert_instr(uzp1)
74320)]
74321#[cfg_attr(
74322 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74323 assert_instr(uzp2)
74324)]
74325#[cfg_attr(
74326 not(target_arch = "arm"),
74327 stable(feature = "neon_intrinsics", since = "1.59.0")
74328)]
74329#[cfg_attr(
74330 target_arch = "arm",
74331 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74332)]
74333pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
74334 unsafe {
74335 let a0: int8x16_t = simd_shuffle!(
74336 a,
74337 b,
74338 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74339 );
74340 let b0: int8x16_t = simd_shuffle!(
74341 a,
74342 b,
74343 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74344 );
74345 transmute((a0, b0))
74346 }
74347}
74348#[doc = "Unzip vectors"]
74349#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
74350#[inline]
74351#[target_feature(enable = "neon")]
74352#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74353#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74354#[cfg_attr(
74355 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74356 assert_instr(uzp1)
74357)]
74358#[cfg_attr(
74359 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74360 assert_instr(uzp2)
74361)]
74362#[cfg_attr(
74363 not(target_arch = "arm"),
74364 stable(feature = "neon_intrinsics", since = "1.59.0")
74365)]
74366#[cfg_attr(
74367 target_arch = "arm",
74368 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74369)]
74370pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
74371 unsafe {
74372 let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74373 let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74374 transmute((a0, b0))
74375 }
74376}
74377#[doc = "Unzip vectors"]
74378#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
74379#[inline]
74380#[target_feature(enable = "neon")]
74381#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74382#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74383#[cfg_attr(
74384 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74385 assert_instr(uzp1)
74386)]
74387#[cfg_attr(
74388 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74389 assert_instr(uzp2)
74390)]
74391#[cfg_attr(
74392 not(target_arch = "arm"),
74393 stable(feature = "neon_intrinsics", since = "1.59.0")
74394)]
74395#[cfg_attr(
74396 target_arch = "arm",
74397 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74398)]
74399pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
74400 unsafe {
74401 let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74402 let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74403 transmute((a0, b0))
74404 }
74405}
74406#[doc = "Unzip vectors"]
74407#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
74408#[inline]
74409#[target_feature(enable = "neon")]
74410#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74411#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74412#[cfg_attr(
74413 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74414 assert_instr(uzp1)
74415)]
74416#[cfg_attr(
74417 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74418 assert_instr(uzp2)
74419)]
74420#[cfg_attr(
74421 not(target_arch = "arm"),
74422 stable(feature = "neon_intrinsics", since = "1.59.0")
74423)]
74424#[cfg_attr(
74425 target_arch = "arm",
74426 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74427)]
74428pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
74429 unsafe {
74430 let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74431 let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74432 transmute((a0, b0))
74433 }
74434}
74435#[doc = "Unzip vectors"]
74436#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
74437#[inline]
74438#[target_feature(enable = "neon")]
74439#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74440#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74441#[cfg_attr(
74442 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74443 assert_instr(uzp1)
74444)]
74445#[cfg_attr(
74446 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74447 assert_instr(uzp2)
74448)]
74449#[cfg_attr(
74450 not(target_arch = "arm"),
74451 stable(feature = "neon_intrinsics", since = "1.59.0")
74452)]
74453#[cfg_attr(
74454 target_arch = "arm",
74455 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74456)]
74457pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
74458 unsafe {
74459 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74460 let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74461 transmute((a0, b0))
74462 }
74463}
74464#[doc = "Unzip vectors"]
74465#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
74466#[inline]
74467#[target_feature(enable = "neon")]
74468#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74469#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74470#[cfg_attr(
74471 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74472 assert_instr(uzp1)
74473)]
74474#[cfg_attr(
74475 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74476 assert_instr(uzp2)
74477)]
74478#[cfg_attr(
74479 not(target_arch = "arm"),
74480 stable(feature = "neon_intrinsics", since = "1.59.0")
74481)]
74482#[cfg_attr(
74483 target_arch = "arm",
74484 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74485)]
74486pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
74487 unsafe {
74488 let a0: uint8x16_t = simd_shuffle!(
74489 a,
74490 b,
74491 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74492 );
74493 let b0: uint8x16_t = simd_shuffle!(
74494 a,
74495 b,
74496 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74497 );
74498 transmute((a0, b0))
74499 }
74500}
74501#[doc = "Unzip vectors"]
74502#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
74503#[inline]
74504#[target_feature(enable = "neon")]
74505#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74506#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74507#[cfg_attr(
74508 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74509 assert_instr(uzp1)
74510)]
74511#[cfg_attr(
74512 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74513 assert_instr(uzp2)
74514)]
74515#[cfg_attr(
74516 not(target_arch = "arm"),
74517 stable(feature = "neon_intrinsics", since = "1.59.0")
74518)]
74519#[cfg_attr(
74520 target_arch = "arm",
74521 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74522)]
74523pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
74524 unsafe {
74525 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74526 let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74527 transmute((a0, b0))
74528 }
74529}
74530#[doc = "Unzip vectors"]
74531#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
74532#[inline]
74533#[target_feature(enable = "neon")]
74534#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74535#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74536#[cfg_attr(
74537 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74538 assert_instr(uzp1)
74539)]
74540#[cfg_attr(
74541 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74542 assert_instr(uzp2)
74543)]
74544#[cfg_attr(
74545 not(target_arch = "arm"),
74546 stable(feature = "neon_intrinsics", since = "1.59.0")
74547)]
74548#[cfg_attr(
74549 target_arch = "arm",
74550 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74551)]
74552pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
74553 unsafe {
74554 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74555 let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74556 transmute((a0, b0))
74557 }
74558}
74559#[doc = "Unzip vectors"]
74560#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
74561#[inline]
74562#[target_feature(enable = "neon")]
74563#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74564#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74565#[cfg_attr(
74566 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74567 assert_instr(uzp1)
74568)]
74569#[cfg_attr(
74570 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74571 assert_instr(uzp2)
74572)]
74573#[cfg_attr(
74574 not(target_arch = "arm"),
74575 stable(feature = "neon_intrinsics", since = "1.59.0")
74576)]
74577#[cfg_attr(
74578 target_arch = "arm",
74579 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74580)]
74581pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
74582 unsafe {
74583 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74584 let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74585 transmute((a0, b0))
74586 }
74587}
74588#[doc = "Unzip vectors"]
74589#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
74590#[inline]
74591#[target_feature(enable = "neon")]
74592#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74593#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74594#[cfg_attr(
74595 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74596 assert_instr(uzp1)
74597)]
74598#[cfg_attr(
74599 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74600 assert_instr(uzp2)
74601)]
74602#[cfg_attr(
74603 not(target_arch = "arm"),
74604 stable(feature = "neon_intrinsics", since = "1.59.0")
74605)]
74606#[cfg_attr(
74607 target_arch = "arm",
74608 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74609)]
74610pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
74611 unsafe {
74612 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74613 let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74614 transmute((a0, b0))
74615 }
74616}
74617#[doc = "Unzip vectors"]
74618#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
74619#[inline]
74620#[target_feature(enable = "neon")]
74621#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74622#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74623#[cfg_attr(
74624 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74625 assert_instr(uzp1)
74626)]
74627#[cfg_attr(
74628 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74629 assert_instr(uzp2)
74630)]
74631#[cfg_attr(
74632 not(target_arch = "arm"),
74633 stable(feature = "neon_intrinsics", since = "1.59.0")
74634)]
74635#[cfg_attr(
74636 target_arch = "arm",
74637 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74638)]
74639pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
74640 unsafe {
74641 let a0: poly8x16_t = simd_shuffle!(
74642 a,
74643 b,
74644 [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]
74645 );
74646 let b0: poly8x16_t = simd_shuffle!(
74647 a,
74648 b,
74649 [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
74650 );
74651 transmute((a0, b0))
74652 }
74653}
74654#[doc = "Unzip vectors"]
74655#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
74656#[inline]
74657#[target_feature(enable = "neon")]
74658#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74659#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74660#[cfg_attr(
74661 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74662 assert_instr(uzp1)
74663)]
74664#[cfg_attr(
74665 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74666 assert_instr(uzp2)
74667)]
74668#[cfg_attr(
74669 not(target_arch = "arm"),
74670 stable(feature = "neon_intrinsics", since = "1.59.0")
74671)]
74672#[cfg_attr(
74673 target_arch = "arm",
74674 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74675)]
74676pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
74677 unsafe {
74678 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]);
74679 let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]);
74680 transmute((a0, b0))
74681 }
74682}
74683#[doc = "Unzip vectors"]
74684#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
74685#[inline]
74686#[target_feature(enable = "neon")]
74687#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74688#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
74689#[cfg_attr(
74690 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74691 assert_instr(uzp1)
74692)]
74693#[cfg_attr(
74694 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74695 assert_instr(uzp2)
74696)]
74697#[cfg_attr(
74698 not(target_arch = "arm"),
74699 stable(feature = "neon_intrinsics", since = "1.59.0")
74700)]
74701#[cfg_attr(
74702 target_arch = "arm",
74703 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74704)]
74705pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
74706 unsafe {
74707 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
74708 let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
74709 transmute((a0, b0))
74710 }
74711}
74712#[doc = "Zip vectors"]
74713#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
74714#[inline]
74715#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74716#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
74717#[cfg_attr(
74718 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74719 assert_instr(zip1)
74720)]
74721#[cfg_attr(
74722 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74723 assert_instr(zip2)
74724)]
74725#[target_feature(enable = "neon,fp16")]
74726#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74727pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
74728 unsafe {
74729 let a0: float16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
74730 let b0: float16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
74731 transmute((a0, b0))
74732 }
74733}
74734#[doc = "Zip vectors"]
74735#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
74736#[inline]
74737#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74738#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
74739#[cfg_attr(
74740 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74741 assert_instr(zip1)
74742)]
74743#[cfg_attr(
74744 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74745 assert_instr(zip2)
74746)]
74747#[target_feature(enable = "neon,fp16")]
74748#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
74749pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
74750 unsafe {
74751 let a0: float16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
74752 let b0: float16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
74753 transmute((a0, b0))
74754 }
74755}
74756#[doc = "Zip vectors"]
74757#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
74758#[inline]
74759#[target_feature(enable = "neon")]
74760#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74761#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74762#[cfg_attr(
74763 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74764 assert_instr(zip1)
74765)]
74766#[cfg_attr(
74767 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74768 assert_instr(zip2)
74769)]
74770#[cfg_attr(
74771 not(target_arch = "arm"),
74772 stable(feature = "neon_intrinsics", since = "1.59.0")
74773)]
74774#[cfg_attr(
74775 target_arch = "arm",
74776 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74777)]
74778pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
74779 unsafe {
74780 let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]);
74781 let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]);
74782 transmute((a0, b0))
74783 }
74784}
74785#[doc = "Zip vectors"]
74786#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
74787#[inline]
74788#[target_feature(enable = "neon")]
74789#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74790#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74791#[cfg_attr(
74792 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74793 assert_instr(zip1)
74794)]
74795#[cfg_attr(
74796 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74797 assert_instr(zip2)
74798)]
74799#[cfg_attr(
74800 not(target_arch = "arm"),
74801 stable(feature = "neon_intrinsics", since = "1.59.0")
74802)]
74803#[cfg_attr(
74804 target_arch = "arm",
74805 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74806)]
74807pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
74808 unsafe {
74809 let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]);
74810 let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]);
74811 transmute((a0, b0))
74812 }
74813}
74814#[doc = "Zip vectors"]
74815#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
74816#[inline]
74817#[target_feature(enable = "neon")]
74818#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74819#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
74820#[cfg_attr(
74821 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74822 assert_instr(zip1)
74823)]
74824#[cfg_attr(
74825 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74826 assert_instr(zip2)
74827)]
74828#[cfg_attr(
74829 not(target_arch = "arm"),
74830 stable(feature = "neon_intrinsics", since = "1.59.0")
74831)]
74832#[cfg_attr(
74833 target_arch = "arm",
74834 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74835)]
74836pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
74837 unsafe {
74838 let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]);
74839 let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]);
74840 transmute((a0, b0))
74841 }
74842}
74843#[doc = "Zip vectors"]
74844#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
74845#[inline]
74846#[target_feature(enable = "neon")]
74847#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74848#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74849#[cfg_attr(
74850 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74851 assert_instr(zip1)
74852)]
74853#[cfg_attr(
74854 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74855 assert_instr(zip2)
74856)]
74857#[cfg_attr(
74858 not(target_arch = "arm"),
74859 stable(feature = "neon_intrinsics", since = "1.59.0")
74860)]
74861#[cfg_attr(
74862 target_arch = "arm",
74863 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74864)]
74865pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
74866 unsafe {
74867 let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
74868 let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
74869 transmute((a0, b0))
74870 }
74871}
74872#[doc = "Zip vectors"]
74873#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
74874#[inline]
74875#[target_feature(enable = "neon")]
74876#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74877#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74878#[cfg_attr(
74879 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74880 assert_instr(zip1)
74881)]
74882#[cfg_attr(
74883 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74884 assert_instr(zip2)
74885)]
74886#[cfg_attr(
74887 not(target_arch = "arm"),
74888 stable(feature = "neon_intrinsics", since = "1.59.0")
74889)]
74890#[cfg_attr(
74891 target_arch = "arm",
74892 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74893)]
74894pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
74895 unsafe {
74896 let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
74897 let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
74898 transmute((a0, b0))
74899 }
74900}
74901#[doc = "Zip vectors"]
74902#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
74903#[inline]
74904#[target_feature(enable = "neon")]
74905#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74906#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74907#[cfg_attr(
74908 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74909 assert_instr(zip1)
74910)]
74911#[cfg_attr(
74912 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74913 assert_instr(zip2)
74914)]
74915#[cfg_attr(
74916 not(target_arch = "arm"),
74917 stable(feature = "neon_intrinsics", since = "1.59.0")
74918)]
74919#[cfg_attr(
74920 target_arch = "arm",
74921 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74922)]
74923pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
74924 unsafe {
74925 let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
74926 let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
74927 transmute((a0, b0))
74928 }
74929}
74930#[doc = "Zip vectors"]
74931#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
74932#[inline]
74933#[target_feature(enable = "neon")]
74934#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74935#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74936#[cfg_attr(
74937 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74938 assert_instr(zip1)
74939)]
74940#[cfg_attr(
74941 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74942 assert_instr(zip2)
74943)]
74944#[cfg_attr(
74945 not(target_arch = "arm"),
74946 stable(feature = "neon_intrinsics", since = "1.59.0")
74947)]
74948#[cfg_attr(
74949 target_arch = "arm",
74950 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74951)]
74952pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
74953 unsafe {
74954 let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
74955 let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
74956 transmute((a0, b0))
74957 }
74958}
74959#[doc = "Zip vectors"]
74960#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
74961#[inline]
74962#[target_feature(enable = "neon")]
74963#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74964#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74965#[cfg_attr(
74966 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74967 assert_instr(zip1)
74968)]
74969#[cfg_attr(
74970 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74971 assert_instr(zip2)
74972)]
74973#[cfg_attr(
74974 not(target_arch = "arm"),
74975 stable(feature = "neon_intrinsics", since = "1.59.0")
74976)]
74977#[cfg_attr(
74978 target_arch = "arm",
74979 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
74980)]
74981pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
74982 unsafe {
74983 let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
74984 let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
74985 transmute((a0, b0))
74986 }
74987}
74988#[doc = "Zip vectors"]
74989#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
74990#[inline]
74991#[target_feature(enable = "neon")]
74992#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
74993#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
74994#[cfg_attr(
74995 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
74996 assert_instr(zip1)
74997)]
74998#[cfg_attr(
74999 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75000 assert_instr(zip2)
75001)]
75002#[cfg_attr(
75003 not(target_arch = "arm"),
75004 stable(feature = "neon_intrinsics", since = "1.59.0")
75005)]
75006#[cfg_attr(
75007 target_arch = "arm",
75008 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75009)]
75010pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
75011 unsafe {
75012 let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75013 let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75014 transmute((a0, b0))
75015 }
75016}
75017#[doc = "Zip vectors"]
75018#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
75019#[inline]
75020#[target_feature(enable = "neon")]
75021#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75022#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75023#[cfg_attr(
75024 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75025 assert_instr(zip1)
75026)]
75027#[cfg_attr(
75028 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75029 assert_instr(zip2)
75030)]
75031#[cfg_attr(
75032 not(target_arch = "arm"),
75033 stable(feature = "neon_intrinsics", since = "1.59.0")
75034)]
75035#[cfg_attr(
75036 target_arch = "arm",
75037 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75038)]
75039pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
75040 unsafe {
75041 let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75042 let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75043 transmute((a0, b0))
75044 }
75045}
75046#[doc = "Zip vectors"]
75047#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
75048#[inline]
75049#[target_feature(enable = "neon")]
75050#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75051#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75052#[cfg_attr(
75053 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75054 assert_instr(zip1)
75055)]
75056#[cfg_attr(
75057 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75058 assert_instr(zip2)
75059)]
75060#[cfg_attr(
75061 not(target_arch = "arm"),
75062 stable(feature = "neon_intrinsics", since = "1.59.0")
75063)]
75064#[cfg_attr(
75065 target_arch = "arm",
75066 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75067)]
75068pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
75069 unsafe {
75070 let a0: int8x16_t = simd_shuffle!(
75071 a,
75072 b,
75073 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75074 );
75075 let b0: int8x16_t = simd_shuffle!(
75076 a,
75077 b,
75078 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75079 );
75080 transmute((a0, b0))
75081 }
75082}
75083#[doc = "Zip vectors"]
75084#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
75085#[inline]
75086#[target_feature(enable = "neon")]
75087#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75088#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75089#[cfg_attr(
75090 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75091 assert_instr(zip1)
75092)]
75093#[cfg_attr(
75094 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75095 assert_instr(zip2)
75096)]
75097#[cfg_attr(
75098 not(target_arch = "arm"),
75099 stable(feature = "neon_intrinsics", since = "1.59.0")
75100)]
75101#[cfg_attr(
75102 target_arch = "arm",
75103 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75104)]
75105pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
75106 unsafe {
75107 let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75108 let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75109 transmute((a0, b0))
75110 }
75111}
75112#[doc = "Zip vectors"]
75113#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
75114#[inline]
75115#[target_feature(enable = "neon")]
75116#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75117#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75118#[cfg_attr(
75119 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75120 assert_instr(zip1)
75121)]
75122#[cfg_attr(
75123 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75124 assert_instr(zip2)
75125)]
75126#[cfg_attr(
75127 not(target_arch = "arm"),
75128 stable(feature = "neon_intrinsics", since = "1.59.0")
75129)]
75130#[cfg_attr(
75131 target_arch = "arm",
75132 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75133)]
75134pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
75135 unsafe {
75136 let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75137 let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75138 transmute((a0, b0))
75139 }
75140}
75141#[doc = "Zip vectors"]
75142#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
75143#[inline]
75144#[target_feature(enable = "neon")]
75145#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75146#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75147#[cfg_attr(
75148 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75149 assert_instr(zip1)
75150)]
75151#[cfg_attr(
75152 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75153 assert_instr(zip2)
75154)]
75155#[cfg_attr(
75156 not(target_arch = "arm"),
75157 stable(feature = "neon_intrinsics", since = "1.59.0")
75158)]
75159#[cfg_attr(
75160 target_arch = "arm",
75161 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75162)]
75163pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
75164 unsafe {
75165 let a0: uint8x16_t = simd_shuffle!(
75166 a,
75167 b,
75168 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75169 );
75170 let b0: uint8x16_t = simd_shuffle!(
75171 a,
75172 b,
75173 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75174 );
75175 transmute((a0, b0))
75176 }
75177}
75178#[doc = "Zip vectors"]
75179#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
75180#[inline]
75181#[target_feature(enable = "neon")]
75182#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75183#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75184#[cfg_attr(
75185 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75186 assert_instr(zip1)
75187)]
75188#[cfg_attr(
75189 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75190 assert_instr(zip2)
75191)]
75192#[cfg_attr(
75193 not(target_arch = "arm"),
75194 stable(feature = "neon_intrinsics", since = "1.59.0")
75195)]
75196#[cfg_attr(
75197 target_arch = "arm",
75198 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75199)]
75200pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
75201 unsafe {
75202 let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75203 let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75204 transmute((a0, b0))
75205 }
75206}
75207#[doc = "Zip vectors"]
75208#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
75209#[inline]
75210#[target_feature(enable = "neon")]
75211#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75212#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75213#[cfg_attr(
75214 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75215 assert_instr(zip1)
75216)]
75217#[cfg_attr(
75218 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75219 assert_instr(zip2)
75220)]
75221#[cfg_attr(
75222 not(target_arch = "arm"),
75223 stable(feature = "neon_intrinsics", since = "1.59.0")
75224)]
75225#[cfg_attr(
75226 target_arch = "arm",
75227 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75228)]
75229pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
75230 unsafe {
75231 let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]);
75232 let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]);
75233 transmute((a0, b0))
75234 }
75235}
75236#[doc = "Zip vectors"]
75237#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
75238#[inline]
75239#[target_feature(enable = "neon")]
75240#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75241#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75242#[cfg_attr(
75243 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75244 assert_instr(zip1)
75245)]
75246#[cfg_attr(
75247 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75248 assert_instr(zip2)
75249)]
75250#[cfg_attr(
75251 not(target_arch = "arm"),
75252 stable(feature = "neon_intrinsics", since = "1.59.0")
75253)]
75254#[cfg_attr(
75255 target_arch = "arm",
75256 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75257)]
75258pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
75259 unsafe {
75260 let a0: poly8x16_t = simd_shuffle!(
75261 a,
75262 b,
75263 [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]
75264 );
75265 let b0: poly8x16_t = simd_shuffle!(
75266 a,
75267 b,
75268 [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]
75269 );
75270 transmute((a0, b0))
75271 }
75272}
75273#[doc = "Zip vectors"]
75274#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
75275#[inline]
75276#[target_feature(enable = "neon")]
75277#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
75278#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
75279#[cfg_attr(
75280 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75281 assert_instr(zip1)
75282)]
75283#[cfg_attr(
75284 all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
75285 assert_instr(zip2)
75286)]
75287#[cfg_attr(
75288 not(target_arch = "arm"),
75289 stable(feature = "neon_intrinsics", since = "1.59.0")
75290)]
75291#[cfg_attr(
75292 target_arch = "arm",
75293 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
75294)]
75295pub fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
75296 unsafe {
75297 let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]);
75298 let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]);
75299 transmute((a0, b0))
75300 }
75301}